EMMC_SD

This section provides information on the EMMC_SD Module Instance. Each of the module registers is described below.

Return to pfsoc_mss_regmap

EMMC_SD Register Mapping Summary

EMMC_SD Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

HRS00

RW

32

0x0001 0000

0x000

0x2000 8000

HRS01

RW

32

0x0000 0032

0x004

0x2000 8004

HRS02

RW

32

0x0003 0000

0x008

0x2000 8008

HRS03

RW

32

0x0000 0000

0x00C

0x2000 800C

HRS04

RW

32

0x0000 0000

0x010

0x2000 8010

HRS06

RW

32

0x0000 0000

0x018

0x2000 8018

HRS07

RW

32

0x0000 0000

0x01C

0x2000 801C

HRS30

RO

32

0x0000 0003

0x078

0x2000 8078

HRS31

RO

32

0x0411 0000

0x07C

0x2000 807C

HRS32

RW

32

0x0000 0000

0x080

0x2000 8080

HRS33

RO

32

0x0000 0000

0x084

0x2000 8084

HRS34

RO

32

0x0000 0000

0x088

0x2000 8088

HRS35

RW

32

0x0000 0000

0x08C

0x2000 808C

HRS36

RO

32

0x0000 0000

0x090

0x2000 8090

HRS37

RW

32

0x0000 0000

0x094

0x2000 8094

HRS38

RW

32

0x0000 0000

0x098

0x2000 8098

CRS63

RO

32

0x0003 0000

0xfc

0x2000 80fc

SRS00

RW

32

0x0000 0000

0x200

0x2000 8200

SRS01

RW

32

0x0000 0000

0x204

0x2000 8204

SRS02

RW

32

0x0000 0000

0x208

0x2000 8208

SRS03

RW

32

0x0000 0000

0x20C

0x2000 820C

SRS04

RO

32

0x0000 0000

0x210

0x2000 8210

SRS05

RO

32

0x0000 0000

0x214

0x2000 8214

SRS06

RO

32

0x0000 0000

0x218

0x2000 8218

SRS07

RO

32

0x0000 0000

0x21C

0x2000 821C

SRS08

RW

32

0x0000 0000

0x220

0x2000 8220

SRS09

RO

32

0x0000 0000

0x224

0x2000 8224

SRS10

RW

32

0x0000 0000

0x228

0x2000 8228

SRS11

RW

32

0x0000 0000

0x22C

0x2000 822C

SRS12

RW

32

0x0000 0000

0x230

0x2000 8230

SRS13

RW

32

0x0000 0000

0x234

0x2000 8234

SRS14

RW

32

0x0000 0000

0x238

0x2000 8238

SRS15

RW

32

0x0000 0000

0x23C

0x2000 823C

SRS16

RO

32

0x176A C8B2

0x240

0x2000 8240

SRS17

RO

32

0x1000 0077

0x244

0x2000 8244

SRS18

RO

32

0x0020 2020

0x248

0x2000 8248

SRS19

RO

32

0x0000 0020

0x24C

0x2000 824C

SRS20

RW

32

0x0000 0000

0x250

0x2000 8250

SRS21

RO

32

0x0000 0000

0x254

0x2000 8254

SRS22

RW

32

0x0000 0000

0x258

0x2000 8258

SRS23

RW

32

0x0000 0000

0x25C

0x2000 825C

SRS24

RO

32

0x0004 00FA

0x260

0x2000 8260

SRS25

RO

32

0x0004 0002

0x264

0x2000 8264

SRS26

RO

32

0x0001 0002

0x268

0x2000 8268

SRS27

RO

32

0x0002 0000

0x26C

0x2000 826C

SRS29

RO

32

0x0000 0000

0x274

0x2000 8274

CQRS00

RO

32

0x0000 0510

0x400

0x2000 8400

CQRS01

RO

32

0x0000 0000

0x404

0x2000 8404

CQRS02

RW

32

0x0000 0000

0x408

0x2000 8408

CQRS03

RW

32

0x0000 0000

0x40C

0x2000 840C

CQRS04

RW

32

0x0000 0000

0x410

0x2000 8410

CQRS05

RW

32

0x0000 0000

0x414

0x2000 8414

CQRS06

RW

32

0x0000 0000

0x418

0x2000 8418

CQRS07

RW

32

0x0000 0000

0x41C

0x2000 841C

CQRS08

RW

32

0x0000 0000

0x420

0x2000 8420

CQRS09

RW

32

0x0000 0000

0x424

0x2000 8424

CQRS10

RW

32

0x0000 0000

0x428

0x2000 8428

CQRS11

RW

32

0x0000 0000

0x42C

0x2000 842C

CQRS12

RO

32

0x0000 0000

0x430

0x2000 8430

CQRS13

RO

32

0x0000 0000

0x434

0x2000 8434

CQRS14

RW

32

0x0000 0000

0x438

0x2000 8438

CQRS16

RW

32

0x0000 0000

0x440

0x2000 8440

CQRS17

RW

32

0x0000 0000

0x444

0x2000 8444

CQRS18

RO

32

0x0000 0000

0x448

0x2000 8448

CQRS20

RW

32

0x0000 0000

0x450

0x2000 8450

CQRS21

RO

32

0x0000 0000

0x454

0x2000 8454

CQRS22

RO

32

0x0000 0000

0x458

0x2000 8458

CQRS23

RO

32

0x0000 0000

0x45C

0x2000 845C

 

EMMC_SD Register Descriptions

EMMC_SD : HRS00

Address offset

0x000

Physical address

0x2000 8000

Instance

EMMC_SD

Description

HRS00 - General Information Register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:24

HRS00_HWINIT1

HWINIT field

RO

0x00

23:16

SAV


SAV - Slot Available\n\n
This field provides a number of implemented slots. Each bit of the field is assigned to one of the slots (slot 0 is assigned to bit 16 of HRS00 register, slot 1 to bit 17, etc.). If given slot is implemented, the bit is read as 1. Otherwise, if given slot in unavailable, corresponding bit is 0. The slot 0 is always available. If slot n is implemented, the slot n-1 also is implemented.\n\n
This configuration supports one slot and this field is equal to 0x01 (although the value can be altered by changing HWINIT_HRS00 value).\n\n
HWINIT Field - Note this field is hardware initialized after reset and the value read back will match the IP configuration.

RO

0x01

15:1

HRS00_HWINIT0

HWINIT field

RO

0x0000

0

SWR


SWR - Software Reset\n\n

When set to 1, the entire core is reset. After reset operation complete, SWR bit is automatically cleared. It takes some time to complete the requested reset operation, so the software should always poll SWR bit status, and continue the other operations only when SWR is cleared to 0.\n\n

There is no difference between SWR and SRS11.SRFA software resets. Both resets the same flip-flops.

RW

0

 

EMMC_SD : HRS01

Address offset

0x004

Physical address

0x2000 8004

Instance

EMMC_SD

Description

HRS01 - Debounce Setting Register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:24

HRS01_HWINIT0

HWINIT field

RO

0x00

23:0

DP


DP - Debounce Period\n\n
Defines the number of system (clk) clock cycles used by the debounce logic, which detects card insertion and removal events. The debounce period is equal to DP * tclk, where tclk is the period of clk clock. If there is no change on s#_sdcd_n signal level for a programmed debounce period, the core logic decodes the card state as stable and triggers card_inserted or card_removed event. Typically, DP value should be chosen to obtain the period of 20ms.\n\n
This register is reset to DEBOUNCE_PERIOD (HWINIT_HRS01) after reset.

RW

0x00 0032

 

EMMC_SD : HRS02

Address offset

0x008

Physical address

0x2000 8008

Instance

EMMC_SD

Description

HRS02 - Bus Setting Register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:18

HRS02_HWINIT1

HWINIT field

RO

0x0000

17:16

OTN


OTN - Number of Outstanding Transfers\n\n
Specifies number of outstanding transfers on DMA (Master) interface. The number of outstadings is (OTN + 1), where OTN can be defined in range 0 to 3.\n\n
This register is set to 3 after reset (i.e. 4 outstanding transfers) (HWINIT_HRS02).

RW

0x3

15:4

HRS02_HWINIT0

HWINIT field

RO

0x000

3:0

PBL


PBL - Programmable Burst Length\n\n
This field defines a maximum number of beats in DMA burst. The value can be changed when no active transfer.\n
This register is 0 after reset.\n
0001b - 1 beat in burst\n
0010b - 2 beats in burst\n
0011b - 4 beats in burst\n
0100b - 8 bits in burst\n
other - 16 beats in burst

RW

0x0

 

EMMC_SD : HRS03

Address offset

0x00C

Physical address

0x2000 800C

Instance

EMMC_SD

Description


HRS03 - AXI ERROR Responses Register\n\n
These registers extend the standard set of SD-HOST interrupt statuses by information about AXI interface exceptions.\n
The registers are divided into three groups:\n
- Signal Enable registers allow to enable/mask signaling the Interrupt Status registers (HRS03[3:0]) on interrupt port\n
- Status Enable registers allow to enable/disable interrupt source for each Interrupt Status separately\n
- Interrupt Status are triggered whenever the interrupt source is detected and the Status Enable register is enabled\n

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:20

Reserved

 

RO
Rreturns0s

0x000

19

AER_IEBS


AER_IEBS - Signal Enable for AXI ERROR Response B channel: SLVERR\n
1 - interrupt enable\n
0 - interrupt masked

RW

0

18

AER_IEBD


AER_IEBD - Signal Enable for AXI ERROR Response B channel: DECERR\n\n
1 - interrupt enable\n
0 - interrupt masked

RW

0

17

AER_IERS


AER_IERS - Signal Enable for AXI ERROR Response R channel: SLVERR\n
1 - interrupt enable\n
0 - interrupt masked

RW

0

16

AER_IERD


AER_IERD - Signal Enable for AXI ERROR Response R channel: DECERR\n
1 - interrupt enable\n
0 - interrupt masked

RW

0

15:12

Reserved

 

RO
Rreturns0s

0x0

11

AER_SENBS


AER_SENBS - Status Enable for AXI ERROR Response B channel: SLVERR\n\n
1 - status enable\n
0 - status disable

RW

0

10

AER_SENBD


AER_SENBD - Status Enable for AXI ERROR Response B channel: DECERR\n\n
1 - status enable\n
0 - status disable

RW

0

9

AER_SENRS


AER_SENRS - Status Enable for AXI ERROR Response R channel: SLVERR\n\n
1 - status enable\n
0 - status disable

RW

0

8

AER_SENRD


AER_SENRD - Status Enable for AXI ERROR Response R channel: DECERR\n\n
1 - status enable\n
0 - status disable

RW

0

7:4

Reserved

 

RO
Rreturns0s

0x0

3

AER_BS


AER_BS - AXI ERROR Response B channel: SLVERR\n\n
This bit is set when a SLVERR is detected on AXI Master bus in B channel (Write Response Channel).

RW
W1toClr

0

2

AER_BD


AER_BD - AXI ERROR Response B channel: DECERR\n\n
This bit is set when a DECERR is detected on AXI Master bus in B channel (Write Response Channel).

RW
W1toClr

0

1

AER_RS


AER_RS - AXI ERROR Response R channel: SLVERR\n\n
This bit is set when a SLVERR is detected on AXI Master bus in R channel (READ Response Channel).

RW
W1toClr

0

0

AER_RD


AER_RD - AXI ERROR Response R channel: DECERR\n\n
This bit is set when a DECERR is detected on AXI Master bus in R channel (READ Response Channel).

RW
W1toClr

0

 

EMMC_SD : HRS04

Address offset

0x010

Physical address

0x2000 8010

Instance

EMMC_SD

Description


HRS04 - SD/eMMC PHY Registers Interface\n\n
This register enables access to the SD/eMMC PHY registers. The interface behavior is described in section SD/eMMC PHY Register Intreface.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:27

Reserved

 

RO
Rreturns0s

0x00

26

UIS_ACK


UIS_ACK - PHY Transaction Acknowledge\n\n
This bit is set 1 when UIS_WR or UIS_RD is confirmed, so either read data is available
in UIS_RDATA, or written data is already updated PHY register.

RO

0

25

UIS_RD


UIS_RD - PHY Read Transaction Request\n\n
This bit requests read transaction from PHY Register.

RW

0

24

UIS_WR


UIS_WR - PHY Write Transaction Requests\n\n
This bit requests write transaction to PHY Register.

RW

0

23:16

UIS_RDATA


UIS_RDATA - PHY Read Data\n\n
This field stories data read from PHY Register.

RO

0x00

15:8

UIS_WDATA


UIS_WDATA - PHY Write Data\n\n
This field stories data to be written to PHY Register.

RW

0x00

7:6

Reserved

 

RO
Rreturns0s

0x0

5:0

UIS_ADDR


UIS_ADDR - PHY Register Address\n\n
This filed stories address of PHY Register which is to be read of written.
Refer to the Integration Manual (cdns_sd4hc_integration_manual.pdf), Table: Remapping register address
to address of registers described in SD/eMMC PHY User Guide (cdns_sd_emmc_dll_phy_user_guide.pdf).

RW

0x00

 

EMMC_SD : HRS06

Address offset

0x018

Physical address

0x2000 8018

Instance

EMMC_SD

Description

HRS06 - eMMC control registers

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

Reserved

 

RO
Rreturns0s

0x0000

15

ETR


ETR - eMMC Tune Request\n\n
Setting this bit 1, the tune value is updated by ETV.
This bit is set 1 until the requested value is applied.
The tuning command request is to be set after this bit is automatically clear to 0.

RW

0

14

Reserved

 

RO
Rreturns0s

0

13:8

ETV


ETV - eMMC Tune Value\n\n
This register contains value can update the tune value and in consequence sample point.
The value become tune value when the ETR transits from 1 to 0.

RW

0x00

7:3

Reserved

 

RO
Rreturns0s

0x00

2:0

EMM


EMM - eMMC Mode select\n\n
This field sets eMMC mode. The mode should reflect to the eMMC device setting.
If the SD card is in use, this field needs to be 0000b.\n
0000b - SD Card in use\n
0010b - SDR\n
0011b - DDR\n
0100b - HS200\n
0101b - HS400\n
0110b - HS400 Enhanced Strobe\n
others - Legacy

RW

0x0

 

EMMC_SD : HRS07

Address offset

0x01C

Physical address

0x2000 801C

Instance

EMMC_SD

Description

HRS07 - IO Delay Information Register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:21

Reserved

 

RO
Rreturns0s

0x000

20:16

ODELAY_VAL


ODELAY_VAL - Output delay value for IO. \n
Designer should update this register with delay value of IO with appriopriate output delay. \n
Delay is count in half of period of sdmclk. If sdmclk is working at 200MHz frequency, \n
then 1 is 2,5 ns. \n
This value will be used to compensate delay of DAT line when controller is READ WAIT. \n
The sum value of IDELAY_VAL, ODELAY_VAL should be less equal 5'd20 for controller to work properly. \n

RW

0x00

15:5

Reserved

 

RO
Rreturns0s

0x000

4:0

IDELAY_VAL


IDELAY_VAL - Input delay value for IO. \n
Designer should update this register with delay value of IO with appriopriate input delay. \n
Delay is count in half of period of sdmclk. If sdmclk is working at 200MHz frequency, \n
then 1 is 2,5 ns. \n
This value will be used to compensate delay of DAT line when controller is driving READ WAIT. \n
The sum value of IDELAY_VAL, ODELAY_VAL should be less equal 5'd20 for controller to work properly. \n

RW

0x00

 

EMMC_SD : HRS30

Address offset

0x078

Physical address

0x2000 8078

Instance

EMMC_SD

Description


HRS30 - Host Capability Register\n
This register states whether configurable options are available or are not available in the SD/eMMC Host Controller configuration. This register gives such information about features not been covered by the standard capability registers (SRS16-SRS18).

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

 

RO
Rreturns0s

0x0000 0000

1

HS400ESSUP

High Speed 400 Enhance Strobe supported\n
This field informs whether HS400 Enhance Strobe mode is supported (1) or is not supported (0).

RO

1

0

CQSUP

Command Queuing supported\n
This field informs whether Command Queuing is supported (1) or is not supported (0).

RO

1

 

EMMC_SD : HRS31

Address offset

0x07C

Physical address

0x2000 807C

Instance

EMMC_SD

Description


HRS31 - Host Controller Version\n
This register contains the host controller version number.

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:28

Reserved

 

RO
Rreturns0s

0x0

27:16

HOSTCTRLVER

Host Controller Version\n
Release number of the Host Controller

RO

0x411

15:8

Reserved

 

RO
Rreturns0s

0x00

7:0

HOSTFIXVER

Fix Version Number\n
Number of the fix related to the Host Controller Version.

RO

0x00

 

EMMC_SD : HRS32

Address offset

0x080

Physical address

0x2000 8080

Instance

EMMC_SD

Description

HRS32 - FSM Monitor Register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

LOAD


LOAD - FSM monitor update request\n
Setting this bit to 1 starts internal FSM monitor to load value from selected FSM.\n
After finishing this bit will be automatically cleared by hardware and FSM status can be read.

RW

0

30:16

ADDR


ADDR - FSM address\n
This field selects which FSM status will be read.\n
All available status machines are listed in Debug section of User Guide.

WO

0x0000

15:0

DATA


DATA - FSM status\n
This register contains read FSM status. Before reading it user should select FSM address (ADDR), set LOAD bit and wait until hardware clears it.

RO

0x0000

 

EMMC_SD : HRS33

Address offset

0x084

Physical address

0x2000 8084

Instance

EMMC_SD

Description

HRS33 - Tune Status 0 Register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

STAT0


STAT0 - Tune status 0\n
After invoking UHS-I tunning procedure each bit of this register represents status of one tuning step.\n
This field correspond to tuning steps 31-0.\n
0 - Step failed\n
1 - Step passed

RO

0x0000 0000

 

EMMC_SD : HRS34

Address offset

0x088

Physical address

0x2000 8088

Instance

EMMC_SD

Description

HRS34 - Tune Status 1 Register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:8

Reserved

 

RO
Rreturns0s

0x00 0000

7:0

STAT1


STAT1 - Tune status 1\n
This field is continuation of STAT0 field.\n
Its value represents status of tuning steps 39-32.

RO

0x00

 

EMMC_SD : HRS35

Address offset

0x08C

Physical address

0x2000 808C

Instance

EMMC_SD

Description

HRS35 - Tune Debug Register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

TFR


TFR - Tune Force Request\n
Setting this bit 1, the tune value is updated by TFV.\n
This bit is set 1 until the requested value is applied.\n
The tuning command request is to be set after this bit is automatically clear to 0.

RW

0

30:22

Reserved

 

RO
Rreturns0s

0x000

21:16

TFV


TFV - Tune Force Value\n
This register contains value which can update the tune value and in consequence sample point.\n
The new tune value becomes valid when the TFR transits from 1 to 0.

RW

0x00

15:6

Reserved

 

RO
Rreturns0s

0x000

5:0

TVAL


TVAL - Tune Current Value\n
This field represents selected value of UHS-I delay.

RO

0x00

 

EMMC_SD : HRS36

Address offset

0x090

Physical address

0x2000 8090

Instance

EMMC_SD

Description

HRS36 - Boot Status Register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:6

Reserved

 

RO
Rreturns0s

0x000 0000

5

BOOT_EDE

Boot Error - End Bit Error

RO

0

4

BOOT_EDC

Boot Error - Data CRC Error

RO

0

3

BOOT_EDT

Boot Error - Data Timeout Error

RO

0

2

BOOT_EAI

Boot Error - Invalid Acknowledge Error

RO

0

1

BOOT_EAT

Boot Error - Acknowledge Timeout Error

RO

0

0

BOOT_ACT


Boot Active\n
Informs that the BOOT is active and the operation cannot be interfere by writing any registers.

RO

0

 

EMMC_SD : HRS37

Address offset

0x094

Physical address

0x2000 8094

Instance

EMMC_SD

Description

HRS37 - Read block gap coefficient interface mode select

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:6

Reserved

 

RO
Rreturns0s

0x000 0000

5:0

RGB_COEFF_IFM


RGB_COEFF_IFM - Read Block Gap Coefficient\n
This register selects a target Read Block Coefficient.\n
The Host Controller has a set of Read Block Coefficient registers. Each SD and eMMC speed mode has one dedicated register. While HRS38 is updated to set a Coefficient value, this register selects a target Read Block Coefficient. Following list shows the addresses to speed modes relation:\n
000000b - Default Speed (DS) \n
000001b - High Speed (HS) \n
001000b - UHS-I SDR12 \n
001001b - UHS-I SDR25 \n
001010b - UHS-I SDR50 \n
001011b - UHS-I SDR104 \n
001100b - UHS-I DDR50 \n
100000b - eMMC Legacy \n
100001b - eMMC SDR \n
100010b - eMMC DDR \n
100011b - eMMC HS200 \n
100100b - eMMC HS400 \n
100101b - eMMC HS400 Enhanced Strobe\n

RW

0x00

 

EMMC_SD : HRS38

Address offset

0x098

Physical address

0x2000 8098

Instance

EMMC_SD

Description

HRS38 - Read block gap coefficient

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:4

Reserved

 

RO
Rreturns0s

0x000 0000

3:0

RGB_COEFF


Read block gap coefficient.\n
Read block gap timing can be variable based on pad timing when the clock is stopped for flow control or stop at block gap purposes.
When stopping the clock the host controller has default settings for each interface mode that ensures read block gap
timing is met with pad delays up to 5ns (input and output path). If pad delays are longer than 5ns then the default settings
can changed (increased) to ensure read block gap timing is not violated.\n
HRS38 has a register for each interface mode and the interface mode is selected by using HRS38.

RW

0x0

 

EMMC_SD : CRS63

Address offset

0xfc

Physical address

0x2000 80fc

Instance

EMMC_SD

Description

CRS63 - Host Controller Version/Slot Interrupt Status

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:24

CRS63_HWINIT1

HWINIT field

RO

0x00

23:16

SVN


SVN - Specification Version Number.\n
This field identifies the Host Controller Specification Version.\n
0h - Version 1.00\n
1h - Version 2.00\n
2h - Version 3.00\n
3h - Version 4.00\n
4h-FFh - reserved\n
The host is compatible with SD Host Specification Version 4.00.\n
HWINIT Field - Note this field is hardware initialized after reset and the value read back will match the IP configuration.

RO

0x03

15:8

CRS63_HWINIT0

HWINIT field

RO

0x00

7:0

ISES


ISES - Interrupt Signal For Each Slot.\n
This field allows to determine which slot is currently signaling Interrupt/Wakeup signals.
Each bit is logical OR of all Interrupts Signal and Wakeup Signal implemented in given slot.\n
0 - Slot 1\n
1 - Slot 2\n
...\n
7 - Slot 8

RO

0x00

 

EMMC_SD : SRS00

Address offset

0x200

Physical address

0x2000 8200

Instance

EMMC_SD

Description

SRS00 - SDMA System Address / Argument 2

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

SAAR


SAAR - System Address / Argument 2
This field is used as:\n
- SDMA system memory address\n
- Auto CMD23 Argument\n\n


System Address:\n
This register is used as base address when SDMA engine is selected (SRS03.DMAE=1 and SRS10.DMASEL=0) and SRS15.HV4E=0.
When the SDMA has stopped at the SDMA block gap, writing to SAAR[31:24] resumes SDMA transfer.
If the SDMA engine is stopped, value of the SAAR[31:24] register is set to the next contiguous system address of the next data position\n\n

Auto CMD23 Argument:\n
This mode is used when non-DMA or ADMA2 engine is selected or SRS15.HV4E=1.
When the block count is enabled, software will set value from range 00000000h to 0000FFFFh.

RW

0x0000 0000

 

EMMC_SD : SRS01

Address offset

0x204

Physical address

0x2000 8204

Instance

EMMC_SD

Description

SRS01 - Block Size / Block Count

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

BCCT


BCCT - Block Count For Current Transfer\n
With this field, the number of data blocks can be defined for next transfer.\n
This register is used when SRS03.BCE is set 1,
otherwise it will be ignored.\n
The value is decremented after each block transfer. When this field is set 0, no data blocks will be transferred.\n
During data transfer read operation may return invalid value, and write operations are ignored.\n
0000h - no block transfer\n
0001h..FFFFh - 1..65535 block(s) transfer.

RW

0x0000

15

Reserved

 

RO
Rreturns0s

0

14:12

SDMABB


SDMABB - SDMA Buffer Boundary\n\n
In this field, the system address boundary can be set for SDMA engine.\n
The SDMA transfer stops crossing the address boundary and generates the DMA Interrupt (SRS12.DMAINT).\n
After the DMA Interrupt, when the SRS15.HV4E is 0, the software should write new SDMA System Address (SRS00.SAAR / SRS22.DMASA1) in order to resume the SDMA transaction.\n
0 - 4k bytes address boundary\n
1 - 8k bytes address boundary\n
2 - 16k bytes address boundary\n
3 - 32k bytes address boundary\n
4 - 64k bytes address boundary\n
5 - 128k bytes address boundary\n
6 - 256k bytes address boundary\n
7 - 512k bytes address boundary\n

RW

0x0

11:0

TBS


TBS - Transfer Block Size\n\n
This field defines block size for block data transfers. During data transfer, read operations may return an invalid value, and write operations are ignored.\n
The software will not set value that exceeds the physically implemented internal FIFO buffer size.
The buffer size is equal to 2^FIFODEPTH, where FIFODEPTH is the generic parameter of the core.\n
The SD/MMC (memory) uses block size up to 512 bytes.\n
The SDIO can use up to 2048 bytes.\n
000h - not used\n
001h - 1 data block\n
002h - 2 data blocks\n
003h - 3 data blocks\n
...\n
1FFh - 511 data blocks\n
200h - 512 data blocks\n
...\n
800h - 2048 data blocks\n
others - not used.\n\n
Note: It is recommended for the software to use native data block size (512B) in case of multiple data block transfer (SRS03.MSBS==1).
Using smaller block may cause unexpected response error when flow control is activated (i.e. SDCLK is disabled) during response transfer.

RW

0x000

 

EMMC_SD : SRS02

Address offset

0x208

Physical address

0x2000 8208

Instance

EMMC_SD

Description

SRS02 - Argument 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

ARG1


ARG1 - Command Argument 1\n\n
This field contains 32-bits argument for command issued by SRS03.CIDX file write.

RW

0x0000 0000

 

EMMC_SD : SRS03

Address offset

0x20C

Physical address

0x2000 820C

Instance

EMMC_SD

Description

SRS03 - Command/Transfer Mode

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:30

Reserved

 

RO
Rreturns0s

0x0

29:24

CIDX


CIDX - Command Index\n\n
This field contains a command number (index) of the command to be sent.\n
The index can be defined in range 00-63, which means all commands (CMD00-CMD63 and ACMD00-ACMD63) defined in related specifications are supported.\n
Writing this filed triggers the actual command transfer. This field is to be written only when Command Inhibit CMD bit is 0 in Present State Register (SRS09.CICMD).\n
To check the list of available commands, refer to the appropriate card/device specifications.

RW

0x00

23:22

CT


CT - Command Type\n\n
This field defines specific type of command.\n
- Normal Command (0) - used by default when other command types are not intended to be used\n
- Suspend Command (01b) - not used\n
- Resume Command (10b) - not used\n
- Abort Command (11b) - used when the software wants to stop the current data transfer (read or write data transfer).
The read transfer ends by stopping transfer to the internal buffer.
The write transfer ends with releasing DAT line to High-Z state.
Then, after sending an Abort Command, the software will issue the software reset.\n\n
The Suspend and Resume Mechanism is not supported by the SD Host version 4.00 and later, and the Suspend and Resume Commands will not be used.

RW

0x0

21

DPS


DPS - Data Present Select\n\n
Set to 1 for commands which transfer data (i.e. read or write data using DAT line).\n
Set to 0 for all other commands, including:\n
- Commands using only CMD line\n
- Commands with busy signalized on DAT[0] line (SRS03.RTS=11b)

RW

0

20

CICE


CICE - Command Index Check Enable\n\n
When set to 1, the host checks if the Command Index field in the response is equal to the SRS03.CIDX value.\n
When 0, the check is not performed and Command Index field of the response is ignored.\n
Recommended settings depends on response type, see following table for details:\n
SRS03.RTS=00: 0 - No Response\n
SRS03.RTS=01: 0 - R2\n
SRS03.RTS=10: 0 - R3, R4\n
SRS03.RTS=10: 1 - R1, R5, R6, R7\n
SRS03.RTS=11: 1 - R1b, R5b

RW

0

19

CRCCE


CRCCE - Command CRC Check Enable\n
When set to 1, the host checks if the CRC field of the response is valid.\n
When 0, the CRC check is disabled and the CRC field of the response is ignored.\n
The CRC check should be disabled for responses which do not contain an actual CRC value
(some responses contain all 1s in place of the CRC field), and enabled for all other kinds of responses.\n
Recommended settings depends on response type, see following table for details:\n
SRS03.RTS=00: 0 - No Response\n
SRS03.RTS=01: 0 - R2\n
SRS03.RTS=10: 0 - R3, R4\n
SRS03.RTS=10: 1 - R1, R5, R6, R7\n
SRS03.RTS=11: 1 - R1b, R5b

RW

0

18

Reserved

 

RO
Rreturns0s

0

17:16

RTS


RTS - Response Type Select\n\n
Defines the expected response length.\n
00b - no response\n
01b - 136-bit response\n
10b - 48-bit response\n
11b - 48-bit response with BUSY\n
Every command implies one of the response types listed above.
To check the response type corresponding to a given command, please refer to the appropriate card/device specifications.

RW

0x0

15:9

Reserved

 

RO
Rreturns0s

0x00

8

RID


RID - Response Interrupt Disable\n\n
When set to 1, the Command Complete Interrupt (SRS12.CC) will be disabled.
The host will ignore the SRS13.CC_SE and behave as the SRS13.CC_SE would be 0.\n
When set to 0, the SRS12.CC will be enabled or disabled depend on the SRS13.CC_SE bit only.

RW

0

7

RECE


RECE - Response Error Check Enable\n\n
When set 1, the host will look after R1/R5 responses.\n
If any error will be detected in the response, the SRS12.ERSP bit is set to 1.\n
The software will set this bit only when R1/R5 response is expected.\n
The software will set SRS03.RID and RECE bits to 1 when the host checks R1/R5 errors. And both bits will be clear to 0, when the Software Driver will checks R1/R5 errors.
On response error, the SRS12.ERSP bit (in Interrupt Status) is set 1.

RW

0

6

RECT


RECT - Response Type R1/R5\n\n
Select R1 or R5 response type for the response content checker. Listed below error bits will be evaluated.\n
RECT = 0, Response Type - R1 (SD Memory):\n
bit 31 OUT_OF_RANGE\n
bit 30 ADDRESS_ERROR\n
bit 29 BLOCK_LEN_ERROR\n
bit 26 WP_VIOLATION\n
bit 25 CARD_IS_LOCKED\n
bit 23 COM_CRC_ERROR\n
bit 21 CARD_ECC_FAILED\n
bit 20 CC_ERROR\n
bit 19 ERRORRECT = 1\n\n
RECT = 1, Response Type - R5 (SDIO):\n
bit 7 COM_CRC_ERROR\n
bit 3 ERROR\n
bit 1 FUNCTION_NUMBER\n
bit 0 OUT_OF_RANGE\n\n
This field is ignored when SRS03.RECE=0.

RW

0

5

MSBS


MSBS - Multi/Single Block Select\n\n
Multi-block or single-block data transfer can be selected with this field.\n
0 - Single-block\n
1 - Multi-block\n
This field is hardware-protected by Command Inhibit DAT bit in Present State Register (SRS09.CIDAT).
When CIDAT=1, all writes to this field are ignored.

RW

0

4

DTDS


DTDS - Data Transfer Direction Select\n\n
Selects direction of data transfer for commands with DPS=1.\n
0 - Write\n
1 - Read\n
For commands with SRS03.DPS=0, this field is ignored.\n
This field is hardware-protected by Command Inhibit DAT bit in Present State Register (SRS09.CIDAT).
When CIDAT=1, all writes to this field are ignored.

RW

0

3:2

ACE


ACE - Auto CMD Enable\n\n
The field allows to send one additional command to the card/device when the command is issued.\n
00b - No auto command\n
01b - Auto CMD12\n
10b - Auto CMD23\n
11b - Reserved\n
If Auto CMD disable (00b) is set, the host does not send any additional command. This setting will be used when auto command is not required or not intended.\n
If Auto CMD12 (01b) is set, the host sends CMD12 (Abort) automatically when last block of multi-block transfer is completed.\n
If Auto CMD23 (10b) is set, the host sends CMD23 (Set Block Count) automatically before issued transfer data command. An argument of this command can be set in SRS00.\n
On any error the issued command will not be sent.\n
This field is hardware-protected by Command Inhibit DAT bit in Present State Register (SRS09.CIDAT).
When SRS09.CIDAT=1, all writes to this field are ignored.

RW

0x0

1

BCE


BCE - Block Count Enable\n
When set to 1, the SRS01.BCCT Block Count is enabled.\n
Each transferred block automatically decrements the counter value. The multi-block transfer will end, when the counter reaches 0. So the finite transfer can not be performed with this setting.\n
When 0, block counting is disabled, and SRS01.BCCT retains its value.\n
The transfer will be infinite in non-DMA and SDMA modes. For ADMA mode the transfer can be infinite or finite.
The finite transfer ends on reading the descriptor with END status (so the transfer length is designated by the table of descriptors).
In case of infinite transfer, the software will explicitly set ABORT command type to stop transfer.\n
This field is hardware-protected by Command Inhibit DAT bit in Present State Register (SRS09.CIDAT).
When CIDAT=1, all writes to this field are ignored.

RW

0

0

DMAE


DMAE - DMA Enable\n\n
When set to 1, it enables DMA functionality. DMA can be enabled only if it is supported as indicated in the DMA Support in the SRS16.DMAS register.
If DMA is not supported (due to host configuration), this bit is ignored.\n
This field is hardware-protected by Command Inhibit DAT bit in Present State Register (SRS09.CIDAT).\n
When SRS09.CIDAT=1, all writes to this field are ignored.\n
Note: The ADMA2 mode uses only the finite transfer mode, i.e. this bit is to be set 1.

RW

0

 

EMMC_SD : SRS04

Address offset

0x210

Physical address

0x2000 8210

Instance

EMMC_SD

Description


The SRS04 - SRS07 registers store the response returned by the card.\n
The mapping of the actual device response and the SRS04 - SRS07 contents depends on the type of response.
The type of response is determined by the RTS field (Response Type) for all user-defined commands.\n
The separate cases are the Auto-CMD12 response (called R1b in the SD Memory Specification) and Auto-CMD23 response (called R1 in the SD Memory Specification).
Auto-CMD12 and Auto-CMD23 responses are handled by the core automatically and goes to the SRS07 register regardless of the RTS value.\n\n

SRS04-SRS07 relation to received response field:\n
Auto-CMD12 resp:\n
Response field R[39:8] - RESP3[31:0]\n\n

Auto-CMD23 resp:\n
Response field R[39:8] - RESP3[31:0]\n\n

No response:\n
RTS=00b\n\n

136-bit:\n
RTS=01b, Response field R[127:8] - {RESP3[23:0], RESP2[31:0], RESP1[31:0], RESP0[31:0]}\n\n

48-bit:\n
RTS=10b, Response field R[39:8] - RESP1[31:0]\n\n

48-bit with BUSY:\n
RTS=11b, Response field R[39:8] - RESP1[31:0]\n\n

Implementation note: Registers value are undefined after reset, and will be valid after response is received.

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

RESP1

RESP1 - Response Register #1

RO

0x0000 0000

 

EMMC_SD : SRS05

Address offset

0x214

Physical address

0x2000 8214

Instance

EMMC_SD

Description


Described in SRS04.

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

RESP2

RESP2 - Response Register #2

RO

0x0000 0000

 

EMMC_SD : SRS06

Address offset

0x218

Physical address

0x2000 8218

Instance

EMMC_SD

Description


Described in SRS04.

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

RESP3

RESP3 - Response Register #3

RO

0x0000 0000

 

EMMC_SD : SRS07

Address offset

0x21C

Physical address

0x2000 821C

Instance

EMMC_SD

Description


Described in SRS04.

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

RESP4

RESP4 - Response Register #4

RO

0x0000 0000

 

EMMC_SD : SRS08

Address offset

0x220

Physical address

0x2000 8220

Instance

EMMC_SD

Description

SRS08 - Data Buffer

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

BDP


BDP - Buffer Data Port\n\n
The field is to access the internal buffer (data block) in non-DMA transfer mode.
8-bit, 16-bit, or 32-bit access to SRS08 is possible with the following restrictions:\n
- Only sequential contiguous access in Little Endian mode is possible.
For example, if the software accesses BDP[7:0], then the next transfer will access BDP[15:8]. No byte skipping is allowed.\n
- Each new block will start at the least significant byte of BDP, which is BDP[7:0].\n
- If the block size is not a multiple of 32-bits, and the software accesses BDP using 32-bit words, then the excess bytes of the last word are ignored.
This allows the software driver to use only 32-bit data transfers regardless of the block size.\n
- Access to the register with precaution - the FIFO pointers can be damaged when buffer is not ready or when number of accesses exceed the transfer block size (SRS01.TBS
).\n\n

Following shows all transfers (byte enable variations) that are allowed on SRS08:\n
Transfer width = 32-bit:\n
be[3:0] = 'b1111 -> BDP[31:0]\n

Transfer width = 16-bit:\n
be[3:0] = 'b0011 -> BDP[15:0]\n
be[3:0] = 'b1100 -> BDP[31:16]\n

Transfer width = 8-bit:\n
be[3:0] = 'b0001 -> BDP[7:0]\n
be[3:0] = 'b0010 -> BDP[15:8]\n
be[3:0] = 'b0100 -> BDP[23:16]\n
be[3:0] = 'b1000 -> BDP[31:24]

RW

0x0000 0000

 

EMMC_SD : SRS09

Address offset

0x224

Physical address

0x2000 8224

Instance

EMMC_SD

Description

SRS09 - Present State Register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:25

Reserved

 

RO
Rreturns0s

0x00

24

CMDSL


CMDSL - CMD Line Signal Level (SD Mode only)\n\n
The value is equal to the actual signal level on CMD line of the SD interface (s#_cmd_i).\n
Is useful for debugging purposes.

RO

0

23:20

DATSL1


DATSL1 - DAT[3:0] Line Signal Level (SD Mode only)\n\n
The value is equal to the actual signal level on DAT pins of the SD interface:\n
SRS09.23 - s#_dat_i[3] pin level\n
SRS09.22 - s#_dat_i[2] pin level\n
SRS09.21 - s#_dat_i[1] pin level\n
SRS09.20 - s#_dat_i[0] pin level

RO

0x0

19

WPSL


WPSL - Write Protect Switch Pin Level\n\n
The value is equal to the actual signal level on Write Protect pin of the SD interface (sdwp_s#_n).\n
1 - means that the write operation is enabled\n
0 - means that the write operations is disabled

RO

0

18

CDSL


CDSL - Card Detect Pin Level\n\n
The value is equal to the inverted signal level on Card Detect pin of the SD interface (sdsl_s#_n).\n
1 - means that the card is inserted\n
0 - means no card is inside the slot\n\n
Debouncing is not performed on CDSL, therefore the use of Card Inserted (CI) bit is recommended during normal work.\n
CDSL bit is useful only for debugging purposes.

RO

0

17

CSS


CSS - Card State Stable\n\n
Indicates if Card Detect Pin Level (CDSL) is stable.\n
1 - means that the CDSL value is stable\n
0 - means that the CDSL is not stable (during card insertion/removal or during the reset)\n\n
Field is useful for debugging purposes.

RO

0

16

CI


CI - Card Inserted\n\n
Indicates if the card is inserted inside the slot.\n
0 - no card in slot\n
1 - card is inserted\n\n
Unlike SRS09.CDSL, value of SRS09.CI bit is guaranteed to be stable (i.e. debouncing is performed on this bit).
Use of this bit is recommended during the normal operation of host.

RO

0

15:12

Reserved

 

RO
Rreturns0s

0x0

11

BRE


BRE - Buffer Read Enable\n\n
This field represents data buffer (SRS08.BDP) state for read transfer in non-DMA mode.\n
1 - valid data can be read from the data buffer\n
0 - no valid data inside the data buffer\n\n
After reading the entire data block, this bit changes to 0.

RO

0

10

BWE


BWE - Buffer Write Enable\n\n
This bit represents data buffer (SRS08.BDP) state for write transfer in non-DMA mode.\n
1 - data can be written to the data buffer\n
0 - data cannot be written\n\n
After reading the entire data block, this changes to 0.\n
This bit will be cleared in case of SBGR at non-DMA write transfer (even if the internal buffer is ready). The buffer must not be written after the SBGR.
If the BWR was set, the only action from the S/W is to clear the interrupt status.

RO

0

9

RTA


RTA - Read Transfer Active (SD Mode only)\n\n
Indicates the status of the read data transfer.\n
0 - no data read transfer in progress\n
1 - data read transfer in progress\n\n
Bit is set 1 after sending the read command, or after restarting the read transfer by the Continue Request (SRS10.CREQ).\n
Bit is set 0 by the hardware after the last block of the read transfer, or after stopping the read transfer by the Stop at Block Gap Request (SRS10.SBGR).\n
In both cases, the entire data is to be read by the system from the internal data buffer before setting this bit to 0.
In other words, SRS09.RTA=0 means that the entire data is already transferred to the system, and internal data buffer is empty.

RO

0

8

WTA


WTA - Write Transfer Active (SD Mode only)\n\n
Indicates the status of the write data transfer.\n
0 - no data write transfer in progress\n
1 - data write transfer in progress\n\n
Bit is set 1 after sending the write command, or after restarting the write transfer by the Continue Request (SRS10.CREQ).\n
Bit is set 0 by the hardware after the last block of the write transfer, or after stopping the write transfer by the Stop at Block Gap Request (SRS10.SBGR).\n
In both cases, the entire data has to be transferred to the card from the internal data buffer before setting this bit to 0.
In other words, WTA=0 means that the entire data is already transferred to the card, and CRC response for the last data block is already received.

RO

0

7:4

DATSL2


DATSL2 - DAT[7:4] Line Signal Level (SD Mode only)\n\n
Field can be used to monitor DAT lines in range 7-4.\n
The value is equal to the actual signal level on DAT pins of the SD interface:\n
SFR9.7 - dat7_i_pin level\n
SFR9.6 - dat6_i_pin level\n
SFR9.5 - dat5_i_pin level\n
SFR9.4 - dat4_i_pin level

RO

0x0

3

Reserved

 

RO
Rreturns0s

0

2

DLA


DLA - DAT Line Active (SD Mode only)\n\n
Indicates if the DAT lines of SD interface are currently in use.\n
1 - DAT lines are active (in use)\n
0 - DAT lines are released (not in use)\n
This bit set to 1, when Read or Write Transfer bits are active (SRS09.RTA=1 or SRS09.WTA=1), or if the card indicates busy state on the DAT lines.
The card can become busy immediately after the write operation, or after command which requires response with busy.\n
Falling edge of this bit (change from 1 to 0) directly triggers Transfer Complete Interrupt (SRS12.TC).

RO

0

1

CIDAT


CIDAT - Command Inhibit DAT (SD Mode only)\n\n
Indicates if the host can issue a command which uses DAT line. Commands which use DAT line include write and read data commands and commands with busy response.\n
1 - command using DAT line cannot be sent\n
0 - command using DAT line can be sent\n
When CIDAT=1 then the SRS03[15:0] is write-protected. The software can write SRS03[15:0] only when CIDAT=0.

RO

0

0

CICMD


CICMD - Command Inhibit CMD\n\n
Indicates if the host can issue a command.\n
0 - command can be sent\n
1 - command cannot be sent\n\n
If this bit is 0, indicates the CMD line is not in use and the Host Controller can issue an SD command using the CMD line.\n
This bit is set immediately after the CI is written, indicating start of command transmission.\n
This bit is cleared when the command response is received.\n
Even if the Command Inhibit DAT is set to 1, commands using only the CMD line can be issued if the Command Inhibit CMD is 0.\n
Change from 1 to 0 directly triggers Command Complete Interrupt (SRS12.CC).

RO

0

 

EMMC_SD : SRS10

Address offset

0x228

Physical address

0x2000 8228

Instance

EMMC_SD

Description

SRS10 - Host Control 1 (General / Power / Block-Gap / Wake-Up)

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:27

Reserved

 

RO
Rreturns0s

0x00

26

WORM


WORM - Wakeup Event Enable On SD Card Removal\n\n
When set to 1, enables wake-up event via Card Removal assertion in the SRS12.CR register.

RW

0

25

WOIS


WOIS - Wake-Up Event Enable On Card Inserted\n\n
When set to 1, enables wake-up event via Card Insertion assertion in the SRS12.CIN register.

RW

0

24

WOIQ


WOIQ - Wakeup Event Enable On Card Interrupt\n\n
When set to 1, enables wake-up event via Card Interrupt assertion in the SRS12.CINT

RW

0

23:20

Reserved

 

RO
Rreturns0s

0x0

19

IBG


IBG - Interrupt At Block Gap (SD Mode only)\n\n
When set to 1, enables interrupt detection at the block gap for a multiple block transfer.\n
This bit is valid only in SD4 mode.\n
If the SD card cannot signal an interrupt during a multiple block transfer, this bit should be set to 0.\n\n
This field is ignored in UHS-II mode.

RW

0

18

RWC


RWC - Read-Wait Control (SD Mode only)\n\n
When set to 1, enables Read Wait control. The Read Wait function is optional for SDIO cards.\n
If the card does not support read wait, this bit would never be set to 1; otherwise, DAT line conflict may occur.\n\n
This field is ignored in UHS-II mode.

RW

0

17

CREQ


CR - Continue Request\n\n
When set to 1, restarts the transfer previously stopped using the Stop At Block Gap.\n
The software will set SRS10.SBGR (Stop At Block Gap) bit to 0 before setting the (CR) Continue Request.\n
When SRS10.SBGR=1, then all write operations to Continue Request are ignored. Clearing SRS10.SBGR can be done before or simultaneously with writing the CR.
Continue Request bit is cleared automatically by the host when SRS09.DLA (Dat Line Active) changes from 0 to 1, indicating the actual restart of the transfer.

RW
W1toSet

0

16

SBGR


SBGR - Stop At Block Gap Request\n\n

When set to 1, orders the stop executing read and write transaction at the next possible block gap for non-DMA, SDMA and ADMA transfers. The software will maintain SBGR=1 until the current transfer is complete (typically by waiting for - Transfer Complete bit). After Transfer Complete event, the software will set SBGR back to 0.\n\n

In case of the read transfer, the host stops after the next data block received from the card.
This uses the Read-Wait mechanism if it is enabled by SRS10.RWC, or stops the card clock (sdclk_s#) if Read-Wait is disabled.
\n\n

In the case of the write transfer, host stops after the last block written to the data buffer. The host sends all data already written to the internal data buffer before stopping the transfer.\n\n

In case of stopping non-DMA write transfer, the software will set this bit only at block gap (
block unit (SD mode)).

RW

0

15:13

BVS2


BVS2 - SD Bus Voltage Select for VDD2
\n\n
The field is used to configure VDD2 voltage level.\n
The state of this field directly drives s#_bus_volt port of the core.\n
000b - VDD2 is not supported\n
001b-011b - Reserved\n
100b - Reserved for 1.2V\n
101b - 1.8V (1.8V VDD Support in Capability registers need to be set)\n
110b-111b - Not used

RW

0x0

12

BP2


BP2 - SD Bus Power for VDD2
\n\n
This bit is used to enable (1) or disable (0) VDD2 supply.\n
The state of this bit directly drives s#_bus_pow2 port of the core.\n
The field is ignored in legacy mode.

RW

0

11:9

BVS


BVS - SD Bus Voltage Select\n\n
This field is used to configure VDD1 voltage level.The state of this field directly drives s#_bus_volt2 port of the core.\n
000b-100b - Reserved\n
101b - 1.8V (typical) for embedded\n
110b - 3.0V (typical)\n
111b - 3.3V (typical)\n
others - Reserved.

RW

0x0

8

BP


BP - SD Bus Power for VDD1\n\n
When set to 1, the VDD1 voltage is supplied to card/device. The state of this bit directly drives s#_bus_pow port of the core.\n
Setting bit to 0 cause that host stops driving SDCLK, CMD/DAT lines. If the device is connected to the host, lines go low before disabling VDD1.\n
The host will set this bit automatically to 0 when card is removed from the slot (i.e. after high to low transition on s#_sdcd_n pin).
This is to provide the hot removal support.

RW

0

7

CDSS


CDSS - Card Detect Signal Selection\n\n
A card detection mechanism will base on either s#_sdcd_n port or register value.\n
0 - s#_sdcd_n pin (normal mode)\n
1 - CDTL(SRS10.6) bit (testing mode)

RW

0

6

CDTL


CDTL - Card Detect Test Level\n\n
Designates card insertion status when SRS10.CDSS=1. Bit provided for test purposes.\n
0 - no card\n
1 - card inserted

RW

0

5

EDTW


EDTW - Extended Data Transfer Width\n\n
This bit is to enable/disable 8-bit DAT bus width mode.\n
0 - bus width selected by SRS10.DTW\n
1 - 8-bit mode enabled

RW

0

4:3

DMASEL


DMASEL - DMA Select\n\n
In this field the DMA mode can be selected. The field behaviour depends on the Host Controller Compatibility bit (SRS15.HV4E).\n
Host Controller version 3.00 compatible mode (SRS15.HV4E=0)\n
00b - SDMA mode\n
01b - Reserved\n
10b - ADMA2 (32-bit Address)\n
11b - ADMA2 (64-bit Address)\n\n

Host Controller version 4.00 compatibility mode (SRS15.HV4E=1)\n
00b - SDMA mode\n
01b - Not Used\n
10b - ADMA2 mode\n
11b - Reserved\n\n
The ADMA2 address bus width is configured by 64-bit Addressing bit in Host Controller 2 register when SRS15.HV4E=1.

RW

0x0

2

HSE


HSE - High Speed Enable (SD mode only)\n\n
Selects operating mode to Default Speed (HSE=0) or High Speed (HSE=1).\n
The maximum SD clock frequency is defined as 0-25MHz in the default speed mode, and 0-50MHz in the High Speed mode.

RW

0

1

DTW


DTW - Data Transfer Width (SD mode only)\n\n
Bit used to configure DAT bus width to 1 or 4.\n
0 - 1-bit mode\n
1 - 4-bit mode\n\n
This bit is ignored when the SRS10.EDTW is set 1 (8-bit mode selected).

RW

0

0

LEDC


LEDC - LED Control\n\n
State of this bit directly drives led port of the host in order to control the external LED diode.\n
LEDC=1 will switch LED on, while LEDC=0 will switch it off.\n
The software will switch LED on to caution the user not to remove the card while the transfer is in progress.

RW

0

 

EMMC_SD : SRS11

Address offset

0x22C

Physical address

0x2000 822C

Instance

EMMC_SD

Description

SRS11 - Host Control 2 (Clock, Timeout, Reset)

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:27

Reserved

 

RO
Rreturns0s

0x00

26

SRDAT


SRDAT - Software Reset For DAT Line (SD Mode only)\n\n
When set to 1, resets the logic related to the data path, including data buffers and the DMA logic.\n
The following registers and bits are cleared:\n
SRS08 register:\n
- Buffer\n\n

SRS09 register:\n
- Buffer Read Enable\n
- Buffer Write Enable\n
- Read Transfer Active\n
- Write Transfer Active\n
- DAT Line Active\n
- Command Inhibit\n\n

DATSRS10 register:\n
- Continue Request\n
- Stop At Block Gap Request\n\n

SRS12 register:\n
- Buffer Read Ready\n
- Buffer Write Ready\n
- DMA Interrupt\n
- Block Gap Event\n
- Transfer Complete\n\n

After completing the reset operation, SRS11.SRDAT bit is automatically cleared.
It takes some time to complete the reset operation, so the software will wait until SRS11.SRDAT=0, and continue the other operations only when SRS11.SRDAT=0.

RW
W1toSet

0

25

SRCMD


SRCMD - Software Reset For CMD Line (SD Mode only)\n\n
When set to 1, resets the logic related to the command generation and response checking.\n
The following registers and bits are cleared:\n
- SRS09 register: Command Inhibit CMD\n
- SRS12 register: Command Complete\n\n

After completing the reset operation, SRS11.SRCMD bit is automatically cleared.
It takes some time to complete the reset operation, so the software will wait until SRCMD=0, and continue the other operations only when SRS11.SRCMD=0.

RW
W1toSet

0

24

SRFA


SRFA - Software Reset For All\n\n
When set to 1, the entire slot is reset.After completing the reset operation, SRFA bit is automatically cleared. It takes some time to complete the reset operation, so the software will wait until SRFA=0, and continue the other operations only when SRFA=0.\n
Additionally, after SRFA, software should reset and reinitialize card inserted to the slot.\n
SD Card Power may be enabled 1 ms after this bit is cleared to ensure SD Card has been reset properly.

RW
W1toSet

0

23:20

Reserved

 

RO
Rreturns0s

0x0

19:16

DTCV


DTCV - Data Timeout Counter Value\n\n
This value determines the interval by which DAT line timeouts are detected.\n
The interval can be computed as below:\n
1111b - Reserved\n
1110b - t_sdmclk*2^(27+2)\n
1101b - t_sdmclk*2^(26+2)\n
...\n
0001b - t_sdmclk*2^(14+2)\n
0000b - t_sdmclk*2^(13+2)\n\n
Where t_sdmclk is the sdmclk clock periodRefer to the Data Timeout Error (SRS12.EDT) register for information on factors which generate data timeouts.

RW

0x0

15:8

SDCFSL


SDCFSL - SDCLK Frequency Select (lower part)\n\n
This register and SRS11.SDCFSH are used to calculate frequency of SDCLK clock.\n
The SDCLK frequency is calculated with following expressions:\n
- sdclk = sdmclk; when (N=0)\n
- sdclk = sdmclk/2N; when (N>0)\n\n
Variable N is concatenation of SRS11.SDCFSH and SRS11.SDCFSL.\n
The value of SDCFSL, SDCFSH registers can be changed only when SRS11.SDCE (SD Clock Enable)=0.

RW

0x00

7:6

SDCFSH

SDCFSH - SDCLK Frequency Select (higher part)\n\n
This register is an extension to SDCFSL.

RW

0x0

5:3

Reserved

 

RO
Rreturns0s

0x0

2

SDCE


SDCE - SD Clock Enable\n\n
When set to 1, SDCLK clock is enabled.\n
When cleared to 0, SDCLK clock is stopped.\n\n
The host clears SDCE automatically when card is removed from the slot (i.e. after the high to low transition on s#_sdcd_n pin).\n
The SDCLK clock should be stopped by the software when changing the clock divider (i.e. SDCE bit will be cleared before writing SRS11.SDCFSL, SRS11.SDCFSH).

RW

0

1

ICS


ICS - Internal Clock Stable\n\n
When read as 1, indicates that the clock on sdmclk pin of the host is stable after setting ICE to 1.\n
When read as 0, indicates that the clock is not stable yet (for example the external PLL that generates the clock is not yet locked).\n\n
The value of ICS is equal to the actual signal level on ics pin of the host. The user will connect ics to the external PLL if required.
Otherwise, ics should be connected directly to the ice output of the host.

RO

0

0

ICE


ICE - Internal Clock Enable\n\n
This field is designated to controls (enable/disable) external clock generator (e.g. PLL).
The ICE bits of every slot are logically OR-ed together and then drive the ice pin.
It means, the ice pin is 0 only when ICE in 0 for every slot implemented inside the host.\n
The ice pin is 1 if at least one of the ICE bits is set to 1.\n
When set to 0, the clock on sdmclk pin can be stopped externally.\n\n
If the sdmclk is stopped, then host goes to a very low power state.
The hosts registers are still operable (read and written operation are valid) even if the clock on sdmclk is stopped.\n
Setting of the ICE bit does not affect card detection. It means, the card detection works even if the clock on sdmclk is stopped.

RW

0

 

EMMC_SD : SRS12

Address offset

0x230

Physical address

0x2000 8230

Instance

EMMC_SD

Description

SRS12 - Error/Normal Interrupt Status

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:28

Reserved

 

RO
Rreturns0s

0x0

27

ERSP


ERSP - Response Error (SD Mode only)\n\n
Generated on error detection inside R1 or R5 response.\n
Errors will be checked only if RECE is set 1.

RW
W1toClr

0

26

Reserved

 

RO
Rreturns0s

0

25

EADMA


EADMA - ADMA Error\n\n
Generated when an error occurs during ADMA read or write transfer.\n
To resolve the cause of the error, the state of the ADMA engine at error occurrence is saved in ADMA Error Status register,
and the address of the descriptor processed at error occurrence is provided in ADMA System Address register.

RW
W1toClr

0

24

EAC


EAC - Auto CMD Error (SD mode only)\n\n
Generated when an error occurs during Auto CMD12/Auto CMD23 command transmission.\n
It indicates one of the following conditions:\n
- one of the bits in SRS15 register has changed from 0 to 1,\n
- Auto CMD12 is not executed due to the previous command error.

RW
W1toClr

0

23

ECL


ECL - Current Limit Error\n\n
Generated when host is not supplying power to SD card due to some failure.\n
The value is equal to the actual signal level on cle pin of the host.

RW
W1toClr

0

22

EDEB


EDEB - Data End Bit Error (SD mode only)\n\n
When set to 1, indicates detecting 0 at the end bit position of read data transfer which uses the DAT line, or at the end bit position of the Write CRC Status.

RW
W1toClr

0

21

EDCRC


EDCRC - Data CRC Error (SD mode only)\n\n
When set to 1, indicates detecting CRC error when transferring read data which uses the DAT line, or when detecting the Write CRC status having a value of other than 010.\n
This bit will be set to 1 immediately when conflict on CMD line detected.\n
The conflict is signalized by setting this bit and SRS12.EDT to 1.

RW
W1toClr

0

20

EDT


EDT - Data Timeout Error (SD mode only)\n\n
When set to 1, indicates detecting one of the following timeout conditions:\n
1. Busy timeout for the response with busy.\n
2. Busy timeout after Write CRC status.\n
3. Write CRC Status timeout.\n
4. Read data timeout.\n\n
This bit will be set to 1 immediately when conflict on CMD line conflict detected.

RW
W1toClr

0

19

ECI


ECI - Command Index Error (SD mode only)\n\n
When set to 1, indicates that Index error occurs in the command response.

RW
W1toClr

0

18

ECEB


ECEB - Command End Bit Error (SD mode only)\n\n
When set to 1, indicates detecting that the end bit of a command response is 0.

RW
W1toClr

0

17

ECCRC


ECCRC - Command CRC Error (SD mode only)\n\n
When set to 1, indicates that command CRC error has occurred.

RW
W1toClr

0

16

ECT


ECT - Command Timeout Error (SD mode only)\n\n
When set to 1, indicates that no response was returned within 64 SDCLK cycles from the end bit of the command.

RW
W1toClr

0

15

EINT


EINT - Error Interrupt\n\n
This bit is set if:
- any of bits in range SRS12[31:16] is set;
The software can check for an error by reading this single bit first.

RO

0

14

CQINT


CQINT - Command Queuing Interrupt\n\n
This interrupt is asserted when at least one of the bits in CQIS register is set.
This interrupt is cleared only by clearing the source interrupt in CQIS register.

RO

0

13:9

Reserved

 

RO
Rreturns0s

0x00

8

CINT


CINT - Card Interrupt\n\n
Indicates the card interrupt. CINT is not sampled by the card clock, so the interrupt can be detected even with SD clock stopped (SRS11.SDCE=0).
Also, CINT is not cleared by writing 1. Instead, the software will clear the source of an interrupt inside the card.After detecting the Card Interrupt,
the software will stop further interrupt detection by clearing SRS13.CINT_SE to 0.
Then, the software will clear the interrupt source inside the card by using the appropriate commands.
For the details, please refer to the SDIO Card Specification.\n
After clearing the interrupt source, the card will stop to drive the interrupt signal to the host.
Finally, when the interrupt service routine is finished, the interrupt detection can be enabled by setting SRS13.CINT_SE back to 1.

RO

0

7

CR


CR - Card Removal\n\n
Generated when the SRS09.CI bit changes from 1 to 0, indicating card removal event.\n
When read as 1, indicates that the card was removed from the slot.\n
When read as 0, indicates that the card state is stable (still inserted or removed) or that the debouncing is in progress.

RW
W1toClr

0

6

CIN


CIN - Card Insertion\n\n
Generated when the SRS09.CI bit changes from 0 to 1, indicating card insertion.\n
When read as 1, indicates that the card was inserted to the slot.\n
When read as 0, indicates that the card state is stable (still inserted or removed) or that the debouncing is in progress.

RW
W1toClr

0

5

BRR


BRR - Buffer Read Ready\n\n
Generated when the BRE changes from 0 to 1, indicating that the data buffer can be read by the software.

RW
W1toClr

0

4

BWR


BWR - Buffer Write Ready\n\n
Generated when the BWE changes from 0 to 1, indicating that the data buffer can be written by the software.

RW
W1toClr

0

3

DMAINT


DMAINT - DMA Interrupt\n\n
In SDMA mode, DMA interrupt is generated when the host controller detects the Host SDMA Buffer boundary.\n
In ADMA mode, DMA interrupt is generated when the INT flag is set in a currently serviced ADMA descriptor.

RW
W1toClr

0

2

BGE


BGE - Block Gap Event\n\n
Generated when the read/write transaction is stopped at a block gap as the result of setting SRS10.SBGR to 1.

RW
W1toClr

0

1

TC


TC - Transfer Complete\n\n
SD Mode:\n
Generated when the transfer which uses the DAT line is complete.
Transfers which use the DAT line include the read/write transfers and commands with a busy response.\n
In case of the read transfer, TC indicates that the entire data was transferred from the card to the host system (i.e. the host FIFO is empty after reading the last data block).\n
In case of the write transfer, TC indicates that the entire data was transferred from the host to the card (i.e. the host FIFO is empty after writing the last data block),
and the card accepted the data (busy signal released after the last block).
In the case of the command with a busy response, TC indicates that the busy signal is released after the response.

RW
W1toClr

0

0

CC


CC - Command Complete\n\n
Generated when the end bit of the response is received, except the response for Auto-CMD12 command. Auto-CMD12 command does not generate CC.

RW
W1toClr

0

 

EMMC_SD : SRS13

Address offset

0x234

Physical address

0x2000 8234

Instance

EMMC_SD

Description

SRS13 - Error/Normal Status Enable

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:28

Reserved

 

RO
Rreturns0s

0x0

27

ERSP_SE


ERSP_SE - Response Error Status Enable (SD mode only)\n\n
1 - enabled\n
0 - masked

RW

0

26

Reserved

 

RO
Rreturns0s

0

25

EADMA_SE


EADMA_SE - ADMA Error Status Enable (SD mode only)\n\n
1 - enabled\n
0 - masked

RW

0

24

EAC_SE


EAC_SE - Auto CMD Error Status Enable (SD mode only)\n\n
1 - enabled\n
0 - masked

RW

0

23

ECL_SE


ECL_SE - Current Limit Error Status Enable (SD mode only)\n\n
1 - enabled\n
0 - masked

RW

0

22

EDEB_SE


EDEB_SE - Data End Bit Error Status Enable (SD mode only)\n\n
1 - enabled\n
0 - masked

RW

0

21

EDCRC_SE


EDCRC_SE - Data CRC Error Status Enable (SD mode only)\n\n
1 - enabled\n
0 - masked

RW

0

20

EDT_SE


EDT_SE - Data Timeout Error Status Enable (SD mode only)\n\n
1 - enabled\n
0 - masked

RW

0

19

ECI_SE


ECI_SE - Command Index Error Status Enable (SD mode only)\n\n
1 - enabled\n
0 - masked

RW

0

18

ECEB_SE


ECEB_SE - Command End Bit Error Status Enable (SD mode only)\n\n
1 - enabled\n
0 - masked

RW

0

17

ECCRC_SE


ECCRC_SE - Command CRC Error Status Enable (SD mode only)\n\n
1 - enabled\n
0 - masked

RW

0

16

ECT_SE


ECT_SE - Command Timeout Error Status Enable (SD mode only)\n\n
1 - enabled\n
0 - masked

RW

0

15

Reserved

 

RO
Rreturns0s

0

14

CQINT_SE

CQINT_SE - Command Queuing Status Enable\n\n
1 - enabled\n
0 - masked

RW

0

13:9

Reserved

 

RO
Rreturns0s

0x00

8

CINT_SE

CINT_SE - Card Interrupt Status Enable\n\n
1 - enabled\n
0 - masked

RW

0

7

CR_SE

CR_SE - Card Removal Status Enable\n\n
1 - enabled\n
0 - masked

RW

0

6

CIN_SE

CIN_SE -Card Insertion Status Enable\n\n
1 - enabled\n
0 - masked

RW

0

5

BRR_SE

BRR_SE - Buffer Read Ready Status Enable\n\n
1 - enabled\n
0 - masked

RW

0

4

BWR_SE

BWR_SE - Buffer Write Ready Status Enable\n\n
1 - enabled\n
0 - masked

RW

0

3

DMAINT_SE


DMAINT_SE - DMA Interrupt Status Enable\n\n
1 - enabled\n
0 - masked

RW

0

2

BGE_SE


BGE_SE - Block Gap Event Status Enable\n\n
1 - enabled\n
0 - masked

RW

0

1

TC_SE


TC_SE - Transfer Complete Status Enable\n\n
1 - enabled\n
0 - masked

RW

0

0

CC_SE


CC_SE - Command Complete Status Enable\n\n
1 - enabled\n
0 - masked

RW

0

 

EMMC_SD : SRS14

Address offset

0x238

Physical address

0x2000 8238

Instance

EMMC_SD

Description

SRS14 - Error/Normal Signal Enable

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:28

Reserved

 

RO
Rreturns0s

0x0

27

ERSP_IE


ERSP_IE - Response Error Interrupt Enable\n\n
1 - enabled\n
0 - masked

RW

0

26

Reserved

 

RO
Rreturns0s

0

25

EADMA_IE


EADMA_IE - ADMA Error Interrupt Enable (SD mode only)\n\n
1 - enabled\n
0 - masked

RW

0

24

EAC_IE


EAC_IE - Auto CMD Error Interrupt Enable (SD mode only)\n\n
1 - enabled\n
0 - masked

RW

0

23

ECL_IE


ECL_IE - Current Limit Error Interrupt Enable (SD mode only)\n\n
1 - enabled\n
0 - masked

RW

0

22

EDEB_IE


EDEB_IE - Data End Bit Error Interrupt Enable (SD mode only)\n\n
1 - enabled\n
0 - masked

RW

0

21

EDCRC_IE


EDCRC_IE - Data CRC Error Interrupt Enable (SD mode only)\n\n
1 - enabled\n
0 - masked

RW

0

20

EDT_IE


EDT_IE - ata Timeout Error Interrupt Enable (SD mode only)\n\n
1 - enabled\n
0 - masked

RW

0

19

ECI_IE


ECI_IE - Command Index Error Interrupt Enable (SD mode only)\n\n
1 - enabled\n
0 - masked

RW

0

18

ECEB_IE


ECEB_IE - Command End Bit Error Interrupt Enable (SD mode only)\n\n
1 - enabled\n
0 - masked

RW

0

17

ECCRC_IE


ECCRC_IE - Command CRC Error Interrupt Enable (SD mode only)\n\n
1 - enabled\n
0 - masked

RW

0

16

ECT_IE


ECT_IE - Command Timeout Error Interrupt Enable (SD mode only)\n\n
1 - enabled\n
0 - masked

RW

0

15

Reserved

 

RO
Rreturns0s

0

14

CQINT_IE


CQINT_IE - Command Queuing - Interrupt Enable\n\n
1 - enabled\n
0 - masked

RW

0

13:9

Reserved

 

RO
Rreturns0s

0x00

8

CINT_IE


CINT_IE - Card Interrupt - Interrupt Enable\n\n
1 - enabled\n
0 - masked

RW

0

7

CR_IE


CR_IE - Card Removal Interrupt Enable\n\n
1 - enabled\n
0 - masked

RW

0

6

CIN_IE


CIN_IE - Card Insertion Interrupt Enable\n\n
1 - enabled\n
0 - masked

RW

0

5

BRR_IE


BRR_IE - Buffer Read Ready Interrupt Enable\n\n
1 - enabled\n
0 - masked

RW

0

4

BWR_IE


BWR_IE - Buffer Write Ready Interrupt Enable\n\n
1 - enabled\n
0 - masked

RW

0

3

DMAINT_IE


DMAINT_IE - DMA Interrupt Enable\n\n
1 - enabled\n
0 - masked

RW

0

2

BGE_IE


BGE_IE - Block Gap Event Interrupt Enable\n\n
1 - enabled\n
0 - masked

RW

0

1

TC_IE

TC_IE - Transfer Complete Interrupt Enable\n\n
1 - enabled\n
0 - masked

RW

0

0

CC_IE


CC_IE - Command Complete Interrupt Enable\n\n
1 - enabled\n
0 - masked

RW

0

 

EMMC_SD : SRS15

Address offset

0x23C

Physical address

0x2000 823C

Instance

EMMC_SD

Description

SRS15 - Host Control #2 / Auto CMD Error Status

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

PVE


PVE - Preset Value Enable\n\n
Setting this bit to 1 triggers an automatically update of SRS11.SDCFSL, SRS11.SDCFSH, SRS11.CGS, SRS15.DSS registers by the host.
Values for an update are taken from SRS24 - SRS27 and depends on SRS15.UMS.

RW

0

30

Reserved

 

RO
Rreturns0s

0

29

A64B


A64B - 64-bit Addressing\n\n
Specifies the addressing mode for DMA ending. This field is ignored when SRS15.HV4E=0.\n
0 - 32-bit addressing\n
1 - 64-bit addressing

RW

0

28

HV4E


HV4E - Host Version 4.00 Enable\n\n
Selects backward (SD Host 3.00 Version) compatibility mode or SD Host 4.00 Version mode.\n
0 - Version 3.00\n
1 - Version 4.00\n\n
The software can select system address register SRS00 (when this bit is 0) or SRS23 / SRS22 (when this bit is 1) for the SDMA engine.

RW

0

27:24

Reserved

 

RO
Rreturns0s

0x0

23

SCS


SCS - Sampling Clock Select (UHS-I only)\n\n
The host updates this bit when the tuning procedure is finished. If this bit is set to 1, this means that the tuning procedure is successfully completed.\n
Otherwise it means that procedure failed and clock tuning logic is disabled.\n
This bit is valid only after the procedure is finished.Writing 1 will be ignored.\n
Writing 0 will reset and disable tuning block.

RW
W0toClr

0

22

EXTNG


EXTNG - Execute Tuning (UHS-I only)\n\n
This register controls tuning procedure.\n
The procedure starts when the bit is set 1.\n
The procedure can be aborted when the bit is cleared.\n\n

The bit is read 1 while the procedure is in progress, and 0 when the procedure is finished.\n
SCS = 0, EXTNG = 0 - Reset and disable clock tuning logic\n
SCS = 0, EXTNG = 1 - Reset and restart tuning process\n
SCS = 1, EXTNG = 0 - Stop tuning procedure\n
SCS = 1, EXTNG = 1 - Start retuning (without clock tuning logic reset)

RW

0

21:20

DSS


DSS - Driver Strength Select (UHS-I only)\n\n
This bit controls the electric parameters of I/O driver. Up to 4 configurations of I/O driver settings can be implemented:\n
00 - Driver Type B (default)\n
01 - Driver Type A\n
10 - Driver Type C\n
11 - Driver Type D\n
The bit is ignored when the V18SE is cleared.

RW

0x0

19

V18SE


V18SE - 1.8V Signaling Enable (UHS-I only)\n\n
This bit controls I/O signaling voltage level.\n
If the bit is 0 or 1, the I/O uses the 3.3V or 1.8V signaling, respectively.\n
The SW driver will set this bit 1 when UHS-I mode.\n
Depend on the selected SD interface mode, the software will set this field as follows:\n
- 0 - for Default Speed, High Speed mode\n
- 1 - for UHS-I mode

RW

0

18:16

UMS


UMS - UHS Mode Select\n\n
Used to select one of UHS-I modes
.\n
000b - SDR12\n
001b - SDR25\n
010b - SDR50\n
011b - SDR104\n
100b - DDR50\n
101b - Reserved\n
110b - Reserved\n
111b - Reserved\n\n

The selected UHS-I mode (when value is in range 000b-100b) will be ignored when V18SE is 0.

RW

0x0

15:8

Reserved

 

RO
Rreturns0s

0x00

7

CNIACE


CNIACE - Command Not Issued By Auto CMD12 Error\n\n
When read as 1, the command was not executed by the Host due to the previous Auto CMD12 error.\n
When Host detects any error during Auto-CMD12, then all further command generation attempts are blocked. The software reset sequence is needed for recovery.\n
Bit is set to 0, when Auto CMD23 Error is detected (any of bits SRS15[4:1] is set).

RO

0

6

Reserved

 

RO
Rreturns0s

0

5

ACRE


ACRE - Auto CMD Response Error\n\n
When read as 1, means an error is detected in response to Auto Command.

RO

0

4

ACIE


ACIE - Auto CMD Index Error\n\n
When read as 1, means that Command Index error occurred in the Auto CMD response.

RO

0

3

ACEBE


ACEBE - Auto CMD End Bit Error\n\n
When read as 1, indicates that the end bit of the Auto-CMD response is 0.

RO

0

2

ACCE


ACCE - Auto CMD CRC Error\n\n
When read as 1, indicates a CRC error was detected in the Auto CMD response or conflict on the CMD lines is detected:\n
ACCE(SRS15.2) = 0, ACTE(SRS15.1) = 0 - No error\n
ACCE(SRS15.2) = 0, ACTE(SRS15.1) = 1 - Auto CMD Timeout error detected\n
ACCE(SRS15.2) = 1, ACTE(SRS15.1) = 0 - Auto CMD CRC error detected\n
ACCE(SRS15.2) = 1, ACTE(SRS15.1) = 1 - Conflict on the CMD line detected

RO

0

1

ACTE


ACTE - Auto CMD Timeout Error\n\n
When read as 1, indicates that there was no response within 64 SDCLK clock cycles from the end bit of the Auto CMD or conflict on the CMD lines is detected (see table in SRS15.ACCE field description).\n
If this bit is set to 1, the other error status bits (SRS15[4:2]) are meaningless.

RO

0

0

ACNE


ACNE - Auto CMD12 Not Executed\n\n
When set to 1, means the host cannot issue Auto CMD12 due to some error. If this bit is set to 1, other error status bits (SRS15[4:1]) are meaningless.\n
Bit is updated with 0, when Auto CMD23 Error is detected (any of bits SRS15[4:1] is set).

RO

0

 

EMMC_SD : SRS16

Address offset

0x240

Physical address

0x2000 8240

Instance

EMMC_SD

Description


SRS16 - Capabilities #1\n
HWINIT Register - Note this register is hardware initialized after reset and the value read back will match the IP configuration.

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:30

SLT


SLT - Slot Type\n\n
These bits inform what type of slot is provided.\n
00 - Removable Card Slot\n
01 - Embedded Slot for One Device\n
10 - Shared Bus Slot\n
11 - Reserved

RO

0x0

29

AIS


AIS - Asynchronous Interrupt Support\n\n
0 - not supported\n
1 - supported

RO

0

28

A64S


A64S - 64-bit System Addressing Support\n\n
0 - not supported\n
1 - supported

RO

1

27

SRS16_HWINIT1

HWINIT field

RO

0

26

VS18


VS18 - Voltage Support 1.8V\n\n
0 - not supported\n
1 - supported

RO

1

25

VS30


VS30 - Voltage Support 3.0V\n\n
0 - not supported\n
1 - supported

RO

1

24

VS33


VS33 - Voltage Support 3.3V\n\n
0 - not supported\n
1 - supported

RO

1

23

SRS


SRS - Suspend / Resume Support\n\n
0 - not supported\n
1 - supported\n\n
The host controller does not support Suspend / Resume mechanism.

RO

0

22

DMAS


DMAS - SDMA Support\n\n
0 - not supported\n
1 - supported\n
This bit defines whether the SDMA is supported in the slot.
There is a separate IMPLEMENT_DMA generic parameter which defines whether the DMA is physically implemented inside host.
If DMAS is set to 1 for any card slot, then the IMPLEMENT_DMA would also be set to 1.

RO

1

21

HSS


HSS - High Speed Support\n\n
0 - not supported\n
1 - supported

RO

1

20

ADMA1S


ADMA1S - ADMA1 Support\n\n
0 - not supported\n
1 - supported

RO

0

19

ADMA2S


ADMA2S - ADMA2 Support\n\n
0 - not supported\n
1 - supported

RO

1

18

EDS8


8EDS - 8-bit Embedded Device Support\n\n
0 - not supported\n
1 - supported\n
If this bit is 0, the SRS10.EDTW register is not implemented.

RO

0

17:16

MBL


SRS16.MBL - Max Block Length\n\n
This value indicates the maximum block size that can be transferred by the host. Three sizes can be defined as indicated below:\n
00b - 512 Bytes\n
01b - 1024 Bytes\n
10b - 2048 Bytes\n
11b - Reserved\n
The physical FIFO buffer size is defined by the separate FIFODEPTH generic parameter, and the physical buffer size is equal to 2^FIFODEPTH * 8 bytes.
Therefore, the Maximum Block Size defined by MBL will always be less or equal to the physical buffer size.

RO

0x2

15:8

BCSDCLK


BCSDCLK - Base Clock Frequency for SD Clock\n\n
Field defines the base clock frequency for the SD Clock in 1MHz units.
The base clock is the clock sourced to sdmclk pin of the host. The maximum clock frequency supported is between 10MHz to 255MHz.\n
If BCSDCLK = 0, the Host System has to obtain the clock information via another method (i.e. not defined by the specification).

RO

0xC8

7

TCU


TCU - Timeout Clock Unit\n\n
Field defines the frequency unit for the SRS16.TCF.\n
0 - kHz\n
1 - MHz

RO

1

6

SRS16_HWINIT0

HWINIT field

RO

0

5:0

TCF


TCF - Timeout Clock Frequency\n\n
Defines the base clock frequency used to detect Data Timeout Error.
The SRS16.TCU bit determines the unit used.\n
111111b - 63kHz(SRS16.TCU=0) or 63MHz(SRS16.TCU=1)\n
111110b - 63kHz(SRS16.TCU=0) or 63MHz(SRS16.TCU=1)\n
...\n
000001b - 1kHz(SRS16.TCU=0) or 1MHz(SRS16.TCU=1)\n
000000b - Host System has to obtain the clock information via another method (i.e. not defined by the spec).

RO

0x32

 

EMMC_SD : SRS17

Address offset

0x244

Physical address

0x2000 8244

Instance

EMMC_SD

Description

SRS17 - Capabilities #2HWINIT Register - Note this register is hardware initialized after reset and the value read back will match the IP configuration.

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:29

SRS17_HWINIT3

HWINIT field

RO

0x0

28

VDD2S


VDD2S - VDD2 Supported\n\n
Information about support or lack of support of optional VDD2.

RO

1

27:24

SRS17_HWINIT2

HWINIT field

RO

0x0

23:16

CLKMPR


CLKMPR - Clock Multiplier\n\n
This field is to be 0 (fixed), as the Clock Multiplier is not supported.

RO

0x00

15:14

RTNGM


RTNGM - Re-Tuning Modes\n\n
Depending on the retuning method, the some restrictions are assumed for the data length between re-tunings.\n
The core can work with supporting one of the three method:\n
0 - Mode1: The software driver will use timer to calculate when the re-tuning is to be rerun. The data length between operations is limited to the 4MB.\n
1 - Mode2: The driver will use either the re-tuning request (external input pin uhsi_retune_req is used for this purpose) or timer to predict when next retuning should be performed.
The data length between operations is limited to the 4MB.\n
2 - Mode3: This mode is similar to the mode2 with one exception. The core is able to perform auto retuning during the transmission, so data length limitation is not exists.
Mode 3 is currently not supported.The driver can configure the timer by getting the RTNGCNT.This field is to be 0 or 1, because the mode 3 is not supported.

RO

0x0

13

UTSM50


UTSM50 - Use Tuning for SDR50\n\n
1 - tuning operation is necessary in SDR50 mode\n
0 - tuning operation is not necessary in SDR50 mode

RO

0

12

SRS17_HWINIT1

HWINIT field

RO

0

11:8

RTNGCNT


RTNGCNT - Timer Count for Re-Tuning\n\n
These bits contain initial value for timer used to starting periodically Re-Tuning Operation.\n
0h - Re-Tuning Timer disabled\n
1h - 1 second\n
...\n
n - 2^(n-1) seconds\n
...\n
Bh - 1024 seconds\n
Eh-Ch - Reserved\n
Fh - Obtain this info in other way

RO

0x0

7

SRS17_HWINIT0

HWINIT field

RO

0

6

DRVD

DRVD - 1.8V Line Driver Type D Supported\n\n
1 - Driver Type D supported\n
0 - Driver Type D not supported

RO

1

5

DRVC

DRVC - 1.8V Line Driver Type C Supported\n\n
1 - Driver Type C supported\n
0 - Driver Type C not supported

RO

1

4

DRVA


DRVA - 1.8V Line Driver Type A Supported\n\n
1 - Driver Type A supported\n
0 - Driver Type A not supported

RO

1

3

UHSII


UHSII - UHS-II Supported\n\n
1 - UHS-II supported\n
0 - UHS-II not supported

RO

0

2

DDR50


DDR50 - DDR50 Supported\n\n
1 - DDR50 mode supported\n
0 - DDR50 mode not supported

RO

1

1

SDR104


SDR104 - SDR104 Supported\n\n
1 - SDR104 mode supported\n
0 - SDR104 mode not supported

RO

1

0

SDR50


SDR50 - SDR50 Supported\n\n
1 - SDR50 mode supported\n
0 - SDR50 mode not supported

RO

1

 

EMMC_SD : SRS18

Address offset

0x248

Physical address

0x2000 8248

Instance

EMMC_SD

Description


SRS18 - Capabilities #3HWINIT Register - Note this register is hardware initialized after reset and the value read back will match the IP configuration.

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:24

SRS18_HWINIT0

HWINIT field

RO

0x00

23:16

MC18


MC18 - Maximum Current for 1.8V\n\n
0 - Host System has to obtain the current value via another method\n
1 - 4 mA\n
2 - 8 mA\n
3 - 12 mA\n
...\n
255 - 1020 mA

RO

0x20

15:8

MC30


MC30 - Maximum Current for 3.0V\n\n
0 - Host System has to obtain the current value via another method\n
1 - 4 mA\n
2 - 8 mA\n
3 - 12 mA\n
...\n
255 - 1020 mA

RO

0x20

7:0

MC33


MC33 - Maximum Current for 3.3V\n\n
0 - Host System has to obtain the current value via another method\n
1 - 4 mA\n
2 - 8 mA\n
3 - 12 mA\n
...\n
255 - 1020 mA

RO

0x20

 

EMMC_SD : SRS19

Address offset

0x24C

Physical address

0x2000 824C

Instance

EMMC_SD

Description


SRS19 - Capabilities #4\n
HWINIT Register - Note this register is hardware initialized after reset and the value read back will match the IP configuration.

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:8

SRS19_HWINIT0

HWINIT field

RO

0x00 0000

7:0

MC18V2


MC18V2 - Maximum Current for 1.8V VDD2\n\n
0 - Host System has to obtain the current value via another method\n
1 - 4 mA\n
2 - 8 mA\n
3 - 12 mA\n
...\n
255 - 1020 mA

RO

0x20

 

EMMC_SD : SRS20

Address offset

0x250

Physical address

0x2000 8250

Instance

EMMC_SD

Description


SRS20 - Force Event\n\n
Each field of this register is related to the specific error status. Writing 1 to field will set the status error. This function is provided for SW debug purpose.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:28

Reserved

 

RO
Rreturns0s

0x0

27

ERESP_FE

ERESP_FE - Force Response Error Event

WO

0

26

ETUNE_FE

ETUNE_FE - Force Tuning Error Event

WO

0

25

EADMA_FE

EADMA_FE - Force ADMA Error Event

WO

0

24

EAC_FE

EAC_FE - Force Auto CMD Error Event

WO

0

23

ECL_FE

ECL_FE - Force Current Limit Error Event

WO

0

22

EDEB_FE

EDEB_FE - Force Data End Bit Error Event

WO

0

21

EDCRC_FE

EDCRC_FE - Force Data CRC Error Event

WO

0

20

EDT_FE

EDT_FE - Force Data Timeout Error Event

WO

0

19

ECI_FE

ECI_FE - Force Command Index Error Event

WO

0

18

ECEB_FE

ECEB_FE - Force Command End Bit Error Event

WO

0

17

ECCRC_FE

ECCRC_FE - Force Command CRC Error Event

WO

0

16

ECT_FE

ECT_FE - Force Command Timeout Error Event

WO

0

15:8

Reserved

 

RO
Rreturns0s

0x00

7

CNIACE_FE

CNIACE_FE - Force Command Not Issued By Auto CMD12 Error Event

WO

0

6:5

Reserved

 

RO
Rreturns0s

0x0

4

ACIE_FE

ACIE_FE - Force Auto CMD Index Error Event

WO

0

3

ACEBE_FE

ACEBE_FE - Force Auto CMD End Bit Error Event

WO

0

2

ACCE_FE

ACCE_FE - Force Auto CMD CRC Error Event

WO

0

1

ACTE_FE

ACTE_FE - Force Auto CMD Timeout Error Event

WO

0

0

ACNE_FE

ACNE_FE - Force Auto CMD12 Not Executed Event

WO

0

 

EMMC_SD : SRS21

Address offset

0x254

Physical address

0x2000 8254

Instance

EMMC_SD

Description

SRS21 - ADMA Error Status

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2

EADMAL


EADMAL - ADMA Length Mismatch Error\n\n
This bit is set when:\n
- total data length specified in ADMA descriptors is different from that specified by the Block Count and Block Length fields (if Block Count Enable is set).\n
- total data length cannot be divided into complete blocks of specified length (if Block Count Enable is not set).

RO

0

1:0

EADMAS


EADMAS - ADMA Error State\n\n
The value of this field reflects the state of the ADMA state machine. The possible values are:\n
00b - ST_STOP (ADMA Stopped)\n
01b - ST_FDS (Fetching descriptor)\n
10b - not used\n
11b - ST_TRF (Transfer data)

RO

0x0

 

EMMC_SD : SRS22

Address offset

0x258

Physical address

0x2000 8258

Instance

EMMC_SD

Description

SRS22 ADMA/SDMA System Address 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

DMASA1


DMASA1 - ADMA System Address\n\n
This field contains the physical address of the currently processed ADMA descriptor or SDMA system address.
The Host Driver will set this register with the descriptors table base address before it starts the ADMA transfers.
The Host Driver should not write this register while the data transfer is active.\n
While the ADMA engine is processing the descriptors list, the ADMASA value is always incremented to point the next descriptor to be fetched.\n
If the ADMA Error occurs, the register holds the descriptor address depending on the ADMA Error State (SRS21.EADMAS) register value, as listed in the table below:\n
00b - Points next of the error descriptor\n
01b - Points the error descriptor\n
10b - not used\n
11b - Points next of the error descriptor\n\n

The host ADMA engine ignores 2 or 3 least significant bits in this register when the 32-bit or 64-bit addressing is active, respectively.\n
If SRS15.HV4E is set 1 and SDMA engine is selected, this field is used instead of SRS00 to define system memory address.
This register incremented and points to the next memory location that will be accessed.

RW

0x0000 0000

 

EMMC_SD : SRS23

Address offset

0x25C

Physical address

0x2000 825C

Instance

EMMC_SD

Description

SRS23 ADMA/SDMA System Address 2

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

DMASA2


DMASA2 - ADMA System Address #2\n\n
In ADMA mode, if 64-bit addressing is enabled (SRS15.A64B=1), this field holds bits 63-32 of the physical address pointing on ADMA descriptor table.\n
In SDMA mode, if host compatibility with version 4.x and 64-bit addressing are enabled (SRS15.HV4E=1 and SRS15.A64B=1), this field holds bits 63-32 of system address.

RW

0x0000 0000

 

EMMC_SD : SRS24

Address offset

0x260

Physical address

0x2000 8260

Instance

EMMC_SD

Description


SRS24 - Preset Value (Default Speed)\n\n
SRS24[31:16] - Default Speed if:\n
SRS15.V18SE=0\n
SRS10.HSE=0\n\n

HWINIT Register - Note this register is hardware initialized after reset and the value read back will match the IP configuration.

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:30

SRS24_DSSPV_31_30


DSSPV## - Driver Strength Select - Preset Value\n\n
This field can be used by the software to update SRS15.DSS.

RO

0x0

29:26

SRS24_HWINIT1

HWINIT field

RO

0x0

25:16

SRS24_SDCFSPV_25_16


SDCFSPV## - SDCLK Clock Frequency Select - Preset Value\n\n
This field can be used by the software to update SRS11.SDCFSH and SRS11.SDCFSL.

RO

0x004

15:0

SRS24_HWINIT0

HWINIT field

RO

0x00FA

 

EMMC_SD : SRS25

Address offset

0x264

Physical address

0x2000 8264

Instance

EMMC_SD

Description


SRS25 - Preset Value (High Speed and SDR12)\n\n
SRS25[15:0] - High Speed if:\n
SRS15.V18SE=0\n
SRS.HSE=1\n\n

SRS25[31:16] - SDR12 if:\n
SRS15.V18SE=1\n
SRS15.UMS=000b\n\n

HWINIT Register - Note this register is hardware initialized after reset and the value read back will match the IP configuration.

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:30

SRS25_DSSPV_31_30


DSSPV## - Driver Strength Select - Preset Value\n\n
This field can be used by the software to update SRS15.DSS.

RO

0x0

29:26

SRS25_HWINIT1

HWINIT field

RO

0x0

25:16

SRS25_SDCFSPV_25_16


SDCFSPV## - SDCLK Clock Frequency Select - Preset Value\n\n
This field can be used by the software to update SRS11.SDCFSH and SRS11.SDCFSL.

RO

0x004

15:14

SRS25_DSSPV_15_14


DSSPV## - Driver Strength Select - Preset Value\n\n
This field can be used by the software to update SRS15.DSS.

RO

0x0

13:10

SRS25_HWINIT0

HWINIT field

RO

0x0

9:0

SRS25_SDCFSPV_09_00


SDCFSPV## - SDCLK Clock Frequency Select - Preset Value\n\n
This field can be used by the software to update SRS11.SDCFSH and SRS11.SDCFSL.

RO

0x002

 

EMMC_SD : SRS26

Address offset

0x268

Physical address

0x2000 8268

Instance

EMMC_SD

Description


SRS26 - Preset Value (SDR25 and SDR50)\n\n
SRS26[15:0] - SDR25 if:\n
SRS15.V18SE=1\n
SRS15.UMS=001b\n\n

SRS26[31:16] - SDR50 if:\n
SRS15.V18SE=1\n
SRS15.UMS=010b\n\n

HWINIT Register - Note this register is hardware initialized after reset and the value read back will match the IP configuration.

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:30

SRS26_DSSPV_31_30


DSSPV## - Driver Strength Select - Preset Value\n\n
This field can be used by the software to update SRS15.DSS.

RO

0x0

29:26

SRS26_HWINIT1

HWINIT field

RO

0x0

25:16

SRS26_SDCFSPV_25_16


SDCFSPV## - SDCLK Clock Frequency Select - Preset Value\n\n
This field can be used by the software to update SRS11.SDCFSH and SRS11.SDCFSL.

RO

0x001

15:14

SRS26_DSSPV_15_14


DSSPV## - Driver Strength Select - Preset Value\n\n
This field can be used by the software to update SRS15.DSS.

RO

0x0

13:11

SRS26_HWINIT0

HWINIT field

RO

0x0

10

SRS26_CGSPV_10


CGSPV## - Clock Generator Select - Preset Value\n\n
This field can be used by the software to update SRS11.CGS.

RO

0

9:0

SRS26_SDCFSPV_09_00


SDCFSPV## - SDCLK Clock Frequency Select - Preset Value\n\n
This field can be used by the software to update SRS11.SDCFSH and SRS11.SDCFSL.

RO

0x002

 

EMMC_SD : SRS27

Address offset

0x26C

Physical address

0x2000 826C

Instance

EMMC_SD

Description


SRS27 - Preset Value (SDR104 and DDR50)\n\n
SRS27[15:0] - SDR104 if:\n
SRS15.V18SE=1\n
SRS15.UMS=011b\n\n

SRS27[31:16] - DDR50 if:\n
SRS15.V18SE=1\n
SRS15.UMS=100b\n\n

HWINIT Register - Note this register is hardware initialized after reset and the value read back will match the IP configuration.

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:30

SRS27_DSSPV_31_30


DSSPV## - Driver Strength Select - Preset Value\n\n
This field can be used by the software to update SRS15.DSS.

RO

0x0

29:26

SRS27_HWINIT1

HWINIT field

RO

0x0

25:16

SRS27_SDCFSPV_25_16


SDCFSPV## - SDCLK Clock Frequency Select - Preset Value\n\n
This field can be used by the software to update SRS11.SDCFSH and SRS11.SDCFSL.

RO

0x002

15:14

SRS27_DSSPV_15_14


DSSPV## - Driver Strength Select - Preset Value\n\n
This field can be used by the software to update SRS15.DSS.

RO

0x0

13:10

SRS27_HWINIT0

HWINIT field

RO

0x0

9:0

SRS27_SDCFSPV_09_00


SDCFSPV## - SDCLK Clock Frequency Select - Preset Value\n\n
This field can be used by the software to update SRS11.SDCFSH and SRS11.SDCFSL.

RO

0x000

 

EMMC_SD : SRS29

Address offset

0x274

Physical address

0x2000 8274

Instance

EMMC_SD

Description


SRS29 - Preset Value for UHS-II\n\n
SRS29[15:0] - UHS-II if:\n
SRS15.V18SE=0\n
SRS15.UMS=111b\n\n

HWINIT Register - Note this register is hardware initialized after reset and the value read back will match the IP configuration.

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:16

SRS29_HWINIT1

HWINIT field

RO

0x0000

15:14

SRS29_DSSPV_15_14


DSSPV## - Driver Strength Select - Preset Value\n\n
This field can be used by the software to update SRS15.DSS.

RO

0x0

13:10

SRS29_HWINIT0

HWINIT field

RO

0x0

9:0

SRS29_SDCFSPV_09_00


SDCFSPV## - SDCLK Clock Frequency Select - Preset Value\n\n
This field can be used by the software to update SRS11.SDCFSH and SRS11.SDCFSL.

RO

0x000

 

EMMC_SD : CQRS00

Address offset

0x400

Physical address

0x2000 8400

Instance

EMMC_SD

Description

CQRS00 - Command Queuing Version

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

 

RO
Rreturns0s

0x0 0000

11:8

CQVN1


CQVN1 - eMMC Major Version Number\n\n
Major version number of supported eMMC standard - 5.

RO

0x5

7:4

CQVN2


CQVN2 - eMMC Minor Version Number\n\n
Minor version number of supported eMMC standard - 1.

RO

0x1

3:0

CQVN3


CQVN3 - eMMC Version Suffix\n\n
Suffix version number of supported eMMC standard - 0.

RO

0x0

 

EMMC_SD : CQRS01

Address offset

0x404

Physical address

0x2000 8404

Instance

EMMC_SD

Description

CQRS01 - Command Queuing Capabilities

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:16

Reserved

 

RO
Rreturns0s

0x0000

15:12

ITCFMUL

ITCFMUL - Internal Timer Clock Frequency Multiplier (ITCFMUL)\n\n
Defines multiplier of internal clock frequency for the coalescing timer and for the SQS polling period.\n
0 - 0.001 MHz\n
1 - 0.01 MHz\n
2 - 0.1 MHz\n
3 - 1 MHz\n
4 - 10 MHz\n\n

The ITCFMUL and ITCFVAL defines the clock frequency.

RO

0x0

11:10

Reserved

 

RO
Rreturns0s

0x0

9:0

ITCFVAL


ITCFVAL - Internal Timer Clock Frequency Value (ITCFVAL)\n\n
Value defines internal clock frequency for the coalescing timer and for the SQS polling period. The frequency is equal to ITCFMUL * ITCFVAL.

RO

0x000

 

EMMC_SD : CQRS02

Address offset

0x408

Physical address

0x2000 8408

Instance

EMMC_SD

Description

CQRS02 - Command Queuing Configuration

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:13

Reserved

 

RO
Rreturns0s

0x0 0000

12

CQDCE


CQDCE - Direct Command (DCMD) Enable\n\n
Process Task Descriptor for slot 31 as Data Transfer Task Descriptor (0) or Direct Command Task Descriptor (1).

RW

0

11:9

Reserved

 

RO
Rreturns0s

0x0

8

CQTDS


CQTDS - Task Descriptor\n\n
Size Expect 128 bit (1) or 64 bit (0) task descriptor. This setting can be changed only when Command Queuing is disabled (CQE = 0).

RW

0

7:1

Reserved

 

RO
Rreturns0s

0x00

0

CQE


CQE - Command Queuing Enable\n\n
Enables (1) or disables (0) the Command Queuing.
This bit can be enabled only when all previous transactions are completed. This bit can be cleared only when all tasks are completed or cleared.

RW

0

 

EMMC_SD : CQRS03

Address offset

0x40C

Physical address

0x2000 840C

Instance

EMMC_SD

Description

CQRS03 - Command Queuing Control

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:9

Reserved

 

RO
Rreturns0s

0x00 0000

8

CQCAT


CQCAT - Clear All Tasks\n\n
Clears (1) all active tasks in the host controller. Software has to poll this register until operation is completed (bit is automatically cleared).
Software can set this bit only when the CQ Engine is halted. Software has to clear all requested tasks in the eMMC device. Writing (0) has no effect.

RW
W1toSet

0

7:1

Reserved

 

RO
Rreturns0s

0x00

0

CQHLT


CQHLT - Halt CQ\n\n
Engine can be halted by writing this bit 1.
Any pending operation will be completed, and awaiting operation will be stopped. Once all tasks are completed or stopped this bit is set 1.
The host controller will not automatically start any new operation, but software can use SRS registers to issue any command directly bypassing CQE.
CQ Engine starts operation after being halted by writing 0 to this register. Writing 0 is ignored when CQ Engine is not halted.

RW

0

 

EMMC_SD : CQRS04

Address offset

0x410

Physical address

0x2000 8410

Instance

EMMC_SD

Description


CQRS04 - Command Queuing Interrupt Status\n
This register has several status bit related to specific interrupt event.
When even happened and related Command Queuing Interrupt Status Enable is set, the status bit is set to 1.
The bits can be cleared by S/W.\n
Write 0 clears bit.\n
Write 1 is ignored.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:4

Reserved

 

RO
Rreturns0s

0x000 0000

3

CQTCL


CQTCL - Task Cleared (TCL)\n\n
When task clear operation or clear individual task is completed, the CQE sets this bit to 1.

RW
W1toClr

0

2

CQREDI


CQREDI - Response Error Detected Interrupt (RED)\n\n
When an error is detected in the response received from eMMC device, the CQE sets this bit to 1.
S/W can select which bits are analyzed by selecting CQRMEM.

RW
W1toClr

0

1

CQTCC


CQTCC - Task Complete Interrupt (TCC)\n\n
CQE sets this bit when either a task with INT=1 is completed or Interrupt Coalescing reports interrupt.

RW
W1toClr

0

0

CQHAC


CQHAC - Halt Complete Interrupt (HAC)\n\n
CQE sets this bit when value of CQHLT changed from 0 to 1.

RW
W1toClr

0

 

EMMC_SD : CQRS05

Address offset

0x414

Physical address

0x2000 8414

Instance

EMMC_SD

Description


CQRS05 - Command Queuing Interrupt Status Enable\n\n
Statuses Enable bits enables interrupt sources. The status is enabled when bit is set 1 (S/W wrote 1 to the field).

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:4

Reserved

 

RO
Rreturns0s

0x000 0000

3

CQTCLST


CQTCLST - Task Cleared Status Enable (TCL)\n\n
Enables CQTCL register.

RW

0

2

CQREDST


CQREDST - Response Error Detected Status Enable (RED)\n\n
Enables CQREDI register.

RW

0

1

CQTCCST


CQTCCST - Task Complete Status Enable (TCC)\n\n
Enables CQHAC register.

RW

0

0

CQHACST


CQHACST - Halt Complete Status Enable (HAC)\n\n
Enables CQTCLST register.

RW

0

 

EMMC_SD : CQRS06

Address offset

0x418

Physical address

0x2000 8418

Instance

EMMC_SD

Description


CQRS06 - Command Queuing Interrupt Signal Enable\n
This register allows to turn on or turn off interrupt notification separately
for each bit of the Command Queuing Interrupt Status. When Interrupt status bit
is set 1 and related field in this register is set (S/W wrote 1 to the filed),
the Interrupt Status is reported on interrupt port.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:4

Reserved

 

RO
Rreturns0s

0x000 0000

3

CQTCLSI


CQTCLSI - Task Cleared Signal Enable (TCL)\n\n
Enables interrupt signaling from CQTCL register.

RW

0

2

CQREDSI


CQREDSI - Response Error Detected Signal Enable (TCC)\n\n
Enables interrupt signaling from CQREDI register.

RW

0

1

CQTCCSI


CQTCCSI - Task Complete Signal Enable (TCC)\n\n
Enables interrupt signaling from CQTCC register.

RW

0

0

CQHACSI


CQHACSI - Halt Complete Signal Enable (HAC)\n\n
Enables interrupt signaling from CQHLT register.

RW

0

 

EMMC_SD : CQRS07

Address offset

0x41C

Physical address

0x2000 841C

Instance

EMMC_SD

Description


CQRS07 - Interrupt Coalescing\n\n
This register allows to group a CQ transfer and report single interrupt for entire group of requested tasks.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

CQICED


CQICED - Interrupt Coalescing Enable/Disable\n\n
Enables coalescing mechanism allowing to generate coalescing interrupts.

RW

0

30:21

Reserved

 

RO
Rreturns0s

0x000

20

CQICSB


CQICSB - Interrupt Coalescing Status Bit (ICSB)\n\n
CQE sets this bit 1 when any task with INT=0 is completed.

RO

0

19:17

Reserved

 

RO
Rreturns0s

0x0

16

CQICCTR


CQICCTR - Counter and Timer Reset(ICCTR)\n\n
S/W resets interrupt coalescing timer and counter.

WO

0

15

CQICCTHWEN


CQICCTHWEN - Interrupt Coalescing Counter Threshold Write Enable (ICCTHWEN)\n\n
This is write enable for CQICCTH. When this bit is set 1, the field will be updated.

WO

0

14:13

Reserved

 

RO
Rreturns0s

0x0

12:8

CQICCTH


CQICCTH - Interrupt Coalescing Counter Threshold (ICCTH)\n\n
CQE increments internal counter when task with INT=0 is completed. When internal counter reaches this value the coalescing generates interrupt.
S/W can select treshold value in range 1 to 31.
S/W can disable internal counter and interrupt generation by setting this field to 0.

RW

0x00

7

CQICTOVALEN


CQICTOVALEN - Interrupt Coalescing Timeout Value Write Enable (ICTOVALWEN)\n\n
This is write enable for CQICTOVAL. When this bit is set 1, the field will be updated.

WO

0

6:0

CQICTOVAL


CQICTOVAL - Interrupt Coalescing Timeout Value (ICTOVAL)\n\n
CQE generates interrupt when internal counter reaches period defined in this field. The counter starts when first transfer with INT=0 is completed.
The counter increments each time when Internal Clock * 1024 period elapsed. S/W can disable this timer by setting this filed to 0.

RW

0x00

 

EMMC_SD : CQRS08

Address offset

0x420

Physical address

0x2000 8420

Instance

EMMC_SD

Description

CQRS08 - Command Queuing Task Descriptor List Base Address

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

CQTDLBA


CQTDLBA - Task Descriptor List Base Address (lower)\n\n
Base address (32 lower bits) of the Task Descriptor List.
S/W will write values aligned to 1kB boundary (lower 10 bits have to be 0).
The hardware ignores 10 lower bits.\n
S/W will update this register only when CQE is disabled.

RW

0x0000 0000

 

EMMC_SD : CQRS09

Address offset

0x424

Physical address

0x2000 8424

Instance

EMMC_SD

Description

CQRS09 - Command Queuing Task Descriptor List Base Address Upper 32 Bits

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

CQTDLBAU


CQTDLBAU - Task Descriptor List Base Address (upper)\n\n
Base address (32 upper bits) of the Task descriptor List.
This register is not used in 32 bit addressing mode (S/W does not change this value).
S/W will update this register only when CQE is disabled.

RW

0x0000 0000

 

EMMC_SD : CQRS10

Address offset

0x428

Physical address

0x2000 8428

Instance

EMMC_SD

Description


CQRS10 - Command Queuing Task Doorbell\n
CQ has 32 tasks have individual bits to start operation on desired task.
The S/W writes 1 on any position from 0 to 31 to start task 0 to 31.
The S/W can request more than one task in single write.
The CQ Engine process tasks in order they were requested:\n
- when more than one task is requested in single register write, the task with
lower number has higher priority over task with higher number\n
- task(s) requested in earlier register write has higher priority over task(s)
in later register write\n
The order of the tasks are maintained during all phases of transaction. If given
task is not ready for execution, the CQ Engine takes next task with highest
number.\n
CQ Engine needs several clock cycles to push requested in the single register
write Task Doorbell to queue. The slave interface ends write transfer as soon
all tasks are in the queue.\n
When S/W writes 0 to bit in this register, the related task won't start - this
value is ignored.\n
Task Doorbell bit remain 1 until task execution is completed, task is cleared by
Clear All Task or Clear Task with this number or CQ Engine is disabled (CQE=0).

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

CQTD31

CQTD31 - Command Queuing Task Doorbell #31

RW
W1toSet

0

30

CQTD30

CQTD30 - Command Queuing Task Doorbell #30

RW
W1toSet

0

29

CQTD29

CQTD29 - Command Queuing Task Doorbell #29

RW
W1toSet

0

28

CQTD28

CQTD28 - Command Queuing Task Doorbell #28

RW
W1toSet

0

27

CQTD27

CQTD27 - Command Queuing Task Doorbell #27

RW
W1toSet

0

26

CQTD26

CQTD26 - Command Queuing Task Doorbell #26

RW
W1toSet

0

25

CQTD25

CQTD25 - Command Queuing Task Doorbell #25

RW
W1toSet

0

24

CQTD24

CQTD24 - Command Queuing Task Doorbell #24

RW
W1toSet

0

23

CQTD23

CQTD23 - Command Queuing Task Doorbell #23

RW
W1toSet

0

22

CQTD22

CQTD22 - Command Queuing Task Doorbell #22

RW
W1toSet

0

21

CQTD21

CQTD21 - Command Queuing Task Doorbell #21

RW
W1toSet

0

20

CQTD20

CQTD20 - Command Queuing Task Doorbell #20

RW
W1toSet

0

19

CQTD19

CQTD19 - Command Queuing Task Doorbell #19

RW
W1toSet

0

18

CQTD18

CQTD18 - Command Queuing Task Doorbell #18

RW
W1toSet

0

17

CQTD17

CQTD17 - Command Queuing Task Doorbell #17

RW
W1toSet

0

16

CQTD16

CQTD16 - Command Queuing Task Doorbell #16

RW
W1toSet

0

15

CQTD15

CQTD15 - Command Queuing Task Doorbell #15

RW
W1toSet

0

14

CQTD14

CQTD14 - Command Queuing Task Doorbell #14

RW
W1toSet

0

13

CQTD13

CQTD13 - Command Queuing Task Doorbell #13

RW
W1toSet

0

12

CQTD12

CQTD12 - Command Queuing Task Doorbell #12

RW
W1toSet

0

11

CQTD11

CQTD11 - Command Queuing Task Doorbell #11

RW
W1toSet

0

10

CQTD10

CQTD10 - Command Queuing Task Doorbell #10

RW
W1toSet

0

9

CQTD09

CQTD09 - Command Queuing Task Doorbell #09

RW
W1toSet

0

8

CQTD08

CQTD08 - Command Queuing Task Doorbell #08

RW
W1toSet

0

7

CQTD07

CQTD07 - Command Queuing Task Doorbell #07

RW
W1toSet

0

6

CQTD06

CQTD06 - Command Queuing Task Doorbell #06

RW
W1toSet

0

5

CQTD05

CQTD05 - Command Queuing Task Doorbell #05

RW
W1toSet

0

4

CQTD04

CQTD04 - Command Queuing Task Doorbell #04

RW
W1toSet

0

3

CQTD03

CQTD03 - Command Queuing Task Doorbell #03

RW
W1toSet

0

2

CQTD02

CQTD02 - Command Queuing Task Doorbell #02

RW
W1toSet

0

1

CQTD01

CQTD01 - Command Queuing Task Doorbell #01

RW
W1toSet

0

0

CQTD00

CQTD00 - Command Queuing Task Doorbell #00

RW
W1toSet

0

 

EMMC_SD : CQRS11

Address offset

0x42C

Physical address

0x2000 842C

Instance

EMMC_SD

Description


CQRS11 - Task Complete Notification\n
32 bits related to 32 tasks. If task N is completed N bit is set 1.
Bit that is set 1 can be cleared by writing 1 to this bit.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

CQTCN31

CQTCN31 - Task Completion Notification #31

RW
W1toClr

0

30

CQTCN30

CQTCN30 - Task Completion Notification #30

RW
W1toClr

0

29

CQTCN29

CQTCN29 - Task Completion Notification #29

RW
W1toClr

0

28

CQTCN28

CQTCN28 - Task Completion Notification #28

RW
W1toClr

0

27

CQTCN27

CQTCN27 - Task Completion Notification #27

RW
W1toClr

0

26

CQTCN26

CQTCN26 - Task Completion Notification #26

RW
W1toClr

0

25

CQTCN25

CQTCN25 - Task Completion Notification #25

RW
W1toClr

0

24

CQTCN24

CQTCN24 - Task Completion Notification #24

RW
W1toClr

0

23

CQTCN23

CQTCN23 - Task Completion Notification #23

RW
W1toClr

0

22

CQTCN22

CQTCN22 - Task Completion Notification #22

RW
W1toClr

0

21

CQTCN21

CQTCN21 - Task Completion Notification #21

RW
W1toClr

0

20

CQTCN20

CQTCN20 - Task Completion Notification #20

RW
W1toClr

0

19

CQTCN19

CQTCN19 - Task Completion Notification #19

RW
W1toClr

0

18

CQTCN18

CQTCN18 - Task Completion Notification #18

RW
W1toClr

0

17

CQTCN17

CQTCN17 - Task Completion Notification #17

RW
W1toClr

0

16

CQTCN16

CQTCN16 - Task Completion Notification #16

RW
W1toClr

0

15

CQTCN15

CQTCN15 - Task Completion Notification #15

RW
W1toClr

0

14

CQTCN14

CQTCN14 - Task Completion Notification #14

RW
W1toClr

0

13

CQTCN13

CQTCN13 - Task Completion Notification #13

RW
W1toClr

0

12

CQTCN12

CQTCN12 - Task Completion Notification #12

RW
W1toClr

0

11

CQTCN11

CQTCN11 - Task Completion Notification #11

RW
W1toClr

0

10

CQTCN10

CQTCN10 - Task Completion Notification #10

RW
W1toClr

0

9

CQTCN09

CQTCN09 - Task Completion Notification #09

RW
W1toClr

0

8

CQTCN08

CQTCN08 - Task Completion Notification #08

RW
W1toClr

0

7

CQTCN07

CQTCN07 - Task Completion Notification #07

RW
W1toClr

0

6

CQTCN06

CQTCN06 - Task Completion Notification #06

RW
W1toClr

0

5

CQTCN05

CQTCN05 - Task Completion Notification #05

RW
W1toClr

0

4

CQTCN04

CQTCN04 - Task Completion Notification #04

RW
W1toClr

0

3

CQTCN03

CQTCN03 - Task Completion Notification #03

RW
W1toClr

0

2

CQTCN02

CQTCN02 - Task Completion Notification #02

RW
W1toClr

0

1

CQTCN01

CQTCN01 - Task Completion Notification #01

RW
W1toClr

0

0

CQTCN00

CQTCN00 - Task Completion Notification #00

RW
W1toClr

0

 

EMMC_SD : CQRS12

Address offset

0x430

Physical address

0x2000 8430

Instance

EMMC_SD

Description

CQRS12 - Device Queue Status

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

CQDQS


CQDQS - Device Queue Status\n\n
This register reflects to eMMC device status. Task N is ready for execution when bit N in this register is set to 1.
This register is updated each time response for SEND_QUEUE_STATUS (CMD13) is received.

RO

0x0000 0000

 

EMMC_SD : CQRS13

Address offset

0x434

Physical address

0x2000 8434

Instance

EMMC_SD

Description


CQRS13 - Device Pending Tasks\n
This register information which task is submitted to eMMC (CMD44 and CMD45 was sent)
and is not executed. Task N is submitted and not executed when N bit is set 1.
Bit N is cleared when task N is completed.

Type

RO

 

Bits

Field Name

Description

Type

Reset

31

CQDPT31

CQDPT31 - Device Pending Tasks #31

RO

0

30

CQDPT30

CQDPT30 - Device Pending Tasks #30

RO

0

29

CQDPT29

CQDPT29 - Device Pending Tasks #29

RO

0

28

CQDPT28

CQDPT28 - Device Pending Tasks #28

RO

0

27

CQDPT27

CQDPT27 - Device Pending Tasks #27

RO

0

26

CQDPT26

CQDPT26 - Device Pending Tasks #26

RO

0

25

CQDPT25

CQDPT25 - Device Pending Tasks #25

RO

0

24

CQDPT24

CQDPT24 - Device Pending Tasks #24

RO

0

23

CQDPT23

CQDPT23 - Device Pending Tasks #23

RO

0

22

CQDPT22

CQDPT22 - Device Pending Tasks #22

RO

0

21

CQDPT21

CQDPT21 - Device Pending Tasks #21

RO

0

20

CQDPT20

CQDPT20 - Device Pending Tasks #20

RO

0

19

CQDPT19

CQDPT19 - Device Pending Tasks #19

RO

0

18

CQDPT18

CQDPT18 - Device Pending Tasks #18

RO

0

17

CQDPT17

CQDPT17 - Device Pending Tasks #17

RO

0

16

CQDPT16

CQDPT16 - Device Pending Tasks #16

RO

0

15

CQDPT15

CQDPT15 - Device Pending Tasks #15

RO

0

14

CQDPT14

CQDPT14 - Device Pending Tasks #14

RO

0

13

CQDPT13

CQDPT13 - Device Pending Tasks #13

RO

0

12

CQDPT12

CQDPT12 - Device Pending Tasks #12

RO

0

11

CQDPT11

CQDPT11 - Device Pending Tasks #11

RO

0

10

CQDPT10

CQDPT10 - Device Pending Tasks #10

RO

0

9

CQDPT09

CQDPT09 - Device Pending Tasks #09

RO

0

8

CQDPT08

CQDPT08 - Device Pending Tasks #08

RO

0

7

CQDPT07

CQDPT07 - Device Pending Tasks #07

RO

0

6

CQDPT06

CQDPT06 - Device Pending Tasks #06

RO

0

5

CQDPT05

CQDPT05 - Device Pending Tasks #05

RO

0

4

CQDPT04

CQDPT04 - Device Pending Tasks #04

RO

0

3

CQDPT03

CQDPT03 - Device Pending Tasks #03

RO

0

2

CQDPT02

CQDPT02 - Device Pending Tasks #02

RO

0

1

CQDPT01

CQDPT01 - Device Pending Tasks #01

RO

0

0

CQDPT00

CQDPT00 - Device Pending Tasks #00

RO

0

 

EMMC_SD : CQRS14

Address offset

0x438

Physical address

0x2000 8438

Instance

EMMC_SD

Description


CQRS14 - Task Clear\n
S/W writes 1 to N bit of this register to clear task N.
Bit remains 1 until clear operation is completed. Once operations ends, the CQE clears this bit to 0.
The S/W has to ensure the CQ Engine is halted before clearing tasks.
The S/W can clear only single task. When any bit of this register is set, the
S/W has no to request new task clear. This operation clears only task in the Host Controller.
The S/W should take care about clearing task in the device.\n
Writing 0 to register is ignored.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

CQTC31

CQTC31 - Command Queuing Task Clear #31

RW
W1toSet

0

30

CQTC30

CQTC30 - Command Queuing Task Clear #30

RW
W1toSet

0

29

CQTC29

CQTC29 - Command Queuing Task Clear #29

RW
W1toSet

0

28

CQTC28

CQTC28 - Command Queuing Task Clear #28

RW
W1toSet

0

27

CQTC27

CQTC27 - Command Queuing Task Clear #27

RW
W1toSet

0

26

CQTC26

CQTC26 - Command Queuing Task Clear #26

RW
W1toSet

0

25

CQTC25

CQTC25 - Command Queuing Task Clear #25

RW
W1toSet

0

24

CQTC24

CQTC24 - Command Queuing Task Clear #24

RW
W1toSet

0

23

CQTC23

CQTC23 - Command Queuing Task Clear #23

RW
W1toSet

0

22

CQTC22

CQTC22 - Command Queuing Task Clear #22

RW
W1toSet

0

21

CQTC21

CQTC21 - Command Queuing Task Clear #21

RW
W1toSet

0

20

CQTC20

CQTC20 - Command Queuing Task Clear #20

RW
W1toSet

0

19

CQTC19

CQTC19 - Command Queuing Task Clear #19

RW
W1toSet

0

18

CQTC18

CQTC18 - Command Queuing Task Clear #18

RW
W1toSet

0

17

CQTC17

CQTC17 - Command Queuing Task Clear #17

RW
W1toSet

0

16

CQTC16

CQTC16 - Command Queuing Task Clear #16

RW
W1toSet

0

15

CQTC15

CQTC15 - Command Queuing Task Clear #15

RW
W1toSet

0

14

CQTC14

CQTC14 - Command Queuing Task Clear #14

RW
W1toSet

0

13

CQTC13

CQTC13 - Command Queuing Task Clear #13

RW
W1toSet

0

12

CQTC12

CQTC12 - Command Queuing Task Clear #12

RW
W1toSet

0

11

CQTC11

CQTC11 - Command Queuing Task Clear #11

RW
W1toSet

0

10

CQTC10

CQTC10 - Command Queuing Task Clear #10

RW
W1toSet

0

9

CQTC09

CQTC09 - Command Queuing Task Clear #09

RW
W1toSet

0

8

CQTC08

CQTC08 - Command Queuing Task Clear #08

RW
W1toSet

0

7

CQTC07

CQTC07 - Command Queuing Task Clear #07

RW
W1toSet

0

6

CQTC06

CQTC06 - Command Queuing Task Clear #06

RW
W1toSet

0

5

CQTC05

CQTC05 - Command Queuing Task Clear #05

RW
W1toSet

0

4

CQTC04

CQTC04 - Command Queuing Task Clear #04

RW
W1toSet

0

3

CQTC03

CQTC03 - Command Queuing Task Clear #03

RW
W1toSet

0

2

CQTC02

CQTC02 - Command Queuing Task Clear #02

RW
W1toSet

0

1

CQTC01

CQTC01 - Command Queuing Task Clear #01

RW
W1toSet

0

0

CQTC00

CQTC00 - Command Queuing Task Clear #00

RW
W1toSet

0

 

EMMC_SD : CQRS16

Address offset

0x440

Physical address

0x2000 8440

Instance

EMMC_SD

Description

CQRS16 - Send Status Configuration 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:20

Reserved

 

RO
Rreturns0s

0x000

19:16

CQSSCBC


CQSSCBC - Send Status Command Block Counter (CBC)\n\n
S/W can define if and when CQE sends SEND_QUEUE_STATUS (CMD13) command during data transfer.\n
When this register is set 0, the CQE does not send CMD13 during data transfer.
The value is 1, 2, or N means, the CQE sends CMD13 is transferred during last, one before last, or (N-1) before last block, respectively.\n
Accepted register value range is 0 to 15.

RW

0x0

15:0

CQSSCIT


CQSSCIT - Send Status Command Idle Timer (CIT)\n\n
When CQE is in idle, the host controller can poll device by sending SEND_QUEUE_STATUS (CMD13) with interval defined by this register.
Accepted register value is in range 1 to 65535.
The interval can be calculated as CQSSICT * internal clock period.

RW

0x0000

 

EMMC_SD : CQRS17

Address offset

0x444

Physical address

0x2000 8444

Instance

EMMC_SD

Description

CQRS17 - Send Status Configuration 2

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

Reserved

 

RO
Rreturns0s

0x0000

15:0

CQSQSR

CQSQSR - Send Queue Status RCA\n\n
S/W writes 16-bit RCA value which is send as an argument in SEND_QUEUE_STATUS (CMD13) command.

RW

0x0000

 

EMMC_SD : CQRS18

Address offset

0x448

Physical address

0x2000 8448

Instance

EMMC_SD

Description

CQRS18 - Command Response for Direct-Command Task

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

CQDCLR


CQDCLR - Direct Command Last Response\n\n
CQE holds the last DCMD command response.

RO

0x0000 0000

 

EMMC_SD : CQRS20

Address offset

0x450

Physical address

0x2000 8450

Instance

EMMC_SD

Description

CQRS20 - Response Mode Error Mask

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

CQRMEM


CQRMEM - Response Mode Error Mask\n\n
CQE is able to automatically detect errors in response.
The S/W defines which bits of the response need to be checked. All bits set to 1 (written by S/W) are analyzed.
The CQE reports Response Error Detected Interrupt (CQREDI) when N bit of CQRMEM is 1 and N bit of response is 1.
Response for SEND_QUEUE_STATUS (CMD13) automatically sent by CQE is ignored.

RW

0x0000 0000

 

EMMC_SD : CQRS21

Address offset

0x454

Physical address

0x2000 8454

Instance

EMMC_SD

Description

CQRS21 - Task Error Information

Type

RO

 

Bits

Field Name

Description

Type

Reset

31

CQDTEFV


CQDTEFV - Data Transfer Error Fields Valid\n\n
Host sets this bit to 1 when error is detected during data transfer.
Host clears this bit to 0 when error is detected and there is no active data transfer.

RO

0

30:29

Reserved

 

RO
Rreturns0s

0x0

28:24

CQDTETID


CQDTETID - Data Transfer Error Task ID\n\n
Host updates this field with ID of the task with active data transfer when error occurred during the data transfer.

RO

0x00

23:22

Reserved

 

RO
Rreturns0s

0x0

21:16

CQDTECI


CQDTECI - Data Transfer Error Command Index\n\n
Host updates this field with index of the data transfer command executed when error occurred during the data transfer.

RO

0x00

15

CQRMEFV


CQRMEFV - Response Mode Error Fields Valid\n\n
Host sets this bit to 1 when error is detected and command transaction is active. Host sets this bit to 0 when error is detected and command transaction is no active.

RO

0

14:13

Reserved

 

RO
Rreturns0s

0x0

12:8

CQRMETID


CQRMETID - Response Mode Error Task ID\n\n
Host updates this field with ID of the task with active command transfer when error occurred during the command transaction.

RO

0x00

7:6

Reserved

 

RO
Rreturns0s

0x0

5:0

CQRMECI


CQRMECI - Response Mode Error Command Index\n\n
Host updates this field with index of the command executed when error occurred during the command transaction.

RO

0x00

 

EMMC_SD : CQRS22

Address offset

0x458

Physical address

0x2000 8458

Instance

EMMC_SD

Description

CQRS22 - Command Response Index

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:6

Reserved

 

RO
Rreturns0s

0x000 0000

5:0

CQLCRI


CQLCRI - Last Command Response Index\n\n
Host updates this field with command index when response is received.

RO

0x00

 

EMMC_SD : CQRS23

Address offset

0x45C

Physical address

0x2000 845C

Instance

EMMC_SD

Description

CQRS23 - Command Response Argument

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

CQLCRA


CQLCRA - Last Command Response Argument\n\n
Host updates this field with command argument when response is received.

RO

0x0000 0000

 

EMMC_SD has no common memories.