This section
provides information on the EMMC_SD Module Instance. Each of the module
registers is described below.
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0001 0000 |
0x000 |
0x2000 8000 |
|
RW |
32 |
0x0000 0032 |
0x004 |
0x2000 8004 |
|
RW |
32 |
0x0003 0000 |
0x008 |
0x2000 8008 |
|
RW |
32 |
0x0000 0000 |
0x00C |
0x2000 800C |
|
RW |
32 |
0x0000 0000 |
0x010 |
0x2000 8010 |
|
RW |
32 |
0x0000 0000 |
0x018 |
0x2000 8018 |
|
RW |
32 |
0x0000 0000 |
0x01C |
0x2000 801C |
|
RO |
32 |
0x0000 0003 |
0x078 |
0x2000 8078 |
|
RO |
32 |
0x0411 0000 |
0x07C |
0x2000 807C |
|
RW |
32 |
0x0000 0000 |
0x080 |
0x2000 8080 |
|
RO |
32 |
0x0000 0000 |
0x084 |
0x2000 8084 |
|
RO |
32 |
0x0000 0000 |
0x088 |
0x2000 8088 |
|
RW |
32 |
0x0000 0000 |
0x08C |
0x2000 808C |
|
RO |
32 |
0x0000 0000 |
0x090 |
0x2000 8090 |
|
RW |
32 |
0x0000 0000 |
0x094 |
0x2000 8094 |
|
RW |
32 |
0x0000 0000 |
0x098 |
0x2000 8098 |
|
RO |
32 |
0x0003 0000 |
0xfc |
0x2000 80fc |
|
RW |
32 |
0x0000 0000 |
0x200 |
0x2000 8200 |
|
RW |
32 |
0x0000 0000 |
0x204 |
0x2000 8204 |
|
RW |
32 |
0x0000 0000 |
0x208 |
0x2000 8208 |
|
RW |
32 |
0x0000 0000 |
0x20C |
0x2000 820C |
|
RO |
32 |
0x0000 0000 |
0x210 |
0x2000 8210 |
|
RO |
32 |
0x0000 0000 |
0x214 |
0x2000 8214 |
|
RO |
32 |
0x0000 0000 |
0x218 |
0x2000 8218 |
|
RO |
32 |
0x0000 0000 |
0x21C |
0x2000 821C |
|
RW |
32 |
0x0000 0000 |
0x220 |
0x2000 8220 |
|
RO |
32 |
0x0000 0000 |
0x224 |
0x2000 8224 |
|
RW |
32 |
0x0000 0000 |
0x228 |
0x2000 8228 |
|
RW |
32 |
0x0000 0000 |
0x22C |
0x2000 822C |
|
RW |
32 |
0x0000 0000 |
0x230 |
0x2000 8230 |
|
RW |
32 |
0x0000 0000 |
0x234 |
0x2000 8234 |
|
RW |
32 |
0x0000 0000 |
0x238 |
0x2000 8238 |
|
RW |
32 |
0x0000 0000 |
0x23C |
0x2000 823C |
|
RO |
32 |
0x176A C8B2 |
0x240 |
0x2000 8240 |
|
RO |
32 |
0x1000 0077 |
0x244 |
0x2000 8244 |
|
RO |
32 |
0x0020 2020 |
0x248 |
0x2000 8248 |
|
RO |
32 |
0x0000 0020 |
0x24C |
0x2000 824C |
|
RW |
32 |
0x0000 0000 |
0x250 |
0x2000 8250 |
|
RO |
32 |
0x0000 0000 |
0x254 |
0x2000 8254 |
|
RW |
32 |
0x0000 0000 |
0x258 |
0x2000 8258 |
|
RW |
32 |
0x0000 0000 |
0x25C |
0x2000 825C |
|
RO |
32 |
0x0004 00FA |
0x260 |
0x2000 8260 |
|
RO |
32 |
0x0004 0002 |
0x264 |
0x2000 8264 |
|
RO |
32 |
0x0001 0002 |
0x268 |
0x2000 8268 |
|
RO |
32 |
0x0002 0000 |
0x26C |
0x2000 826C |
|
RO |
32 |
0x0000 0000 |
0x274 |
0x2000 8274 |
|
RO |
32 |
0x0000 0510 |
0x400 |
0x2000 8400 |
|
RO |
32 |
0x0000 0000 |
0x404 |
0x2000 8404 |
|
RW |
32 |
0x0000 0000 |
0x408 |
0x2000 8408 |
|
RW |
32 |
0x0000 0000 |
0x40C |
0x2000 840C |
|
RW |
32 |
0x0000 0000 |
0x410 |
0x2000 8410 |
|
RW |
32 |
0x0000 0000 |
0x414 |
0x2000 8414 |
|
RW |
32 |
0x0000 0000 |
0x418 |
0x2000 8418 |
|
RW |
32 |
0x0000 0000 |
0x41C |
0x2000 841C |
|
RW |
32 |
0x0000 0000 |
0x420 |
0x2000 8420 |
|
RW |
32 |
0x0000 0000 |
0x424 |
0x2000 8424 |
|
RW |
32 |
0x0000 0000 |
0x428 |
0x2000 8428 |
|
RW |
32 |
0x0000 0000 |
0x42C |
0x2000 842C |
|
RO |
32 |
0x0000 0000 |
0x430 |
0x2000 8430 |
|
RO |
32 |
0x0000 0000 |
0x434 |
0x2000 8434 |
|
RW |
32 |
0x0000 0000 |
0x438 |
0x2000 8438 |
|
RW |
32 |
0x0000 0000 |
0x440 |
0x2000 8440 |
|
RW |
32 |
0x0000 0000 |
0x444 |
0x2000 8444 |
|
RO |
32 |
0x0000 0000 |
0x448 |
0x2000 8448 |
|
RW |
32 |
0x0000 0000 |
0x450 |
0x2000 8450 |
|
RO |
32 |
0x0000 0000 |
0x454 |
0x2000 8454 |
|
RO |
32 |
0x0000 0000 |
0x458 |
0x2000 8458 |
|
RO |
32 |
0x0000 0000 |
0x45C |
0x2000 845C |
Address offset |
0x000 |
||
Physical address |
0x2000 8000 |
Instance |
EMMC_SD |
Description |
HRS00 - General Information Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
HRS00_HWINIT1 |
HWINIT field |
RO |
0x00 |
23:16 |
SAV |
|
RO |
0x01 |
15:1 |
HRS00_HWINIT0 |
HWINIT field |
RO |
0x0000 |
0 |
SWR |
|
RW |
0 |
Address offset |
0x004 |
||
Physical address |
0x2000 8004 |
Instance |
EMMC_SD |
Description |
HRS01 - Debounce Setting Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
HRS01_HWINIT0 |
HWINIT field |
RO |
0x00 |
23:0 |
DP |
|
RW |
0x00 0032 |
Address offset |
0x008 |
||
Physical address |
0x2000 8008 |
Instance |
EMMC_SD |
Description |
HRS02 - Bus Setting Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:18 |
HRS02_HWINIT1 |
HWINIT field |
RO |
0x0000 |
17:16 |
OTN |
|
RW |
0x3 |
15:4 |
HRS02_HWINIT0 |
HWINIT field |
RO |
0x000 |
3:0 |
PBL |
|
RW |
0x0 |
Address offset |
0x00C |
||
Physical address |
0x2000 800C |
Instance |
EMMC_SD |
Description |
|
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:20 |
Reserved |
|
RO |
0x000 |
19 |
AER_IEBS |
|
RW |
0 |
18 |
AER_IEBD |
|
RW |
0 |
17 |
AER_IERS |
|
RW |
0 |
16 |
AER_IERD |
|
RW |
0 |
15:12 |
Reserved |
|
RO |
0x0 |
11 |
AER_SENBS |
|
RW |
0 |
10 |
AER_SENBD |
|
RW |
0 |
9 |
AER_SENRS |
|
RW |
0 |
8 |
AER_SENRD |
|
RW |
0 |
7:4 |
Reserved |
|
RO |
0x0 |
3 |
AER_BS |
|
RW |
0 |
2 |
AER_BD |
|
RW |
0 |
1 |
AER_RS |
|
RW |
0 |
0 |
AER_RD |
|
RW |
0 |
Address offset |
0x010 |
||
Physical address |
0x2000 8010 |
Instance |
EMMC_SD |
Description |
|
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:27 |
Reserved |
|
RO |
0x00 |
26 |
UIS_ACK |
|
RO |
0 |
25 |
UIS_RD |
|
RW |
0 |
24 |
UIS_WR |
|
RW |
0 |
23:16 |
UIS_RDATA |
|
RO |
0x00 |
15:8 |
UIS_WDATA |
|
RW |
0x00 |
7:6 |
Reserved |
|
RO |
0x0 |
5:0 |
UIS_ADDR |
|
RW |
0x00 |
Address offset |
0x018 |
||
Physical address |
0x2000 8018 |
Instance |
EMMC_SD |
Description |
HRS06 - eMMC control registers |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:16 |
Reserved |
|
RO |
0x0000 |
15 |
ETR |
|
RW |
0 |
14 |
Reserved |
|
RO |
0 |
13:8 |
ETV |
|
RW |
0x00 |
7:3 |
Reserved |
|
RO |
0x00 |
2:0 |
EMM |
|
RW |
0x0 |
Address offset |
0x01C |
||
Physical address |
0x2000 801C |
Instance |
EMMC_SD |
Description |
HRS07 - IO Delay Information Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:21 |
Reserved |
|
RO |
0x000 |
20:16 |
ODELAY_VAL |
|
RW |
0x00 |
15:5 |
Reserved |
|
RO |
0x000 |
4:0 |
IDELAY_VAL |
|
RW |
0x00 |
Address offset |
0x078 |
||
Physical address |
0x2000 8078 |
Instance |
EMMC_SD |
Description |
|
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:2 |
Reserved |
|
RO |
0x0000 0000 |
1 |
HS400ESSUP |
High Speed 400 Enhance Strobe supported\n |
RO |
1 |
0 |
CQSUP |
Command Queuing supported\n |
RO |
1 |
Address offset |
0x07C |
||
Physical address |
0x2000 807C |
Instance |
EMMC_SD |
Description |
|
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:28 |
Reserved |
|
RO |
0x0 |
27:16 |
HOSTCTRLVER |
Host Controller Version\n |
RO |
0x411 |
15:8 |
Reserved |
|
RO |
0x00 |
7:0 |
HOSTFIXVER |
Fix Version Number\n |
RO |
0x00 |
Address offset |
0x080 |
||
Physical address |
0x2000 8080 |
Instance |
EMMC_SD |
Description |
HRS32 - FSM Monitor Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31 |
LOAD |
|
RW |
0 |
30:16 |
ADDR |
|
WO |
0x0000 |
15:0 |
DATA |
|
RO |
0x0000 |
Address offset |
0x084 |
||
Physical address |
0x2000 8084 |
Instance |
EMMC_SD |
Description |
HRS33 - Tune Status 0 Register |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
STAT0 |
|
RO |
0x0000 0000 |
Address offset |
0x088 |
||
Physical address |
0x2000 8088 |
Instance |
EMMC_SD |
Description |
HRS34 - Tune Status 1 Register |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
Reserved |
|
RO |
0x00 0000 |
7:0 |
STAT1 |
|
RO |
0x00 |
Address offset |
0x08C |
||
Physical address |
0x2000 808C |
Instance |
EMMC_SD |
Description |
HRS35 - Tune Debug Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31 |
TFR |
|
RW |
0 |
30:22 |
Reserved |
|
RO |
0x000 |
21:16 |
TFV |
|
RW |
0x00 |
15:6 |
Reserved |
|
RO |
0x000 |
5:0 |
TVAL |
|
RO |
0x00 |
Address offset |
0x090 |
||
Physical address |
0x2000 8090 |
Instance |
EMMC_SD |
Description |
HRS36 - Boot Status Register |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:6 |
Reserved |
|
RO |
0x000 0000 |
5 |
BOOT_EDE |
Boot Error - End Bit Error |
RO |
0 |
4 |
BOOT_EDC |
Boot Error - Data CRC Error |
RO |
0 |
3 |
BOOT_EDT |
Boot Error - Data Timeout Error |
RO |
0 |
2 |
BOOT_EAI |
Boot Error - Invalid Acknowledge Error |
RO |
0 |
1 |
BOOT_EAT |
Boot Error - Acknowledge Timeout Error |
RO |
0 |
0 |
BOOT_ACT |
|
RO |
0 |
Address offset |
0x094 |
||
Physical address |
0x2000 8094 |
Instance |
EMMC_SD |
Description |
HRS37 - Read block gap coefficient interface mode select |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:6 |
Reserved |
|
RO |
0x000 0000 |
5:0 |
RGB_COEFF_IFM |
|
RW |
0x00 |
Address offset |
0x098 |
||
Physical address |
0x2000 8098 |
Instance |
EMMC_SD |
Description |
HRS38 - Read block gap coefficient |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
Reserved |
|
RO |
0x000 0000 |
3:0 |
RGB_COEFF |
|
RW |
0x0 |
Address offset |
0xfc |
||
Physical address |
0x2000 80fc |
Instance |
EMMC_SD |
Description |
CRS63 - Host Controller Version/Slot Interrupt Status |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
CRS63_HWINIT1 |
HWINIT field |
RO |
0x00 |
23:16 |
SVN |
|
RO |
0x03 |
15:8 |
CRS63_HWINIT0 |
HWINIT field |
RO |
0x00 |
7:0 |
ISES |
|
RO |
0x00 |
Address offset |
0x200 |
||
Physical address |
0x2000 8200 |
Instance |
EMMC_SD |
Description |
SRS00 - SDMA System Address / Argument 2 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
SAAR |
|
RW |
0x0000 0000 |
Address offset |
0x204 |
||
Physical address |
0x2000 8204 |
Instance |
EMMC_SD |
Description |
SRS01 - Block Size / Block Count |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:16 |
BCCT |
|
RW |
0x0000 |
15 |
Reserved |
|
RO |
0 |
14:12 |
SDMABB |
|
RW |
0x0 |
11:0 |
TBS |
|
RW |
0x000 |
Address offset |
0x208 |
||
Physical address |
0x2000 8208 |
Instance |
EMMC_SD |
Description |
SRS02 - Argument 1 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
ARG1 |
|
RW |
0x0000 0000 |
Address offset |
0x20C |
||
Physical address |
0x2000 820C |
Instance |
EMMC_SD |
Description |
SRS03 - Command/Transfer Mode |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:30 |
Reserved |
|
RO |
0x0 |
29:24 |
CIDX |
|
RW |
0x00 |
23:22 |
CT |
|
RW |
0x0 |
21 |
DPS |
|
RW |
0 |
20 |
CICE |
|
RW |
0 |
19 |
CRCCE |
|
RW |
0 |
18 |
Reserved |
|
RO |
0 |
17:16 |
RTS |
|
RW |
0x0 |
15:9 |
Reserved |
|
RO |
0x00 |
8 |
RID |
|
RW |
0 |
7 |
RECE |
|
RW |
0 |
6 |
RECT |
|
RW |
0 |
5 |
MSBS |
|
RW |
0 |
4 |
DTDS |
|
RW |
0 |
3:2 |
ACE |
|
RW |
0x0 |
1 |
BCE |
|
RW |
0 |
0 |
DMAE |
|
RW |
0 |
Address offset |
0x210 |
||
Physical address |
0x2000 8210 |
Instance |
EMMC_SD |
Description |
|
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RESP1 |
RESP1 - Response Register #1 |
RO |
0x0000 0000 |
Address offset |
0x214 |
||
Physical address |
0x2000 8214 |
Instance |
EMMC_SD |
Description |
|
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RESP2 |
RESP2 - Response Register #2 |
RO |
0x0000 0000 |
Address offset |
0x218 |
||
Physical address |
0x2000 8218 |
Instance |
EMMC_SD |
Description |
|
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RESP3 |
RESP3 - Response Register #3 |
RO |
0x0000 0000 |
Address offset |
0x21C |
||
Physical address |
0x2000 821C |
Instance |
EMMC_SD |
Description |
|
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RESP4 |
RESP4 - Response Register #4 |
RO |
0x0000 0000 |
Address offset |
0x220 |
||
Physical address |
0x2000 8220 |
Instance |
EMMC_SD |
Description |
SRS08 - Data Buffer |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
BDP |
|
RW |
0x0000 0000 |
Address offset |
0x224 |
||
Physical address |
0x2000 8224 |
Instance |
EMMC_SD |
Description |
SRS09 - Present State Register |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:25 |
Reserved |
|
RO |
0x00 |
24 |
CMDSL |
|
RO |
0 |
23:20 |
DATSL1 |
|
RO |
0x0 |
19 |
WPSL |
|
RO |
0 |
18 |
CDSL |
|
RO |
0 |
17 |
CSS |
|
RO |
0 |
16 |
CI |
|
RO |
0 |
15:12 |
Reserved |
|
RO |
0x0 |
11 |
BRE |
|
RO |
0 |
10 |
BWE |
|
RO |
0 |
9 |
RTA |
|
RO |
0 |
8 |
WTA |
|
RO |
0 |
7:4 |
DATSL2 |
|
RO |
0x0 |
3 |
Reserved |
|
RO |
0 |
2 |
DLA |
|
RO |
0 |
1 |
CIDAT |
|
RO |
0 |
0 |
CICMD |
|
RO |
0 |
Address offset |
0x228 |
||
Physical address |
0x2000 8228 |
Instance |
EMMC_SD |
Description |
SRS10 - Host Control 1 (General / Power / Block-Gap /
Wake-Up) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:27 |
Reserved |
|
RO |
0x00 |
26 |
WORM |
|
RW |
0 |
25 |
WOIS |
|
RW |
0 |
24 |
WOIQ |
|
RW |
0 |
23:20 |
Reserved |
|
RO |
0x0 |
19 |
IBG |
|
RW |
0 |
18 |
RWC |
|
RW |
0 |
17 |
CREQ |
|
RW |
0 |
16 |
SBGR |
|
RW |
0 |
15:13 |
BVS2 |
|
RW |
0x0 |
12 |
BP2 |
|
RW |
0 |
11:9 |
BVS |
|
RW |
0x0 |
8 |
BP |
|
RW |
0 |
7 |
CDSS |
|
RW |
0 |
6 |
CDTL |
|
RW |
0 |
5 |
EDTW |
|
RW |
0 |
4:3 |
DMASEL |
|
RW |
0x0 |
2 |
HSE |
|
RW |
0 |
1 |
DTW |
|
RW |
0 |
0 |
LEDC |
|
RW |
0 |
Address offset |
0x22C |
||
Physical address |
0x2000 822C |
Instance |
EMMC_SD |
Description |
SRS11 - Host Control 2 (Clock, Timeout, Reset) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:27 |
Reserved |
|
RO |
0x00 |
26 |
SRDAT |
|
RW |
0 |
25 |
SRCMD |
|
RW |
0 |
24 |
SRFA |
|
RW |
0 |
23:20 |
Reserved |
|
RO |
0x0 |
19:16 |
DTCV |
|
RW |
0x0 |
15:8 |
SDCFSL |
|
RW |
0x00 |
7:6 |
SDCFSH |
SDCFSH - SDCLK Frequency Select (higher part)\n\n |
RW |
0x0 |
5:3 |
Reserved |
|
RO |
0x0 |
2 |
SDCE |
|
RW |
0 |
1 |
ICS |
|
RO |
0 |
0 |
ICE |
|
RW |
0 |
Address offset |
0x230 |
||
Physical address |
0x2000 8230 |
Instance |
EMMC_SD |
Description |
SRS12 - Error/Normal Interrupt Status |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:28 |
Reserved |
|
RO |
0x0 |
27 |
ERSP |
|
RW |
0 |
26 |
Reserved |
|
RO |
0 |
25 |
EADMA |
|
RW |
0 |
24 |
EAC |
|
RW |
0 |
23 |
ECL |
|
RW |
0 |
22 |
EDEB |
|
RW |
0 |
21 |
EDCRC |
|
RW |
0 |
20 |
EDT |
|
RW |
0 |
19 |
ECI |
|
RW |
0 |
18 |
ECEB |
|
RW |
0 |
17 |
ECCRC |
|
RW |
0 |
16 |
ECT |
|
RW |
0 |
15 |
EINT |
|
RO |
0 |
14 |
CQINT |
|
RO |
0 |
13:9 |
Reserved |
|
RO |
0x00 |
8 |
CINT |
|
RO |
0 |
7 |
CR |
|
RW |
0 |
6 |
CIN |
|
RW |
0 |
5 |
BRR |
|
RW |
0 |
4 |
BWR |
|
RW |
0 |
3 |
DMAINT |
|
RW |
0 |
2 |
BGE |
|
RW |
0 |
1 |
TC |
|
RW |
0 |
0 |
CC |
|
RW |
0 |
Address offset |
0x234 |
||
Physical address |
0x2000 8234 |
Instance |
EMMC_SD |
Description |
SRS13 - Error/Normal Status Enable |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:28 |
Reserved |
|
RO |
0x0 |
27 |
ERSP_SE |
|
RW |
0 |
26 |
Reserved |
|
RO |
0 |
25 |
EADMA_SE |
|
RW |
0 |
24 |
EAC_SE |
|
RW |
0 |
23 |
ECL_SE |
|
RW |
0 |
22 |
EDEB_SE |
|
RW |
0 |
21 |
EDCRC_SE |
|
RW |
0 |
20 |
EDT_SE |
|
RW |
0 |
19 |
ECI_SE |
|
RW |
0 |
18 |
ECEB_SE |
|
RW |
0 |
17 |
ECCRC_SE |
|
RW |
0 |
16 |
ECT_SE |
|
RW |
0 |
15 |
Reserved |
|
RO |
0 |
14 |
CQINT_SE |
CQINT_SE - Command Queuing Status Enable\n\n |
RW |
0 |
13:9 |
Reserved |
|
RO |
0x00 |
8 |
CINT_SE |
CINT_SE - Card Interrupt Status Enable\n\n |
RW |
0 |
7 |
CR_SE |
CR_SE - Card Removal Status Enable\n\n |
RW |
0 |
6 |
CIN_SE |
CIN_SE -Card Insertion Status Enable\n\n |
RW |
0 |
5 |
BRR_SE |
BRR_SE - Buffer Read Ready Status Enable\n\n |
RW |
0 |
4 |
BWR_SE |
BWR_SE - Buffer Write Ready Status Enable\n\n |
RW |
0 |
3 |
DMAINT_SE |
|
RW |
0 |
2 |
BGE_SE |
|
RW |
0 |
1 |
TC_SE |
|
RW |
0 |
0 |
CC_SE |
|
RW |
0 |
Address offset |
0x238 |
||
Physical address |
0x2000 8238 |
Instance |
EMMC_SD |
Description |
SRS14 - Error/Normal Signal Enable |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:28 |
Reserved |
|
RO |
0x0 |
27 |
ERSP_IE |
|
RW |
0 |
26 |
Reserved |
|
RO |
0 |
25 |
EADMA_IE |
|
RW |
0 |
24 |
EAC_IE |
|
RW |
0 |
23 |
ECL_IE |
|
RW |
0 |
22 |
EDEB_IE |
|
RW |
0 |
21 |
EDCRC_IE |
|
RW |
0 |
20 |
EDT_IE |
|
RW |
0 |
19 |
ECI_IE |
|
RW |
0 |
18 |
ECEB_IE |
|
RW |
0 |
17 |
ECCRC_IE |
|
RW |
0 |
16 |
ECT_IE |
|
RW |
0 |
15 |
Reserved |
|
RO |
0 |
14 |
CQINT_IE |
|
RW |
0 |
13:9 |
Reserved |
|
RO |
0x00 |
8 |
CINT_IE |
|
RW |
0 |
7 |
CR_IE |
|
RW |
0 |
6 |
CIN_IE |
|
RW |
0 |
5 |
BRR_IE |
|
RW |
0 |
4 |
BWR_IE |
|
RW |
0 |
3 |
DMAINT_IE |
|
RW |
0 |
2 |
BGE_IE |
|
RW |
0 |
1 |
TC_IE |
TC_IE - Transfer Complete Interrupt Enable\n\n |
RW |
0 |
0 |
CC_IE |
|
RW |
0 |
Address offset |
0x23C |
||
Physical address |
0x2000 823C |
Instance |
EMMC_SD |
Description |
SRS15 - Host Control #2 / Auto CMD Error Status |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31 |
PVE |
|
RW |
0 |
30 |
Reserved |
|
RO |
0 |
29 |
A64B |
|
RW |
0 |
28 |
HV4E |
|
RW |
0 |
27:24 |
Reserved |
|
RO |
0x0 |
23 |
SCS |
|
RW |
0 |
22 |
EXTNG |
|
RW |
0 |
21:20 |
DSS |
|
RW |
0x0 |
19 |
V18SE |
|
RW |
0 |
18:16 |
UMS |
|
RW |
0x0 |
15:8 |
Reserved |
|
RO |
0x00 |
7 |
CNIACE |
|
RO |
0 |
6 |
Reserved |
|
RO |
0 |
5 |
ACRE |
|
RO |
0 |
4 |
ACIE |
|
RO |
0 |
3 |
ACEBE |
|
RO |
0 |
2 |
ACCE |
|
RO |
0 |
1 |
ACTE |
|
RO |
0 |
0 |
ACNE |
|
RO |
0 |
Address offset |
0x240 |
||
Physical address |
0x2000 8240 |
Instance |
EMMC_SD |
Description |
|
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:30 |
SLT |
|
RO |
0x0 |
29 |
AIS |
|
RO |
0 |
28 |
A64S |
|
RO |
1 |
27 |
SRS16_HWINIT1 |
HWINIT field |
RO |
0 |
26 |
VS18 |
|
RO |
1 |
25 |
VS30 |
|
RO |
1 |
24 |
VS33 |
|
RO |
1 |
23 |
SRS |
|
RO |
0 |
22 |
DMAS |
|
RO |
1 |
21 |
HSS |
|
RO |
1 |
20 |
ADMA1S |
|
RO |
0 |
19 |
ADMA2S |
|
RO |
1 |
18 |
EDS8 |
|
RO |
0 |
17:16 |
MBL |
|
RO |
0x2 |
15:8 |
BCSDCLK |
|
RO |
0xC8 |
7 |
TCU |
|
RO |
1 |
6 |
SRS16_HWINIT0 |
HWINIT field |
RO |
0 |
5:0 |
TCF |
|
RO |
0x32 |
Address offset |
0x244 |
||
Physical address |
0x2000 8244 |
Instance |
EMMC_SD |
Description |
SRS17 - Capabilities #2HWINIT Register - Note this
register is hardware initialized after reset and the value read back will
match the IP configuration. |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:29 |
SRS17_HWINIT3 |
HWINIT field |
RO |
0x0 |
28 |
VDD2S |
|
RO |
1 |
27:24 |
SRS17_HWINIT2 |
HWINIT field |
RO |
0x0 |
23:16 |
CLKMPR |
|
RO |
0x00 |
15:14 |
RTNGM |
|
RO |
0x0 |
13 |
UTSM50 |
|
RO |
0 |
12 |
SRS17_HWINIT1 |
HWINIT field |
RO |
0 |
11:8 |
RTNGCNT |
|
RO |
0x0 |
7 |
SRS17_HWINIT0 |
HWINIT field |
RO |
0 |
6 |
DRVD |
DRVD - 1.8V Line Driver Type D Supported\n\n |
RO |
1 |
5 |
DRVC |
DRVC - 1.8V Line Driver Type C Supported\n\n |
RO |
1 |
4 |
DRVA |
|
RO |
1 |
3 |
UHSII |
|
RO |
0 |
2 |
DDR50 |
|
RO |
1 |
1 |
SDR104 |
|
RO |
1 |
0 |
SDR50 |
|
RO |
1 |
Address offset |
0x248 |
||
Physical address |
0x2000 8248 |
Instance |
EMMC_SD |
Description |
|
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
SRS18_HWINIT0 |
HWINIT field |
RO |
0x00 |
23:16 |
MC18 |
|
RO |
0x20 |
15:8 |
MC30 |
|
RO |
0x20 |
7:0 |
MC33 |
|
RO |
0x20 |
Address offset |
0x24C |
||
Physical address |
0x2000 824C |
Instance |
EMMC_SD |
Description |
|
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
SRS19_HWINIT0 |
HWINIT field |
RO |
0x00 0000 |
7:0 |
MC18V2 |
|
RO |
0x20 |
Address offset |
0x250 |
||
Physical address |
0x2000 8250 |
Instance |
EMMC_SD |
Description |
|
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:28 |
Reserved |
|
RO |
0x0 |
27 |
ERESP_FE |
ERESP_FE - Force Response Error Event |
WO |
0 |
26 |
ETUNE_FE |
ETUNE_FE - Force Tuning Error Event |
WO |
0 |
25 |
EADMA_FE |
EADMA_FE - Force ADMA Error Event |
WO |
0 |
24 |
EAC_FE |
EAC_FE - Force Auto CMD Error Event |
WO |
0 |
23 |
ECL_FE |
ECL_FE - Force Current Limit Error Event |
WO |
0 |
22 |
EDEB_FE |
EDEB_FE - Force Data End Bit Error Event |
WO |
0 |
21 |
EDCRC_FE |
EDCRC_FE - Force Data CRC Error Event |
WO |
0 |
20 |
EDT_FE |
EDT_FE - Force Data Timeout Error Event |
WO |
0 |
19 |
ECI_FE |
ECI_FE - Force Command Index Error Event |
WO |
0 |
18 |
ECEB_FE |
ECEB_FE - Force Command End Bit Error Event |
WO |
0 |
17 |
ECCRC_FE |
ECCRC_FE - Force Command CRC Error Event |
WO |
0 |
16 |
ECT_FE |
ECT_FE - Force Command Timeout Error Event |
WO |
0 |
15:8 |
Reserved |
|
RO |
0x00 |
7 |
CNIACE_FE |
CNIACE_FE - Force Command Not Issued By Auto CMD12 Error
Event |
WO |
0 |
6:5 |
Reserved |
|
RO |
0x0 |
4 |
ACIE_FE |
ACIE_FE - Force Auto CMD Index Error Event |
WO |
0 |
3 |
ACEBE_FE |
ACEBE_FE - Force Auto CMD End Bit Error Event |
WO |
0 |
2 |
ACCE_FE |
ACCE_FE - Force Auto CMD CRC Error Event |
WO |
0 |
1 |
ACTE_FE |
ACTE_FE - Force Auto CMD Timeout Error Event |
WO |
0 |
0 |
ACNE_FE |
ACNE_FE - Force Auto CMD12 Not Executed Event |
WO |
0 |
Address offset |
0x254 |
||
Physical address |
0x2000 8254 |
Instance |
EMMC_SD |
Description |
SRS21 - ADMA Error Status |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
Reserved |
|
RO |
0x0000 0000 |
2 |
EADMAL |
|
RO |
0 |
1:0 |
EADMAS |
|
RO |
0x0 |
Address offset |
0x258 |
||
Physical address |
0x2000 8258 |
Instance |
EMMC_SD |
Description |
SRS22 ADMA/SDMA System Address 1 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
DMASA1 |
|
RW |
0x0000 0000 |
Address offset |
0x25C |
||
Physical address |
0x2000 825C |
Instance |
EMMC_SD |
Description |
SRS23 ADMA/SDMA System Address 2 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
DMASA2 |
|
RW |
0x0000 0000 |
Address offset |
0x260 |
||
Physical address |
0x2000 8260 |
Instance |
EMMC_SD |
Description |
|
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:30 |
SRS24_DSSPV_31_30 |
|
RO |
0x0 |
29:26 |
SRS24_HWINIT1 |
HWINIT field |
RO |
0x0 |
25:16 |
SRS24_SDCFSPV_25_16 |
|
RO |
0x004 |
15:0 |
SRS24_HWINIT0 |
HWINIT field |
RO |
0x00FA |
Address offset |
0x264 |
||
Physical address |
0x2000 8264 |
Instance |
EMMC_SD |
Description |
|
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:30 |
SRS25_DSSPV_31_30 |
|
RO |
0x0 |
29:26 |
SRS25_HWINIT1 |
HWINIT field |
RO |
0x0 |
25:16 |
SRS25_SDCFSPV_25_16 |
|
RO |
0x004 |
15:14 |
SRS25_DSSPV_15_14 |
|
RO |
0x0 |
13:10 |
SRS25_HWINIT0 |
HWINIT field |
RO |
0x0 |
9:0 |
SRS25_SDCFSPV_09_00 |
|
RO |
0x002 |
Address offset |
0x268 |
||
Physical address |
0x2000 8268 |
Instance |
EMMC_SD |
Description |
|
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:30 |
SRS26_DSSPV_31_30 |
|
RO |
0x0 |
29:26 |
SRS26_HWINIT1 |
HWINIT field |
RO |
0x0 |
25:16 |
SRS26_SDCFSPV_25_16 |
|
RO |
0x001 |
15:14 |
SRS26_DSSPV_15_14 |
|
RO |
0x0 |
13:11 |
SRS26_HWINIT0 |
HWINIT field |
RO |
0x0 |
10 |
SRS26_CGSPV_10 |
|
RO |
0 |
9:0 |
SRS26_SDCFSPV_09_00 |
|
RO |
0x002 |
Address offset |
0x26C |
||
Physical address |
0x2000 826C |
Instance |
EMMC_SD |
Description |
|
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:30 |
SRS27_DSSPV_31_30 |
|
RO |
0x0 |
29:26 |
SRS27_HWINIT1 |
HWINIT field |
RO |
0x0 |
25:16 |
SRS27_SDCFSPV_25_16 |
|
RO |
0x002 |
15:14 |
SRS27_DSSPV_15_14 |
|
RO |
0x0 |
13:10 |
SRS27_HWINIT0 |
HWINIT field |
RO |
0x0 |
9:0 |
SRS27_SDCFSPV_09_00 |
|
RO |
0x000 |
Address offset |
0x274 |
||
Physical address |
0x2000 8274 |
Instance |
EMMC_SD |
Description |
|
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:16 |
SRS29_HWINIT1 |
HWINIT field |
RO |
0x0000 |
15:14 |
SRS29_DSSPV_15_14 |
|
RO |
0x0 |
13:10 |
SRS29_HWINIT0 |
HWINIT field |
RO |
0x0 |
9:0 |
SRS29_SDCFSPV_09_00 |
|
RO |
0x000 |
Address offset |
0x400 |
||
Physical address |
0x2000 8400 |
Instance |
EMMC_SD |
Description |
CQRS00 - Command Queuing Version |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:12 |
Reserved |
|
RO |
0x0 0000 |
11:8 |
CQVN1 |
|
RO |
0x5 |
7:4 |
CQVN2 |
|
RO |
0x1 |
3:0 |
CQVN3 |
|
RO |
0x0 |
Address offset |
0x404 |
||
Physical address |
0x2000 8404 |
Instance |
EMMC_SD |
Description |
CQRS01 - Command Queuing Capabilities |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:16 |
Reserved |
|
RO |
0x0000 |
15:12 |
ITCFMUL |
ITCFMUL - Internal Timer Clock Frequency Multiplier
(ITCFMUL)\n\n |
RO |
0x0 |
11:10 |
Reserved |
|
RO |
0x0 |
9:0 |
ITCFVAL |
|
RO |
0x000 |
Address offset |
0x408 |
||
Physical address |
0x2000 8408 |
Instance |
EMMC_SD |
Description |
CQRS02 - Command Queuing Configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:13 |
Reserved |
|
RO |
0x0 0000 |
12 |
CQDCE |
|
RW |
0 |
11:9 |
Reserved |
|
RO |
0x0 |
8 |
CQTDS |
|
RW |
0 |
7:1 |
Reserved |
|
RO |
0x00 |
0 |
CQE |
|
RW |
0 |
Address offset |
0x40C |
||
Physical address |
0x2000 840C |
Instance |
EMMC_SD |
Description |
CQRS03 - Command Queuing Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:9 |
Reserved |
|
RO |
0x00 0000 |
8 |
CQCAT |
|
RW |
0 |
7:1 |
Reserved |
|
RO |
0x00 |
0 |
CQHLT |
|
RW |
0 |
Address offset |
0x410 |
||
Physical address |
0x2000 8410 |
Instance |
EMMC_SD |
Description |
|
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
Reserved |
|
RO |
0x000 0000 |
3 |
CQTCL |
|
RW |
0 |
2 |
CQREDI |
|
RW |
0 |
1 |
CQTCC |
|
RW |
0 |
0 |
CQHAC |
|
RW |
0 |
Address offset |
0x414 |
||
Physical address |
0x2000 8414 |
Instance |
EMMC_SD |
Description |
|
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
Reserved |
|
RO |
0x000 0000 |
3 |
CQTCLST |
|
RW |
0 |
2 |
CQREDST |
|
RW |
0 |
1 |
CQTCCST |
|
RW |
0 |
0 |
CQHACST |
|
RW |
0 |
Address offset |
0x418 |
||
Physical address |
0x2000 8418 |
Instance |
EMMC_SD |
Description |
|
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
Reserved |
|
RO |
0x000 0000 |
3 |
CQTCLSI |
|
RW |
0 |
2 |
CQREDSI |
|
RW |
0 |
1 |
CQTCCSI |
|
RW |
0 |
0 |
CQHACSI |
|
RW |
0 |
Address offset |
0x41C |
||
Physical address |
0x2000 841C |
Instance |
EMMC_SD |
Description |
|
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31 |
CQICED |
|
RW |
0 |
30:21 |
Reserved |
|
RO |
0x000 |
20 |
CQICSB |
|
RO |
0 |
19:17 |
Reserved |
|
RO |
0x0 |
16 |
CQICCTR |
|
WO |
0 |
15 |
CQICCTHWEN |
|
WO |
0 |
14:13 |
Reserved |
|
RO |
0x0 |
12:8 |
CQICCTH |
|
RW |
0x00 |
7 |
CQICTOVALEN |
|
WO |
0 |
6:0 |
CQICTOVAL |
|
RW |
0x00 |
Address offset |
0x420 |
||
Physical address |
0x2000 8420 |
Instance |
EMMC_SD |
Description |
CQRS08 - Command Queuing Task Descriptor List Base Address
|
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
CQTDLBA |
|
RW |
0x0000 0000 |
Address offset |
0x424 |
||
Physical address |
0x2000 8424 |
Instance |
EMMC_SD |
Description |
CQRS09 - Command Queuing Task Descriptor List Base Address
Upper 32 Bits |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
CQTDLBAU |
|
RW |
0x0000 0000 |
Address offset |
0x428 |
||
Physical address |
0x2000 8428 |
Instance |
EMMC_SD |
Description |
|
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31 |
CQTD31 |
CQTD31 - Command Queuing Task Doorbell #31 |
RW |
0 |
30 |
CQTD30 |
CQTD30 - Command Queuing Task Doorbell #30 |
RW |
0 |
29 |
CQTD29 |
CQTD29 - Command Queuing Task Doorbell #29 |
RW |
0 |
28 |
CQTD28 |
CQTD28 - Command Queuing Task Doorbell #28 |
RW |
0 |
27 |
CQTD27 |
CQTD27 - Command Queuing Task Doorbell #27 |
RW |
0 |
26 |
CQTD26 |
CQTD26 - Command Queuing Task Doorbell #26 |
RW |
0 |
25 |
CQTD25 |
CQTD25 - Command Queuing Task Doorbell #25 |
RW |
0 |
24 |
CQTD24 |
CQTD24 - Command Queuing Task Doorbell #24 |
RW |
0 |
23 |
CQTD23 |
CQTD23 - Command Queuing Task Doorbell #23 |
RW |
0 |
22 |
CQTD22 |
CQTD22 - Command Queuing Task Doorbell #22 |
RW |
0 |
21 |
CQTD21 |
CQTD21 - Command Queuing Task Doorbell #21 |
RW |
0 |
20 |
CQTD20 |
CQTD20 - Command Queuing Task Doorbell #20 |
RW |
0 |
19 |
CQTD19 |
CQTD19 - Command Queuing Task Doorbell #19 |
RW |
0 |
18 |
CQTD18 |
CQTD18 - Command Queuing Task Doorbell #18 |
RW |
0 |
17 |
CQTD17 |
CQTD17 - Command Queuing Task Doorbell #17 |
RW |
0 |
16 |
CQTD16 |
CQTD16 - Command Queuing Task Doorbell #16 |
RW |
0 |
15 |
CQTD15 |
CQTD15 - Command Queuing Task Doorbell #15 |
RW |
0 |
14 |
CQTD14 |
CQTD14 - Command Queuing Task Doorbell #14 |
RW |
0 |
13 |
CQTD13 |
CQTD13 - Command Queuing Task Doorbell #13 |
RW |
0 |
12 |
CQTD12 |
CQTD12 - Command Queuing Task Doorbell #12 |
RW |
0 |
11 |
CQTD11 |
CQTD11 - Command Queuing Task Doorbell #11 |
RW |
0 |
10 |
CQTD10 |
CQTD10 - Command Queuing Task Doorbell #10 |
RW |
0 |
9 |
CQTD09 |
CQTD09 - Command Queuing Task Doorbell #09 |
RW |
0 |
8 |
CQTD08 |
CQTD08 - Command Queuing Task Doorbell #08 |
RW |
0 |
7 |
CQTD07 |
CQTD07 - Command Queuing Task Doorbell #07 |
RW |
0 |
6 |
CQTD06 |
CQTD06 - Command Queuing Task Doorbell #06 |
RW |
0 |
5 |
CQTD05 |
CQTD05 - Command Queuing Task Doorbell #05 |
RW |
0 |
4 |
CQTD04 |
CQTD04 - Command Queuing Task Doorbell #04 |
RW |
0 |
3 |
CQTD03 |
CQTD03 - Command Queuing Task Doorbell #03 |
RW |
0 |
2 |
CQTD02 |
CQTD02 - Command Queuing Task Doorbell #02 |
RW |
0 |
1 |
CQTD01 |
CQTD01 - Command Queuing Task Doorbell #01 |
RW |
0 |
0 |
CQTD00 |
CQTD00 - Command Queuing Task Doorbell #00 |
RW |
0 |
Address offset |
0x42C |
||
Physical address |
0x2000 842C |
Instance |
EMMC_SD |
Description |
|
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31 |
CQTCN31 |
CQTCN31 - Task Completion Notification #31 |
RW |
0 |
30 |
CQTCN30 |
CQTCN30 - Task Completion Notification #30 |
RW |
0 |
29 |
CQTCN29 |
CQTCN29 - Task Completion Notification #29 |
RW |
0 |
28 |
CQTCN28 |
CQTCN28 - Task Completion Notification #28 |
RW |
0 |
27 |
CQTCN27 |
CQTCN27 - Task Completion Notification #27 |
RW |
0 |
26 |
CQTCN26 |
CQTCN26 - Task Completion Notification #26 |
RW |
0 |
25 |
CQTCN25 |
CQTCN25 - Task Completion Notification #25 |
RW |
0 |
24 |
CQTCN24 |
CQTCN24 - Task Completion Notification #24 |
RW |
0 |
23 |
CQTCN23 |
CQTCN23 - Task Completion Notification #23 |
RW |
0 |
22 |
CQTCN22 |
CQTCN22 - Task Completion Notification #22 |
RW |
0 |
21 |
CQTCN21 |
CQTCN21 - Task Completion Notification #21 |
RW |
0 |
20 |
CQTCN20 |
CQTCN20 - Task Completion Notification #20 |
RW |
0 |
19 |
CQTCN19 |
CQTCN19 - Task Completion Notification #19 |
RW |
0 |
18 |
CQTCN18 |
CQTCN18 - Task Completion Notification #18 |
RW |
0 |
17 |
CQTCN17 |
CQTCN17 - Task Completion Notification #17 |
RW |
0 |
16 |
CQTCN16 |
CQTCN16 - Task Completion Notification #16 |
RW |
0 |
15 |
CQTCN15 |
CQTCN15 - Task Completion Notification #15 |
RW |
0 |
14 |
CQTCN14 |
CQTCN14 - Task Completion Notification #14 |
RW |
0 |
13 |
CQTCN13 |
CQTCN13 - Task Completion Notification #13 |
RW |
0 |
12 |
CQTCN12 |
CQTCN12 - Task Completion Notification #12 |
RW |
0 |
11 |
CQTCN11 |
CQTCN11 - Task Completion Notification #11 |
RW |
0 |
10 |
CQTCN10 |
CQTCN10 - Task Completion Notification #10 |
RW |
0 |
9 |
CQTCN09 |
CQTCN09 - Task Completion Notification #09 |
RW |
0 |
8 |
CQTCN08 |
CQTCN08 - Task Completion Notification #08 |
RW |
0 |
7 |
CQTCN07 |
CQTCN07 - Task Completion Notification #07 |
RW |
0 |
6 |
CQTCN06 |
CQTCN06 - Task Completion Notification #06 |
RW |
0 |
5 |
CQTCN05 |
CQTCN05 - Task Completion Notification #05 |
RW |
0 |
4 |
CQTCN04 |
CQTCN04 - Task Completion Notification #04 |
RW |
0 |
3 |
CQTCN03 |
CQTCN03 - Task Completion Notification #03 |
RW |
0 |
2 |
CQTCN02 |
CQTCN02 - Task Completion Notification #02 |
RW |
0 |
1 |
CQTCN01 |
CQTCN01 - Task Completion Notification #01 |
RW |
0 |
0 |
CQTCN00 |
CQTCN00 - Task Completion Notification #00 |
RW |
0 |
Address offset |
0x430 |
||
Physical address |
0x2000 8430 |
Instance |
EMMC_SD |
Description |
CQRS12 - Device Queue Status |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
CQDQS |
|
RO |
0x0000 0000 |
Address offset |
0x434 |
||
Physical address |
0x2000 8434 |
Instance |
EMMC_SD |
Description |
|
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31 |
CQDPT31 |
CQDPT31 - Device Pending Tasks #31 |
RO |
0 |
30 |
CQDPT30 |
CQDPT30 - Device Pending Tasks #30 |
RO |
0 |
29 |
CQDPT29 |
CQDPT29 - Device Pending Tasks #29 |
RO |
0 |
28 |
CQDPT28 |
CQDPT28 - Device Pending Tasks #28 |
RO |
0 |
27 |
CQDPT27 |
CQDPT27 - Device Pending Tasks #27 |
RO |
0 |
26 |
CQDPT26 |
CQDPT26 - Device Pending Tasks #26 |
RO |
0 |
25 |
CQDPT25 |
CQDPT25 - Device Pending Tasks #25 |
RO |
0 |
24 |
CQDPT24 |
CQDPT24 - Device Pending Tasks #24 |
RO |
0 |
23 |
CQDPT23 |
CQDPT23 - Device Pending Tasks #23 |
RO |
0 |
22 |
CQDPT22 |
CQDPT22 - Device Pending Tasks #22 |
RO |
0 |
21 |
CQDPT21 |
CQDPT21 - Device Pending Tasks #21 |
RO |
0 |
20 |
CQDPT20 |
CQDPT20 - Device Pending Tasks #20 |
RO |
0 |
19 |
CQDPT19 |
CQDPT19 - Device Pending Tasks #19 |
RO |
0 |
18 |
CQDPT18 |
CQDPT18 - Device Pending Tasks #18 |
RO |
0 |
17 |
CQDPT17 |
CQDPT17 - Device Pending Tasks #17 |
RO |
0 |
16 |
CQDPT16 |
CQDPT16 - Device Pending Tasks #16 |
RO |
0 |
15 |
CQDPT15 |
CQDPT15 - Device Pending Tasks #15 |
RO |
0 |
14 |
CQDPT14 |
CQDPT14 - Device Pending Tasks #14 |
RO |
0 |
13 |
CQDPT13 |
CQDPT13 - Device Pending Tasks #13 |
RO |
0 |
12 |
CQDPT12 |
CQDPT12 - Device Pending Tasks #12 |
RO |
0 |
11 |
CQDPT11 |
CQDPT11 - Device Pending Tasks #11 |
RO |
0 |
10 |
CQDPT10 |
CQDPT10 - Device Pending Tasks #10 |
RO |
0 |
9 |
CQDPT09 |
CQDPT09 - Device Pending Tasks #09 |
RO |
0 |
8 |
CQDPT08 |
CQDPT08 - Device Pending Tasks #08 |
RO |
0 |
7 |
CQDPT07 |
CQDPT07 - Device Pending Tasks #07 |
RO |
0 |
6 |
CQDPT06 |
CQDPT06 - Device Pending Tasks #06 |
RO |
0 |
5 |
CQDPT05 |
CQDPT05 - Device Pending Tasks #05 |
RO |
0 |
4 |
CQDPT04 |
CQDPT04 - Device Pending Tasks #04 |
RO |
0 |
3 |
CQDPT03 |
CQDPT03 - Device Pending Tasks #03 |
RO |
0 |
2 |
CQDPT02 |
CQDPT02 - Device Pending Tasks #02 |
RO |
0 |
1 |
CQDPT01 |
CQDPT01 - Device Pending Tasks #01 |
RO |
0 |
0 |
CQDPT00 |
CQDPT00 - Device Pending Tasks #00 |
RO |
0 |
Address offset |
0x438 |
||
Physical address |
0x2000 8438 |
Instance |
EMMC_SD |
Description |
|
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31 |
CQTC31 |
CQTC31 - Command Queuing Task Clear #31 |
RW |
0 |
30 |
CQTC30 |
CQTC30 - Command Queuing Task Clear #30 |
RW |
0 |
29 |
CQTC29 |
CQTC29 - Command Queuing Task Clear #29 |
RW |
0 |
28 |
CQTC28 |
CQTC28 - Command Queuing Task Clear #28 |
RW |
0 |
27 |
CQTC27 |
CQTC27 - Command Queuing Task Clear #27 |
RW |
0 |
26 |
CQTC26 |
CQTC26 - Command Queuing Task Clear #26 |
RW |
0 |
25 |
CQTC25 |
CQTC25 - Command Queuing Task Clear #25 |
RW |
0 |
24 |
CQTC24 |
CQTC24 - Command Queuing Task Clear #24 |
RW |
0 |
23 |
CQTC23 |
CQTC23 - Command Queuing Task Clear #23 |
RW |
0 |
22 |
CQTC22 |
CQTC22 - Command Queuing Task Clear #22 |
RW |
0 |
21 |
CQTC21 |
CQTC21 - Command Queuing Task Clear #21 |
RW |
0 |
20 |
CQTC20 |
CQTC20 - Command Queuing Task Clear #20 |
RW |
0 |
19 |
CQTC19 |
CQTC19 - Command Queuing Task Clear #19 |
RW |
0 |
18 |
CQTC18 |
CQTC18 - Command Queuing Task Clear #18 |
RW |
0 |
17 |
CQTC17 |
CQTC17 - Command Queuing Task Clear #17 |
RW |
0 |
16 |
CQTC16 |
CQTC16 - Command Queuing Task Clear #16 |
RW |
0 |
15 |
CQTC15 |
CQTC15 - Command Queuing Task Clear #15 |
RW |
0 |
14 |
CQTC14 |
CQTC14 - Command Queuing Task Clear #14 |
RW |
0 |
13 |
CQTC13 |
CQTC13 - Command Queuing Task Clear #13 |
RW |
0 |
12 |
CQTC12 |
CQTC12 - Command Queuing Task Clear #12 |
RW |
0 |
11 |
CQTC11 |
CQTC11 - Command Queuing Task Clear #11 |
RW |
0 |
10 |
CQTC10 |
CQTC10 - Command Queuing Task Clear #10 |
RW |
0 |
9 |
CQTC09 |
CQTC09 - Command Queuing Task Clear #09 |
RW |
0 |
8 |
CQTC08 |
CQTC08 - Command Queuing Task Clear #08 |
RW |
0 |
7 |
CQTC07 |
CQTC07 - Command Queuing Task Clear #07 |
RW |
0 |
6 |
CQTC06 |
CQTC06 - Command Queuing Task Clear #06 |
RW |
0 |
5 |
CQTC05 |
CQTC05 - Command Queuing Task Clear #05 |
RW |
0 |
4 |
CQTC04 |
CQTC04 - Command Queuing Task Clear #04 |
RW |
0 |
3 |
CQTC03 |
CQTC03 - Command Queuing Task Clear #03 |
RW |
0 |
2 |
CQTC02 |
CQTC02 - Command Queuing Task Clear #02 |
RW |
0 |
1 |
CQTC01 |
CQTC01 - Command Queuing Task Clear #01 |
RW |
0 |
0 |
CQTC00 |
CQTC00 - Command Queuing Task Clear #00 |
RW |
0 |
Address offset |
0x440 |
||
Physical address |
0x2000 8440 |
Instance |
EMMC_SD |
Description |
CQRS16 - Send Status Configuration 1 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:20 |
Reserved |
|
RO |
0x000 |
19:16 |
CQSSCBC |
|
RW |
0x0 |
15:0 |
CQSSCIT |
|
RW |
0x0000 |
Address offset |
0x444 |
||
Physical address |
0x2000 8444 |
Instance |
EMMC_SD |
Description |
CQRS17 - Send Status Configuration 2 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:16 |
Reserved |
|
RO |
0x0000 |
15:0 |
CQSQSR |
CQSQSR - Send Queue Status RCA\n\n |
RW |
0x0000 |
Address offset |
0x448 |
||
Physical address |
0x2000 8448 |
Instance |
EMMC_SD |
Description |
CQRS18 - Command Response for Direct-Command Task |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
CQDCLR |
|
RO |
0x0000 0000 |
Address offset |
0x450 |
||
Physical address |
0x2000 8450 |
Instance |
EMMC_SD |
Description |
CQRS20 - Response Mode Error Mask |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
CQRMEM |
|
RW |
0x0000 0000 |
Address offset |
0x454 |
||
Physical address |
0x2000 8454 |
Instance |
EMMC_SD |
Description |
CQRS21 - Task Error Information |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31 |
CQDTEFV |
|
RO |
0 |
30:29 |
Reserved |
|
RO |
0x0 |
28:24 |
CQDTETID |
|
RO |
0x00 |
23:22 |
Reserved |
|
RO |
0x0 |
21:16 |
CQDTECI |
|
RO |
0x00 |
15 |
CQRMEFV |
|
RO |
0 |
14:13 |
Reserved |
|
RO |
0x0 |
12:8 |
CQRMETID |
|
RO |
0x00 |
7:6 |
Reserved |
|
RO |
0x0 |
5:0 |
CQRMECI |
|
RO |
0x00 |
Address offset |
0x458 |
||
Physical address |
0x2000 8458 |
Instance |
EMMC_SD |
Description |
CQRS22 - Command Response Index |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:6 |
Reserved |
|
RO |
0x000 0000 |
5:0 |
CQLCRI |
|
RO |
0x00 |
Address offset |
0x45C |
||
Physical address |
0x2000 845C |
Instance |
EMMC_SD |
Description |
CQRS23 - Command Response Argument |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
CQLCRA |
|
RO |
0x0000 0000 |
EMMC_SD has no
common memories.