GEM_GXIMICROSEMI

This section provides information on the gem_gximicrosemi Module Instance. Each of the module registers is described below.

No lock registers supported.

Return to pfsoc_mss_regmap

GEM_GXIMICROSEMI Register Mapping Summary

gem_gximicrosemi Common Register Mapping Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

NETWORK_CONTROL

RW

32

0x0000 0000

0x0000

NETWORK_CONFIG

RW

32

0x0008 0000

0x0004

NETWORK_STATUS

RO

32

0x0000 0004

0x0008

DMA_CONFIG

RW

32

0x0002 07C4

0x0010

TRANSMIT_STATUS

RW

32

0x0000 0000

0x0014

RECEIVE_Q_PTR

RW

32

0x0000 0000

0x0018

TRANSMIT_Q_PTR

RW

32

0x0000 0000

0x001C

RECEIVE_STATUS

RW

32

0x0000 0000

0x0020

INT_STATUS

RW

32

0x0000 0000

0x0024

INT_ENABLE

RW

32

0x0000 0000

0x0028

INT_DISABLE

RW

32

0x0000 0000

0x002C

INT_MASK

RO

32

0xFFFC FCFF

0x0030

PHY_MANAGEMENT

RW

32

0x0000 0000

0x0034

PAUSE_TIME

RO

32

0x0000 0000

0x0038

TX_PAUSE_QUANTUM

RW

32

0x0000 FFFF

0x003C

PBUF_TXCUTTHRU

RW

32

0x0000 1FFF

0x0040

PBUF_RXCUTTHRU

RW

32

0x0000 07FF

0x0044

JUMBO_MAX_LENGTH

RW

32

0x0000 3FFF

0x0048

AXI_MAX_PIPELINE

RW

32

0x0000 0101

0x0054

RSC_CONTROL

RW

32

0x0000 0000

0x0058

INT_MODERATION

RW

32

0x0000 0000

0x005C

SYS_WAKE_TIME

RW

32

0x0000 0000

0x0060

LOCKUP_CONFIG

RW

32

0x07FF FFFF

0x0068

MAC_LOCKUP_TIME

RW

32

0x07FF FFFF

0x006C

LOCKUP_CONFIG3

RW

32

0x0000 0000

0x0070

RX_WATER_MARK

RW

32

0x0000 0000

0x007C

HASH_BOTTOM

RW

32

0x0000 0000

0x0080

HASH_TOP

RW

32

0x0000 0000

0x0084

SPEC_ADD1_BOTTOM

RW

32

0x0000 0000

0x0088

SPEC_ADD1_TOP

RW

32

0x0000 0000

0x008C

SPEC_ADD2_BOTTOM

RW

32

0x0000 0000

0x0090

SPEC_ADD2_TOP

RW

32

0x0000 0000

0x0094

SPEC_ADD3_BOTTOM

RW

32

0x0000 0000

0x0098

SPEC_ADD3_TOP

RW

32

0x0000 0000

0x009C

SPEC_ADD4_BOTTOM

RW

32

0x0000 0000

0x00A0

SPEC_ADD4_TOP

RW

32

0x0000 0000

0x00A4

SPEC_TYPE1

RW

32

0x0000 0000

0x00A8

SPEC_TYPE2

RW

32

0x0000 0000

0x00AC

SPEC_TYPE3

RW

32

0x0000 0000

0x00B0

SPEC_TYPE4

RW

32

0x0000 0000

0x00B4

WOL_REGISTER

RW

32

0x0000 0000

0x00B8

STRETCH_RATIO

RW

32

0x0000 0000

0x00BC

STACKED_VLAN

RW

32

0x0000 0000

0x00C0

TX_PFC_PAUSE

RW

32

0x0000 0000

0x00C4

MASK_ADD1_BOTTOM

RW

32

0x0000 0000

0x00C8

MASK_ADD1_TOP

RW

32

0x0000 0000

0x00CC

DMA_ADDR_OR_MASK

RW

32

0x0000 0000

0x00D0

RX_PTP_UNICAST

RW

32

0x0000 0000

0x00D4

TX_PTP_UNICAST

RW

32

0x0000 0000

0x00D8

TSU_NSEC_CMP

RW

32

0x0000 0000

0x00DC

TSU_SEC_CMP

RW

32

0x0000 0000

0x00E0

TSU_MSB_SEC_CMP

RW

32

0x0000 0000

0x00E4

TSU_PTP_TX_MSB_SEC

RO

32

0x0000 0000

0x00E8

TSU_PTP_RX_MSB_SEC

RO

32

0x0000 0000

0x00EC

TSU_PEER_TX_MSB_SEC

RO

32

0x0000 0000

0x00F0

TSU_PEER_RX_MSB_SEC

RO

32

0x0000 0000

0x00F4

DPRAM_FILL_DBG

RW

32

0x0000 0000

0x00F8

REVISION_REG

RO

32

0x0107 010C

0x00FC

OCTETS_TXED_BOTTOM

RO

32

0x0000 0000

0x0100

OCTETS_TXED_TOP

RO

32

0x0000 0000

0x0104

FRAMES_TXED_OK

RO

32

0x0000 0000

0x0108

BROADCAST_TXED

RO

32

0x0000 0000

0x010C

MULTICAST_TXED

RO

32

0x0000 0000

0x0110

PAUSE_FRAMES_TXED

RO

32

0x0000 0000

0x0114

FRAMES_TXED_64

RO

32

0x0000 0000

0x0118

FRAMES_TXED_65

RO

32

0x0000 0000

0x011C

FRAMES_TXED_128

RO

32

0x0000 0000

0x0120

FRAMES_TXED_256

RO

32

0x0000 0000

0x0124

FRAMES_TXED_512

RO

32

0x0000 0000

0x0128

FRAMES_TXED_1024

RO

32

0x0000 0000

0x012C

FRAMES_TXED_1519

RO

32

0x0000 0000

0x0130

TX_UNDERRUNS

RO

32

0x0000 0000

0x0134

SINGLE_COLLISIONS

RO

32

0x0000 0000

0x0138

MULTIPLE_COLLISIONS

RO

32

0x0000 0000

0x013C

EXCESSIVE_COLLISIONS

RO

32

0x0000 0000

0x0140

LATE_COLLISIONS

RO

32

0x0000 0000

0x0144

DEFERRED_FRAMES

RO

32

0x0000 0000

0x0148

CRS_ERRORS

RO

32

0x0000 0000

0x014C

OCTETS_RXED_BOTTOM

RO

32

0x0000 0000

0x0150

OCTETS_RXED_TOP

RO

32

0x0000 0000

0x0154

FRAMES_RXED_OK

RO

32

0x0000 0000

0x0158

BROADCAST_RXED

RO

32

0x0000 0000

0x015C

MULTICAST_RXED

RO

32

0x0000 0000

0x0160

PAUSE_FRAMES_RXED

RO

32

0x0000 0000

0x0164

FRAMES_RXED_64

RO

32

0x0000 0000

0x0168

FRAMES_RXED_65

RO

32

0x0000 0000

0x016C

FRAMES_RXED_128

RO

32

0x0000 0000

0x0170

FRAMES_RXED_256

RO

32

0x0000 0000

0x0174

FRAMES_RXED_512

RO

32

0x0000 0000

0x0178

FRAMES_RXED_1024

RO

32

0x0000 0000

0x017C

FRAMES_RXED_1519

RO

32

0x0000 0000

0x0180

UNDERSIZE_FRAMES

RO

32

0x0000 0000

0x0184

EXCESSIVE_RX_LENGTH

RO

32

0x0000 0000

0x0188

RX_JABBERS

RO

32

0x0000 0000

0x018C

FCS_ERRORS

RO

32

0x0000 0000

0x0190

RX_LENGTH_ERRORS

RO

32

0x0000 0000

0x0194

RX_SYMBOL_ERRORS

RO

32

0x0000 0000

0x0198

ALIGNMENT_ERRORS

RO

32

0x0000 0000

0x019C

RX_RESOURCE_ERRORS

RO

32

0x0000 0000

0x01A0

RX_OVERRUNS

RO

32

0x0000 0000

0x01A4

RX_IP_CK_ERRORS

RO

32

0x0000 0000

0x01A8

RX_TCP_CK_ERRORS

RO

32

0x0000 0000

0x01AC

RX_UDP_CK_ERRORS

RO

32

0x0000 0000

0x01B0

AUTO_FLUSHED_PKTS

RO

32

0x0000 0000

0x01B4

TSU_TIMER_INCR_SUB_NSEC

RW

32

0x0000 0000

0x01BC

TSU_TIMER_MSB_SEC

RW

32

0x0000 0000

0x01C0

TSU_STROBE_MSB_SEC

RO

32

0x0000 0000

0x01C4

TSU_STROBE_SEC

RO

32

0x0000 0000

0x01C8

TSU_STROBE_NSEC

RO

32

0x0000 0000

0x01CC

TSU_TIMER_SEC

RW

32

0x0000 0000

0x01D0

TSU_TIMER_NSEC

RW

32

0x0000 0000

0x01D4

TSU_TIMER_ADJUST

RW

32

0x0000 0000

0x01D8

TSU_TIMER_INCR

RW

32

0x0000 0000

0x01DC

TSU_PTP_TX_SEC

RO

32

0x0000 0000

0x01E0

TSU_PTP_TX_NSEC

RO

32

0x0000 0000

0x01E4

TSU_PTP_RX_SEC

RO

32

0x0000 0000

0x01E8

TSU_PTP_RX_NSEC

RO

32

0x0000 0000

0x01EC

TSU_PEER_TX_SEC

RO

32

0x0000 0000

0x01F0

TSU_PEER_TX_NSEC

RO

32

0x0000 0000

0x01F4

TSU_PEER_RX_SEC

RO

32

0x0000 0000

0x01F8

TSU_PEER_RX_NSEC

RO

32

0x0000 0000

0x01FC

PFC_STATUS

RO

32

0x0000 0000

0x026C

RX_LPI

RO

32

0x0000 0000

0x0270

RX_LPI_TIME

RO

32

0x0000 0000

0x0274

TX_LPI

RO

32

0x0000 0000

0x0278

TX_LPI_TIME

RO

32

0x0000 0000

0x027C

DESIGNCFG_DEBUG1

RO

32

0x0850 8511

0x0280

DESIGNCFG_DEBUG2

RO

32

0x76F1 3FFF

0x0284

DESIGNCFG_DEBUG3

RO

32

0x0400 0000

0x0288

DESIGNCFG_DEBUG4

RO

32

0x0000 0000

0x028C

DESIGNCFG_DEBUG5

RO

32

0x402F A345

0x0290

DESIGNCFG_DEBUG6

RO

32

0x0C84 FFFE

0x0294

DESIGNCFG_DEBUG7

RO

32

0x0000 0000

0x0298

DESIGNCFG_DEBUG8

RO

32

0x1010 0820

0x029C

DESIGNCFG_DEBUG9

RO

32

0x0000 0000

0x02A0

DESIGNCFG_DEBUG10

RO

32

0x2444 4442

0x02A4

DESIGNCFG_DEBUG11

RO

32

0x0000 0000

0x02A8

DESIGNCFG_DEBUG12

RO

32

0x0154 4001

0x02AC

AXI_QOS_CFG_0

RW

32

0x0000 0000

0x02E0

AXI_QOS_CFG_1

RW

32

0x0000 0000

0x02E4

AXI_QOS_CFG_2

RW

32

0x0000 0000

0x02E8

AXI_QOS_CFG_3

RW

32

0x0000 0000

0x02EC

INT_Q1_STATUS

RW

32

0x0000 0000

0x0400

INT_Q2_STATUS

RW

32

0x0000 0000

0x0404

INT_Q3_STATUS

RW

32

0x0000 0000

0x0408

INT_Q4_STATUS

RW

32

0x0000 0000

0x040C

INT_Q5_STATUS

RW

32

0x0000 0000

0x0410

INT_Q6_STATUS

RW

32

0x0000 0000

0x0414

INT_Q7_STATUS

RW

32

0x0000 0000

0x0418

INT_Q8_STATUS

RW

32

0x0000 0000

0x041C

INT_Q9_STATUS

RW

32

0x0000 0000

0x0420

INT_Q10_STATUS

RW

32

0x0000 0000

0x0424

INT_Q11_STATUS

RW

32

0x0000 0000

0x0428

INT_Q12_STATUS

RW

32

0x0000 0000

0x042C

INT_Q13_STATUS

RW

32

0x0000 0000

0x0430

INT_Q14_STATUS

RW

32

0x0000 0000

0x0434

INT_Q15_STATUS

RW

32

0x0000 0000

0x0438

TRANSMIT_Q1_PTR

RW

32

0x0000 0000

0x0440

TRANSMIT_Q2_PTR

RW

32

0x0000 0000

0x0444

TRANSMIT_Q3_PTR

RW

32

0x0000 0000

0x0448

TRANSMIT_Q4_PTR

RW

32

0x0000 0000

0x044C

TRANSMIT_Q5_PTR

RW

32

0x0000 0000

0x0450

TRANSMIT_Q6_PTR

RW

32

0x0000 0000

0x0454

TRANSMIT_Q7_PTR

RW

32

0x0000 0000

0x0458

TRANSMIT_Q8_PTR

RW

32

0x0000 0000

0x045C

TRANSMIT_Q9_PTR

RW

32

0x0000 0000

0x0460

TRANSMIT_Q10_PTR

RW

32

0x0000 0000

0x0464

TRANSMIT_Q11_PTR

RW

32

0x0000 0000

0x0468

TRANSMIT_Q12_PTR

RW

32

0x0000 0000

0x046C

TRANSMIT_Q13_PTR

RW

32

0x0000 0000

0x0470

TRANSMIT_Q14_PTR

RW

32

0x0000 0000

0x0474

TRANSMIT_Q15_PTR

RW

32

0x0000 0000

0x0478

RECEIVE_Q1_PTR

RW

32

0x0000 0000

0x0480

RECEIVE_Q2_PTR

RW

32

0x0000 0000

0x0484

RECEIVE_Q3_PTR

RW

32

0x0000 0000

0x0488

RECEIVE_Q4_PTR

RW

32

0x0000 0000

0x048C

RECEIVE_Q5_PTR

RW

32

0x0000 0000

0x0490

RECEIVE_Q6_PTR

RW

32

0x0000 0000

0x0494

RECEIVE_Q7_PTR

RW

32

0x0000 0000

0x0498

DMA_RXBUF_SIZE_Q1

RW

32

0x0000 0002

0x04A0

DMA_RXBUF_SIZE_Q2

RW

32

0x0000 0002

0x04A4

DMA_RXBUF_SIZE_Q3

RW

32

0x0000 0002

0x04A8

DMA_RXBUF_SIZE_Q4

RW

32

0x0000 0002

0x04AC

DMA_RXBUF_SIZE_Q5

RW

32

0x0000 0002

0x04B0

DMA_RXBUF_SIZE_Q6

RW

32

0x0000 0002

0x04B4

DMA_RXBUF_SIZE_Q7

RW

32

0x0000 0002

0x04B8

CBS_CONTROL

RW

32

0x0000 0000

0x04BC

CBS_IDLESLOPE_Q_A

RW

32

0x0000 0000

0x04C0

CBS_IDLESLOPE_Q_B

RW

32

0x0000 0000

0x04C4

UPPER_TX_Q_BASE_ADDR

RW

32

0x0000 0000

0x04C8

TX_BD_CONTROL

RW

32

0x0000 0000

0x04CC

RX_BD_CONTROL

RW

32

0x0000 0000

0x04D0

UPPER_RX_Q_BASE_ADDR

RW

32

0x0000 0000

0x04D4

WD_COUNTER

RW

32

0x0000 0007

0x04EC

AXI_TX_FULL_THRESH0

RW

32

0x0006 0008

0x04F8

AXI_TX_FULL_THRESH1

RW

32

0x0000 0000

0x04FC

SCREENING_TYPE_1_REGISTER_0

RW

32

0x0000 0000

0x0500

SCREENING_TYPE_1_REGISTER_1

RW

32

0x0000 0000

0x0504

SCREENING_TYPE_1_REGISTER_2

RW

32

0x0000 0000

0x0508

SCREENING_TYPE_1_REGISTER_3

RW

32

0x0000 0000

0x050C

SCREENING_TYPE_1_REGISTER_4

RW

32

0x0000 0000

0x0510

SCREENING_TYPE_1_REGISTER_5

RW

32

0x0000 0000

0x0514

SCREENING_TYPE_1_REGISTER_6

RW

32

0x0000 0000

0x0518

SCREENING_TYPE_1_REGISTER_7

RW

32

0x0000 0000

0x051C

SCREENING_TYPE_1_REGISTER_8

RW

32

0x0000 0000

0x0520

SCREENING_TYPE_1_REGISTER_9

RW

32

0x0000 0000

0x0524

SCREENING_TYPE_1_REGISTER_10

RW

32

0x0000 0000

0x0528

SCREENING_TYPE_1_REGISTER_11

RW

32

0x0000 0000

0x052C

SCREENING_TYPE_1_REGISTER_12

RW

32

0x0000 0000

0x0530

SCREENING_TYPE_1_REGISTER_13

RW

32

0x0000 0000

0x0534

SCREENING_TYPE_1_REGISTER_14

RW

32

0x0000 0000

0x0538

SCREENING_TYPE_1_REGISTER_15

RW

32

0x0000 0000

0x053C

SCREENING_TYPE_2_REGISTER_0

RW

32

0x0000 0000

0x0540

SCREENING_TYPE_2_REGISTER_1

RW

32

0x0000 0000

0x0544

SCREENING_TYPE_2_REGISTER_2

RW

32

0x0000 0000

0x0548

SCREENING_TYPE_2_REGISTER_3

RW

32

0x0000 0000

0x054C

SCREENING_TYPE_2_REGISTER_4

RW

32

0x0000 0000

0x0550

SCREENING_TYPE_2_REGISTER_5

RW

32

0x0000 0000

0x0554

SCREENING_TYPE_2_REGISTER_6

RW

32

0x0000 0000

0x0558

SCREENING_TYPE_2_REGISTER_7

RW

32

0x0000 0000

0x055C

SCREENING_TYPE_2_REGISTER_8

RW

32

0x0000 0000

0x0560

SCREENING_TYPE_2_REGISTER_9

RW

32

0x0000 0000

0x0564

SCREENING_TYPE_2_REGISTER_10

RW

32

0x0000 0000

0x0568

SCREENING_TYPE_2_REGISTER_11

RW

32

0x0000 0000

0x056C

SCREENING_TYPE_2_REGISTER_12

RW

32

0x0000 0000

0x0570

SCREENING_TYPE_2_REGISTER_13

RW

32

0x0000 0000

0x0574

SCREENING_TYPE_2_REGISTER_14

RW

32

0x0000 0000

0x0578

SCREENING_TYPE_2_REGISTER_15

RW

32

0x0000 0000

0x057C

TX_SCHED_CTRL

RW

32

0x0000 0000

0x0580

BW_RATE_LIMIT_Q0TO3

RW

32

0x0000 0000

0x0590

BW_RATE_LIMIT_Q4TO7

RW

32

0x0000 0000

0x0594

BW_RATE_LIMIT_Q8TO11

RW

32

0x0000 0000

0x0598

BW_RATE_LIMIT_Q12TO15

RW

32

0x0000 0000

0x059C

TX_Q_SEG_ALLOC_Q_LOWER

RW

32

0x0000 0000

0x05A0

TX_Q_SEG_ALLOC_Q_UPPER

RW

32

0x0000 0000

0x05A4

RECEIVE_Q8_PTR

RW

32

0x0000 0000

0x05C0

RECEIVE_Q9_PTR

RW

32

0x0000 0000

0x05C4

RECEIVE_Q10_PTR

RW

32

0x0000 0000

0x05C8

RECEIVE_Q11_PTR

RW

32

0x0000 0000

0x05CC

RECEIVE_Q12_PTR

RW

32

0x0000 0000

0x05D0

RECEIVE_Q13_PTR

RW

32

0x0000 0000

0x05D4

RECEIVE_Q14_PTR

RW

32

0x0000 0000

0x05D8

RECEIVE_Q15_PTR

RW

32

0x0000 0000

0x05DC

DMA_RXBUF_SIZE_Q8

RW

32

0x0000 0002

0x05E0

DMA_RXBUF_SIZE_Q9

RW

32

0x0000 0002

0x05E4

DMA_RXBUF_SIZE_Q10

RW

32

0x0000 0002

0x05E8

DMA_RXBUF_SIZE_Q11

RW

32

0x0000 0002

0x05EC

DMA_RXBUF_SIZE_Q12

RW

32

0x0000 0002

0x05F0

DMA_RXBUF_SIZE_Q13

RW

32

0x0000 0002

0x05F4

DMA_RXBUF_SIZE_Q14

RW

32

0x0000 0002

0x05F8

DMA_RXBUF_SIZE_Q15

RW

32

0x0000 0002

0x05FC

INT_Q1_ENABLE

RW

32

0x0000 0000

0x0600

INT_Q2_ENABLE

RW

32

0x0000 0000

0x0604

INT_Q3_ENABLE

RW

32

0x0000 0000

0x0608

INT_Q4_ENABLE

RW

32

0x0000 0000

0x060C

INT_Q5_ENABLE

RW

32

0x0000 0000

0x0610

INT_Q6_ENABLE

RW

32

0x0000 0000

0x0614

INT_Q7_ENABLE

RW

32

0x0000 0000

0x0618

INT_Q1_DISABLE

RW

32

0x0000 0000

0x0620

INT_Q2_DISABLE

RW

32

0x0000 0000

0x0624

INT_Q3_DISABLE

RW

32

0x0000 0000

0x0628

INT_Q4_DISABLE

RW

32

0x0000 0000

0x062C

INT_Q5_DISABLE

RW

32

0x0000 0000

0x0630

INT_Q6_DISABLE

RW

32

0x0000 0000

0x0634

INT_Q7_DISABLE

RW

32

0x0000 0000

0x0638

INT_Q1_MASK

RO

32

0x0000 08E6

0x0640

INT_Q2_MASK

RO

32

0x0000 08E6

0x0644

INT_Q3_MASK

RO

32

0x0000 08E6

0x0648

INT_Q4_MASK

RO

32

0x0000 08E6

0x064C

INT_Q5_MASK

RO

32

0x0000 08E6

0x0650

INT_Q6_MASK

RO

32

0x0000 08E6

0x0654

INT_Q7_MASK

RO

32

0x0000 08E6

0x0658

INT_Q8_ENABLE

RW

32

0x0000 0000

0x0660

INT_Q9_ENABLE

RW

32

0x0000 0000

0x0664

INT_Q10_ENABLE

RW

32

0x0000 0000

0x0668

INT_Q11_ENABLE

RW

32

0x0000 0000

0x066C

INT_Q12_ENABLE

RW

32

0x0000 0000

0x0670

INT_Q13_ENABLE

RW

32

0x0000 0000

0x0674

INT_Q14_ENABLE

RW

32

0x0000 0000

0x0678

INT_Q15_ENABLE

RW

32

0x0000 0000

0x067C

INT_Q8_DISABLE

RW

32

0x0000 0000

0x0680

INT_Q9_DISABLE

RW

32

0x0000 0000

0x0684

INT_Q10_DISABLE

RW

32

0x0000 0000

0x0688

INT_Q11_DISABLE

RW

32

0x0000 0000

0x068C

INT_Q12_DISABLE

RW

32

0x0000 0000

0x0690

INT_Q13_DISABLE

RW

32

0x0000 0000

0x0694

INT_Q14_DISABLE

RW

32

0x0000 0000

0x0698

INT_Q15_DISABLE

RW

32

0x0000 0000

0x069C

INT_Q8_MASK

RO

32

0x0000 08E6

0x06A0

INT_Q9_MASK

RO

32

0x0000 08E6

0x06A4

INT_Q10_MASK

RO

32

0x0000 08E6

0x06A8

INT_Q11_MASK

RO

32

0x0000 08E6

0x06AC

INT_Q12_MASK

RO

32

0x0000 08E6

0x06B0

INT_Q13_MASK

RO

32

0x0000 08E6

0x06B4

INT_Q14_MASK

RO

32

0x0000 08E6

0x06B8

INT_Q15_MASK

RO

32

0x0000 08E6

0x06BC

SCREENING_TYPE_2_ETHERTYPE_REG_0

RW

32

0x0000 0000

0x06E0

SCREENING_TYPE_2_ETHERTYPE_REG_1

RW

32

0x0000 0000

0x06E4

SCREENING_TYPE_2_ETHERTYPE_REG_2

RW

32

0x0000 0000

0x06E8

SCREENING_TYPE_2_ETHERTYPE_REG_3

RW

32

0x0000 0000

0x06EC

SCREENING_TYPE_2_ETHERTYPE_REG_4

RW

32

0x0000 0000

0x06F0

SCREENING_TYPE_2_ETHERTYPE_REG_5

RW

32

0x0000 0000

0x06F4

SCREENING_TYPE_2_ETHERTYPE_REG_6

RW

32

0x0000 0000

0x06F8

SCREENING_TYPE_2_ETHERTYPE_REG_7

RW

32

0x0000 0000

0x06FC

TYPE2_COMPARE_0_WORD_0

RW

32

0x0000 0000

0x0700

TYPE2_COMPARE_0_WORD_1

RW

32

0x0000 0000

0x0704

TYPE2_COMPARE_1_WORD_0

RW

32

0x0000 0000

0x0708

TYPE2_COMPARE_1_WORD_1

RW

32

0x0000 0000

0x070C

TYPE2_COMPARE_2_WORD_0

RW

32

0x0000 0000

0x0710

TYPE2_COMPARE_2_WORD_1

RW

32

0x0000 0000

0x0714

TYPE2_COMPARE_3_WORD_0

RW

32

0x0000 0000

0x0718

TYPE2_COMPARE_3_WORD_1

RW

32

0x0000 0000

0x071C

TYPE2_COMPARE_4_WORD_0

RW

32

0x0000 0000

0x0720

TYPE2_COMPARE_4_WORD_1

RW

32

0x0000 0000

0x0724

TYPE2_COMPARE_5_WORD_0

RW

32

0x0000 0000

0x0728

TYPE2_COMPARE_5_WORD_1

RW

32

0x0000 0000

0x072C

TYPE2_COMPARE_6_WORD_0

RW

32

0x0000 0000

0x0730

TYPE2_COMPARE_6_WORD_1

RW

32

0x0000 0000

0x0734

TYPE2_COMPARE_7_WORD_0

RW

32

0x0000 0000

0x0738

TYPE2_COMPARE_7_WORD_1

RW

32

0x0000 0000

0x073C

TYPE2_COMPARE_8_WORD_0

RW

32

0x0000 0000

0x0740

TYPE2_COMPARE_8_WORD_1

RW

32

0x0000 0000

0x0744

TYPE2_COMPARE_9_WORD_0

RW

32

0x0000 0000

0x0748

TYPE2_COMPARE_9_WORD_1

RW

32

0x0000 0000

0x074C

TYPE2_COMPARE_10_WORD_0

RW

32

0x0000 0000

0x0750

TYPE2_COMPARE_10_WORD_1

RW

32

0x0000 0000

0x0754

TYPE2_COMPARE_11_WORD_0

RW

32

0x0000 0000

0x0758

TYPE2_COMPARE_11_WORD_1

RW

32

0x0000 0000

0x075C

TYPE2_COMPARE_12_WORD_0

RW

32

0x0000 0000

0x0760

TYPE2_COMPARE_12_WORD_1

RW

32

0x0000 0000

0x0764

TYPE2_COMPARE_13_WORD_0

RW

32

0x0000 0000

0x0768

TYPE2_COMPARE_13_WORD_1

RW

32

0x0000 0000

0x076C

TYPE2_COMPARE_14_WORD_0

RW

32

0x0000 0000

0x0770

TYPE2_COMPARE_14_WORD_1

RW

32

0x0000 0000

0x0774

TYPE2_COMPARE_15_WORD_0

RW

32

0x0000 0000

0x0778

TYPE2_COMPARE_15_WORD_1

RW

32

0x0000 0000

0x077C

TYPE2_COMPARE_16_WORD_0

RW

32

0x0000 0000

0x0780

TYPE2_COMPARE_16_WORD_1

RW

32

0x0000 0000

0x0784

TYPE2_COMPARE_17_WORD_0

RW

32

0x0000 0000

0x0788

TYPE2_COMPARE_17_WORD_1

RW

32

0x0000 0000

0x078C

TYPE2_COMPARE_18_WORD_0

RW

32

0x0000 0000

0x0790

TYPE2_COMPARE_18_WORD_1

RW

32

0x0000 0000

0x0794

TYPE2_COMPARE_19_WORD_0

RW

32

0x0000 0000

0x0798

TYPE2_COMPARE_19_WORD_1

RW

32

0x0000 0000

0x079C

TYPE2_COMPARE_20_WORD_0

RW

32

0x0000 0000

0x07A0

TYPE2_COMPARE_20_WORD_1

RW

32

0x0000 0000

0x07A4

TYPE2_COMPARE_21_WORD_0

RW

32

0x0000 0000

0x07A8

TYPE2_COMPARE_21_WORD_1

RW

32

0x0000 0000

0x07AC

TYPE2_COMPARE_22_WORD_0

RW

32

0x0000 0000

0x07B0

TYPE2_COMPARE_22_WORD_1

RW

32

0x0000 0000

0x07B4

TYPE2_COMPARE_23_WORD_0

RW

32

0x0000 0000

0x07B8

TYPE2_COMPARE_23_WORD_1

RW

32

0x0000 0000

0x07BC

TYPE2_COMPARE_24_WORD_0

RW

32

0x0000 0000

0x07C0

TYPE2_COMPARE_24_WORD_1

RW

32

0x0000 0000

0x07C4

TYPE2_COMPARE_25_WORD_0

RW

32

0x0000 0000

0x07C8

TYPE2_COMPARE_25_WORD_1

RW

32

0x0000 0000

0x07CC

TYPE2_COMPARE_26_WORD_0

RW

32

0x0000 0000

0x07D0

TYPE2_COMPARE_26_WORD_1

RW

32

0x0000 0000

0x07D4

TYPE2_COMPARE_27_WORD_0

RW

32

0x0000 0000

0x07D8

TYPE2_COMPARE_27_WORD_1

RW

32

0x0000 0000

0x07DC

TYPE2_COMPARE_28_WORD_0

RW

32

0x0000 0000

0x07E0

TYPE2_COMPARE_28_WORD_1

RW

32

0x0000 0000

0x07E4

TYPE2_COMPARE_29_WORD_0

RW

32

0x0000 0000

0x07E8

TYPE2_COMPARE_29_WORD_1

RW

32

0x0000 0000

0x07EC

TYPE2_COMPARE_30_WORD_0

RW

32

0x0000 0000

0x07F0

TYPE2_COMPARE_30_WORD_1

RW

32

0x0000 0000

0x07F4

TYPE2_COMPARE_31_WORD_0

RW

32

0x0000 0000

0x07F8

TYPE2_COMPARE_31_WORD_1

RW

32

0x0000 0000

0x07FC

ENST_START_TIME_Q8

RW

32

0x0000 0000

0x0800

ENST_START_TIME_Q9

RW

32

0x0000 0000

0x0804

ENST_START_TIME_Q10

RW

32

0x0000 0000

0x0808

ENST_START_TIME_Q11

RW

32

0x0000 0000

0x080C

ENST_START_TIME_Q12

RW

32

0x0000 0000

0x0810

ENST_START_TIME_Q13

RW

32

0x0000 0000

0x0814

ENST_START_TIME_Q14

RW

32

0x0000 0000

0x0818

ENST_START_TIME_Q15

RW

32

0x0000 0000

0x081C

ENST_ON_TIME_Q8

RW

32

0x0001 FFFF

0x0820

ENST_ON_TIME_Q9

RW

32

0x0001 FFFF

0x0824

ENST_ON_TIME_Q10

RW

32

0x0001 FFFF

0x0828

ENST_ON_TIME_Q11

RW

32

0x0001 FFFF

0x082C

ENST_ON_TIME_Q12

RW

32

0x0001 FFFF

0x0830

ENST_ON_TIME_Q13

RW

32

0x0001 FFFF

0x0834

ENST_ON_TIME_Q14

RW

32

0x0001 FFFF

0x0838

ENST_ON_TIME_Q15

RW

32

0x0001 FFFF

0x083C

ENST_OFF_TIME_Q8

RW

32

0x0000 0000

0x0840

ENST_OFF_TIME_Q9

RW

32

0x0000 0000

0x0844

ENST_OFF_TIME_Q10

RW

32

0x0000 0000

0x0848

ENST_OFF_TIME_Q11

RW

32

0x0000 0000

0x084C

ENST_OFF_TIME_Q12

RW

32

0x0000 0000

0x0850

ENST_OFF_TIME_Q13

RW

32

0x0000 0000

0x0854

ENST_OFF_TIME_Q14

RW

32

0x0000 0000

0x0858

ENST_OFF_TIME_Q15

RW

32

0x0000 0000

0x085C

ENST_CONTROL

RW

32

0x0000 0000

0x0880

RX_Q0_FLUSH

RW

32

0x0000 0000

0x0B00

RX_Q1_FLUSH

RW

32

0x0000 0000

0x0B04

RX_Q2_FLUSH

RW

32

0x0000 0000

0x0B08

RX_Q3_FLUSH

RW

32

0x0000 0000

0x0B0C

RX_Q4_FLUSH

RW

32

0x0000 0000

0x0B10

RX_Q5_FLUSH

RW

32

0x0000 0000

0x0B14

RX_Q6_FLUSH

RW

32

0x0000 0000

0x0B18

RX_Q7_FLUSH

RW

32

0x0000 0000

0x0B1C

RX_Q8_FLUSH

RW

32

0x0000 0000

0x0B20

RX_Q9_FLUSH

RW

32

0x0000 0000

0x0B24

RX_Q10_FLUSH

RW

32

0x0000 0000

0x0B28

RX_Q11_FLUSH

RW

32

0x0000 0000

0x0B2C

RX_Q12_FLUSH

RW

32

0x0000 0000

0x0B30

RX_Q13_FLUSH

RW

32

0x0000 0000

0x0B34

RX_Q14_FLUSH

RW

32

0x0000 0000

0x0B38

RX_Q15_FLUSH

RW

32

0x0000 0000

0x0B3C

SCR2_REG0_RATE_LIMIT

RW

32

0x0000 0000

0x0B40

SCR2_REG1_RATE_LIMIT

RW

32

0x0000 0000

0x0B44

SCR2_REG2_RATE_LIMIT

RW

32

0x0000 0000

0x0B48

SCR2_REG3_RATE_LIMIT

RW

32

0x0000 0000

0x0B4C

SCR2_REG4_RATE_LIMIT

RW

32

0x0000 0000

0x0B50

SCR2_REG5_RATE_LIMIT

RW

32

0x0000 0000

0x0B54

SCR2_REG6_RATE_LIMIT

RW

32

0x0000 0000

0x0B58

SCR2_REG7_RATE_LIMIT

RW

32

0x0000 0000

0x0B5C

SCR2_REG8_RATE_LIMIT

RW

32

0x0000 0000

0x0B60

SCR2_REG9_RATE_LIMIT

RW

32

0x0000 0000

0x0B64

SCR2_REG10_RATE_LIMIT

RW

32

0x0000 0000

0x0B68

SCR2_REG11_RATE_LIMIT

RW

32

0x0000 0000

0x0B6C

SCR2_REG12_RATE_LIMIT

RW

32

0x0000 0000

0x0B70

SCR2_REG13_RATE_LIMIT

RW

32

0x0000 0000

0x0B74

SCR2_REG14_RATE_LIMIT

RW

32

0x0000 0000

0x0B78

SCR2_REG15_RATE_LIMIT

RW

32

0x0000 0000

0x0B7C

SCR2_RATE_STATUS

RO

32

0x0000 0000

0x0B80

ASF_INT_STATUS

RW

32

0x0000 0000

0x0E00

ASF_INT_RAW_STATUS

RW

32

0x0000 0000

0x0E04

ASF_INT_MASK

RW

32

0x0000 0030

0x0E08

ASF_INT_TEST

RW

32

0x0000 0000

0x0E0C

ASF_FATAL_NONFATAL_SELECT

RW

32

0x0000 0030

0x0E10

ASF_TRANS_TO_FAULT_MASK

RW

32

0x0000 000F

0x0E34

ASF_TRANS_TO_FAULT_STATUS

RW

32

0x0000 0000

0x0E38

ASF_PROTOCOL_FAULT_MASK

RW

32

0x003F 01FF

0x0E40

ASF_PROTOCOL_FAULT_STATUS

RW

32

0x0000 0000

0x0E44

gem_gximicrosemi Instances Mapping Summary

gem_gximicrosemi : GEM_A_LO Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

NETWORK_CONTROL

RW

32

0x0000 0000

0x0000

0x2011 0000

NETWORK_CONFIG

RW

32

0x0008 0000

0x0004

0x2011 0004

NETWORK_STATUS

RO

32

0x0000 0004

0x0008

0x2011 0008

DMA_CONFIG

RW

32

0x0002 07C4

0x0010

0x2011 0010

TRANSMIT_STATUS

RW

32

0x0000 0000

0x0014

0x2011 0014

RECEIVE_Q_PTR

RW

32

0x0000 0000

0x0018

0x2011 0018

TRANSMIT_Q_PTR

RW

32

0x0000 0000

0x001C

0x2011 001C

RECEIVE_STATUS

RW

32

0x0000 0000

0x0020

0x2011 0020

INT_STATUS

RW

32

0x0000 0000

0x0024

0x2011 0024

INT_ENABLE

RW

32

0x0000 0000

0x0028

0x2011 0028

INT_DISABLE

RW

32

0x0000 0000

0x002C

0x2011 002C

INT_MASK

RO

32

0xFFFC FCFF

0x0030

0x2011 0030

PHY_MANAGEMENT

RW

32

0x0000 0000

0x0034

0x2011 0034

PAUSE_TIME

RO

32

0x0000 0000

0x0038

0x2011 0038

TX_PAUSE_QUANTUM

RW

32

0x0000 FFFF

0x003C

0x2011 003C

PBUF_TXCUTTHRU

RW

32

0x0000 1FFF

0x0040

0x2011 0040

PBUF_RXCUTTHRU

RW

32

0x0000 07FF

0x0044

0x2011 0044

JUMBO_MAX_LENGTH

RW

32

0x0000 3FFF

0x0048

0x2011 0048

AXI_MAX_PIPELINE

RW

32

0x0000 0101

0x0054

0x2011 0054

RSC_CONTROL

RW

32

0x0000 0000

0x0058

0x2011 0058

INT_MODERATION

RW

32

0x0000 0000

0x005C

0x2011 005C

SYS_WAKE_TIME

RW

32

0x0000 0000

0x0060

0x2011 0060

LOCKUP_CONFIG

RW

32

0x07FF FFFF

0x0068

0x2011 0068

MAC_LOCKUP_TIME

RW

32

0x07FF FFFF

0x006C

0x2011 006C

LOCKUP_CONFIG3

RW

32

0x0000 0000

0x0070

0x2011 0070

RX_WATER_MARK

RW

32

0x0000 0000

0x007C

0x2011 007C

HASH_BOTTOM

RW

32

0x0000 0000

0x0080

0x2011 0080

HASH_TOP

RW

32

0x0000 0000

0x0084

0x2011 0084

SPEC_ADD1_BOTTOM

RW

32

0x0000 0000

0x0088

0x2011 0088

SPEC_ADD1_TOP

RW

32

0x0000 0000

0x008C

0x2011 008C

SPEC_ADD2_BOTTOM

RW

32

0x0000 0000

0x0090

0x2011 0090

SPEC_ADD2_TOP

RW

32

0x0000 0000

0x0094

0x2011 0094

SPEC_ADD3_BOTTOM

RW

32

0x0000 0000

0x0098

0x2011 0098

SPEC_ADD3_TOP

RW

32

0x0000 0000

0x009C

0x2011 009C

SPEC_ADD4_BOTTOM

RW

32

0x0000 0000

0x00A0

0x2011 00A0

SPEC_ADD4_TOP

RW

32

0x0000 0000

0x00A4

0x2011 00A4

SPEC_TYPE1

RW

32

0x0000 0000

0x00A8

0x2011 00A8

SPEC_TYPE2

RW

32

0x0000 0000

0x00AC

0x2011 00AC

SPEC_TYPE3

RW

32

0x0000 0000

0x00B0

0x2011 00B0

SPEC_TYPE4

RW

32

0x0000 0000

0x00B4

0x2011 00B4

WOL_REGISTER

RW

32

0x0000 0000

0x00B8

0x2011 00B8

STRETCH_RATIO

RW

32

0x0000 0000

0x00BC

0x2011 00BC

STACKED_VLAN

RW

32

0x0000 0000

0x00C0

0x2011 00C0

TX_PFC_PAUSE

RW

32

0x0000 0000

0x00C4

0x2011 00C4

MASK_ADD1_BOTTOM

RW

32

0x0000 0000

0x00C8

0x2011 00C8

MASK_ADD1_TOP

RW

32

0x0000 0000

0x00CC

0x2011 00CC

DMA_ADDR_OR_MASK

RW

32

0x0000 0000

0x00D0

0x2011 00D0

RX_PTP_UNICAST

RW

32

0x0000 0000

0x00D4

0x2011 00D4

TX_PTP_UNICAST

RW

32

0x0000 0000

0x00D8

0x2011 00D8

TSU_NSEC_CMP

RW

32

0x0000 0000

0x00DC

0x2011 00DC

TSU_SEC_CMP

RW

32

0x0000 0000

0x00E0

0x2011 00E0

TSU_MSB_SEC_CMP

RW

32

0x0000 0000

0x00E4

0x2011 00E4

TSU_PTP_TX_MSB_SEC

RO

32

0x0000 0000

0x00E8

0x2011 00E8

TSU_PTP_RX_MSB_SEC

RO

32

0x0000 0000

0x00EC

0x2011 00EC

TSU_PEER_TX_MSB_SEC

RO

32

0x0000 0000

0x00F0

0x2011 00F0

TSU_PEER_RX_MSB_SEC

RO

32

0x0000 0000

0x00F4

0x2011 00F4

DPRAM_FILL_DBG

RW

32

0x0000 0000

0x00F8

0x2011 00F8

REVISION_REG

RO

32

0x0107 010C

0x00FC

0x2011 00FC

OCTETS_TXED_BOTTOM

RO

32

0x0000 0000

0x0100

0x2011 0100

OCTETS_TXED_TOP

RO

32

0x0000 0000

0x0104

0x2011 0104

FRAMES_TXED_OK

RO

32

0x0000 0000

0x0108

0x2011 0108

BROADCAST_TXED

RO

32

0x0000 0000

0x010C

0x2011 010C

MULTICAST_TXED

RO

32

0x0000 0000

0x0110

0x2011 0110

PAUSE_FRAMES_TXED

RO

32

0x0000 0000

0x0114

0x2011 0114

FRAMES_TXED_64

RO

32

0x0000 0000

0x0118

0x2011 0118

FRAMES_TXED_65

RO

32

0x0000 0000

0x011C

0x2011 011C

FRAMES_TXED_128

RO

32

0x0000 0000

0x0120

0x2011 0120

FRAMES_TXED_256

RO

32

0x0000 0000

0x0124

0x2011 0124

FRAMES_TXED_512

RO

32

0x0000 0000

0x0128

0x2011 0128

FRAMES_TXED_1024

RO

32

0x0000 0000

0x012C

0x2011 012C

FRAMES_TXED_1519

RO

32

0x0000 0000

0x0130

0x2011 0130

TX_UNDERRUNS

RO

32

0x0000 0000

0x0134

0x2011 0134

SINGLE_COLLISIONS

RO

32

0x0000 0000

0x0138

0x2011 0138

MULTIPLE_COLLISIONS

RO

32

0x0000 0000

0x013C

0x2011 013C

EXCESSIVE_COLLISIONS

RO

32

0x0000 0000

0x0140

0x2011 0140

LATE_COLLISIONS

RO

32

0x0000 0000

0x0144

0x2011 0144

DEFERRED_FRAMES

RO

32

0x0000 0000

0x0148

0x2011 0148

CRS_ERRORS

RO

32

0x0000 0000

0x014C

0x2011 014C

OCTETS_RXED_BOTTOM

RO

32

0x0000 0000

0x0150

0x2011 0150

OCTETS_RXED_TOP

RO

32

0x0000 0000

0x0154

0x2011 0154

FRAMES_RXED_OK

RO

32

0x0000 0000

0x0158

0x2011 0158

BROADCAST_RXED

RO

32

0x0000 0000

0x015C

0x2011 015C

MULTICAST_RXED

RO

32

0x0000 0000

0x0160

0x2011 0160

PAUSE_FRAMES_RXED

RO

32

0x0000 0000

0x0164

0x2011 0164

FRAMES_RXED_64

RO

32

0x0000 0000

0x0168

0x2011 0168

FRAMES_RXED_65

RO

32

0x0000 0000

0x016C

0x2011 016C

FRAMES_RXED_128

RO

32

0x0000 0000

0x0170

0x2011 0170

FRAMES_RXED_256

RO

32

0x0000 0000

0x0174

0x2011 0174

FRAMES_RXED_512

RO

32

0x0000 0000

0x0178

0x2011 0178

FRAMES_RXED_1024

RO

32

0x0000 0000

0x017C

0x2011 017C

FRAMES_RXED_1519

RO

32

0x0000 0000

0x0180

0x2011 0180

UNDERSIZE_FRAMES

RO

32

0x0000 0000

0x0184

0x2011 0184

EXCESSIVE_RX_LENGTH

RO

32

0x0000 0000

0x0188

0x2011 0188

RX_JABBERS

RO

32

0x0000 0000

0x018C

0x2011 018C

FCS_ERRORS

RO

32

0x0000 0000

0x0190

0x2011 0190

RX_LENGTH_ERRORS

RO

32

0x0000 0000

0x0194

0x2011 0194

RX_SYMBOL_ERRORS

RO

32

0x0000 0000

0x0198

0x2011 0198

ALIGNMENT_ERRORS

RO

32

0x0000 0000

0x019C

0x2011 019C

RX_RESOURCE_ERRORS

RO

32

0x0000 0000

0x01A0

0x2011 01A0

RX_OVERRUNS

RO

32

0x0000 0000

0x01A4

0x2011 01A4

RX_IP_CK_ERRORS

RO

32

0x0000 0000

0x01A8

0x2011 01A8

RX_TCP_CK_ERRORS

RO

32

0x0000 0000

0x01AC

0x2011 01AC

RX_UDP_CK_ERRORS

RO

32

0x0000 0000

0x01B0

0x2011 01B0

AUTO_FLUSHED_PKTS

RO

32

0x0000 0000

0x01B4

0x2011 01B4

TSU_TIMER_INCR_SUB_NSEC

RW

32

0x0000 0000

0x01BC

0x2011 01BC

TSU_TIMER_MSB_SEC

RW

32

0x0000 0000

0x01C0

0x2011 01C0

TSU_STROBE_MSB_SEC

RO

32

0x0000 0000

0x01C4

0x2011 01C4

TSU_STROBE_SEC

RO

32

0x0000 0000

0x01C8

0x2011 01C8

TSU_STROBE_NSEC

RO

32

0x0000 0000

0x01CC

0x2011 01CC

TSU_TIMER_SEC

RW

32

0x0000 0000

0x01D0

0x2011 01D0

TSU_TIMER_NSEC

RW

32

0x0000 0000

0x01D4

0x2011 01D4

TSU_TIMER_ADJUST

RW

32

0x0000 0000

0x01D8

0x2011 01D8

TSU_TIMER_INCR

RW

32

0x0000 0000

0x01DC

0x2011 01DC

TSU_PTP_TX_SEC

RO

32

0x0000 0000

0x01E0

0x2011 01E0

TSU_PTP_TX_NSEC

RO

32

0x0000 0000

0x01E4

0x2011 01E4

TSU_PTP_RX_SEC

RO

32

0x0000 0000

0x01E8

0x2011 01E8

TSU_PTP_RX_NSEC

RO

32

0x0000 0000

0x01EC

0x2011 01EC

TSU_PEER_TX_SEC

RO

32

0x0000 0000

0x01F0

0x2011 01F0

TSU_PEER_TX_NSEC

RO

32

0x0000 0000

0x01F4

0x2011 01F4

TSU_PEER_RX_SEC

RO

32

0x0000 0000

0x01F8

0x2011 01F8

TSU_PEER_RX_NSEC

RO

32

0x0000 0000

0x01FC

0x2011 01FC

PFC_STATUS

RO

32

0x0000 0000

0x026C

0x2011 026C

RX_LPI

RO

32

0x0000 0000

0x0270

0x2011 0270

RX_LPI_TIME

RO

32

0x0000 0000

0x0274

0x2011 0274

TX_LPI

RO

32

0x0000 0000

0x0278

0x2011 0278

TX_LPI_TIME

RO

32

0x0000 0000

0x027C

0x2011 027C

DESIGNCFG_DEBUG1

RO

32

0x0850 8511

0x0280

0x2011 0280

DESIGNCFG_DEBUG2

RO

32

0x76F1 3FFF

0x0284

0x2011 0284

DESIGNCFG_DEBUG3

RO

32

0x0400 0000

0x0288

0x2011 0288

DESIGNCFG_DEBUG4

RO

32

0x0000 0000

0x028C

0x2011 028C

DESIGNCFG_DEBUG5

RO

32

0x402F A345

0x0290

0x2011 0290

DESIGNCFG_DEBUG6

RO

32

0x0C84 FFFE

0x0294

0x2011 0294

DESIGNCFG_DEBUG7

RO

32

0x0000 0000

0x0298

0x2011 0298

DESIGNCFG_DEBUG8

RO

32

0x1010 0820

0x029C

0x2011 029C

DESIGNCFG_DEBUG9

RO

32

0x0000 0000

0x02A0

0x2011 02A0

DESIGNCFG_DEBUG10

RO

32

0x2444 4442

0x02A4

0x2011 02A4

DESIGNCFG_DEBUG11

RO

32

0x0000 0000

0x02A8

0x2011 02A8

DESIGNCFG_DEBUG12

RO

32

0x0154 4001

0x02AC

0x2011 02AC

AXI_QOS_CFG_0

RW

32

0x0000 0000

0x02E0

0x2011 02E0

AXI_QOS_CFG_1

RW

32

0x0000 0000

0x02E4

0x2011 02E4

AXI_QOS_CFG_2

RW

32

0x0000 0000

0x02E8

0x2011 02E8

AXI_QOS_CFG_3

RW

32

0x0000 0000

0x02EC

0x2011 02EC

INT_Q1_STATUS

RW

32

0x0000 0000

0x0400

0x2011 0400

INT_Q2_STATUS

RW

32

0x0000 0000

0x0404

0x2011 0404

INT_Q3_STATUS

RW

32

0x0000 0000

0x0408

0x2011 0408

INT_Q4_STATUS

RW

32

0x0000 0000

0x040C

0x2011 040C

INT_Q5_STATUS

RW

32

0x0000 0000

0x0410

0x2011 0410

INT_Q6_STATUS

RW

32

0x0000 0000

0x0414

0x2011 0414

INT_Q7_STATUS

RW

32

0x0000 0000

0x0418

0x2011 0418

INT_Q8_STATUS

RW

32

0x0000 0000

0x041C

0x2011 041C

INT_Q9_STATUS

RW

32

0x0000 0000

0x0420

0x2011 0420

INT_Q10_STATUS

RW

32

0x0000 0000

0x0424

0x2011 0424

INT_Q11_STATUS

RW

32

0x0000 0000

0x0428

0x2011 0428

INT_Q12_STATUS

RW

32

0x0000 0000

0x042C

0x2011 042C

INT_Q13_STATUS

RW

32

0x0000 0000

0x0430

0x2011 0430

INT_Q14_STATUS

RW

32

0x0000 0000

0x0434

0x2011 0434

INT_Q15_STATUS

RW

32

0x0000 0000

0x0438

0x2011 0438

TRANSMIT_Q1_PTR

RW

32

0x0000 0000

0x0440

0x2011 0440

TRANSMIT_Q2_PTR

RW

32

0x0000 0000

0x0444

0x2011 0444

TRANSMIT_Q3_PTR

RW

32

0x0000 0000

0x0448

0x2011 0448

TRANSMIT_Q4_PTR

RW

32

0x0000 0000

0x044C

0x2011 044C

TRANSMIT_Q5_PTR

RW

32

0x0000 0000

0x0450

0x2011 0450

TRANSMIT_Q6_PTR

RW

32

0x0000 0000

0x0454

0x2011 0454

TRANSMIT_Q7_PTR

RW

32

0x0000 0000

0x0458

0x2011 0458

TRANSMIT_Q8_PTR

RW

32

0x0000 0000

0x045C

0x2011 045C

TRANSMIT_Q9_PTR

RW

32

0x0000 0000

0x0460

0x2011 0460

TRANSMIT_Q10_PTR

RW

32

0x0000 0000

0x0464

0x2011 0464

TRANSMIT_Q11_PTR

RW

32

0x0000 0000

0x0468

0x2011 0468

TRANSMIT_Q12_PTR

RW

32

0x0000 0000

0x046C

0x2011 046C

TRANSMIT_Q13_PTR

RW

32

0x0000 0000

0x0470

0x2011 0470

TRANSMIT_Q14_PTR

RW

32

0x0000 0000

0x0474

0x2011 0474

TRANSMIT_Q15_PTR

RW

32

0x0000 0000

0x0478

0x2011 0478

RECEIVE_Q1_PTR

RW

32

0x0000 0000

0x0480

0x2011 0480

RECEIVE_Q2_PTR

RW

32

0x0000 0000

0x0484

0x2011 0484

RECEIVE_Q3_PTR

RW

32

0x0000 0000

0x0488

0x2011 0488

RECEIVE_Q4_PTR

RW

32

0x0000 0000

0x048C

0x2011 048C

RECEIVE_Q5_PTR

RW

32

0x0000 0000

0x0490

0x2011 0490

RECEIVE_Q6_PTR

RW

32

0x0000 0000

0x0494

0x2011 0494

RECEIVE_Q7_PTR

RW

32

0x0000 0000

0x0498

0x2011 0498

DMA_RXBUF_SIZE_Q1

RW

32

0x0000 0002

0x04A0

0x2011 04A0

DMA_RXBUF_SIZE_Q2

RW

32

0x0000 0002

0x04A4

0x2011 04A4

DMA_RXBUF_SIZE_Q3

RW

32

0x0000 0002

0x04A8

0x2011 04A8

DMA_RXBUF_SIZE_Q4

RW

32

0x0000 0002

0x04AC

0x2011 04AC

DMA_RXBUF_SIZE_Q5

RW

32

0x0000 0002

0x04B0

0x2011 04B0

DMA_RXBUF_SIZE_Q6

RW

32

0x0000 0002

0x04B4

0x2011 04B4

DMA_RXBUF_SIZE_Q7

RW

32

0x0000 0002

0x04B8

0x2011 04B8

CBS_CONTROL

RW

32

0x0000 0000

0x04BC

0x2011 04BC

CBS_IDLESLOPE_Q_A

RW

32

0x0000 0000

0x04C0

0x2011 04C0

CBS_IDLESLOPE_Q_B

RW

32

0x0000 0000

0x04C4

0x2011 04C4

UPPER_TX_Q_BASE_ADDR

RW

32

0x0000 0000

0x04C8

0x2011 04C8

TX_BD_CONTROL

RW

32

0x0000 0000

0x04CC

0x2011 04CC

RX_BD_CONTROL

RW

32

0x0000 0000

0x04D0

0x2011 04D0

UPPER_RX_Q_BASE_ADDR

RW

32

0x0000 0000

0x04D4

0x2011 04D4

WD_COUNTER

RW

32

0x0000 0007

0x04EC

0x2011 04EC

AXI_TX_FULL_THRESH0

RW

32

0x0006 0008

0x04F8

0x2011 04F8

AXI_TX_FULL_THRESH1

RW

32

0x0000 0000

0x04FC

0x2011 04FC

SCREENING_TYPE_1_REGISTER_0

RW

32

0x0000 0000

0x0500

0x2011 0500

SCREENING_TYPE_1_REGISTER_1

RW

32

0x0000 0000

0x0504

0x2011 0504

SCREENING_TYPE_1_REGISTER_2

RW

32

0x0000 0000

0x0508

0x2011 0508

SCREENING_TYPE_1_REGISTER_3

RW

32

0x0000 0000

0x050C

0x2011 050C

SCREENING_TYPE_1_REGISTER_4

RW

32

0x0000 0000

0x0510

0x2011 0510

SCREENING_TYPE_1_REGISTER_5

RW

32

0x0000 0000

0x0514

0x2011 0514

SCREENING_TYPE_1_REGISTER_6

RW

32

0x0000 0000

0x0518

0x2011 0518

SCREENING_TYPE_1_REGISTER_7

RW

32

0x0000 0000

0x051C

0x2011 051C

SCREENING_TYPE_1_REGISTER_8

RW

32

0x0000 0000

0x0520

0x2011 0520

SCREENING_TYPE_1_REGISTER_9

RW

32

0x0000 0000

0x0524

0x2011 0524

SCREENING_TYPE_1_REGISTER_10

RW

32

0x0000 0000

0x0528

0x2011 0528

SCREENING_TYPE_1_REGISTER_11

RW

32

0x0000 0000

0x052C

0x2011 052C

SCREENING_TYPE_1_REGISTER_12

RW

32

0x0000 0000

0x0530

0x2011 0530

SCREENING_TYPE_1_REGISTER_13

RW

32

0x0000 0000

0x0534

0x2011 0534

SCREENING_TYPE_1_REGISTER_14

RW

32

0x0000 0000

0x0538

0x2011 0538

SCREENING_TYPE_1_REGISTER_15

RW

32

0x0000 0000

0x053C

0x2011 053C

SCREENING_TYPE_2_REGISTER_0

RW

32

0x0000 0000

0x0540

0x2011 0540

SCREENING_TYPE_2_REGISTER_1

RW

32

0x0000 0000

0x0544

0x2011 0544

SCREENING_TYPE_2_REGISTER_2

RW

32

0x0000 0000

0x0548

0x2011 0548

SCREENING_TYPE_2_REGISTER_3

RW

32

0x0000 0000

0x054C

0x2011 054C

SCREENING_TYPE_2_REGISTER_4

RW

32

0x0000 0000

0x0550

0x2011 0550

SCREENING_TYPE_2_REGISTER_5

RW

32

0x0000 0000

0x0554

0x2011 0554

SCREENING_TYPE_2_REGISTER_6

RW

32

0x0000 0000

0x0558

0x2011 0558

SCREENING_TYPE_2_REGISTER_7

RW

32

0x0000 0000

0x055C

0x2011 055C

SCREENING_TYPE_2_REGISTER_8

RW

32

0x0000 0000

0x0560

0x2011 0560

SCREENING_TYPE_2_REGISTER_9

RW

32

0x0000 0000

0x0564

0x2011 0564

SCREENING_TYPE_2_REGISTER_10

RW

32

0x0000 0000

0x0568

0x2011 0568

SCREENING_TYPE_2_REGISTER_11

RW

32

0x0000 0000

0x056C

0x2011 056C

SCREENING_TYPE_2_REGISTER_12

RW

32

0x0000 0000

0x0570

0x2011 0570

SCREENING_TYPE_2_REGISTER_13

RW

32

0x0000 0000

0x0574

0x2011 0574

SCREENING_TYPE_2_REGISTER_14

RW

32

0x0000 0000

0x0578

0x2011 0578

SCREENING_TYPE_2_REGISTER_15

RW

32

0x0000 0000

0x057C

0x2011 057C

TX_SCHED_CTRL

RW

32

0x0000 0000

0x0580

0x2011 0580

BW_RATE_LIMIT_Q0TO3

RW

32

0x0000 0000

0x0590

0x2011 0590

BW_RATE_LIMIT_Q4TO7

RW

32

0x0000 0000

0x0594

0x2011 0594

BW_RATE_LIMIT_Q8TO11

RW

32

0x0000 0000

0x0598

0x2011 0598

BW_RATE_LIMIT_Q12TO15

RW

32

0x0000 0000

0x059C

0x2011 059C

TX_Q_SEG_ALLOC_Q_LOWER

RW

32

0x0000 0000

0x05A0

0x2011 05A0

TX_Q_SEG_ALLOC_Q_UPPER

RW

32

0x0000 0000

0x05A4

0x2011 05A4

RECEIVE_Q8_PTR

RW

32

0x0000 0000

0x05C0

0x2011 05C0

RECEIVE_Q9_PTR

RW

32

0x0000 0000

0x05C4

0x2011 05C4

RECEIVE_Q10_PTR

RW

32

0x0000 0000

0x05C8

0x2011 05C8

RECEIVE_Q11_PTR

RW

32

0x0000 0000

0x05CC

0x2011 05CC

RECEIVE_Q12_PTR

RW

32

0x0000 0000

0x05D0

0x2011 05D0

RECEIVE_Q13_PTR

RW

32

0x0000 0000

0x05D4

0x2011 05D4

RECEIVE_Q14_PTR

RW

32

0x0000 0000

0x05D8

0x2011 05D8

RECEIVE_Q15_PTR

RW

32

0x0000 0000

0x05DC

0x2011 05DC

DMA_RXBUF_SIZE_Q8

RW

32

0x0000 0002

0x05E0

0x2011 05E0

DMA_RXBUF_SIZE_Q9

RW

32

0x0000 0002

0x05E4

0x2011 05E4

DMA_RXBUF_SIZE_Q10

RW

32

0x0000 0002

0x05E8

0x2011 05E8

DMA_RXBUF_SIZE_Q11

RW

32

0x0000 0002

0x05EC

0x2011 05EC

DMA_RXBUF_SIZE_Q12

RW

32

0x0000 0002

0x05F0

0x2011 05F0

DMA_RXBUF_SIZE_Q13

RW

32

0x0000 0002

0x05F4

0x2011 05F4

DMA_RXBUF_SIZE_Q14

RW

32

0x0000 0002

0x05F8

0x2011 05F8

DMA_RXBUF_SIZE_Q15

RW

32

0x0000 0002

0x05FC

0x2011 05FC

INT_Q1_ENABLE

RW

32

0x0000 0000

0x0600

0x2011 0600

INT_Q2_ENABLE

RW

32

0x0000 0000

0x0604

0x2011 0604

INT_Q3_ENABLE

RW

32

0x0000 0000

0x0608

0x2011 0608

INT_Q4_ENABLE

RW

32

0x0000 0000

0x060C

0x2011 060C

INT_Q5_ENABLE

RW

32

0x0000 0000

0x0610

0x2011 0610

INT_Q6_ENABLE

RW

32

0x0000 0000

0x0614

0x2011 0614

INT_Q7_ENABLE

RW

32

0x0000 0000

0x0618

0x2011 0618

INT_Q1_DISABLE

RW

32

0x0000 0000

0x0620

0x2011 0620

INT_Q2_DISABLE

RW

32

0x0000 0000

0x0624

0x2011 0624

INT_Q3_DISABLE

RW

32

0x0000 0000

0x0628

0x2011 0628

INT_Q4_DISABLE

RW

32

0x0000 0000

0x062C

0x2011 062C

INT_Q5_DISABLE

RW

32

0x0000 0000

0x0630

0x2011 0630

INT_Q6_DISABLE

RW

32

0x0000 0000

0x0634

0x2011 0634

INT_Q7_DISABLE

RW

32

0x0000 0000

0x0638

0x2011 0638

INT_Q1_MASK

RO

32

0x0000 08E6

0x0640

0x2011 0640

INT_Q2_MASK

RO

32

0x0000 08E6

0x0644

0x2011 0644

INT_Q3_MASK

RO

32

0x0000 08E6

0x0648

0x2011 0648

INT_Q4_MASK

RO

32

0x0000 08E6

0x064C

0x2011 064C

INT_Q5_MASK

RO

32

0x0000 08E6

0x0650

0x2011 0650

INT_Q6_MASK

RO

32

0x0000 08E6

0x0654

0x2011 0654

INT_Q7_MASK

RO

32

0x0000 08E6

0x0658

0x2011 0658

INT_Q8_ENABLE

RW

32

0x0000 0000

0x0660

0x2011 0660

INT_Q9_ENABLE

RW

32

0x0000 0000

0x0664

0x2011 0664

INT_Q10_ENABLE

RW

32

0x0000 0000

0x0668

0x2011 0668

INT_Q11_ENABLE

RW

32

0x0000 0000

0x066C

0x2011 066C

INT_Q12_ENABLE

RW

32

0x0000 0000

0x0670

0x2011 0670

INT_Q13_ENABLE

RW

32

0x0000 0000

0x0674

0x2011 0674

INT_Q14_ENABLE

RW

32

0x0000 0000

0x0678

0x2011 0678

INT_Q15_ENABLE

RW

32

0x0000 0000

0x067C

0x2011 067C

INT_Q8_DISABLE

RW

32

0x0000 0000

0x0680

0x2011 0680

INT_Q9_DISABLE

RW

32

0x0000 0000

0x0684

0x2011 0684

INT_Q10_DISABLE

RW

32

0x0000 0000

0x0688

0x2011 0688

INT_Q11_DISABLE

RW

32

0x0000 0000

0x068C

0x2011 068C

INT_Q12_DISABLE

RW

32

0x0000 0000

0x0690

0x2011 0690

INT_Q13_DISABLE

RW

32

0x0000 0000

0x0694

0x2011 0694

INT_Q14_DISABLE

RW

32

0x0000 0000

0x0698

0x2011 0698

INT_Q15_DISABLE

RW

32

0x0000 0000

0x069C

0x2011 069C

INT_Q8_MASK

RO

32

0x0000 08E6

0x06A0

0x2011 06A0

INT_Q9_MASK

RO

32

0x0000 08E6

0x06A4

0x2011 06A4

INT_Q10_MASK

RO

32

0x0000 08E6

0x06A8

0x2011 06A8

INT_Q11_MASK

RO

32

0x0000 08E6

0x06AC

0x2011 06AC

INT_Q12_MASK

RO

32

0x0000 08E6

0x06B0

0x2011 06B0

INT_Q13_MASK

RO

32

0x0000 08E6

0x06B4

0x2011 06B4

INT_Q14_MASK

RO

32

0x0000 08E6

0x06B8

0x2011 06B8

INT_Q15_MASK

RO

32

0x0000 08E6

0x06BC

0x2011 06BC

SCREENING_TYPE_2_ETHERTYPE_REG_0

RW

32

0x0000 0000

0x06E0

0x2011 06E0

SCREENING_TYPE_2_ETHERTYPE_REG_1

RW

32

0x0000 0000

0x06E4

0x2011 06E4

SCREENING_TYPE_2_ETHERTYPE_REG_2

RW

32

0x0000 0000

0x06E8

0x2011 06E8

SCREENING_TYPE_2_ETHERTYPE_REG_3

RW

32

0x0000 0000

0x06EC

0x2011 06EC

SCREENING_TYPE_2_ETHERTYPE_REG_4

RW

32

0x0000 0000

0x06F0

0x2011 06F0

SCREENING_TYPE_2_ETHERTYPE_REG_5

RW

32

0x0000 0000

0x06F4

0x2011 06F4

SCREENING_TYPE_2_ETHERTYPE_REG_6

RW

32

0x0000 0000

0x06F8

0x2011 06F8

SCREENING_TYPE_2_ETHERTYPE_REG_7

RW

32

0x0000 0000

0x06FC

0x2011 06FC

TYPE2_COMPARE_0_WORD_0

RW

32

0x0000 0000

0x0700

0x2011 0700

TYPE2_COMPARE_0_WORD_1

RW

32

0x0000 0000

0x0704

0x2011 0704

TYPE2_COMPARE_1_WORD_0

RW

32

0x0000 0000

0x0708

0x2011 0708

TYPE2_COMPARE_1_WORD_1

RW

32

0x0000 0000

0x070C

0x2011 070C

TYPE2_COMPARE_2_WORD_0

RW

32

0x0000 0000

0x0710

0x2011 0710

TYPE2_COMPARE_2_WORD_1

RW

32

0x0000 0000

0x0714

0x2011 0714

TYPE2_COMPARE_3_WORD_0

RW

32

0x0000 0000

0x0718

0x2011 0718

TYPE2_COMPARE_3_WORD_1

RW

32

0x0000 0000

0x071C

0x2011 071C

TYPE2_COMPARE_4_WORD_0

RW

32

0x0000 0000

0x0720

0x2011 0720

TYPE2_COMPARE_4_WORD_1

RW

32

0x0000 0000

0x0724

0x2011 0724

TYPE2_COMPARE_5_WORD_0

RW

32

0x0000 0000

0x0728

0x2011 0728

TYPE2_COMPARE_5_WORD_1

RW

32

0x0000 0000

0x072C

0x2011 072C

TYPE2_COMPARE_6_WORD_0

RW

32

0x0000 0000

0x0730

0x2011 0730

TYPE2_COMPARE_6_WORD_1

RW

32

0x0000 0000

0x0734

0x2011 0734

TYPE2_COMPARE_7_WORD_0

RW

32

0x0000 0000

0x0738

0x2011 0738

TYPE2_COMPARE_7_WORD_1

RW

32

0x0000 0000

0x073C

0x2011 073C

TYPE2_COMPARE_8_WORD_0

RW

32

0x0000 0000

0x0740

0x2011 0740

TYPE2_COMPARE_8_WORD_1

RW

32

0x0000 0000

0x0744

0x2011 0744

TYPE2_COMPARE_9_WORD_0

RW

32

0x0000 0000

0x0748

0x2011 0748

TYPE2_COMPARE_9_WORD_1

RW

32

0x0000 0000

0x074C

0x2011 074C

TYPE2_COMPARE_10_WORD_0

RW

32

0x0000 0000

0x0750

0x2011 0750

TYPE2_COMPARE_10_WORD_1

RW

32

0x0000 0000

0x0754

0x2011 0754

TYPE2_COMPARE_11_WORD_0

RW

32

0x0000 0000

0x0758

0x2011 0758

TYPE2_COMPARE_11_WORD_1

RW

32

0x0000 0000

0x075C

0x2011 075C

TYPE2_COMPARE_12_WORD_0

RW

32

0x0000 0000

0x0760

0x2011 0760

TYPE2_COMPARE_12_WORD_1

RW

32

0x0000 0000

0x0764

0x2011 0764

TYPE2_COMPARE_13_WORD_0

RW

32

0x0000 0000

0x0768

0x2011 0768

TYPE2_COMPARE_13_WORD_1

RW

32

0x0000 0000

0x076C

0x2011 076C

TYPE2_COMPARE_14_WORD_0

RW

32

0x0000 0000

0x0770

0x2011 0770

TYPE2_COMPARE_14_WORD_1

RW

32

0x0000 0000

0x0774

0x2011 0774

TYPE2_COMPARE_15_WORD_0

RW

32

0x0000 0000

0x0778

0x2011 0778

TYPE2_COMPARE_15_WORD_1

RW

32

0x0000 0000

0x077C

0x2011 077C

TYPE2_COMPARE_16_WORD_0

RW

32

0x0000 0000

0x0780

0x2011 0780

TYPE2_COMPARE_16_WORD_1

RW

32

0x0000 0000

0x0784

0x2011 0784

TYPE2_COMPARE_17_WORD_0

RW

32

0x0000 0000

0x0788

0x2011 0788

TYPE2_COMPARE_17_WORD_1

RW

32

0x0000 0000

0x078C

0x2011 078C

TYPE2_COMPARE_18_WORD_0

RW

32

0x0000 0000

0x0790

0x2011 0790

TYPE2_COMPARE_18_WORD_1

RW

32

0x0000 0000

0x0794

0x2011 0794

TYPE2_COMPARE_19_WORD_0

RW

32

0x0000 0000

0x0798

0x2011 0798

TYPE2_COMPARE_19_WORD_1

RW

32

0x0000 0000

0x079C

0x2011 079C

TYPE2_COMPARE_20_WORD_0

RW

32

0x0000 0000

0x07A0

0x2011 07A0

TYPE2_COMPARE_20_WORD_1

RW

32

0x0000 0000

0x07A4

0x2011 07A4

TYPE2_COMPARE_21_WORD_0

RW

32

0x0000 0000

0x07A8

0x2011 07A8

TYPE2_COMPARE_21_WORD_1

RW

32

0x0000 0000

0x07AC

0x2011 07AC

TYPE2_COMPARE_22_WORD_0

RW

32

0x0000 0000

0x07B0

0x2011 07B0

TYPE2_COMPARE_22_WORD_1

RW

32

0x0000 0000

0x07B4

0x2011 07B4

TYPE2_COMPARE_23_WORD_0

RW

32

0x0000 0000

0x07B8

0x2011 07B8

TYPE2_COMPARE_23_WORD_1

RW

32

0x0000 0000

0x07BC

0x2011 07BC

TYPE2_COMPARE_24_WORD_0

RW

32

0x0000 0000

0x07C0

0x2011 07C0

TYPE2_COMPARE_24_WORD_1

RW

32

0x0000 0000

0x07C4

0x2011 07C4

TYPE2_COMPARE_25_WORD_0

RW

32

0x0000 0000

0x07C8

0x2011 07C8

TYPE2_COMPARE_25_WORD_1

RW

32

0x0000 0000

0x07CC

0x2011 07CC

TYPE2_COMPARE_26_WORD_0

RW

32

0x0000 0000

0x07D0

0x2011 07D0

TYPE2_COMPARE_26_WORD_1

RW

32

0x0000 0000

0x07D4

0x2011 07D4

TYPE2_COMPARE_27_WORD_0

RW

32

0x0000 0000

0x07D8

0x2011 07D8

TYPE2_COMPARE_27_WORD_1

RW

32

0x0000 0000

0x07DC

0x2011 07DC

TYPE2_COMPARE_28_WORD_0

RW

32

0x0000 0000

0x07E0

0x2011 07E0

TYPE2_COMPARE_28_WORD_1

RW

32

0x0000 0000

0x07E4

0x2011 07E4

TYPE2_COMPARE_29_WORD_0

RW

32

0x0000 0000

0x07E8

0x2011 07E8

TYPE2_COMPARE_29_WORD_1

RW

32

0x0000 0000

0x07EC

0x2011 07EC

TYPE2_COMPARE_30_WORD_0

RW

32

0x0000 0000

0x07F0

0x2011 07F0

TYPE2_COMPARE_30_WORD_1

RW

32

0x0000 0000

0x07F4

0x2011 07F4

TYPE2_COMPARE_31_WORD_0

RW

32

0x0000 0000

0x07F8

0x2011 07F8

TYPE2_COMPARE_31_WORD_1

RW

32

0x0000 0000

0x07FC

0x2011 07FC

ENST_START_TIME_Q8

RW

32

0x0000 0000

0x0800

0x2011 0800

ENST_START_TIME_Q9

RW

32

0x0000 0000

0x0804

0x2011 0804

ENST_START_TIME_Q10

RW

32

0x0000 0000

0x0808

0x2011 0808

ENST_START_TIME_Q11

RW

32

0x0000 0000

0x080C

0x2011 080C

ENST_START_TIME_Q12

RW

32

0x0000 0000

0x0810

0x2011 0810

ENST_START_TIME_Q13

RW

32

0x0000 0000

0x0814

0x2011 0814

ENST_START_TIME_Q14

RW

32

0x0000 0000

0x0818

0x2011 0818

ENST_START_TIME_Q15

RW

32

0x0000 0000

0x081C

0x2011 081C

ENST_ON_TIME_Q8

RW

32

0x0001 FFFF

0x0820

0x2011 0820

ENST_ON_TIME_Q9

RW

32

0x0001 FFFF

0x0824

0x2011 0824

ENST_ON_TIME_Q10

RW

32

0x0001 FFFF

0x0828

0x2011 0828

ENST_ON_TIME_Q11

RW

32

0x0001 FFFF

0x082C

0x2011 082C

ENST_ON_TIME_Q12

RW

32

0x0001 FFFF

0x0830

0x2011 0830

ENST_ON_TIME_Q13

RW

32

0x0001 FFFF

0x0834

0x2011 0834

ENST_ON_TIME_Q14

RW

32

0x0001 FFFF

0x0838

0x2011 0838

ENST_ON_TIME_Q15

RW

32

0x0001 FFFF

0x083C

0x2011 083C

ENST_OFF_TIME_Q8

RW

32

0x0000 0000

0x0840

0x2011 0840

ENST_OFF_TIME_Q9

RW

32

0x0000 0000

0x0844

0x2011 0844

ENST_OFF_TIME_Q10

RW

32

0x0000 0000

0x0848

0x2011 0848

ENST_OFF_TIME_Q11

RW

32

0x0000 0000

0x084C

0x2011 084C

ENST_OFF_TIME_Q12

RW

32

0x0000 0000

0x0850

0x2011 0850

ENST_OFF_TIME_Q13

RW

32

0x0000 0000

0x0854

0x2011 0854

ENST_OFF_TIME_Q14

RW

32

0x0000 0000

0x0858

0x2011 0858

ENST_OFF_TIME_Q15

RW

32

0x0000 0000

0x085C

0x2011 085C

ENST_CONTROL

RW

32

0x0000 0000

0x0880

0x2011 0880

RX_Q0_FLUSH

RW

32

0x0000 0000

0x0B00

0x2011 0B00

RX_Q1_FLUSH

RW

32

0x0000 0000

0x0B04

0x2011 0B04

RX_Q2_FLUSH

RW

32

0x0000 0000

0x0B08

0x2011 0B08

RX_Q3_FLUSH

RW

32

0x0000 0000

0x0B0C

0x2011 0B0C

RX_Q4_FLUSH

RW

32

0x0000 0000

0x0B10

0x2011 0B10

RX_Q5_FLUSH

RW

32

0x0000 0000

0x0B14

0x2011 0B14

RX_Q6_FLUSH

RW

32

0x0000 0000

0x0B18

0x2011 0B18

RX_Q7_FLUSH

RW

32

0x0000 0000

0x0B1C

0x2011 0B1C

RX_Q8_FLUSH

RW

32

0x0000 0000

0x0B20

0x2011 0B20

RX_Q9_FLUSH

RW

32

0x0000 0000

0x0B24

0x2011 0B24

RX_Q10_FLUSH

RW

32

0x0000 0000

0x0B28

0x2011 0B28

RX_Q11_FLUSH

RW

32

0x0000 0000

0x0B2C

0x2011 0B2C

RX_Q12_FLUSH

RW

32

0x0000 0000

0x0B30

0x2011 0B30

RX_Q13_FLUSH

RW

32

0x0000 0000

0x0B34

0x2011 0B34

RX_Q14_FLUSH

RW

32

0x0000 0000

0x0B38

0x2011 0B38

RX_Q15_FLUSH

RW

32

0x0000 0000

0x0B3C

0x2011 0B3C

SCR2_REG0_RATE_LIMIT

RW

32

0x0000 0000

0x0B40

0x2011 0B40

SCR2_REG1_RATE_LIMIT

RW

32

0x0000 0000

0x0B44

0x2011 0B44

SCR2_REG2_RATE_LIMIT

RW

32

0x0000 0000

0x0B48

0x2011 0B48

SCR2_REG3_RATE_LIMIT

RW

32

0x0000 0000

0x0B4C

0x2011 0B4C

SCR2_REG4_RATE_LIMIT

RW

32

0x0000 0000

0x0B50

0x2011 0B50

SCR2_REG5_RATE_LIMIT

RW

32

0x0000 0000

0x0B54

0x2011 0B54

SCR2_REG6_RATE_LIMIT

RW

32

0x0000 0000

0x0B58

0x2011 0B58

SCR2_REG7_RATE_LIMIT

RW

32

0x0000 0000

0x0B5C

0x2011 0B5C

SCR2_REG8_RATE_LIMIT

RW

32

0x0000 0000

0x0B60

0x2011 0B60

SCR2_REG9_RATE_LIMIT

RW

32

0x0000 0000

0x0B64

0x2011 0B64

SCR2_REG10_RATE_LIMIT

RW

32

0x0000 0000

0x0B68

0x2011 0B68

SCR2_REG11_RATE_LIMIT

RW

32

0x0000 0000

0x0B6C

0x2011 0B6C

SCR2_REG12_RATE_LIMIT

RW

32

0x0000 0000

0x0B70

0x2011 0B70

SCR2_REG13_RATE_LIMIT

RW

32

0x0000 0000

0x0B74

0x2011 0B74

SCR2_REG14_RATE_LIMIT

RW

32

0x0000 0000

0x0B78

0x2011 0B78

SCR2_REG15_RATE_LIMIT

RW

32

0x0000 0000

0x0B7C

0x2011 0B7C

SCR2_RATE_STATUS

RO

32

0x0000 0000

0x0B80

0x2011 0B80

ASF_INT_STATUS

RW

32

0x0000 0000

0x0E00

0x2011 0E00

ASF_INT_RAW_STATUS

RW

32

0x0000 0000

0x0E04

0x2011 0E04

ASF_INT_MASK

RW

32

0x0000 0030

0x0E08

0x2011 0E08

ASF_INT_TEST

RW

32

0x0000 0000

0x0E0C

0x2011 0E0C

ASF_FATAL_NONFATAL_SELECT

RW

32

0x0000 0030

0x0E10

0x2011 0E10

ASF_TRANS_TO_FAULT_MASK

RW

32

0x0000 000F

0x0E34

0x2011 0E34

ASF_TRANS_TO_FAULT_STATUS

RW

32

0x0000 0000

0x0E38

0x2011 0E38

ASF_PROTOCOL_FAULT_MASK

RW

32

0x003F 01FF

0x0E40

0x2011 0E40

ASF_PROTOCOL_FAULT_STATUS

RW

32

0x0000 0000

0x0E44

0x2011 0E44

 

gem_gximicrosemi : GEM_B_LO Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

NETWORK_CONTROL

RW

32

0x0000 0000

0x0000

0x2011 2000

NETWORK_CONFIG

RW

32

0x0008 0000

0x0004

0x2011 2004

NETWORK_STATUS

RO

32

0x0000 0004

0x0008

0x2011 2008

DMA_CONFIG

RW

32

0x0002 07C4

0x0010

0x2011 2010

TRANSMIT_STATUS

RW

32

0x0000 0000

0x0014

0x2011 2014

RECEIVE_Q_PTR

RW

32

0x0000 0000

0x0018

0x2011 2018

TRANSMIT_Q_PTR

RW

32

0x0000 0000

0x001C

0x2011 201C

RECEIVE_STATUS

RW

32

0x0000 0000

0x0020

0x2011 2020

INT_STATUS

RW

32

0x0000 0000

0x0024

0x2011 2024

INT_ENABLE

RW

32

0x0000 0000

0x0028

0x2011 2028

INT_DISABLE

RW

32

0x0000 0000

0x002C

0x2011 202C

INT_MASK

RO

32

0xFFFC FCFF

0x0030

0x2011 2030

PHY_MANAGEMENT

RW

32

0x0000 0000

0x0034

0x2011 2034

PAUSE_TIME

RO

32

0x0000 0000

0x0038

0x2011 2038

TX_PAUSE_QUANTUM

RW

32

0x0000 FFFF

0x003C

0x2011 203C

PBUF_TXCUTTHRU

RW

32

0x0000 1FFF

0x0040

0x2011 2040

PBUF_RXCUTTHRU

RW

32

0x0000 07FF

0x0044

0x2011 2044

JUMBO_MAX_LENGTH

RW

32

0x0000 3FFF

0x0048

0x2011 2048

AXI_MAX_PIPELINE

RW

32

0x0000 0101

0x0054

0x2011 2054

RSC_CONTROL

RW

32

0x0000 0000

0x0058

0x2011 2058

INT_MODERATION

RW

32

0x0000 0000

0x005C

0x2011 205C

SYS_WAKE_TIME

RW

32

0x0000 0000

0x0060

0x2011 2060

LOCKUP_CONFIG

RW

32

0x07FF FFFF

0x0068

0x2011 2068

MAC_LOCKUP_TIME

RW

32

0x07FF FFFF

0x006C

0x2011 206C

LOCKUP_CONFIG3

RW

32

0x0000 0000

0x0070

0x2011 2070

RX_WATER_MARK

RW

32

0x0000 0000

0x007C

0x2011 207C

HASH_BOTTOM

RW

32

0x0000 0000

0x0080

0x2011 2080

HASH_TOP

RW

32

0x0000 0000

0x0084

0x2011 2084

SPEC_ADD1_BOTTOM

RW

32

0x0000 0000

0x0088

0x2011 2088

SPEC_ADD1_TOP

RW

32

0x0000 0000

0x008C

0x2011 208C

SPEC_ADD2_BOTTOM

RW

32

0x0000 0000

0x0090

0x2011 2090

SPEC_ADD2_TOP

RW

32

0x0000 0000

0x0094

0x2011 2094

SPEC_ADD3_BOTTOM

RW

32

0x0000 0000

0x0098

0x2011 2098

SPEC_ADD3_TOP

RW

32

0x0000 0000

0x009C

0x2011 209C

SPEC_ADD4_BOTTOM

RW

32

0x0000 0000

0x00A0

0x2011 20A0

SPEC_ADD4_TOP

RW

32

0x0000 0000

0x00A4

0x2011 20A4

SPEC_TYPE1

RW

32

0x0000 0000

0x00A8

0x2011 20A8

SPEC_TYPE2

RW

32

0x0000 0000

0x00AC

0x2011 20AC

SPEC_TYPE3

RW

32

0x0000 0000

0x00B0

0x2011 20B0

SPEC_TYPE4

RW

32

0x0000 0000

0x00B4

0x2011 20B4

WOL_REGISTER

RW

32

0x0000 0000

0x00B8

0x2011 20B8

STRETCH_RATIO

RW

32

0x0000 0000

0x00BC

0x2011 20BC

STACKED_VLAN

RW

32

0x0000 0000

0x00C0

0x2011 20C0

TX_PFC_PAUSE

RW

32

0x0000 0000

0x00C4

0x2011 20C4

MASK_ADD1_BOTTOM

RW

32

0x0000 0000

0x00C8

0x2011 20C8

MASK_ADD1_TOP

RW

32

0x0000 0000

0x00CC

0x2011 20CC

DMA_ADDR_OR_MASK

RW

32

0x0000 0000

0x00D0

0x2011 20D0

RX_PTP_UNICAST

RW

32

0x0000 0000

0x00D4

0x2011 20D4

TX_PTP_UNICAST

RW

32

0x0000 0000

0x00D8

0x2011 20D8

TSU_NSEC_CMP

RW

32

0x0000 0000

0x00DC

0x2011 20DC

TSU_SEC_CMP

RW

32

0x0000 0000

0x00E0

0x2011 20E0

TSU_MSB_SEC_CMP

RW

32

0x0000 0000

0x00E4

0x2011 20E4

TSU_PTP_TX_MSB_SEC

RO

32

0x0000 0000

0x00E8

0x2011 20E8

TSU_PTP_RX_MSB_SEC

RO

32

0x0000 0000

0x00EC

0x2011 20EC

TSU_PEER_TX_MSB_SEC

RO

32

0x0000 0000

0x00F0

0x2011 20F0

TSU_PEER_RX_MSB_SEC

RO

32

0x0000 0000

0x00F4

0x2011 20F4

DPRAM_FILL_DBG

RW

32

0x0000 0000

0x00F8

0x2011 20F8

REVISION_REG

RO

32

0x0107 010C

0x00FC

0x2011 20FC

OCTETS_TXED_BOTTOM

RO

32

0x0000 0000

0x0100

0x2011 2100

OCTETS_TXED_TOP

RO

32

0x0000 0000

0x0104

0x2011 2104

FRAMES_TXED_OK

RO

32

0x0000 0000

0x0108

0x2011 2108

BROADCAST_TXED

RO

32

0x0000 0000

0x010C

0x2011 210C

MULTICAST_TXED

RO

32

0x0000 0000

0x0110

0x2011 2110

PAUSE_FRAMES_TXED

RO

32

0x0000 0000

0x0114

0x2011 2114

FRAMES_TXED_64

RO

32

0x0000 0000

0x0118

0x2011 2118

FRAMES_TXED_65

RO

32

0x0000 0000

0x011C

0x2011 211C

FRAMES_TXED_128

RO

32

0x0000 0000

0x0120

0x2011 2120

FRAMES_TXED_256

RO

32

0x0000 0000

0x0124

0x2011 2124

FRAMES_TXED_512

RO

32

0x0000 0000

0x0128

0x2011 2128

FRAMES_TXED_1024

RO

32

0x0000 0000

0x012C

0x2011 212C

FRAMES_TXED_1519

RO

32

0x0000 0000

0x0130

0x2011 2130

TX_UNDERRUNS

RO

32

0x0000 0000

0x0134

0x2011 2134

SINGLE_COLLISIONS

RO

32

0x0000 0000

0x0138

0x2011 2138

MULTIPLE_COLLISIONS

RO

32

0x0000 0000

0x013C

0x2011 213C

EXCESSIVE_COLLISIONS

RO

32

0x0000 0000

0x0140

0x2011 2140

LATE_COLLISIONS

RO

32

0x0000 0000

0x0144

0x2011 2144

DEFERRED_FRAMES

RO

32

0x0000 0000

0x0148

0x2011 2148

CRS_ERRORS

RO

32

0x0000 0000

0x014C

0x2011 214C

OCTETS_RXED_BOTTOM

RO

32

0x0000 0000

0x0150

0x2011 2150

OCTETS_RXED_TOP

RO

32

0x0000 0000

0x0154

0x2011 2154

FRAMES_RXED_OK

RO

32

0x0000 0000

0x0158

0x2011 2158

BROADCAST_RXED

RO

32

0x0000 0000

0x015C

0x2011 215C

MULTICAST_RXED

RO

32

0x0000 0000

0x0160

0x2011 2160

PAUSE_FRAMES_RXED

RO

32

0x0000 0000

0x0164

0x2011 2164

FRAMES_RXED_64

RO

32

0x0000 0000

0x0168

0x2011 2168

FRAMES_RXED_65

RO

32

0x0000 0000

0x016C

0x2011 216C

FRAMES_RXED_128

RO

32

0x0000 0000

0x0170

0x2011 2170

FRAMES_RXED_256

RO

32

0x0000 0000

0x0174

0x2011 2174

FRAMES_RXED_512

RO

32

0x0000 0000

0x0178

0x2011 2178

FRAMES_RXED_1024

RO

32

0x0000 0000

0x017C

0x2011 217C

FRAMES_RXED_1519

RO

32

0x0000 0000

0x0180

0x2011 2180

UNDERSIZE_FRAMES

RO

32

0x0000 0000

0x0184

0x2011 2184

EXCESSIVE_RX_LENGTH

RO

32

0x0000 0000

0x0188

0x2011 2188

RX_JABBERS

RO

32

0x0000 0000

0x018C

0x2011 218C

FCS_ERRORS

RO

32

0x0000 0000

0x0190

0x2011 2190

RX_LENGTH_ERRORS

RO

32

0x0000 0000

0x0194

0x2011 2194

RX_SYMBOL_ERRORS

RO

32

0x0000 0000

0x0198

0x2011 2198

ALIGNMENT_ERRORS

RO

32

0x0000 0000

0x019C

0x2011 219C

RX_RESOURCE_ERRORS

RO

32

0x0000 0000

0x01A0

0x2011 21A0

RX_OVERRUNS

RO

32

0x0000 0000

0x01A4

0x2011 21A4

RX_IP_CK_ERRORS

RO

32

0x0000 0000

0x01A8

0x2011 21A8

RX_TCP_CK_ERRORS

RO

32

0x0000 0000

0x01AC

0x2011 21AC

RX_UDP_CK_ERRORS

RO

32

0x0000 0000

0x01B0

0x2011 21B0

AUTO_FLUSHED_PKTS

RO

32

0x0000 0000

0x01B4

0x2011 21B4

TSU_TIMER_INCR_SUB_NSEC

RW

32

0x0000 0000

0x01BC

0x2011 21BC

TSU_TIMER_MSB_SEC

RW

32

0x0000 0000

0x01C0

0x2011 21C0

TSU_STROBE_MSB_SEC

RO

32

0x0000 0000

0x01C4

0x2011 21C4

TSU_STROBE_SEC

RO

32

0x0000 0000

0x01C8

0x2011 21C8

TSU_STROBE_NSEC

RO

32

0x0000 0000

0x01CC

0x2011 21CC

TSU_TIMER_SEC

RW

32

0x0000 0000

0x01D0

0x2011 21D0

TSU_TIMER_NSEC

RW

32

0x0000 0000

0x01D4

0x2011 21D4

TSU_TIMER_ADJUST

RW

32

0x0000 0000

0x01D8

0x2011 21D8

TSU_TIMER_INCR

RW

32

0x0000 0000

0x01DC

0x2011 21DC

TSU_PTP_TX_SEC

RO

32

0x0000 0000

0x01E0

0x2011 21E0

TSU_PTP_TX_NSEC

RO

32

0x0000 0000

0x01E4

0x2011 21E4

TSU_PTP_RX_SEC

RO

32

0x0000 0000

0x01E8

0x2011 21E8

TSU_PTP_RX_NSEC

RO

32

0x0000 0000

0x01EC

0x2011 21EC

TSU_PEER_TX_SEC

RO

32

0x0000 0000

0x01F0

0x2011 21F0

TSU_PEER_TX_NSEC

RO

32

0x0000 0000

0x01F4

0x2011 21F4

TSU_PEER_RX_SEC

RO

32

0x0000 0000

0x01F8

0x2011 21F8

TSU_PEER_RX_NSEC

RO

32

0x0000 0000

0x01FC

0x2011 21FC

PFC_STATUS

RO

32

0x0000 0000

0x026C

0x2011 226C

RX_LPI

RO

32

0x0000 0000

0x0270

0x2011 2270

RX_LPI_TIME

RO

32

0x0000 0000

0x0274

0x2011 2274

TX_LPI

RO

32

0x0000 0000

0x0278

0x2011 2278

TX_LPI_TIME

RO

32

0x0000 0000

0x027C

0x2011 227C

DESIGNCFG_DEBUG1

RO

32

0x0850 8511

0x0280

0x2011 2280

DESIGNCFG_DEBUG2

RO

32

0x76F1 3FFF

0x0284

0x2011 2284

DESIGNCFG_DEBUG3

RO

32

0x0400 0000

0x0288

0x2011 2288

DESIGNCFG_DEBUG4

RO

32

0x0000 0000

0x028C

0x2011 228C

DESIGNCFG_DEBUG5

RO

32

0x402F A345

0x0290

0x2011 2290

DESIGNCFG_DEBUG6

RO

32

0x0C84 FFFE

0x0294

0x2011 2294

DESIGNCFG_DEBUG7

RO

32

0x0000 0000

0x0298

0x2011 2298

DESIGNCFG_DEBUG8

RO

32

0x1010 0820

0x029C

0x2011 229C

DESIGNCFG_DEBUG9

RO

32

0x0000 0000

0x02A0

0x2011 22A0

DESIGNCFG_DEBUG10

RO

32

0x2444 4442

0x02A4

0x2011 22A4

DESIGNCFG_DEBUG11

RO

32

0x0000 0000

0x02A8

0x2011 22A8

DESIGNCFG_DEBUG12

RO

32

0x0154 4001

0x02AC

0x2011 22AC

AXI_QOS_CFG_0

RW

32

0x0000 0000

0x02E0

0x2011 22E0

AXI_QOS_CFG_1

RW

32

0x0000 0000

0x02E4

0x2011 22E4

AXI_QOS_CFG_2

RW

32

0x0000 0000

0x02E8

0x2011 22E8

AXI_QOS_CFG_3

RW

32

0x0000 0000

0x02EC

0x2011 22EC

INT_Q1_STATUS

RW

32

0x0000 0000

0x0400

0x2011 2400

INT_Q2_STATUS

RW

32

0x0000 0000

0x0404

0x2011 2404

INT_Q3_STATUS

RW

32

0x0000 0000

0x0408

0x2011 2408

INT_Q4_STATUS

RW

32

0x0000 0000

0x040C

0x2011 240C

INT_Q5_STATUS

RW

32

0x0000 0000

0x0410

0x2011 2410

INT_Q6_STATUS

RW

32

0x0000 0000

0x0414

0x2011 2414

INT_Q7_STATUS

RW

32

0x0000 0000

0x0418

0x2011 2418

INT_Q8_STATUS

RW

32

0x0000 0000

0x041C

0x2011 241C

INT_Q9_STATUS

RW

32

0x0000 0000

0x0420

0x2011 2420

INT_Q10_STATUS

RW

32

0x0000 0000

0x0424

0x2011 2424

INT_Q11_STATUS

RW

32

0x0000 0000

0x0428

0x2011 2428

INT_Q12_STATUS

RW

32

0x0000 0000

0x042C

0x2011 242C

INT_Q13_STATUS

RW

32

0x0000 0000

0x0430

0x2011 2430

INT_Q14_STATUS

RW

32

0x0000 0000

0x0434

0x2011 2434

INT_Q15_STATUS

RW

32

0x0000 0000

0x0438

0x2011 2438

TRANSMIT_Q1_PTR

RW

32

0x0000 0000

0x0440

0x2011 2440

TRANSMIT_Q2_PTR

RW

32

0x0000 0000

0x0444

0x2011 2444

TRANSMIT_Q3_PTR

RW

32

0x0000 0000

0x0448

0x2011 2448

TRANSMIT_Q4_PTR

RW

32

0x0000 0000

0x044C

0x2011 244C

TRANSMIT_Q5_PTR

RW

32

0x0000 0000

0x0450

0x2011 2450

TRANSMIT_Q6_PTR

RW

32

0x0000 0000

0x0454

0x2011 2454

TRANSMIT_Q7_PTR

RW

32

0x0000 0000

0x0458

0x2011 2458

TRANSMIT_Q8_PTR

RW

32

0x0000 0000

0x045C

0x2011 245C

TRANSMIT_Q9_PTR

RW

32

0x0000 0000

0x0460

0x2011 2460

TRANSMIT_Q10_PTR

RW

32

0x0000 0000

0x0464

0x2011 2464

TRANSMIT_Q11_PTR

RW

32

0x0000 0000

0x0468

0x2011 2468

TRANSMIT_Q12_PTR

RW

32

0x0000 0000

0x046C

0x2011 246C

TRANSMIT_Q13_PTR

RW

32

0x0000 0000

0x0470

0x2011 2470

TRANSMIT_Q14_PTR

RW

32

0x0000 0000

0x0474

0x2011 2474

TRANSMIT_Q15_PTR

RW

32

0x0000 0000

0x0478

0x2011 2478

RECEIVE_Q1_PTR

RW

32

0x0000 0000

0x0480

0x2011 2480

RECEIVE_Q2_PTR

RW

32

0x0000 0000

0x0484

0x2011 2484

RECEIVE_Q3_PTR

RW

32

0x0000 0000

0x0488

0x2011 2488

RECEIVE_Q4_PTR

RW

32

0x0000 0000

0x048C

0x2011 248C

RECEIVE_Q5_PTR

RW

32

0x0000 0000

0x0490

0x2011 2490

RECEIVE_Q6_PTR

RW

32

0x0000 0000

0x0494

0x2011 2494

RECEIVE_Q7_PTR

RW

32

0x0000 0000

0x0498

0x2011 2498

DMA_RXBUF_SIZE_Q1

RW

32

0x0000 0002

0x04A0

0x2011 24A0

DMA_RXBUF_SIZE_Q2

RW

32

0x0000 0002

0x04A4

0x2011 24A4

DMA_RXBUF_SIZE_Q3

RW

32

0x0000 0002

0x04A8

0x2011 24A8

DMA_RXBUF_SIZE_Q4

RW

32

0x0000 0002

0x04AC

0x2011 24AC

DMA_RXBUF_SIZE_Q5

RW

32

0x0000 0002

0x04B0

0x2011 24B0

DMA_RXBUF_SIZE_Q6

RW

32

0x0000 0002

0x04B4

0x2011 24B4

DMA_RXBUF_SIZE_Q7

RW

32

0x0000 0002

0x04B8

0x2011 24B8

CBS_CONTROL

RW

32

0x0000 0000

0x04BC

0x2011 24BC

CBS_IDLESLOPE_Q_A

RW

32

0x0000 0000

0x04C0

0x2011 24C0

CBS_IDLESLOPE_Q_B

RW

32

0x0000 0000

0x04C4

0x2011 24C4

UPPER_TX_Q_BASE_ADDR

RW

32

0x0000 0000

0x04C8

0x2011 24C8

TX_BD_CONTROL

RW

32

0x0000 0000

0x04CC

0x2011 24CC

RX_BD_CONTROL

RW

32

0x0000 0000

0x04D0

0x2011 24D0

UPPER_RX_Q_BASE_ADDR

RW

32

0x0000 0000

0x04D4

0x2011 24D4

WD_COUNTER

RW

32

0x0000 0007

0x04EC

0x2011 24EC

AXI_TX_FULL_THRESH0

RW

32

0x0006 0008

0x04F8

0x2011 24F8

AXI_TX_FULL_THRESH1

RW

32

0x0000 0000

0x04FC

0x2011 24FC

SCREENING_TYPE_1_REGISTER_0

RW

32

0x0000 0000

0x0500

0x2011 2500

SCREENING_TYPE_1_REGISTER_1

RW

32

0x0000 0000

0x0504

0x2011 2504

SCREENING_TYPE_1_REGISTER_2

RW

32

0x0000 0000

0x0508

0x2011 2508

SCREENING_TYPE_1_REGISTER_3

RW

32

0x0000 0000

0x050C

0x2011 250C

SCREENING_TYPE_1_REGISTER_4

RW

32

0x0000 0000

0x0510

0x2011 2510

SCREENING_TYPE_1_REGISTER_5

RW

32

0x0000 0000

0x0514

0x2011 2514

SCREENING_TYPE_1_REGISTER_6

RW

32

0x0000 0000

0x0518

0x2011 2518

SCREENING_TYPE_1_REGISTER_7

RW

32

0x0000 0000

0x051C

0x2011 251C

SCREENING_TYPE_1_REGISTER_8

RW

32

0x0000 0000

0x0520

0x2011 2520

SCREENING_TYPE_1_REGISTER_9

RW

32

0x0000 0000

0x0524

0x2011 2524

SCREENING_TYPE_1_REGISTER_10

RW

32

0x0000 0000

0x0528

0x2011 2528

SCREENING_TYPE_1_REGISTER_11

RW

32

0x0000 0000

0x052C

0x2011 252C

SCREENING_TYPE_1_REGISTER_12

RW

32

0x0000 0000

0x0530

0x2011 2530

SCREENING_TYPE_1_REGISTER_13

RW

32

0x0000 0000

0x0534

0x2011 2534

SCREENING_TYPE_1_REGISTER_14

RW

32

0x0000 0000

0x0538

0x2011 2538

SCREENING_TYPE_1_REGISTER_15

RW

32

0x0000 0000

0x053C

0x2011 253C

SCREENING_TYPE_2_REGISTER_0

RW

32

0x0000 0000

0x0540

0x2011 2540

SCREENING_TYPE_2_REGISTER_1

RW

32

0x0000 0000

0x0544

0x2011 2544

SCREENING_TYPE_2_REGISTER_2

RW

32

0x0000 0000

0x0548

0x2011 2548

SCREENING_TYPE_2_REGISTER_3

RW

32

0x0000 0000

0x054C

0x2011 254C

SCREENING_TYPE_2_REGISTER_4

RW

32

0x0000 0000

0x0550

0x2011 2550

SCREENING_TYPE_2_REGISTER_5

RW

32

0x0000 0000

0x0554

0x2011 2554

SCREENING_TYPE_2_REGISTER_6

RW

32

0x0000 0000

0x0558

0x2011 2558

SCREENING_TYPE_2_REGISTER_7

RW

32

0x0000 0000

0x055C

0x2011 255C

SCREENING_TYPE_2_REGISTER_8

RW

32

0x0000 0000

0x0560

0x2011 2560

SCREENING_TYPE_2_REGISTER_9

RW

32

0x0000 0000

0x0564

0x2011 2564

SCREENING_TYPE_2_REGISTER_10

RW

32

0x0000 0000

0x0568

0x2011 2568

SCREENING_TYPE_2_REGISTER_11

RW

32

0x0000 0000

0x056C

0x2011 256C

SCREENING_TYPE_2_REGISTER_12

RW

32

0x0000 0000

0x0570

0x2011 2570

SCREENING_TYPE_2_REGISTER_13

RW

32

0x0000 0000

0x0574

0x2011 2574

SCREENING_TYPE_2_REGISTER_14

RW

32

0x0000 0000

0x0578

0x2011 2578

SCREENING_TYPE_2_REGISTER_15

RW

32

0x0000 0000

0x057C

0x2011 257C

TX_SCHED_CTRL

RW

32

0x0000 0000

0x0580

0x2011 2580

BW_RATE_LIMIT_Q0TO3

RW

32

0x0000 0000

0x0590

0x2011 2590

BW_RATE_LIMIT_Q4TO7

RW

32

0x0000 0000

0x0594

0x2011 2594

BW_RATE_LIMIT_Q8TO11

RW

32

0x0000 0000

0x0598

0x2011 2598

BW_RATE_LIMIT_Q12TO15

RW

32

0x0000 0000

0x059C

0x2011 259C

TX_Q_SEG_ALLOC_Q_LOWER

RW

32

0x0000 0000

0x05A0

0x2011 25A0

TX_Q_SEG_ALLOC_Q_UPPER

RW

32

0x0000 0000

0x05A4

0x2011 25A4

RECEIVE_Q8_PTR

RW

32

0x0000 0000

0x05C0

0x2011 25C0

RECEIVE_Q9_PTR

RW

32

0x0000 0000

0x05C4

0x2011 25C4

RECEIVE_Q10_PTR

RW

32

0x0000 0000

0x05C8

0x2011 25C8

RECEIVE_Q11_PTR

RW

32

0x0000 0000

0x05CC

0x2011 25CC

RECEIVE_Q12_PTR

RW

32

0x0000 0000

0x05D0

0x2011 25D0

RECEIVE_Q13_PTR

RW

32

0x0000 0000

0x05D4

0x2011 25D4

RECEIVE_Q14_PTR

RW

32

0x0000 0000

0x05D8

0x2011 25D8

RECEIVE_Q15_PTR

RW

32

0x0000 0000

0x05DC

0x2011 25DC

DMA_RXBUF_SIZE_Q8

RW

32

0x0000 0002

0x05E0

0x2011 25E0

DMA_RXBUF_SIZE_Q9

RW

32

0x0000 0002

0x05E4

0x2011 25E4

DMA_RXBUF_SIZE_Q10

RW

32

0x0000 0002

0x05E8

0x2011 25E8

DMA_RXBUF_SIZE_Q11

RW

32

0x0000 0002

0x05EC

0x2011 25EC

DMA_RXBUF_SIZE_Q12

RW

32

0x0000 0002

0x05F0

0x2011 25F0

DMA_RXBUF_SIZE_Q13

RW

32

0x0000 0002

0x05F4

0x2011 25F4

DMA_RXBUF_SIZE_Q14

RW

32

0x0000 0002

0x05F8

0x2011 25F8

DMA_RXBUF_SIZE_Q15

RW

32

0x0000 0002

0x05FC

0x2011 25FC

INT_Q1_ENABLE

RW

32

0x0000 0000

0x0600

0x2011 2600

INT_Q2_ENABLE

RW

32

0x0000 0000

0x0604

0x2011 2604

INT_Q3_ENABLE

RW

32

0x0000 0000

0x0608

0x2011 2608

INT_Q4_ENABLE

RW

32

0x0000 0000

0x060C

0x2011 260C

INT_Q5_ENABLE

RW

32

0x0000 0000

0x0610

0x2011 2610

INT_Q6_ENABLE

RW

32

0x0000 0000

0x0614

0x2011 2614

INT_Q7_ENABLE

RW

32

0x0000 0000

0x0618

0x2011 2618

INT_Q1_DISABLE

RW

32

0x0000 0000

0x0620

0x2011 2620

INT_Q2_DISABLE

RW

32

0x0000 0000

0x0624

0x2011 2624

INT_Q3_DISABLE

RW

32

0x0000 0000

0x0628

0x2011 2628

INT_Q4_DISABLE

RW

32

0x0000 0000

0x062C

0x2011 262C

INT_Q5_DISABLE

RW

32

0x0000 0000

0x0630

0x2011 2630

INT_Q6_DISABLE

RW

32

0x0000 0000

0x0634

0x2011 2634

INT_Q7_DISABLE

RW

32

0x0000 0000

0x0638

0x2011 2638

INT_Q1_MASK

RO

32

0x0000 08E6

0x0640

0x2011 2640

INT_Q2_MASK

RO

32

0x0000 08E6

0x0644

0x2011 2644

INT_Q3_MASK

RO

32

0x0000 08E6

0x0648

0x2011 2648

INT_Q4_MASK

RO

32

0x0000 08E6

0x064C

0x2011 264C

INT_Q5_MASK

RO

32

0x0000 08E6

0x0650

0x2011 2650

INT_Q6_MASK

RO

32

0x0000 08E6

0x0654

0x2011 2654

INT_Q7_MASK

RO

32

0x0000 08E6

0x0658

0x2011 2658

INT_Q8_ENABLE

RW

32

0x0000 0000

0x0660

0x2011 2660

INT_Q9_ENABLE

RW

32

0x0000 0000

0x0664

0x2011 2664

INT_Q10_ENABLE

RW

32

0x0000 0000

0x0668

0x2011 2668

INT_Q11_ENABLE

RW

32

0x0000 0000

0x066C

0x2011 266C

INT_Q12_ENABLE

RW

32

0x0000 0000

0x0670

0x2011 2670

INT_Q13_ENABLE

RW

32

0x0000 0000

0x0674

0x2011 2674

INT_Q14_ENABLE

RW

32

0x0000 0000

0x0678

0x2011 2678

INT_Q15_ENABLE

RW

32

0x0000 0000

0x067C

0x2011 267C

INT_Q8_DISABLE

RW

32

0x0000 0000

0x0680

0x2011 2680

INT_Q9_DISABLE

RW

32

0x0000 0000

0x0684

0x2011 2684

INT_Q10_DISABLE

RW

32

0x0000 0000

0x0688

0x2011 2688

INT_Q11_DISABLE

RW

32

0x0000 0000

0x068C

0x2011 268C

INT_Q12_DISABLE

RW

32

0x0000 0000

0x0690

0x2011 2690

INT_Q13_DISABLE

RW

32

0x0000 0000

0x0694

0x2011 2694

INT_Q14_DISABLE

RW

32

0x0000 0000

0x0698

0x2011 2698

INT_Q15_DISABLE

RW

32

0x0000 0000

0x069C

0x2011 269C

INT_Q8_MASK

RO

32

0x0000 08E6

0x06A0

0x2011 26A0

INT_Q9_MASK

RO

32

0x0000 08E6

0x06A4

0x2011 26A4

INT_Q10_MASK

RO

32

0x0000 08E6

0x06A8

0x2011 26A8

INT_Q11_MASK

RO

32

0x0000 08E6

0x06AC

0x2011 26AC

INT_Q12_MASK

RO

32

0x0000 08E6

0x06B0

0x2011 26B0

INT_Q13_MASK

RO

32

0x0000 08E6

0x06B4

0x2011 26B4

INT_Q14_MASK

RO

32

0x0000 08E6

0x06B8

0x2011 26B8

INT_Q15_MASK

RO

32

0x0000 08E6

0x06BC

0x2011 26BC

SCREENING_TYPE_2_ETHERTYPE_REG_0

RW

32

0x0000 0000

0x06E0

0x2011 26E0

SCREENING_TYPE_2_ETHERTYPE_REG_1

RW

32

0x0000 0000

0x06E4

0x2011 26E4

SCREENING_TYPE_2_ETHERTYPE_REG_2

RW

32

0x0000 0000

0x06E8

0x2011 26E8

SCREENING_TYPE_2_ETHERTYPE_REG_3

RW

32

0x0000 0000

0x06EC

0x2011 26EC

SCREENING_TYPE_2_ETHERTYPE_REG_4

RW

32

0x0000 0000

0x06F0

0x2011 26F0

SCREENING_TYPE_2_ETHERTYPE_REG_5

RW

32

0x0000 0000

0x06F4

0x2011 26F4

SCREENING_TYPE_2_ETHERTYPE_REG_6

RW

32

0x0000 0000

0x06F8

0x2011 26F8

SCREENING_TYPE_2_ETHERTYPE_REG_7

RW

32

0x0000 0000

0x06FC

0x2011 26FC

TYPE2_COMPARE_0_WORD_0

RW

32

0x0000 0000

0x0700

0x2011 2700

TYPE2_COMPARE_0_WORD_1

RW

32

0x0000 0000

0x0704

0x2011 2704

TYPE2_COMPARE_1_WORD_0

RW

32

0x0000 0000

0x0708

0x2011 2708

TYPE2_COMPARE_1_WORD_1

RW

32

0x0000 0000

0x070C

0x2011 270C

TYPE2_COMPARE_2_WORD_0

RW

32

0x0000 0000

0x0710

0x2011 2710

TYPE2_COMPARE_2_WORD_1

RW

32

0x0000 0000

0x0714

0x2011 2714

TYPE2_COMPARE_3_WORD_0

RW

32

0x0000 0000

0x0718

0x2011 2718

TYPE2_COMPARE_3_WORD_1

RW

32

0x0000 0000

0x071C

0x2011 271C

TYPE2_COMPARE_4_WORD_0

RW

32

0x0000 0000

0x0720

0x2011 2720

TYPE2_COMPARE_4_WORD_1

RW

32

0x0000 0000

0x0724

0x2011 2724

TYPE2_COMPARE_5_WORD_0

RW

32

0x0000 0000

0x0728

0x2011 2728

TYPE2_COMPARE_5_WORD_1

RW

32

0x0000 0000

0x072C

0x2011 272C

TYPE2_COMPARE_6_WORD_0

RW

32

0x0000 0000

0x0730

0x2011 2730

TYPE2_COMPARE_6_WORD_1

RW

32

0x0000 0000

0x0734

0x2011 2734

TYPE2_COMPARE_7_WORD_0

RW

32

0x0000 0000

0x0738

0x2011 2738

TYPE2_COMPARE_7_WORD_1

RW

32

0x0000 0000

0x073C

0x2011 273C

TYPE2_COMPARE_8_WORD_0

RW

32

0x0000 0000

0x0740

0x2011 2740

TYPE2_COMPARE_8_WORD_1

RW

32

0x0000 0000

0x0744

0x2011 2744

TYPE2_COMPARE_9_WORD_0

RW

32

0x0000 0000

0x0748

0x2011 2748

TYPE2_COMPARE_9_WORD_1

RW

32

0x0000 0000

0x074C

0x2011 274C

TYPE2_COMPARE_10_WORD_0

RW

32

0x0000 0000

0x0750

0x2011 2750

TYPE2_COMPARE_10_WORD_1

RW

32

0x0000 0000

0x0754

0x2011 2754

TYPE2_COMPARE_11_WORD_0

RW

32

0x0000 0000

0x0758

0x2011 2758

TYPE2_COMPARE_11_WORD_1

RW

32

0x0000 0000

0x075C

0x2011 275C

TYPE2_COMPARE_12_WORD_0

RW

32

0x0000 0000

0x0760

0x2011 2760

TYPE2_COMPARE_12_WORD_1

RW

32

0x0000 0000

0x0764

0x2011 2764

TYPE2_COMPARE_13_WORD_0

RW

32

0x0000 0000

0x0768

0x2011 2768

TYPE2_COMPARE_13_WORD_1

RW

32

0x0000 0000

0x076C

0x2011 276C

TYPE2_COMPARE_14_WORD_0

RW

32

0x0000 0000

0x0770

0x2011 2770

TYPE2_COMPARE_14_WORD_1

RW

32

0x0000 0000

0x0774

0x2011 2774

TYPE2_COMPARE_15_WORD_0

RW

32

0x0000 0000

0x0778

0x2011 2778

TYPE2_COMPARE_15_WORD_1

RW

32

0x0000 0000

0x077C

0x2011 277C

TYPE2_COMPARE_16_WORD_0

RW

32

0x0000 0000

0x0780

0x2011 2780

TYPE2_COMPARE_16_WORD_1

RW

32

0x0000 0000

0x0784

0x2011 2784

TYPE2_COMPARE_17_WORD_0

RW

32

0x0000 0000

0x0788

0x2011 2788

TYPE2_COMPARE_17_WORD_1

RW

32

0x0000 0000

0x078C

0x2011 278C

TYPE2_COMPARE_18_WORD_0

RW

32

0x0000 0000

0x0790

0x2011 2790

TYPE2_COMPARE_18_WORD_1

RW

32

0x0000 0000

0x0794

0x2011 2794

TYPE2_COMPARE_19_WORD_0

RW

32

0x0000 0000

0x0798

0x2011 2798

TYPE2_COMPARE_19_WORD_1

RW

32

0x0000 0000

0x079C

0x2011 279C

TYPE2_COMPARE_20_WORD_0

RW

32

0x0000 0000

0x07A0

0x2011 27A0

TYPE2_COMPARE_20_WORD_1

RW

32

0x0000 0000

0x07A4

0x2011 27A4

TYPE2_COMPARE_21_WORD_0

RW

32

0x0000 0000

0x07A8

0x2011 27A8

TYPE2_COMPARE_21_WORD_1

RW

32

0x0000 0000

0x07AC

0x2011 27AC

TYPE2_COMPARE_22_WORD_0

RW

32

0x0000 0000

0x07B0

0x2011 27B0

TYPE2_COMPARE_22_WORD_1

RW

32

0x0000 0000

0x07B4

0x2011 27B4

TYPE2_COMPARE_23_WORD_0

RW

32

0x0000 0000

0x07B8

0x2011 27B8

TYPE2_COMPARE_23_WORD_1

RW

32

0x0000 0000

0x07BC

0x2011 27BC

TYPE2_COMPARE_24_WORD_0

RW

32

0x0000 0000

0x07C0

0x2011 27C0

TYPE2_COMPARE_24_WORD_1

RW

32

0x0000 0000

0x07C4

0x2011 27C4

TYPE2_COMPARE_25_WORD_0

RW

32

0x0000 0000

0x07C8

0x2011 27C8

TYPE2_COMPARE_25_WORD_1

RW

32

0x0000 0000

0x07CC

0x2011 27CC

TYPE2_COMPARE_26_WORD_0

RW

32

0x0000 0000

0x07D0

0x2011 27D0

TYPE2_COMPARE_26_WORD_1

RW

32

0x0000 0000

0x07D4

0x2011 27D4

TYPE2_COMPARE_27_WORD_0

RW

32

0x0000 0000

0x07D8

0x2011 27D8

TYPE2_COMPARE_27_WORD_1

RW

32

0x0000 0000

0x07DC

0x2011 27DC

TYPE2_COMPARE_28_WORD_0

RW

32

0x0000 0000

0x07E0

0x2011 27E0

TYPE2_COMPARE_28_WORD_1

RW

32

0x0000 0000

0x07E4

0x2011 27E4

TYPE2_COMPARE_29_WORD_0

RW

32

0x0000 0000

0x07E8

0x2011 27E8

TYPE2_COMPARE_29_WORD_1

RW

32

0x0000 0000

0x07EC

0x2011 27EC

TYPE2_COMPARE_30_WORD_0

RW

32

0x0000 0000

0x07F0

0x2011 27F0

TYPE2_COMPARE_30_WORD_1

RW

32

0x0000 0000

0x07F4

0x2011 27F4

TYPE2_COMPARE_31_WORD_0

RW

32

0x0000 0000

0x07F8

0x2011 27F8

TYPE2_COMPARE_31_WORD_1

RW

32

0x0000 0000

0x07FC

0x2011 27FC

ENST_START_TIME_Q8

RW

32

0x0000 0000

0x0800

0x2011 2800

ENST_START_TIME_Q9

RW

32

0x0000 0000

0x0804

0x2011 2804

ENST_START_TIME_Q10

RW

32

0x0000 0000

0x0808

0x2011 2808

ENST_START_TIME_Q11

RW

32

0x0000 0000

0x080C

0x2011 280C

ENST_START_TIME_Q12

RW

32

0x0000 0000

0x0810

0x2011 2810

ENST_START_TIME_Q13

RW

32

0x0000 0000

0x0814

0x2011 2814

ENST_START_TIME_Q14

RW

32

0x0000 0000

0x0818

0x2011 2818

ENST_START_TIME_Q15

RW

32

0x0000 0000

0x081C

0x2011 281C

ENST_ON_TIME_Q8

RW

32

0x0001 FFFF

0x0820

0x2011 2820

ENST_ON_TIME_Q9

RW

32

0x0001 FFFF

0x0824

0x2011 2824

ENST_ON_TIME_Q10

RW

32

0x0001 FFFF

0x0828

0x2011 2828

ENST_ON_TIME_Q11

RW

32

0x0001 FFFF

0x082C

0x2011 282C

ENST_ON_TIME_Q12

RW

32

0x0001 FFFF

0x0830

0x2011 2830

ENST_ON_TIME_Q13

RW

32

0x0001 FFFF

0x0834

0x2011 2834

ENST_ON_TIME_Q14

RW

32

0x0001 FFFF

0x0838

0x2011 2838

ENST_ON_TIME_Q15

RW

32

0x0001 FFFF

0x083C

0x2011 283C

ENST_OFF_TIME_Q8

RW

32

0x0000 0000

0x0840

0x2011 2840

ENST_OFF_TIME_Q9

RW

32

0x0000 0000

0x0844

0x2011 2844

ENST_OFF_TIME_Q10

RW

32

0x0000 0000

0x0848

0x2011 2848

ENST_OFF_TIME_Q11

RW

32

0x0000 0000

0x084C

0x2011 284C

ENST_OFF_TIME_Q12

RW

32

0x0000 0000

0x0850

0x2011 2850

ENST_OFF_TIME_Q13

RW

32

0x0000 0000

0x0854

0x2011 2854

ENST_OFF_TIME_Q14

RW

32

0x0000 0000

0x0858

0x2011 2858

ENST_OFF_TIME_Q15

RW

32

0x0000 0000

0x085C

0x2011 285C

ENST_CONTROL

RW

32

0x0000 0000

0x0880

0x2011 2880

RX_Q0_FLUSH

RW

32

0x0000 0000

0x0B00

0x2011 2B00

RX_Q1_FLUSH

RW

32

0x0000 0000

0x0B04

0x2011 2B04

RX_Q2_FLUSH

RW

32

0x0000 0000

0x0B08

0x2011 2B08

RX_Q3_FLUSH

RW

32

0x0000 0000

0x0B0C

0x2011 2B0C

RX_Q4_FLUSH

RW

32

0x0000 0000

0x0B10

0x2011 2B10

RX_Q5_FLUSH

RW

32

0x0000 0000

0x0B14

0x2011 2B14

RX_Q6_FLUSH

RW

32

0x0000 0000

0x0B18

0x2011 2B18

RX_Q7_FLUSH

RW

32

0x0000 0000

0x0B1C

0x2011 2B1C

RX_Q8_FLUSH

RW

32

0x0000 0000

0x0B20

0x2011 2B20

RX_Q9_FLUSH

RW

32

0x0000 0000

0x0B24

0x2011 2B24

RX_Q10_FLUSH

RW

32

0x0000 0000

0x0B28

0x2011 2B28

RX_Q11_FLUSH

RW

32

0x0000 0000

0x0B2C

0x2011 2B2C

RX_Q12_FLUSH

RW

32

0x0000 0000

0x0B30

0x2011 2B30

RX_Q13_FLUSH

RW

32

0x0000 0000

0x0B34

0x2011 2B34

RX_Q14_FLUSH

RW

32

0x0000 0000

0x0B38

0x2011 2B38

RX_Q15_FLUSH

RW

32

0x0000 0000

0x0B3C

0x2011 2B3C

SCR2_REG0_RATE_LIMIT

RW

32

0x0000 0000

0x0B40

0x2011 2B40

SCR2_REG1_RATE_LIMIT

RW

32

0x0000 0000

0x0B44

0x2011 2B44

SCR2_REG2_RATE_LIMIT

RW

32

0x0000 0000

0x0B48

0x2011 2B48

SCR2_REG3_RATE_LIMIT

RW

32

0x0000 0000

0x0B4C

0x2011 2B4C

SCR2_REG4_RATE_LIMIT

RW

32

0x0000 0000

0x0B50

0x2011 2B50

SCR2_REG5_RATE_LIMIT

RW

32

0x0000 0000

0x0B54

0x2011 2B54

SCR2_REG6_RATE_LIMIT

RW

32

0x0000 0000

0x0B58

0x2011 2B58

SCR2_REG7_RATE_LIMIT

RW

32

0x0000 0000

0x0B5C

0x2011 2B5C

SCR2_REG8_RATE_LIMIT

RW

32

0x0000 0000

0x0B60

0x2011 2B60

SCR2_REG9_RATE_LIMIT

RW

32

0x0000 0000

0x0B64

0x2011 2B64

SCR2_REG10_RATE_LIMIT

RW

32

0x0000 0000

0x0B68

0x2011 2B68

SCR2_REG11_RATE_LIMIT

RW

32

0x0000 0000

0x0B6C

0x2011 2B6C

SCR2_REG12_RATE_LIMIT

RW

32

0x0000 0000

0x0B70

0x2011 2B70

SCR2_REG13_RATE_LIMIT

RW

32

0x0000 0000

0x0B74

0x2011 2B74

SCR2_REG14_RATE_LIMIT

RW

32

0x0000 0000

0x0B78

0x2011 2B78

SCR2_REG15_RATE_LIMIT

RW

32

0x0000 0000

0x0B7C

0x2011 2B7C

SCR2_RATE_STATUS

RO

32

0x0000 0000

0x0B80

0x2011 2B80

ASF_INT_STATUS

RW

32

0x0000 0000

0x0E00

0x2011 2E00

ASF_INT_RAW_STATUS

RW

32

0x0000 0000

0x0E04

0x2011 2E04

ASF_INT_MASK

RW

32

0x0000 0030

0x0E08

0x2011 2E08

ASF_INT_TEST

RW

32

0x0000 0000

0x0E0C

0x2011 2E0C

ASF_FATAL_NONFATAL_SELECT

RW

32

0x0000 0030

0x0E10

0x2011 2E10

ASF_TRANS_TO_FAULT_MASK

RW

32

0x0000 000F

0x0E34

0x2011 2E34

ASF_TRANS_TO_FAULT_STATUS

RW

32

0x0000 0000

0x0E38

0x2011 2E38

ASF_PROTOCOL_FAULT_MASK

RW

32

0x003F 01FF

0x0E40

0x2011 2E40

ASF_PROTOCOL_FAULT_STATUS

RW

32

0x0000 0000

0x0E44

0x2011 2E44

 

gem_gximicrosemi : GEM_A_HI Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

NETWORK_CONTROL

RW

32

0x0000 0000

0x0000

0x2811 0000

NETWORK_CONFIG

RW

32

0x0008 0000

0x0004

0x2811 0004

NETWORK_STATUS

RO

32

0x0000 0004

0x0008

0x2811 0008

DMA_CONFIG

RW

32

0x0002 07C4

0x0010

0x2811 0010

TRANSMIT_STATUS

RW

32

0x0000 0000

0x0014

0x2811 0014

RECEIVE_Q_PTR

RW

32

0x0000 0000

0x0018

0x2811 0018

TRANSMIT_Q_PTR

RW

32

0x0000 0000

0x001C

0x2811 001C

RECEIVE_STATUS

RW

32

0x0000 0000

0x0020

0x2811 0020

INT_STATUS

RW

32

0x0000 0000

0x0024

0x2811 0024

INT_ENABLE

RW

32

0x0000 0000

0x0028

0x2811 0028

INT_DISABLE

RW

32

0x0000 0000

0x002C

0x2811 002C

INT_MASK

RO

32

0xFFFC FCFF

0x0030

0x2811 0030

PHY_MANAGEMENT

RW

32

0x0000 0000

0x0034

0x2811 0034

PAUSE_TIME

RO

32

0x0000 0000

0x0038

0x2811 0038

TX_PAUSE_QUANTUM

RW

32

0x0000 FFFF

0x003C

0x2811 003C

PBUF_TXCUTTHRU

RW

32

0x0000 1FFF

0x0040

0x2811 0040

PBUF_RXCUTTHRU

RW

32

0x0000 07FF

0x0044

0x2811 0044

JUMBO_MAX_LENGTH

RW

32

0x0000 3FFF

0x0048

0x2811 0048

AXI_MAX_PIPELINE

RW

32

0x0000 0101

0x0054

0x2811 0054

RSC_CONTROL

RW

32

0x0000 0000

0x0058

0x2811 0058

INT_MODERATION

RW

32

0x0000 0000

0x005C

0x2811 005C

SYS_WAKE_TIME

RW

32

0x0000 0000

0x0060

0x2811 0060

LOCKUP_CONFIG

RW

32

0x07FF FFFF

0x0068

0x2811 0068

MAC_LOCKUP_TIME

RW

32

0x07FF FFFF

0x006C

0x2811 006C

LOCKUP_CONFIG3

RW

32

0x0000 0000

0x0070

0x2811 0070

RX_WATER_MARK

RW

32

0x0000 0000

0x007C

0x2811 007C

HASH_BOTTOM

RW

32

0x0000 0000

0x0080

0x2811 0080

HASH_TOP

RW

32

0x0000 0000

0x0084

0x2811 0084

SPEC_ADD1_BOTTOM

RW

32

0x0000 0000

0x0088

0x2811 0088

SPEC_ADD1_TOP

RW

32

0x0000 0000

0x008C

0x2811 008C

SPEC_ADD2_BOTTOM

RW

32

0x0000 0000

0x0090

0x2811 0090

SPEC_ADD2_TOP

RW

32

0x0000 0000

0x0094

0x2811 0094

SPEC_ADD3_BOTTOM

RW

32

0x0000 0000

0x0098

0x2811 0098

SPEC_ADD3_TOP

RW

32

0x0000 0000

0x009C

0x2811 009C

SPEC_ADD4_BOTTOM

RW

32

0x0000 0000

0x00A0

0x2811 00A0

SPEC_ADD4_TOP

RW

32

0x0000 0000

0x00A4

0x2811 00A4

SPEC_TYPE1

RW

32

0x0000 0000

0x00A8

0x2811 00A8

SPEC_TYPE2

RW

32

0x0000 0000

0x00AC

0x2811 00AC

SPEC_TYPE3

RW

32

0x0000 0000

0x00B0

0x2811 00B0

SPEC_TYPE4

RW

32

0x0000 0000

0x00B4

0x2811 00B4

WOL_REGISTER

RW

32

0x0000 0000

0x00B8

0x2811 00B8

STRETCH_RATIO

RW

32

0x0000 0000

0x00BC

0x2811 00BC

STACKED_VLAN

RW

32

0x0000 0000

0x00C0

0x2811 00C0

TX_PFC_PAUSE

RW

32

0x0000 0000

0x00C4

0x2811 00C4

MASK_ADD1_BOTTOM

RW

32

0x0000 0000

0x00C8

0x2811 00C8

MASK_ADD1_TOP

RW

32

0x0000 0000

0x00CC

0x2811 00CC

DMA_ADDR_OR_MASK

RW

32

0x0000 0000

0x00D0

0x2811 00D0

RX_PTP_UNICAST

RW

32

0x0000 0000

0x00D4

0x2811 00D4

TX_PTP_UNICAST

RW

32

0x0000 0000

0x00D8

0x2811 00D8

TSU_NSEC_CMP

RW

32

0x0000 0000

0x00DC

0x2811 00DC

TSU_SEC_CMP

RW

32

0x0000 0000

0x00E0

0x2811 00E0

TSU_MSB_SEC_CMP

RW

32

0x0000 0000

0x00E4

0x2811 00E4

TSU_PTP_TX_MSB_SEC

RO

32

0x0000 0000

0x00E8

0x2811 00E8

TSU_PTP_RX_MSB_SEC

RO

32

0x0000 0000

0x00EC

0x2811 00EC

TSU_PEER_TX_MSB_SEC

RO

32

0x0000 0000

0x00F0

0x2811 00F0

TSU_PEER_RX_MSB_SEC

RO

32

0x0000 0000

0x00F4

0x2811 00F4

DPRAM_FILL_DBG

RW

32

0x0000 0000

0x00F8

0x2811 00F8

REVISION_REG

RO

32

0x0107 010C

0x00FC

0x2811 00FC

OCTETS_TXED_BOTTOM

RO

32

0x0000 0000

0x0100

0x2811 0100

OCTETS_TXED_TOP

RO

32

0x0000 0000

0x0104

0x2811 0104

FRAMES_TXED_OK

RO

32

0x0000 0000

0x0108

0x2811 0108

BROADCAST_TXED

RO

32

0x0000 0000

0x010C

0x2811 010C

MULTICAST_TXED

RO

32

0x0000 0000

0x0110

0x2811 0110

PAUSE_FRAMES_TXED

RO

32

0x0000 0000

0x0114

0x2811 0114

FRAMES_TXED_64

RO

32

0x0000 0000

0x0118

0x2811 0118

FRAMES_TXED_65

RO

32

0x0000 0000

0x011C

0x2811 011C

FRAMES_TXED_128

RO

32

0x0000 0000

0x0120

0x2811 0120

FRAMES_TXED_256

RO

32

0x0000 0000

0x0124

0x2811 0124

FRAMES_TXED_512

RO

32

0x0000 0000

0x0128

0x2811 0128

FRAMES_TXED_1024

RO

32

0x0000 0000

0x012C

0x2811 012C

FRAMES_TXED_1519

RO

32

0x0000 0000

0x0130

0x2811 0130

TX_UNDERRUNS

RO

32

0x0000 0000

0x0134

0x2811 0134

SINGLE_COLLISIONS

RO

32

0x0000 0000

0x0138

0x2811 0138

MULTIPLE_COLLISIONS

RO

32

0x0000 0000

0x013C

0x2811 013C

EXCESSIVE_COLLISIONS

RO

32

0x0000 0000

0x0140

0x2811 0140

LATE_COLLISIONS

RO

32

0x0000 0000

0x0144

0x2811 0144

DEFERRED_FRAMES

RO

32

0x0000 0000

0x0148

0x2811 0148

CRS_ERRORS

RO

32

0x0000 0000

0x014C

0x2811 014C

OCTETS_RXED_BOTTOM

RO

32

0x0000 0000

0x0150

0x2811 0150

OCTETS_RXED_TOP

RO

32

0x0000 0000

0x0154

0x2811 0154

FRAMES_RXED_OK

RO

32

0x0000 0000

0x0158

0x2811 0158

BROADCAST_RXED

RO

32

0x0000 0000

0x015C

0x2811 015C

MULTICAST_RXED

RO

32

0x0000 0000

0x0160

0x2811 0160

PAUSE_FRAMES_RXED

RO

32

0x0000 0000

0x0164

0x2811 0164

FRAMES_RXED_64

RO

32

0x0000 0000

0x0168

0x2811 0168

FRAMES_RXED_65

RO

32

0x0000 0000

0x016C

0x2811 016C

FRAMES_RXED_128

RO

32

0x0000 0000

0x0170

0x2811 0170

FRAMES_RXED_256

RO

32

0x0000 0000

0x0174

0x2811 0174

FRAMES_RXED_512

RO

32

0x0000 0000

0x0178

0x2811 0178

FRAMES_RXED_1024

RO

32

0x0000 0000

0x017C

0x2811 017C

FRAMES_RXED_1519

RO

32

0x0000 0000

0x0180

0x2811 0180

UNDERSIZE_FRAMES

RO

32

0x0000 0000

0x0184

0x2811 0184

EXCESSIVE_RX_LENGTH

RO

32

0x0000 0000

0x0188

0x2811 0188

RX_JABBERS

RO

32

0x0000 0000

0x018C

0x2811 018C

FCS_ERRORS

RO

32

0x0000 0000

0x0190

0x2811 0190

RX_LENGTH_ERRORS

RO

32

0x0000 0000

0x0194

0x2811 0194

RX_SYMBOL_ERRORS

RO

32

0x0000 0000

0x0198

0x2811 0198

ALIGNMENT_ERRORS

RO

32

0x0000 0000

0x019C

0x2811 019C

RX_RESOURCE_ERRORS

RO

32

0x0000 0000

0x01A0

0x2811 01A0

RX_OVERRUNS

RO

32

0x0000 0000

0x01A4

0x2811 01A4

RX_IP_CK_ERRORS

RO

32

0x0000 0000

0x01A8

0x2811 01A8

RX_TCP_CK_ERRORS

RO

32

0x0000 0000

0x01AC

0x2811 01AC

RX_UDP_CK_ERRORS

RO

32

0x0000 0000

0x01B0

0x2811 01B0

AUTO_FLUSHED_PKTS

RO

32

0x0000 0000

0x01B4

0x2811 01B4

TSU_TIMER_INCR_SUB_NSEC

RW

32

0x0000 0000

0x01BC

0x2811 01BC

TSU_TIMER_MSB_SEC

RW

32

0x0000 0000

0x01C0

0x2811 01C0

TSU_STROBE_MSB_SEC

RO

32

0x0000 0000

0x01C4

0x2811 01C4

TSU_STROBE_SEC

RO

32

0x0000 0000

0x01C8

0x2811 01C8

TSU_STROBE_NSEC

RO

32

0x0000 0000

0x01CC

0x2811 01CC

TSU_TIMER_SEC

RW

32

0x0000 0000

0x01D0

0x2811 01D0

TSU_TIMER_NSEC

RW

32

0x0000 0000

0x01D4

0x2811 01D4

TSU_TIMER_ADJUST

RW

32

0x0000 0000

0x01D8

0x2811 01D8

TSU_TIMER_INCR

RW

32

0x0000 0000

0x01DC

0x2811 01DC

TSU_PTP_TX_SEC

RO

32

0x0000 0000

0x01E0

0x2811 01E0

TSU_PTP_TX_NSEC

RO

32

0x0000 0000

0x01E4

0x2811 01E4

TSU_PTP_RX_SEC

RO

32

0x0000 0000

0x01E8

0x2811 01E8

TSU_PTP_RX_NSEC

RO

32

0x0000 0000

0x01EC

0x2811 01EC

TSU_PEER_TX_SEC

RO

32

0x0000 0000

0x01F0

0x2811 01F0

TSU_PEER_TX_NSEC

RO

32

0x0000 0000

0x01F4

0x2811 01F4

TSU_PEER_RX_SEC

RO

32

0x0000 0000

0x01F8

0x2811 01F8

TSU_PEER_RX_NSEC

RO

32

0x0000 0000

0x01FC

0x2811 01FC

PFC_STATUS

RO

32

0x0000 0000

0x026C

0x2811 026C

RX_LPI

RO

32

0x0000 0000

0x0270

0x2811 0270

RX_LPI_TIME

RO

32

0x0000 0000

0x0274

0x2811 0274

TX_LPI

RO

32

0x0000 0000

0x0278

0x2811 0278

TX_LPI_TIME

RO

32

0x0000 0000

0x027C

0x2811 027C

DESIGNCFG_DEBUG1

RO

32

0x0850 8511

0x0280

0x2811 0280

DESIGNCFG_DEBUG2

RO

32

0x76F1 3FFF

0x0284

0x2811 0284

DESIGNCFG_DEBUG3

RO

32

0x0400 0000

0x0288

0x2811 0288

DESIGNCFG_DEBUG4

RO

32

0x0000 0000

0x028C

0x2811 028C

DESIGNCFG_DEBUG5

RO

32

0x402F A345

0x0290

0x2811 0290

DESIGNCFG_DEBUG6

RO

32

0x0C84 FFFE

0x0294

0x2811 0294

DESIGNCFG_DEBUG7

RO

32

0x0000 0000

0x0298

0x2811 0298

DESIGNCFG_DEBUG8

RO

32

0x1010 0820

0x029C

0x2811 029C

DESIGNCFG_DEBUG9

RO

32

0x0000 0000

0x02A0

0x2811 02A0

DESIGNCFG_DEBUG10

RO

32

0x2444 4442

0x02A4

0x2811 02A4

DESIGNCFG_DEBUG11

RO

32

0x0000 0000

0x02A8

0x2811 02A8

DESIGNCFG_DEBUG12

RO

32

0x0154 4001

0x02AC

0x2811 02AC

AXI_QOS_CFG_0

RW

32

0x0000 0000

0x02E0

0x2811 02E0

AXI_QOS_CFG_1

RW

32

0x0000 0000

0x02E4

0x2811 02E4

AXI_QOS_CFG_2

RW

32

0x0000 0000

0x02E8

0x2811 02E8

AXI_QOS_CFG_3

RW

32

0x0000 0000

0x02EC

0x2811 02EC

INT_Q1_STATUS

RW

32

0x0000 0000

0x0400

0x2811 0400

INT_Q2_STATUS

RW

32

0x0000 0000

0x0404

0x2811 0404

INT_Q3_STATUS

RW

32

0x0000 0000

0x0408

0x2811 0408

INT_Q4_STATUS

RW

32

0x0000 0000

0x040C

0x2811 040C

INT_Q5_STATUS

RW

32

0x0000 0000

0x0410

0x2811 0410

INT_Q6_STATUS

RW

32

0x0000 0000

0x0414

0x2811 0414

INT_Q7_STATUS

RW

32

0x0000 0000

0x0418

0x2811 0418

INT_Q8_STATUS

RW

32

0x0000 0000

0x041C

0x2811 041C

INT_Q9_STATUS

RW

32

0x0000 0000

0x0420

0x2811 0420

INT_Q10_STATUS

RW

32

0x0000 0000

0x0424

0x2811 0424

INT_Q11_STATUS

RW

32

0x0000 0000

0x0428

0x2811 0428

INT_Q12_STATUS

RW

32

0x0000 0000

0x042C

0x2811 042C

INT_Q13_STATUS

RW

32

0x0000 0000

0x0430

0x2811 0430

INT_Q14_STATUS

RW

32

0x0000 0000

0x0434

0x2811 0434

INT_Q15_STATUS

RW

32

0x0000 0000

0x0438

0x2811 0438

TRANSMIT_Q1_PTR

RW

32

0x0000 0000

0x0440

0x2811 0440

TRANSMIT_Q2_PTR

RW

32

0x0000 0000

0x0444

0x2811 0444

TRANSMIT_Q3_PTR

RW

32

0x0000 0000

0x0448

0x2811 0448

TRANSMIT_Q4_PTR

RW

32

0x0000 0000

0x044C

0x2811 044C

TRANSMIT_Q5_PTR

RW

32

0x0000 0000

0x0450

0x2811 0450

TRANSMIT_Q6_PTR

RW

32

0x0000 0000

0x0454

0x2811 0454

TRANSMIT_Q7_PTR

RW

32

0x0000 0000

0x0458

0x2811 0458

TRANSMIT_Q8_PTR

RW

32

0x0000 0000

0x045C

0x2811 045C

TRANSMIT_Q9_PTR

RW

32

0x0000 0000

0x0460

0x2811 0460

TRANSMIT_Q10_PTR

RW

32

0x0000 0000

0x0464

0x2811 0464

TRANSMIT_Q11_PTR

RW

32

0x0000 0000

0x0468

0x2811 0468

TRANSMIT_Q12_PTR

RW

32

0x0000 0000

0x046C

0x2811 046C

TRANSMIT_Q13_PTR

RW

32

0x0000 0000

0x0470

0x2811 0470

TRANSMIT_Q14_PTR

RW

32

0x0000 0000

0x0474

0x2811 0474

TRANSMIT_Q15_PTR

RW

32

0x0000 0000

0x0478

0x2811 0478

RECEIVE_Q1_PTR

RW

32

0x0000 0000

0x0480

0x2811 0480

RECEIVE_Q2_PTR

RW

32

0x0000 0000

0x0484

0x2811 0484

RECEIVE_Q3_PTR

RW

32

0x0000 0000

0x0488

0x2811 0488

RECEIVE_Q4_PTR

RW

32

0x0000 0000

0x048C

0x2811 048C

RECEIVE_Q5_PTR

RW

32

0x0000 0000

0x0490

0x2811 0490

RECEIVE_Q6_PTR

RW

32

0x0000 0000

0x0494

0x2811 0494

RECEIVE_Q7_PTR

RW

32

0x0000 0000

0x0498

0x2811 0498

DMA_RXBUF_SIZE_Q1

RW

32

0x0000 0002

0x04A0

0x2811 04A0

DMA_RXBUF_SIZE_Q2

RW

32

0x0000 0002

0x04A4

0x2811 04A4

DMA_RXBUF_SIZE_Q3

RW

32

0x0000 0002

0x04A8

0x2811 04A8

DMA_RXBUF_SIZE_Q4

RW

32

0x0000 0002

0x04AC

0x2811 04AC

DMA_RXBUF_SIZE_Q5

RW

32

0x0000 0002

0x04B0

0x2811 04B0

DMA_RXBUF_SIZE_Q6

RW

32

0x0000 0002

0x04B4

0x2811 04B4

DMA_RXBUF_SIZE_Q7

RW

32

0x0000 0002

0x04B8

0x2811 04B8

CBS_CONTROL

RW

32

0x0000 0000

0x04BC

0x2811 04BC

CBS_IDLESLOPE_Q_A

RW

32

0x0000 0000

0x04C0

0x2811 04C0

CBS_IDLESLOPE_Q_B

RW

32

0x0000 0000

0x04C4

0x2811 04C4

UPPER_TX_Q_BASE_ADDR

RW

32

0x0000 0000

0x04C8

0x2811 04C8

TX_BD_CONTROL

RW

32

0x0000 0000

0x04CC

0x2811 04CC

RX_BD_CONTROL

RW

32

0x0000 0000

0x04D0

0x2811 04D0

UPPER_RX_Q_BASE_ADDR

RW

32

0x0000 0000

0x04D4

0x2811 04D4

WD_COUNTER

RW

32

0x0000 0007

0x04EC

0x2811 04EC

AXI_TX_FULL_THRESH0

RW

32

0x0006 0008

0x04F8

0x2811 04F8

AXI_TX_FULL_THRESH1

RW

32

0x0000 0000

0x04FC

0x2811 04FC

SCREENING_TYPE_1_REGISTER_0

RW

32

0x0000 0000

0x0500

0x2811 0500

SCREENING_TYPE_1_REGISTER_1

RW

32

0x0000 0000

0x0504

0x2811 0504

SCREENING_TYPE_1_REGISTER_2

RW

32

0x0000 0000

0x0508

0x2811 0508

SCREENING_TYPE_1_REGISTER_3

RW

32

0x0000 0000

0x050C

0x2811 050C

SCREENING_TYPE_1_REGISTER_4

RW

32

0x0000 0000

0x0510

0x2811 0510

SCREENING_TYPE_1_REGISTER_5

RW

32

0x0000 0000

0x0514

0x2811 0514

SCREENING_TYPE_1_REGISTER_6

RW

32

0x0000 0000

0x0518

0x2811 0518

SCREENING_TYPE_1_REGISTER_7

RW

32

0x0000 0000

0x051C

0x2811 051C

SCREENING_TYPE_1_REGISTER_8

RW

32

0x0000 0000

0x0520

0x2811 0520

SCREENING_TYPE_1_REGISTER_9

RW

32

0x0000 0000

0x0524

0x2811 0524

SCREENING_TYPE_1_REGISTER_10

RW

32

0x0000 0000

0x0528

0x2811 0528

SCREENING_TYPE_1_REGISTER_11

RW

32

0x0000 0000

0x052C

0x2811 052C

SCREENING_TYPE_1_REGISTER_12

RW

32

0x0000 0000

0x0530

0x2811 0530

SCREENING_TYPE_1_REGISTER_13

RW

32

0x0000 0000

0x0534

0x2811 0534

SCREENING_TYPE_1_REGISTER_14

RW

32

0x0000 0000

0x0538

0x2811 0538

SCREENING_TYPE_1_REGISTER_15

RW

32

0x0000 0000

0x053C

0x2811 053C

SCREENING_TYPE_2_REGISTER_0

RW

32

0x0000 0000

0x0540

0x2811 0540

SCREENING_TYPE_2_REGISTER_1

RW

32

0x0000 0000

0x0544

0x2811 0544

SCREENING_TYPE_2_REGISTER_2

RW

32

0x0000 0000

0x0548

0x2811 0548

SCREENING_TYPE_2_REGISTER_3

RW

32

0x0000 0000

0x054C

0x2811 054C

SCREENING_TYPE_2_REGISTER_4

RW

32

0x0000 0000

0x0550

0x2811 0550

SCREENING_TYPE_2_REGISTER_5

RW

32

0x0000 0000

0x0554

0x2811 0554

SCREENING_TYPE_2_REGISTER_6

RW

32

0x0000 0000

0x0558

0x2811 0558

SCREENING_TYPE_2_REGISTER_7

RW

32

0x0000 0000

0x055C

0x2811 055C

SCREENING_TYPE_2_REGISTER_8

RW

32

0x0000 0000

0x0560

0x2811 0560

SCREENING_TYPE_2_REGISTER_9

RW

32

0x0000 0000

0x0564

0x2811 0564

SCREENING_TYPE_2_REGISTER_10

RW

32

0x0000 0000

0x0568

0x2811 0568

SCREENING_TYPE_2_REGISTER_11

RW

32

0x0000 0000

0x056C

0x2811 056C

SCREENING_TYPE_2_REGISTER_12

RW

32

0x0000 0000

0x0570

0x2811 0570

SCREENING_TYPE_2_REGISTER_13

RW

32

0x0000 0000

0x0574

0x2811 0574

SCREENING_TYPE_2_REGISTER_14

RW

32

0x0000 0000

0x0578

0x2811 0578

SCREENING_TYPE_2_REGISTER_15

RW

32

0x0000 0000

0x057C

0x2811 057C

TX_SCHED_CTRL

RW

32

0x0000 0000

0x0580

0x2811 0580

BW_RATE_LIMIT_Q0TO3

RW

32

0x0000 0000

0x0590

0x2811 0590

BW_RATE_LIMIT_Q4TO7

RW

32

0x0000 0000

0x0594

0x2811 0594

BW_RATE_LIMIT_Q8TO11

RW

32

0x0000 0000

0x0598

0x2811 0598

BW_RATE_LIMIT_Q12TO15

RW

32

0x0000 0000

0x059C

0x2811 059C

TX_Q_SEG_ALLOC_Q_LOWER

RW

32

0x0000 0000

0x05A0

0x2811 05A0

TX_Q_SEG_ALLOC_Q_UPPER

RW

32

0x0000 0000

0x05A4

0x2811 05A4

RECEIVE_Q8_PTR

RW

32

0x0000 0000

0x05C0

0x2811 05C0

RECEIVE_Q9_PTR

RW

32

0x0000 0000

0x05C4

0x2811 05C4

RECEIVE_Q10_PTR

RW

32

0x0000 0000

0x05C8

0x2811 05C8

RECEIVE_Q11_PTR

RW

32

0x0000 0000

0x05CC

0x2811 05CC

RECEIVE_Q12_PTR

RW

32

0x0000 0000

0x05D0

0x2811 05D0

RECEIVE_Q13_PTR

RW

32

0x0000 0000

0x05D4

0x2811 05D4

RECEIVE_Q14_PTR

RW

32

0x0000 0000

0x05D8

0x2811 05D8

RECEIVE_Q15_PTR

RW

32

0x0000 0000

0x05DC

0x2811 05DC

DMA_RXBUF_SIZE_Q8

RW

32

0x0000 0002

0x05E0

0x2811 05E0

DMA_RXBUF_SIZE_Q9

RW

32

0x0000 0002

0x05E4

0x2811 05E4

DMA_RXBUF_SIZE_Q10

RW

32

0x0000 0002

0x05E8

0x2811 05E8

DMA_RXBUF_SIZE_Q11

RW

32

0x0000 0002

0x05EC

0x2811 05EC

DMA_RXBUF_SIZE_Q12

RW

32

0x0000 0002

0x05F0

0x2811 05F0

DMA_RXBUF_SIZE_Q13

RW

32

0x0000 0002

0x05F4

0x2811 05F4

DMA_RXBUF_SIZE_Q14

RW

32

0x0000 0002

0x05F8

0x2811 05F8

DMA_RXBUF_SIZE_Q15

RW

32

0x0000 0002

0x05FC

0x2811 05FC

INT_Q1_ENABLE

RW

32

0x0000 0000

0x0600

0x2811 0600

INT_Q2_ENABLE

RW

32

0x0000 0000

0x0604

0x2811 0604

INT_Q3_ENABLE

RW

32

0x0000 0000

0x0608

0x2811 0608

INT_Q4_ENABLE

RW

32

0x0000 0000

0x060C

0x2811 060C

INT_Q5_ENABLE

RW

32

0x0000 0000

0x0610

0x2811 0610

INT_Q6_ENABLE

RW

32

0x0000 0000

0x0614

0x2811 0614

INT_Q7_ENABLE

RW

32

0x0000 0000

0x0618

0x2811 0618

INT_Q1_DISABLE

RW

32

0x0000 0000

0x0620

0x2811 0620

INT_Q2_DISABLE

RW

32

0x0000 0000

0x0624

0x2811 0624

INT_Q3_DISABLE

RW

32

0x0000 0000

0x0628

0x2811 0628

INT_Q4_DISABLE

RW

32

0x0000 0000

0x062C

0x2811 062C

INT_Q5_DISABLE

RW

32

0x0000 0000

0x0630

0x2811 0630

INT_Q6_DISABLE

RW

32

0x0000 0000

0x0634

0x2811 0634

INT_Q7_DISABLE

RW

32

0x0000 0000

0x0638

0x2811 0638

INT_Q1_MASK

RO

32

0x0000 08E6

0x0640

0x2811 0640

INT_Q2_MASK

RO

32

0x0000 08E6

0x0644

0x2811 0644

INT_Q3_MASK

RO

32

0x0000 08E6

0x0648

0x2811 0648

INT_Q4_MASK

RO

32

0x0000 08E6

0x064C

0x2811 064C

INT_Q5_MASK

RO

32

0x0000 08E6

0x0650

0x2811 0650

INT_Q6_MASK

RO

32

0x0000 08E6

0x0654

0x2811 0654

INT_Q7_MASK

RO

32

0x0000 08E6

0x0658

0x2811 0658

INT_Q8_ENABLE

RW

32

0x0000 0000

0x0660

0x2811 0660

INT_Q9_ENABLE

RW

32

0x0000 0000

0x0664

0x2811 0664

INT_Q10_ENABLE

RW

32

0x0000 0000

0x0668

0x2811 0668

INT_Q11_ENABLE

RW

32

0x0000 0000

0x066C

0x2811 066C

INT_Q12_ENABLE

RW

32

0x0000 0000

0x0670

0x2811 0670

INT_Q13_ENABLE

RW

32

0x0000 0000

0x0674

0x2811 0674

INT_Q14_ENABLE

RW

32

0x0000 0000

0x0678

0x2811 0678

INT_Q15_ENABLE

RW

32

0x0000 0000

0x067C

0x2811 067C

INT_Q8_DISABLE

RW

32

0x0000 0000

0x0680

0x2811 0680

INT_Q9_DISABLE

RW

32

0x0000 0000

0x0684

0x2811 0684

INT_Q10_DISABLE

RW

32

0x0000 0000

0x0688

0x2811 0688

INT_Q11_DISABLE

RW

32

0x0000 0000

0x068C

0x2811 068C

INT_Q12_DISABLE

RW

32

0x0000 0000

0x0690

0x2811 0690

INT_Q13_DISABLE

RW

32

0x0000 0000

0x0694

0x2811 0694

INT_Q14_DISABLE

RW

32

0x0000 0000

0x0698

0x2811 0698

INT_Q15_DISABLE

RW

32

0x0000 0000

0x069C

0x2811 069C

INT_Q8_MASK

RO

32

0x0000 08E6

0x06A0

0x2811 06A0

INT_Q9_MASK

RO

32

0x0000 08E6

0x06A4

0x2811 06A4

INT_Q10_MASK

RO

32

0x0000 08E6

0x06A8

0x2811 06A8

INT_Q11_MASK

RO

32

0x0000 08E6

0x06AC

0x2811 06AC

INT_Q12_MASK

RO

32

0x0000 08E6

0x06B0

0x2811 06B0

INT_Q13_MASK

RO

32

0x0000 08E6

0x06B4

0x2811 06B4

INT_Q14_MASK

RO

32

0x0000 08E6

0x06B8

0x2811 06B8

INT_Q15_MASK

RO

32

0x0000 08E6

0x06BC

0x2811 06BC

SCREENING_TYPE_2_ETHERTYPE_REG_0

RW

32

0x0000 0000

0x06E0

0x2811 06E0

SCREENING_TYPE_2_ETHERTYPE_REG_1

RW

32

0x0000 0000

0x06E4

0x2811 06E4

SCREENING_TYPE_2_ETHERTYPE_REG_2

RW

32

0x0000 0000

0x06E8

0x2811 06E8

SCREENING_TYPE_2_ETHERTYPE_REG_3

RW

32

0x0000 0000

0x06EC

0x2811 06EC

SCREENING_TYPE_2_ETHERTYPE_REG_4

RW

32

0x0000 0000

0x06F0

0x2811 06F0

SCREENING_TYPE_2_ETHERTYPE_REG_5

RW

32

0x0000 0000

0x06F4

0x2811 06F4

SCREENING_TYPE_2_ETHERTYPE_REG_6

RW

32

0x0000 0000

0x06F8

0x2811 06F8

SCREENING_TYPE_2_ETHERTYPE_REG_7

RW

32

0x0000 0000

0x06FC

0x2811 06FC

TYPE2_COMPARE_0_WORD_0

RW

32

0x0000 0000

0x0700

0x2811 0700

TYPE2_COMPARE_0_WORD_1

RW

32

0x0000 0000

0x0704

0x2811 0704

TYPE2_COMPARE_1_WORD_0

RW

32

0x0000 0000

0x0708

0x2811 0708

TYPE2_COMPARE_1_WORD_1

RW

32

0x0000 0000

0x070C

0x2811 070C

TYPE2_COMPARE_2_WORD_0

RW

32

0x0000 0000

0x0710

0x2811 0710

TYPE2_COMPARE_2_WORD_1

RW

32

0x0000 0000

0x0714

0x2811 0714

TYPE2_COMPARE_3_WORD_0

RW

32

0x0000 0000

0x0718

0x2811 0718

TYPE2_COMPARE_3_WORD_1

RW

32

0x0000 0000

0x071C

0x2811 071C

TYPE2_COMPARE_4_WORD_0

RW

32

0x0000 0000

0x0720

0x2811 0720

TYPE2_COMPARE_4_WORD_1

RW

32

0x0000 0000

0x0724

0x2811 0724

TYPE2_COMPARE_5_WORD_0

RW

32

0x0000 0000

0x0728

0x2811 0728

TYPE2_COMPARE_5_WORD_1

RW

32

0x0000 0000

0x072C

0x2811 072C

TYPE2_COMPARE_6_WORD_0

RW

32

0x0000 0000

0x0730

0x2811 0730

TYPE2_COMPARE_6_WORD_1

RW

32

0x0000 0000

0x0734

0x2811 0734

TYPE2_COMPARE_7_WORD_0

RW

32

0x0000 0000

0x0738

0x2811 0738

TYPE2_COMPARE_7_WORD_1

RW

32

0x0000 0000

0x073C

0x2811 073C

TYPE2_COMPARE_8_WORD_0

RW

32

0x0000 0000

0x0740

0x2811 0740

TYPE2_COMPARE_8_WORD_1

RW

32

0x0000 0000

0x0744

0x2811 0744

TYPE2_COMPARE_9_WORD_0

RW

32

0x0000 0000

0x0748

0x2811 0748

TYPE2_COMPARE_9_WORD_1

RW

32

0x0000 0000

0x074C

0x2811 074C

TYPE2_COMPARE_10_WORD_0

RW

32

0x0000 0000

0x0750

0x2811 0750

TYPE2_COMPARE_10_WORD_1

RW

32

0x0000 0000

0x0754

0x2811 0754

TYPE2_COMPARE_11_WORD_0

RW

32

0x0000 0000

0x0758

0x2811 0758

TYPE2_COMPARE_11_WORD_1

RW

32

0x0000 0000

0x075C

0x2811 075C

TYPE2_COMPARE_12_WORD_0

RW

32

0x0000 0000

0x0760

0x2811 0760

TYPE2_COMPARE_12_WORD_1

RW

32

0x0000 0000

0x0764

0x2811 0764

TYPE2_COMPARE_13_WORD_0

RW

32

0x0000 0000

0x0768

0x2811 0768

TYPE2_COMPARE_13_WORD_1

RW

32

0x0000 0000

0x076C

0x2811 076C

TYPE2_COMPARE_14_WORD_0

RW

32

0x0000 0000

0x0770

0x2811 0770

TYPE2_COMPARE_14_WORD_1

RW

32

0x0000 0000

0x0774

0x2811 0774

TYPE2_COMPARE_15_WORD_0

RW

32

0x0000 0000

0x0778

0x2811 0778

TYPE2_COMPARE_15_WORD_1

RW

32

0x0000 0000

0x077C

0x2811 077C

TYPE2_COMPARE_16_WORD_0

RW

32

0x0000 0000

0x0780

0x2811 0780

TYPE2_COMPARE_16_WORD_1

RW

32

0x0000 0000

0x0784

0x2811 0784

TYPE2_COMPARE_17_WORD_0

RW

32

0x0000 0000

0x0788

0x2811 0788

TYPE2_COMPARE_17_WORD_1

RW

32

0x0000 0000

0x078C

0x2811 078C

TYPE2_COMPARE_18_WORD_0

RW

32

0x0000 0000

0x0790

0x2811 0790

TYPE2_COMPARE_18_WORD_1

RW

32

0x0000 0000

0x0794

0x2811 0794

TYPE2_COMPARE_19_WORD_0

RW

32

0x0000 0000

0x0798

0x2811 0798

TYPE2_COMPARE_19_WORD_1

RW

32

0x0000 0000

0x079C

0x2811 079C

TYPE2_COMPARE_20_WORD_0

RW

32

0x0000 0000

0x07A0

0x2811 07A0

TYPE2_COMPARE_20_WORD_1

RW

32

0x0000 0000

0x07A4

0x2811 07A4

TYPE2_COMPARE_21_WORD_0

RW

32

0x0000 0000

0x07A8

0x2811 07A8

TYPE2_COMPARE_21_WORD_1

RW

32

0x0000 0000

0x07AC

0x2811 07AC

TYPE2_COMPARE_22_WORD_0

RW

32

0x0000 0000

0x07B0

0x2811 07B0

TYPE2_COMPARE_22_WORD_1

RW

32

0x0000 0000

0x07B4

0x2811 07B4

TYPE2_COMPARE_23_WORD_0

RW

32

0x0000 0000

0x07B8

0x2811 07B8

TYPE2_COMPARE_23_WORD_1

RW

32

0x0000 0000

0x07BC

0x2811 07BC

TYPE2_COMPARE_24_WORD_0

RW

32

0x0000 0000

0x07C0

0x2811 07C0

TYPE2_COMPARE_24_WORD_1

RW

32

0x0000 0000

0x07C4

0x2811 07C4

TYPE2_COMPARE_25_WORD_0

RW

32

0x0000 0000

0x07C8

0x2811 07C8

TYPE2_COMPARE_25_WORD_1

RW

32

0x0000 0000

0x07CC

0x2811 07CC

TYPE2_COMPARE_26_WORD_0

RW

32

0x0000 0000

0x07D0

0x2811 07D0

TYPE2_COMPARE_26_WORD_1

RW

32

0x0000 0000

0x07D4

0x2811 07D4

TYPE2_COMPARE_27_WORD_0

RW

32

0x0000 0000

0x07D8

0x2811 07D8

TYPE2_COMPARE_27_WORD_1

RW

32

0x0000 0000

0x07DC

0x2811 07DC

TYPE2_COMPARE_28_WORD_0

RW

32

0x0000 0000

0x07E0

0x2811 07E0

TYPE2_COMPARE_28_WORD_1

RW

32

0x0000 0000

0x07E4

0x2811 07E4

TYPE2_COMPARE_29_WORD_0

RW

32

0x0000 0000

0x07E8

0x2811 07E8

TYPE2_COMPARE_29_WORD_1

RW

32

0x0000 0000

0x07EC

0x2811 07EC

TYPE2_COMPARE_30_WORD_0

RW

32

0x0000 0000

0x07F0

0x2811 07F0

TYPE2_COMPARE_30_WORD_1

RW

32

0x0000 0000

0x07F4

0x2811 07F4

TYPE2_COMPARE_31_WORD_0

RW

32

0x0000 0000

0x07F8

0x2811 07F8

TYPE2_COMPARE_31_WORD_1

RW

32

0x0000 0000

0x07FC

0x2811 07FC

ENST_START_TIME_Q8

RW

32

0x0000 0000

0x0800

0x2811 0800

ENST_START_TIME_Q9

RW

32

0x0000 0000

0x0804

0x2811 0804

ENST_START_TIME_Q10

RW

32

0x0000 0000

0x0808

0x2811 0808

ENST_START_TIME_Q11

RW

32

0x0000 0000

0x080C

0x2811 080C

ENST_START_TIME_Q12

RW

32

0x0000 0000

0x0810

0x2811 0810

ENST_START_TIME_Q13

RW

32

0x0000 0000

0x0814

0x2811 0814

ENST_START_TIME_Q14

RW

32

0x0000 0000

0x0818

0x2811 0818

ENST_START_TIME_Q15

RW

32

0x0000 0000

0x081C

0x2811 081C

ENST_ON_TIME_Q8

RW

32

0x0001 FFFF

0x0820

0x2811 0820

ENST_ON_TIME_Q9

RW

32

0x0001 FFFF

0x0824

0x2811 0824

ENST_ON_TIME_Q10

RW

32

0x0001 FFFF

0x0828

0x2811 0828

ENST_ON_TIME_Q11

RW

32

0x0001 FFFF

0x082C

0x2811 082C

ENST_ON_TIME_Q12

RW

32

0x0001 FFFF

0x0830

0x2811 0830

ENST_ON_TIME_Q13

RW

32

0x0001 FFFF

0x0834

0x2811 0834

ENST_ON_TIME_Q14

RW

32

0x0001 FFFF

0x0838

0x2811 0838

ENST_ON_TIME_Q15

RW

32

0x0001 FFFF

0x083C

0x2811 083C

ENST_OFF_TIME_Q8

RW

32

0x0000 0000

0x0840

0x2811 0840

ENST_OFF_TIME_Q9

RW

32

0x0000 0000

0x0844

0x2811 0844

ENST_OFF_TIME_Q10

RW

32

0x0000 0000

0x0848

0x2811 0848

ENST_OFF_TIME_Q11

RW

32

0x0000 0000

0x084C

0x2811 084C

ENST_OFF_TIME_Q12

RW

32

0x0000 0000

0x0850

0x2811 0850

ENST_OFF_TIME_Q13

RW

32

0x0000 0000

0x0854

0x2811 0854

ENST_OFF_TIME_Q14

RW

32

0x0000 0000

0x0858

0x2811 0858

ENST_OFF_TIME_Q15

RW

32

0x0000 0000

0x085C

0x2811 085C

ENST_CONTROL

RW

32

0x0000 0000

0x0880

0x2811 0880

RX_Q0_FLUSH

RW

32

0x0000 0000

0x0B00

0x2811 0B00

RX_Q1_FLUSH

RW

32

0x0000 0000

0x0B04

0x2811 0B04

RX_Q2_FLUSH

RW

32

0x0000 0000

0x0B08

0x2811 0B08

RX_Q3_FLUSH

RW

32

0x0000 0000

0x0B0C

0x2811 0B0C

RX_Q4_FLUSH

RW

32

0x0000 0000

0x0B10

0x2811 0B10

RX_Q5_FLUSH

RW

32

0x0000 0000

0x0B14

0x2811 0B14

RX_Q6_FLUSH

RW

32

0x0000 0000

0x0B18

0x2811 0B18

RX_Q7_FLUSH

RW

32

0x0000 0000

0x0B1C

0x2811 0B1C

RX_Q8_FLUSH

RW

32

0x0000 0000

0x0B20

0x2811 0B20

RX_Q9_FLUSH

RW

32

0x0000 0000

0x0B24

0x2811 0B24

RX_Q10_FLUSH

RW

32

0x0000 0000

0x0B28

0x2811 0B28

RX_Q11_FLUSH

RW

32

0x0000 0000

0x0B2C

0x2811 0B2C

RX_Q12_FLUSH

RW

32

0x0000 0000

0x0B30

0x2811 0B30

RX_Q13_FLUSH

RW

32

0x0000 0000

0x0B34

0x2811 0B34

RX_Q14_FLUSH

RW

32

0x0000 0000

0x0B38

0x2811 0B38

RX_Q15_FLUSH

RW

32

0x0000 0000

0x0B3C

0x2811 0B3C

SCR2_REG0_RATE_LIMIT

RW

32

0x0000 0000

0x0B40

0x2811 0B40

SCR2_REG1_RATE_LIMIT

RW

32

0x0000 0000

0x0B44

0x2811 0B44

SCR2_REG2_RATE_LIMIT

RW

32

0x0000 0000

0x0B48

0x2811 0B48

SCR2_REG3_RATE_LIMIT

RW

32

0x0000 0000

0x0B4C

0x2811 0B4C

SCR2_REG4_RATE_LIMIT

RW

32

0x0000 0000

0x0B50

0x2811 0B50

SCR2_REG5_RATE_LIMIT

RW

32

0x0000 0000

0x0B54

0x2811 0B54

SCR2_REG6_RATE_LIMIT

RW

32

0x0000 0000

0x0B58

0x2811 0B58

SCR2_REG7_RATE_LIMIT

RW

32

0x0000 0000

0x0B5C

0x2811 0B5C

SCR2_REG8_RATE_LIMIT

RW

32

0x0000 0000

0x0B60

0x2811 0B60

SCR2_REG9_RATE_LIMIT

RW

32

0x0000 0000

0x0B64

0x2811 0B64

SCR2_REG10_RATE_LIMIT

RW

32

0x0000 0000

0x0B68

0x2811 0B68

SCR2_REG11_RATE_LIMIT

RW

32

0x0000 0000

0x0B6C

0x2811 0B6C

SCR2_REG12_RATE_LIMIT

RW

32

0x0000 0000

0x0B70

0x2811 0B70

SCR2_REG13_RATE_LIMIT

RW

32

0x0000 0000

0x0B74

0x2811 0B74

SCR2_REG14_RATE_LIMIT

RW

32

0x0000 0000

0x0B78

0x2811 0B78

SCR2_REG15_RATE_LIMIT

RW

32

0x0000 0000

0x0B7C

0x2811 0B7C

SCR2_RATE_STATUS

RO

32

0x0000 0000

0x0B80

0x2811 0B80

ASF_INT_STATUS

RW

32

0x0000 0000

0x0E00

0x2811 0E00

ASF_INT_RAW_STATUS

RW

32

0x0000 0000

0x0E04

0x2811 0E04

ASF_INT_MASK

RW

32

0x0000 0030

0x0E08

0x2811 0E08

ASF_INT_TEST

RW

32

0x0000 0000

0x0E0C

0x2811 0E0C

ASF_FATAL_NONFATAL_SELECT

RW

32

0x0000 0030

0x0E10

0x2811 0E10

ASF_TRANS_TO_FAULT_MASK

RW

32

0x0000 000F

0x0E34

0x2811 0E34

ASF_TRANS_TO_FAULT_STATUS

RW

32

0x0000 0000

0x0E38

0x2811 0E38

ASF_PROTOCOL_FAULT_MASK

RW

32

0x003F 01FF

0x0E40

0x2811 0E40

ASF_PROTOCOL_FAULT_STATUS

RW

32

0x0000 0000

0x0E44

0x2811 0E44

 

gem_gximicrosemi : GEM_B_HI Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

NETWORK_CONTROL

RW

32

0x0000 0000

0x0000

0x2811 2000

NETWORK_CONFIG

RW

32

0x0008 0000

0x0004

0x2811 2004

NETWORK_STATUS

RO

32

0x0000 0004

0x0008

0x2811 2008

DMA_CONFIG

RW

32

0x0002 07C4

0x0010

0x2811 2010

TRANSMIT_STATUS

RW

32

0x0000 0000

0x0014

0x2811 2014

RECEIVE_Q_PTR

RW

32

0x0000 0000

0x0018

0x2811 2018

TRANSMIT_Q_PTR

RW

32

0x0000 0000

0x001C

0x2811 201C

RECEIVE_STATUS

RW

32

0x0000 0000

0x0020

0x2811 2020

INT_STATUS

RW

32

0x0000 0000

0x0024

0x2811 2024

INT_ENABLE

RW

32

0x0000 0000

0x0028

0x2811 2028

INT_DISABLE

RW

32

0x0000 0000

0x002C

0x2811 202C

INT_MASK

RO

32

0xFFFC FCFF

0x0030

0x2811 2030

PHY_MANAGEMENT

RW

32

0x0000 0000

0x0034

0x2811 2034

PAUSE_TIME

RO

32

0x0000 0000

0x0038

0x2811 2038

TX_PAUSE_QUANTUM

RW

32

0x0000 FFFF

0x003C

0x2811 203C

PBUF_TXCUTTHRU

RW

32

0x0000 1FFF

0x0040

0x2811 2040

PBUF_RXCUTTHRU

RW

32

0x0000 07FF

0x0044

0x2811 2044

JUMBO_MAX_LENGTH

RW

32

0x0000 3FFF

0x0048

0x2811 2048

AXI_MAX_PIPELINE

RW

32

0x0000 0101

0x0054

0x2811 2054

RSC_CONTROL

RW

32

0x0000 0000

0x0058

0x2811 2058

INT_MODERATION

RW

32

0x0000 0000

0x005C

0x2811 205C

SYS_WAKE_TIME

RW

32

0x0000 0000

0x0060

0x2811 2060

LOCKUP_CONFIG

RW

32

0x07FF FFFF

0x0068

0x2811 2068

MAC_LOCKUP_TIME

RW

32

0x07FF FFFF

0x006C

0x2811 206C

LOCKUP_CONFIG3

RW

32

0x0000 0000

0x0070

0x2811 2070

RX_WATER_MARK

RW

32

0x0000 0000

0x007C

0x2811 207C

HASH_BOTTOM

RW

32

0x0000 0000

0x0080

0x2811 2080

HASH_TOP

RW

32

0x0000 0000

0x0084

0x2811 2084

SPEC_ADD1_BOTTOM

RW

32

0x0000 0000

0x0088

0x2811 2088

SPEC_ADD1_TOP

RW

32

0x0000 0000

0x008C

0x2811 208C

SPEC_ADD2_BOTTOM

RW

32

0x0000 0000

0x0090

0x2811 2090

SPEC_ADD2_TOP

RW

32

0x0000 0000

0x0094

0x2811 2094

SPEC_ADD3_BOTTOM

RW

32

0x0000 0000

0x0098

0x2811 2098

SPEC_ADD3_TOP

RW

32

0x0000 0000

0x009C

0x2811 209C

SPEC_ADD4_BOTTOM

RW

32

0x0000 0000

0x00A0

0x2811 20A0

SPEC_ADD4_TOP

RW

32

0x0000 0000

0x00A4

0x2811 20A4

SPEC_TYPE1

RW

32

0x0000 0000

0x00A8

0x2811 20A8

SPEC_TYPE2

RW

32

0x0000 0000

0x00AC

0x2811 20AC

SPEC_TYPE3

RW

32

0x0000 0000

0x00B0

0x2811 20B0

SPEC_TYPE4

RW

32

0x0000 0000

0x00B4

0x2811 20B4

WOL_REGISTER

RW

32

0x0000 0000

0x00B8

0x2811 20B8

STRETCH_RATIO

RW

32

0x0000 0000

0x00BC

0x2811 20BC

STACKED_VLAN

RW

32

0x0000 0000

0x00C0

0x2811 20C0

TX_PFC_PAUSE

RW

32

0x0000 0000

0x00C4

0x2811 20C4

MASK_ADD1_BOTTOM

RW

32

0x0000 0000

0x00C8

0x2811 20C8

MASK_ADD1_TOP

RW

32

0x0000 0000

0x00CC

0x2811 20CC

DMA_ADDR_OR_MASK

RW

32

0x0000 0000

0x00D0

0x2811 20D0

RX_PTP_UNICAST

RW

32

0x0000 0000

0x00D4

0x2811 20D4

TX_PTP_UNICAST

RW

32

0x0000 0000

0x00D8

0x2811 20D8

TSU_NSEC_CMP

RW

32

0x0000 0000

0x00DC

0x2811 20DC

TSU_SEC_CMP

RW

32

0x0000 0000

0x00E0

0x2811 20E0

TSU_MSB_SEC_CMP

RW

32

0x0000 0000

0x00E4

0x2811 20E4

TSU_PTP_TX_MSB_SEC

RO

32

0x0000 0000

0x00E8

0x2811 20E8

TSU_PTP_RX_MSB_SEC

RO

32

0x0000 0000

0x00EC

0x2811 20EC

TSU_PEER_TX_MSB_SEC

RO

32

0x0000 0000

0x00F0

0x2811 20F0

TSU_PEER_RX_MSB_SEC

RO

32

0x0000 0000

0x00F4

0x2811 20F4

DPRAM_FILL_DBG

RW

32

0x0000 0000

0x00F8

0x2811 20F8

REVISION_REG

RO

32

0x0107 010C

0x00FC

0x2811 20FC

OCTETS_TXED_BOTTOM

RO

32

0x0000 0000

0x0100

0x2811 2100

OCTETS_TXED_TOP

RO

32

0x0000 0000

0x0104

0x2811 2104

FRAMES_TXED_OK

RO

32

0x0000 0000

0x0108

0x2811 2108

BROADCAST_TXED

RO

32

0x0000 0000

0x010C

0x2811 210C

MULTICAST_TXED

RO

32

0x0000 0000

0x0110

0x2811 2110

PAUSE_FRAMES_TXED

RO

32

0x0000 0000

0x0114

0x2811 2114

FRAMES_TXED_64

RO

32

0x0000 0000

0x0118

0x2811 2118

FRAMES_TXED_65

RO

32

0x0000 0000

0x011C

0x2811 211C

FRAMES_TXED_128

RO

32

0x0000 0000

0x0120

0x2811 2120

FRAMES_TXED_256

RO

32

0x0000 0000

0x0124

0x2811 2124

FRAMES_TXED_512

RO

32

0x0000 0000

0x0128

0x2811 2128

FRAMES_TXED_1024

RO

32

0x0000 0000

0x012C

0x2811 212C

FRAMES_TXED_1519

RO

32

0x0000 0000

0x0130

0x2811 2130

TX_UNDERRUNS

RO

32

0x0000 0000

0x0134

0x2811 2134

SINGLE_COLLISIONS

RO

32

0x0000 0000

0x0138

0x2811 2138

MULTIPLE_COLLISIONS

RO

32

0x0000 0000

0x013C

0x2811 213C

EXCESSIVE_COLLISIONS

RO

32

0x0000 0000

0x0140

0x2811 2140

LATE_COLLISIONS

RO

32

0x0000 0000

0x0144

0x2811 2144

DEFERRED_FRAMES

RO

32

0x0000 0000

0x0148

0x2811 2148

CRS_ERRORS

RO

32

0x0000 0000

0x014C

0x2811 214C

OCTETS_RXED_BOTTOM

RO

32

0x0000 0000

0x0150

0x2811 2150

OCTETS_RXED_TOP

RO

32

0x0000 0000

0x0154

0x2811 2154

FRAMES_RXED_OK

RO

32

0x0000 0000

0x0158

0x2811 2158

BROADCAST_RXED

RO

32

0x0000 0000

0x015C

0x2811 215C

MULTICAST_RXED

RO

32

0x0000 0000

0x0160

0x2811 2160

PAUSE_FRAMES_RXED

RO

32

0x0000 0000

0x0164

0x2811 2164

FRAMES_RXED_64

RO

32

0x0000 0000

0x0168

0x2811 2168

FRAMES_RXED_65

RO

32

0x0000 0000

0x016C

0x2811 216C

FRAMES_RXED_128

RO

32

0x0000 0000

0x0170

0x2811 2170

FRAMES_RXED_256

RO

32

0x0000 0000

0x0174

0x2811 2174

FRAMES_RXED_512

RO

32

0x0000 0000

0x0178

0x2811 2178

FRAMES_RXED_1024

RO

32

0x0000 0000

0x017C

0x2811 217C

FRAMES_RXED_1519

RO

32

0x0000 0000

0x0180

0x2811 2180

UNDERSIZE_FRAMES

RO

32

0x0000 0000

0x0184

0x2811 2184

EXCESSIVE_RX_LENGTH

RO

32

0x0000 0000

0x0188

0x2811 2188

RX_JABBERS

RO

32

0x0000 0000

0x018C

0x2811 218C

FCS_ERRORS

RO

32

0x0000 0000

0x0190

0x2811 2190

RX_LENGTH_ERRORS

RO

32

0x0000 0000

0x0194

0x2811 2194

RX_SYMBOL_ERRORS

RO

32

0x0000 0000

0x0198

0x2811 2198

ALIGNMENT_ERRORS

RO

32

0x0000 0000

0x019C

0x2811 219C

RX_RESOURCE_ERRORS

RO

32

0x0000 0000

0x01A0

0x2811 21A0

RX_OVERRUNS

RO

32

0x0000 0000

0x01A4

0x2811 21A4

RX_IP_CK_ERRORS

RO

32

0x0000 0000

0x01A8

0x2811 21A8

RX_TCP_CK_ERRORS

RO

32

0x0000 0000

0x01AC

0x2811 21AC

RX_UDP_CK_ERRORS

RO

32

0x0000 0000

0x01B0

0x2811 21B0

AUTO_FLUSHED_PKTS

RO

32

0x0000 0000

0x01B4

0x2811 21B4

TSU_TIMER_INCR_SUB_NSEC

RW

32

0x0000 0000

0x01BC

0x2811 21BC

TSU_TIMER_MSB_SEC

RW

32

0x0000 0000

0x01C0

0x2811 21C0

TSU_STROBE_MSB_SEC

RO

32

0x0000 0000

0x01C4

0x2811 21C4

TSU_STROBE_SEC

RO

32

0x0000 0000

0x01C8

0x2811 21C8

TSU_STROBE_NSEC

RO

32

0x0000 0000

0x01CC

0x2811 21CC

TSU_TIMER_SEC

RW

32

0x0000 0000

0x01D0

0x2811 21D0

TSU_TIMER_NSEC

RW

32

0x0000 0000

0x01D4

0x2811 21D4

TSU_TIMER_ADJUST

RW

32

0x0000 0000

0x01D8

0x2811 21D8

TSU_TIMER_INCR

RW

32

0x0000 0000

0x01DC

0x2811 21DC

TSU_PTP_TX_SEC

RO

32

0x0000 0000

0x01E0

0x2811 21E0

TSU_PTP_TX_NSEC

RO

32

0x0000 0000

0x01E4

0x2811 21E4

TSU_PTP_RX_SEC

RO

32

0x0000 0000

0x01E8

0x2811 21E8

TSU_PTP_RX_NSEC

RO

32

0x0000 0000

0x01EC

0x2811 21EC

TSU_PEER_TX_SEC

RO

32

0x0000 0000

0x01F0

0x2811 21F0

TSU_PEER_TX_NSEC

RO

32

0x0000 0000

0x01F4

0x2811 21F4

TSU_PEER_RX_SEC

RO

32

0x0000 0000

0x01F8

0x2811 21F8

TSU_PEER_RX_NSEC

RO

32

0x0000 0000

0x01FC

0x2811 21FC

PFC_STATUS

RO

32

0x0000 0000

0x026C

0x2811 226C

RX_LPI

RO

32

0x0000 0000

0x0270

0x2811 2270

RX_LPI_TIME

RO

32

0x0000 0000

0x0274

0x2811 2274

TX_LPI

RO

32

0x0000 0000

0x0278

0x2811 2278

TX_LPI_TIME

RO

32

0x0000 0000

0x027C

0x2811 227C

DESIGNCFG_DEBUG1

RO

32

0x0850 8511

0x0280

0x2811 2280

DESIGNCFG_DEBUG2

RO

32

0x76F1 3FFF

0x0284

0x2811 2284

DESIGNCFG_DEBUG3

RO

32

0x0400 0000

0x0288

0x2811 2288

DESIGNCFG_DEBUG4

RO

32

0x0000 0000

0x028C

0x2811 228C

DESIGNCFG_DEBUG5

RO

32

0x402F A345

0x0290

0x2811 2290

DESIGNCFG_DEBUG6

RO

32

0x0C84 FFFE

0x0294

0x2811 2294

DESIGNCFG_DEBUG7

RO

32

0x0000 0000

0x0298

0x2811 2298

DESIGNCFG_DEBUG8

RO

32

0x1010 0820

0x029C

0x2811 229C

DESIGNCFG_DEBUG9

RO

32

0x0000 0000

0x02A0

0x2811 22A0

DESIGNCFG_DEBUG10

RO

32

0x2444 4442

0x02A4

0x2811 22A4

DESIGNCFG_DEBUG11

RO

32

0x0000 0000

0x02A8

0x2811 22A8

DESIGNCFG_DEBUG12

RO

32

0x0154 4001

0x02AC

0x2811 22AC

AXI_QOS_CFG_0

RW

32

0x0000 0000

0x02E0

0x2811 22E0

AXI_QOS_CFG_1

RW

32

0x0000 0000

0x02E4

0x2811 22E4

AXI_QOS_CFG_2

RW

32

0x0000 0000

0x02E8

0x2811 22E8

AXI_QOS_CFG_3

RW

32

0x0000 0000

0x02EC

0x2811 22EC

INT_Q1_STATUS

RW

32

0x0000 0000

0x0400

0x2811 2400

INT_Q2_STATUS

RW

32

0x0000 0000

0x0404

0x2811 2404

INT_Q3_STATUS

RW

32

0x0000 0000

0x0408

0x2811 2408

INT_Q4_STATUS

RW

32

0x0000 0000

0x040C

0x2811 240C

INT_Q5_STATUS

RW

32

0x0000 0000

0x0410

0x2811 2410

INT_Q6_STATUS

RW

32

0x0000 0000

0x0414

0x2811 2414

INT_Q7_STATUS

RW

32

0x0000 0000

0x0418

0x2811 2418

INT_Q8_STATUS

RW

32

0x0000 0000

0x041C

0x2811 241C

INT_Q9_STATUS

RW

32

0x0000 0000

0x0420

0x2811 2420

INT_Q10_STATUS

RW

32

0x0000 0000

0x0424

0x2811 2424

INT_Q11_STATUS

RW

32

0x0000 0000

0x0428

0x2811 2428

INT_Q12_STATUS

RW

32

0x0000 0000

0x042C

0x2811 242C

INT_Q13_STATUS

RW

32

0x0000 0000

0x0430

0x2811 2430

INT_Q14_STATUS

RW

32

0x0000 0000

0x0434

0x2811 2434

INT_Q15_STATUS

RW

32

0x0000 0000

0x0438

0x2811 2438

TRANSMIT_Q1_PTR

RW

32

0x0000 0000

0x0440

0x2811 2440

TRANSMIT_Q2_PTR

RW

32

0x0000 0000

0x0444

0x2811 2444

TRANSMIT_Q3_PTR

RW

32

0x0000 0000

0x0448

0x2811 2448

TRANSMIT_Q4_PTR

RW

32

0x0000 0000

0x044C

0x2811 244C

TRANSMIT_Q5_PTR

RW

32

0x0000 0000

0x0450

0x2811 2450

TRANSMIT_Q6_PTR

RW

32

0x0000 0000

0x0454

0x2811 2454

TRANSMIT_Q7_PTR

RW

32

0x0000 0000

0x0458

0x2811 2458

TRANSMIT_Q8_PTR

RW

32

0x0000 0000

0x045C

0x2811 245C

TRANSMIT_Q9_PTR

RW

32

0x0000 0000

0x0460

0x2811 2460

TRANSMIT_Q10_PTR

RW

32

0x0000 0000

0x0464

0x2811 2464

TRANSMIT_Q11_PTR

RW

32

0x0000 0000

0x0468

0x2811 2468

TRANSMIT_Q12_PTR

RW

32

0x0000 0000

0x046C

0x2811 246C

TRANSMIT_Q13_PTR

RW

32

0x0000 0000

0x0470

0x2811 2470

TRANSMIT_Q14_PTR

RW

32

0x0000 0000

0x0474

0x2811 2474

TRANSMIT_Q15_PTR

RW

32

0x0000 0000

0x0478

0x2811 2478

RECEIVE_Q1_PTR

RW

32

0x0000 0000

0x0480

0x2811 2480

RECEIVE_Q2_PTR

RW

32

0x0000 0000

0x0484

0x2811 2484

RECEIVE_Q3_PTR

RW

32

0x0000 0000

0x0488

0x2811 2488

RECEIVE_Q4_PTR

RW

32

0x0000 0000

0x048C

0x2811 248C

RECEIVE_Q5_PTR

RW

32

0x0000 0000

0x0490

0x2811 2490

RECEIVE_Q6_PTR

RW

32

0x0000 0000

0x0494

0x2811 2494

RECEIVE_Q7_PTR

RW

32

0x0000 0000

0x0498

0x2811 2498

DMA_RXBUF_SIZE_Q1

RW

32

0x0000 0002

0x04A0

0x2811 24A0

DMA_RXBUF_SIZE_Q2

RW

32

0x0000 0002

0x04A4

0x2811 24A4

DMA_RXBUF_SIZE_Q3

RW

32

0x0000 0002

0x04A8

0x2811 24A8

DMA_RXBUF_SIZE_Q4

RW

32

0x0000 0002

0x04AC

0x2811 24AC

DMA_RXBUF_SIZE_Q5

RW

32

0x0000 0002

0x04B0

0x2811 24B0

DMA_RXBUF_SIZE_Q6

RW

32

0x0000 0002

0x04B4

0x2811 24B4

DMA_RXBUF_SIZE_Q7

RW

32

0x0000 0002

0x04B8

0x2811 24B8

CBS_CONTROL

RW

32

0x0000 0000

0x04BC

0x2811 24BC

CBS_IDLESLOPE_Q_A

RW

32

0x0000 0000

0x04C0

0x2811 24C0

CBS_IDLESLOPE_Q_B

RW

32

0x0000 0000

0x04C4

0x2811 24C4

UPPER_TX_Q_BASE_ADDR

RW

32

0x0000 0000

0x04C8

0x2811 24C8

TX_BD_CONTROL

RW

32

0x0000 0000

0x04CC

0x2811 24CC

RX_BD_CONTROL

RW

32

0x0000 0000

0x04D0

0x2811 24D0

UPPER_RX_Q_BASE_ADDR

RW

32

0x0000 0000

0x04D4

0x2811 24D4

WD_COUNTER

RW

32

0x0000 0007

0x04EC

0x2811 24EC

AXI_TX_FULL_THRESH0

RW

32

0x0006 0008

0x04F8

0x2811 24F8

AXI_TX_FULL_THRESH1

RW

32

0x0000 0000

0x04FC

0x2811 24FC

SCREENING_TYPE_1_REGISTER_0

RW

32

0x0000 0000

0x0500

0x2811 2500

SCREENING_TYPE_1_REGISTER_1

RW

32

0x0000 0000

0x0504

0x2811 2504

SCREENING_TYPE_1_REGISTER_2

RW

32

0x0000 0000

0x0508

0x2811 2508

SCREENING_TYPE_1_REGISTER_3

RW

32

0x0000 0000

0x050C

0x2811 250C

SCREENING_TYPE_1_REGISTER_4

RW

32

0x0000 0000

0x0510

0x2811 2510

SCREENING_TYPE_1_REGISTER_5

RW

32

0x0000 0000

0x0514

0x2811 2514

SCREENING_TYPE_1_REGISTER_6

RW

32

0x0000 0000

0x0518

0x2811 2518

SCREENING_TYPE_1_REGISTER_7

RW

32

0x0000 0000

0x051C

0x2811 251C

SCREENING_TYPE_1_REGISTER_8

RW

32

0x0000 0000

0x0520

0x2811 2520

SCREENING_TYPE_1_REGISTER_9

RW

32

0x0000 0000

0x0524

0x2811 2524

SCREENING_TYPE_1_REGISTER_10

RW

32

0x0000 0000

0x0528

0x2811 2528

SCREENING_TYPE_1_REGISTER_11

RW

32

0x0000 0000

0x052C

0x2811 252C

SCREENING_TYPE_1_REGISTER_12

RW

32

0x0000 0000

0x0530

0x2811 2530

SCREENING_TYPE_1_REGISTER_13

RW

32

0x0000 0000

0x0534

0x2811 2534

SCREENING_TYPE_1_REGISTER_14

RW

32

0x0000 0000

0x0538

0x2811 2538

SCREENING_TYPE_1_REGISTER_15

RW

32

0x0000 0000

0x053C

0x2811 253C

SCREENING_TYPE_2_REGISTER_0

RW

32

0x0000 0000

0x0540

0x2811 2540

SCREENING_TYPE_2_REGISTER_1

RW

32

0x0000 0000

0x0544

0x2811 2544

SCREENING_TYPE_2_REGISTER_2

RW

32

0x0000 0000

0x0548

0x2811 2548

SCREENING_TYPE_2_REGISTER_3

RW

32

0x0000 0000

0x054C

0x2811 254C

SCREENING_TYPE_2_REGISTER_4

RW

32

0x0000 0000

0x0550

0x2811 2550

SCREENING_TYPE_2_REGISTER_5

RW

32

0x0000 0000

0x0554

0x2811 2554

SCREENING_TYPE_2_REGISTER_6

RW

32

0x0000 0000

0x0558

0x2811 2558

SCREENING_TYPE_2_REGISTER_7

RW

32

0x0000 0000

0x055C

0x2811 255C

SCREENING_TYPE_2_REGISTER_8

RW

32

0x0000 0000

0x0560

0x2811 2560

SCREENING_TYPE_2_REGISTER_9

RW

32

0x0000 0000

0x0564

0x2811 2564

SCREENING_TYPE_2_REGISTER_10

RW

32

0x0000 0000

0x0568

0x2811 2568

SCREENING_TYPE_2_REGISTER_11

RW

32

0x0000 0000

0x056C

0x2811 256C

SCREENING_TYPE_2_REGISTER_12

RW

32

0x0000 0000

0x0570

0x2811 2570

SCREENING_TYPE_2_REGISTER_13

RW

32

0x0000 0000

0x0574

0x2811 2574

SCREENING_TYPE_2_REGISTER_14

RW

32

0x0000 0000

0x0578

0x2811 2578

SCREENING_TYPE_2_REGISTER_15

RW

32

0x0000 0000

0x057C

0x2811 257C

TX_SCHED_CTRL

RW

32

0x0000 0000

0x0580

0x2811 2580

BW_RATE_LIMIT_Q0TO3

RW

32

0x0000 0000

0x0590

0x2811 2590

BW_RATE_LIMIT_Q4TO7

RW

32

0x0000 0000

0x0594

0x2811 2594

BW_RATE_LIMIT_Q8TO11

RW

32

0x0000 0000

0x0598

0x2811 2598

BW_RATE_LIMIT_Q12TO15

RW

32

0x0000 0000

0x059C

0x2811 259C

TX_Q_SEG_ALLOC_Q_LOWER

RW

32

0x0000 0000

0x05A0

0x2811 25A0

TX_Q_SEG_ALLOC_Q_UPPER

RW

32

0x0000 0000

0x05A4

0x2811 25A4

RECEIVE_Q8_PTR

RW

32

0x0000 0000

0x05C0

0x2811 25C0

RECEIVE_Q9_PTR

RW

32

0x0000 0000

0x05C4

0x2811 25C4

RECEIVE_Q10_PTR

RW

32

0x0000 0000

0x05C8

0x2811 25C8

RECEIVE_Q11_PTR

RW

32

0x0000 0000

0x05CC

0x2811 25CC

RECEIVE_Q12_PTR

RW

32

0x0000 0000

0x05D0

0x2811 25D0

RECEIVE_Q13_PTR

RW

32

0x0000 0000

0x05D4

0x2811 25D4

RECEIVE_Q14_PTR

RW

32

0x0000 0000

0x05D8

0x2811 25D8

RECEIVE_Q15_PTR

RW

32

0x0000 0000

0x05DC

0x2811 25DC

DMA_RXBUF_SIZE_Q8

RW

32

0x0000 0002

0x05E0

0x2811 25E0

DMA_RXBUF_SIZE_Q9

RW

32

0x0000 0002

0x05E4

0x2811 25E4

DMA_RXBUF_SIZE_Q10

RW

32

0x0000 0002

0x05E8

0x2811 25E8

DMA_RXBUF_SIZE_Q11

RW

32

0x0000 0002

0x05EC

0x2811 25EC

DMA_RXBUF_SIZE_Q12

RW

32

0x0000 0002

0x05F0

0x2811 25F0

DMA_RXBUF_SIZE_Q13

RW

32

0x0000 0002

0x05F4

0x2811 25F4

DMA_RXBUF_SIZE_Q14

RW

32

0x0000 0002

0x05F8

0x2811 25F8

DMA_RXBUF_SIZE_Q15

RW

32

0x0000 0002

0x05FC

0x2811 25FC

INT_Q1_ENABLE

RW

32

0x0000 0000

0x0600

0x2811 2600

INT_Q2_ENABLE

RW

32

0x0000 0000

0x0604

0x2811 2604

INT_Q3_ENABLE

RW

32

0x0000 0000

0x0608

0x2811 2608

INT_Q4_ENABLE

RW

32

0x0000 0000

0x060C

0x2811 260C

INT_Q5_ENABLE

RW

32

0x0000 0000

0x0610

0x2811 2610

INT_Q6_ENABLE

RW

32

0x0000 0000

0x0614

0x2811 2614

INT_Q7_ENABLE

RW

32

0x0000 0000

0x0618

0x2811 2618

INT_Q1_DISABLE

RW

32

0x0000 0000

0x0620

0x2811 2620

INT_Q2_DISABLE

RW

32

0x0000 0000

0x0624

0x2811 2624

INT_Q3_DISABLE

RW

32

0x0000 0000

0x0628

0x2811 2628

INT_Q4_DISABLE

RW

32

0x0000 0000

0x062C

0x2811 262C

INT_Q5_DISABLE

RW

32

0x0000 0000

0x0630

0x2811 2630

INT_Q6_DISABLE

RW

32

0x0000 0000

0x0634

0x2811 2634

INT_Q7_DISABLE

RW

32

0x0000 0000

0x0638

0x2811 2638

INT_Q1_MASK

RO

32

0x0000 08E6

0x0640

0x2811 2640

INT_Q2_MASK

RO

32

0x0000 08E6

0x0644

0x2811 2644

INT_Q3_MASK

RO

32

0x0000 08E6

0x0648

0x2811 2648

INT_Q4_MASK

RO

32

0x0000 08E6

0x064C

0x2811 264C

INT_Q5_MASK

RO

32

0x0000 08E6

0x0650

0x2811 2650

INT_Q6_MASK

RO

32

0x0000 08E6

0x0654

0x2811 2654

INT_Q7_MASK

RO

32

0x0000 08E6

0x0658

0x2811 2658

INT_Q8_ENABLE

RW

32

0x0000 0000

0x0660

0x2811 2660

INT_Q9_ENABLE

RW

32

0x0000 0000

0x0664

0x2811 2664

INT_Q10_ENABLE

RW

32

0x0000 0000

0x0668

0x2811 2668

INT_Q11_ENABLE

RW

32

0x0000 0000

0x066C

0x2811 266C

INT_Q12_ENABLE

RW

32

0x0000 0000

0x0670

0x2811 2670

INT_Q13_ENABLE

RW

32

0x0000 0000

0x0674

0x2811 2674

INT_Q14_ENABLE

RW

32

0x0000 0000

0x0678

0x2811 2678

INT_Q15_ENABLE

RW

32

0x0000 0000

0x067C

0x2811 267C

INT_Q8_DISABLE

RW

32

0x0000 0000

0x0680

0x2811 2680

INT_Q9_DISABLE

RW

32

0x0000 0000

0x0684

0x2811 2684

INT_Q10_DISABLE

RW

32

0x0000 0000

0x0688

0x2811 2688

INT_Q11_DISABLE

RW

32

0x0000 0000

0x068C

0x2811 268C

INT_Q12_DISABLE

RW

32

0x0000 0000

0x0690

0x2811 2690

INT_Q13_DISABLE

RW

32

0x0000 0000

0x0694

0x2811 2694

INT_Q14_DISABLE

RW

32

0x0000 0000

0x0698

0x2811 2698

INT_Q15_DISABLE

RW

32

0x0000 0000

0x069C

0x2811 269C

INT_Q8_MASK

RO

32

0x0000 08E6

0x06A0

0x2811 26A0

INT_Q9_MASK

RO

32

0x0000 08E6

0x06A4

0x2811 26A4

INT_Q10_MASK

RO

32

0x0000 08E6

0x06A8

0x2811 26A8

INT_Q11_MASK

RO

32

0x0000 08E6

0x06AC

0x2811 26AC

INT_Q12_MASK

RO

32

0x0000 08E6

0x06B0

0x2811 26B0

INT_Q13_MASK

RO

32

0x0000 08E6

0x06B4

0x2811 26B4

INT_Q14_MASK

RO

32

0x0000 08E6

0x06B8

0x2811 26B8

INT_Q15_MASK

RO

32

0x0000 08E6

0x06BC

0x2811 26BC

SCREENING_TYPE_2_ETHERTYPE_REG_0

RW

32

0x0000 0000

0x06E0

0x2811 26E0

SCREENING_TYPE_2_ETHERTYPE_REG_1

RW

32

0x0000 0000

0x06E4

0x2811 26E4

SCREENING_TYPE_2_ETHERTYPE_REG_2

RW

32

0x0000 0000

0x06E8

0x2811 26E8

SCREENING_TYPE_2_ETHERTYPE_REG_3

RW

32

0x0000 0000

0x06EC

0x2811 26EC

SCREENING_TYPE_2_ETHERTYPE_REG_4

RW

32

0x0000 0000

0x06F0

0x2811 26F0

SCREENING_TYPE_2_ETHERTYPE_REG_5

RW

32

0x0000 0000

0x06F4

0x2811 26F4

SCREENING_TYPE_2_ETHERTYPE_REG_6

RW

32

0x0000 0000

0x06F8

0x2811 26F8

SCREENING_TYPE_2_ETHERTYPE_REG_7

RW

32

0x0000 0000

0x06FC

0x2811 26FC

TYPE2_COMPARE_0_WORD_0

RW

32

0x0000 0000

0x0700

0x2811 2700

TYPE2_COMPARE_0_WORD_1

RW

32

0x0000 0000

0x0704

0x2811 2704

TYPE2_COMPARE_1_WORD_0

RW

32

0x0000 0000

0x0708

0x2811 2708

TYPE2_COMPARE_1_WORD_1

RW

32

0x0000 0000

0x070C

0x2811 270C

TYPE2_COMPARE_2_WORD_0

RW

32

0x0000 0000

0x0710

0x2811 2710

TYPE2_COMPARE_2_WORD_1

RW

32

0x0000 0000

0x0714

0x2811 2714

TYPE2_COMPARE_3_WORD_0

RW

32

0x0000 0000

0x0718

0x2811 2718

TYPE2_COMPARE_3_WORD_1

RW

32

0x0000 0000

0x071C

0x2811 271C

TYPE2_COMPARE_4_WORD_0

RW

32

0x0000 0000

0x0720

0x2811 2720

TYPE2_COMPARE_4_WORD_1

RW

32

0x0000 0000

0x0724

0x2811 2724

TYPE2_COMPARE_5_WORD_0

RW

32

0x0000 0000

0x0728

0x2811 2728

TYPE2_COMPARE_5_WORD_1

RW

32

0x0000 0000

0x072C

0x2811 272C

TYPE2_COMPARE_6_WORD_0

RW

32

0x0000 0000

0x0730

0x2811 2730

TYPE2_COMPARE_6_WORD_1

RW

32

0x0000 0000

0x0734

0x2811 2734

TYPE2_COMPARE_7_WORD_0

RW

32

0x0000 0000

0x0738

0x2811 2738

TYPE2_COMPARE_7_WORD_1

RW

32

0x0000 0000

0x073C

0x2811 273C

TYPE2_COMPARE_8_WORD_0

RW

32

0x0000 0000

0x0740

0x2811 2740

TYPE2_COMPARE_8_WORD_1

RW

32

0x0000 0000

0x0744

0x2811 2744

TYPE2_COMPARE_9_WORD_0

RW

32

0x0000 0000

0x0748

0x2811 2748

TYPE2_COMPARE_9_WORD_1

RW

32

0x0000 0000

0x074C

0x2811 274C

TYPE2_COMPARE_10_WORD_0

RW

32

0x0000 0000

0x0750

0x2811 2750

TYPE2_COMPARE_10_WORD_1

RW

32

0x0000 0000

0x0754

0x2811 2754

TYPE2_COMPARE_11_WORD_0

RW

32

0x0000 0000

0x0758

0x2811 2758

TYPE2_COMPARE_11_WORD_1

RW

32

0x0000 0000

0x075C

0x2811 275C

TYPE2_COMPARE_12_WORD_0

RW

32

0x0000 0000

0x0760

0x2811 2760

TYPE2_COMPARE_12_WORD_1

RW

32

0x0000 0000

0x0764

0x2811 2764

TYPE2_COMPARE_13_WORD_0

RW

32

0x0000 0000

0x0768

0x2811 2768

TYPE2_COMPARE_13_WORD_1

RW

32

0x0000 0000

0x076C

0x2811 276C

TYPE2_COMPARE_14_WORD_0

RW

32

0x0000 0000

0x0770

0x2811 2770

TYPE2_COMPARE_14_WORD_1

RW

32

0x0000 0000

0x0774

0x2811 2774

TYPE2_COMPARE_15_WORD_0

RW

32

0x0000 0000

0x0778

0x2811 2778

TYPE2_COMPARE_15_WORD_1

RW

32

0x0000 0000

0x077C

0x2811 277C

TYPE2_COMPARE_16_WORD_0

RW

32

0x0000 0000

0x0780

0x2811 2780

TYPE2_COMPARE_16_WORD_1

RW

32

0x0000 0000

0x0784

0x2811 2784

TYPE2_COMPARE_17_WORD_0

RW

32

0x0000 0000

0x0788

0x2811 2788

TYPE2_COMPARE_17_WORD_1

RW

32

0x0000 0000

0x078C

0x2811 278C

TYPE2_COMPARE_18_WORD_0

RW

32

0x0000 0000

0x0790

0x2811 2790

TYPE2_COMPARE_18_WORD_1

RW

32

0x0000 0000

0x0794

0x2811 2794

TYPE2_COMPARE_19_WORD_0

RW

32

0x0000 0000

0x0798

0x2811 2798

TYPE2_COMPARE_19_WORD_1

RW

32

0x0000 0000

0x079C

0x2811 279C

TYPE2_COMPARE_20_WORD_0

RW

32

0x0000 0000

0x07A0

0x2811 27A0

TYPE2_COMPARE_20_WORD_1

RW

32

0x0000 0000

0x07A4

0x2811 27A4

TYPE2_COMPARE_21_WORD_0

RW

32

0x0000 0000

0x07A8

0x2811 27A8

TYPE2_COMPARE_21_WORD_1

RW

32

0x0000 0000

0x07AC

0x2811 27AC

TYPE2_COMPARE_22_WORD_0

RW

32

0x0000 0000

0x07B0

0x2811 27B0

TYPE2_COMPARE_22_WORD_1

RW

32

0x0000 0000

0x07B4

0x2811 27B4

TYPE2_COMPARE_23_WORD_0

RW

32

0x0000 0000

0x07B8

0x2811 27B8

TYPE2_COMPARE_23_WORD_1

RW

32

0x0000 0000

0x07BC

0x2811 27BC

TYPE2_COMPARE_24_WORD_0

RW

32

0x0000 0000

0x07C0

0x2811 27C0

TYPE2_COMPARE_24_WORD_1

RW

32

0x0000 0000

0x07C4

0x2811 27C4

TYPE2_COMPARE_25_WORD_0

RW

32

0x0000 0000

0x07C8

0x2811 27C8

TYPE2_COMPARE_25_WORD_1

RW

32

0x0000 0000

0x07CC

0x2811 27CC

TYPE2_COMPARE_26_WORD_0

RW

32

0x0000 0000

0x07D0

0x2811 27D0

TYPE2_COMPARE_26_WORD_1

RW

32

0x0000 0000

0x07D4

0x2811 27D4

TYPE2_COMPARE_27_WORD_0

RW

32

0x0000 0000

0x07D8

0x2811 27D8

TYPE2_COMPARE_27_WORD_1

RW

32

0x0000 0000

0x07DC

0x2811 27DC

TYPE2_COMPARE_28_WORD_0

RW

32

0x0000 0000

0x07E0

0x2811 27E0

TYPE2_COMPARE_28_WORD_1

RW

32

0x0000 0000

0x07E4

0x2811 27E4

TYPE2_COMPARE_29_WORD_0

RW

32

0x0000 0000

0x07E8

0x2811 27E8

TYPE2_COMPARE_29_WORD_1

RW

32

0x0000 0000

0x07EC

0x2811 27EC

TYPE2_COMPARE_30_WORD_0

RW

32

0x0000 0000

0x07F0

0x2811 27F0

TYPE2_COMPARE_30_WORD_1

RW

32

0x0000 0000

0x07F4

0x2811 27F4

TYPE2_COMPARE_31_WORD_0

RW

32

0x0000 0000

0x07F8

0x2811 27F8

TYPE2_COMPARE_31_WORD_1

RW

32

0x0000 0000

0x07FC

0x2811 27FC

ENST_START_TIME_Q8

RW

32

0x0000 0000

0x0800

0x2811 2800

ENST_START_TIME_Q9

RW

32

0x0000 0000

0x0804

0x2811 2804

ENST_START_TIME_Q10

RW

32

0x0000 0000

0x0808

0x2811 2808

ENST_START_TIME_Q11

RW

32

0x0000 0000

0x080C

0x2811 280C

ENST_START_TIME_Q12

RW

32

0x0000 0000

0x0810

0x2811 2810

ENST_START_TIME_Q13

RW

32

0x0000 0000

0x0814

0x2811 2814

ENST_START_TIME_Q14

RW

32

0x0000 0000

0x0818

0x2811 2818

ENST_START_TIME_Q15

RW

32

0x0000 0000

0x081C

0x2811 281C

ENST_ON_TIME_Q8

RW

32

0x0001 FFFF

0x0820

0x2811 2820

ENST_ON_TIME_Q9

RW

32

0x0001 FFFF

0x0824

0x2811 2824

ENST_ON_TIME_Q10

RW

32

0x0001 FFFF

0x0828

0x2811 2828

ENST_ON_TIME_Q11

RW

32

0x0001 FFFF

0x082C

0x2811 282C

ENST_ON_TIME_Q12

RW

32

0x0001 FFFF

0x0830

0x2811 2830

ENST_ON_TIME_Q13

RW

32

0x0001 FFFF

0x0834

0x2811 2834

ENST_ON_TIME_Q14

RW

32

0x0001 FFFF

0x0838

0x2811 2838

ENST_ON_TIME_Q15

RW

32

0x0001 FFFF

0x083C

0x2811 283C

ENST_OFF_TIME_Q8

RW

32

0x0000 0000

0x0840

0x2811 2840

ENST_OFF_TIME_Q9

RW

32

0x0000 0000

0x0844

0x2811 2844

ENST_OFF_TIME_Q10

RW

32

0x0000 0000

0x0848

0x2811 2848

ENST_OFF_TIME_Q11

RW

32

0x0000 0000

0x084C

0x2811 284C

ENST_OFF_TIME_Q12

RW

32

0x0000 0000

0x0850

0x2811 2850

ENST_OFF_TIME_Q13

RW

32

0x0000 0000

0x0854

0x2811 2854

ENST_OFF_TIME_Q14

RW

32

0x0000 0000

0x0858

0x2811 2858

ENST_OFF_TIME_Q15

RW

32

0x0000 0000

0x085C

0x2811 285C

ENST_CONTROL

RW

32

0x0000 0000

0x0880

0x2811 2880

RX_Q0_FLUSH

RW

32

0x0000 0000

0x0B00

0x2811 2B00

RX_Q1_FLUSH

RW

32

0x0000 0000

0x0B04

0x2811 2B04

RX_Q2_FLUSH

RW

32

0x0000 0000

0x0B08

0x2811 2B08

RX_Q3_FLUSH

RW

32

0x0000 0000

0x0B0C

0x2811 2B0C

RX_Q4_FLUSH

RW

32

0x0000 0000

0x0B10

0x2811 2B10

RX_Q5_FLUSH

RW

32

0x0000 0000

0x0B14

0x2811 2B14

RX_Q6_FLUSH

RW

32

0x0000 0000

0x0B18

0x2811 2B18

RX_Q7_FLUSH

RW

32

0x0000 0000

0x0B1C

0x2811 2B1C

RX_Q8_FLUSH

RW

32

0x0000 0000

0x0B20

0x2811 2B20

RX_Q9_FLUSH

RW

32

0x0000 0000

0x0B24

0x2811 2B24

RX_Q10_FLUSH

RW

32

0x0000 0000

0x0B28

0x2811 2B28

RX_Q11_FLUSH

RW

32

0x0000 0000

0x0B2C

0x2811 2B2C

RX_Q12_FLUSH

RW

32

0x0000 0000

0x0B30

0x2811 2B30

RX_Q13_FLUSH

RW

32

0x0000 0000

0x0B34

0x2811 2B34

RX_Q14_FLUSH

RW

32

0x0000 0000

0x0B38

0x2811 2B38

RX_Q15_FLUSH

RW

32

0x0000 0000

0x0B3C

0x2811 2B3C

SCR2_REG0_RATE_LIMIT

RW

32

0x0000 0000

0x0B40

0x2811 2B40

SCR2_REG1_RATE_LIMIT

RW

32

0x0000 0000

0x0B44

0x2811 2B44

SCR2_REG2_RATE_LIMIT

RW

32

0x0000 0000

0x0B48

0x2811 2B48

SCR2_REG3_RATE_LIMIT

RW

32

0x0000 0000

0x0B4C

0x2811 2B4C

SCR2_REG4_RATE_LIMIT

RW

32

0x0000 0000

0x0B50

0x2811 2B50

SCR2_REG5_RATE_LIMIT

RW

32

0x0000 0000

0x0B54

0x2811 2B54

SCR2_REG6_RATE_LIMIT

RW

32

0x0000 0000

0x0B58

0x2811 2B58

SCR2_REG7_RATE_LIMIT

RW

32

0x0000 0000

0x0B5C

0x2811 2B5C

SCR2_REG8_RATE_LIMIT

RW

32

0x0000 0000

0x0B60

0x2811 2B60

SCR2_REG9_RATE_LIMIT

RW

32

0x0000 0000

0x0B64

0x2811 2B64

SCR2_REG10_RATE_LIMIT

RW

32

0x0000 0000

0x0B68

0x2811 2B68

SCR2_REG11_RATE_LIMIT

RW

32

0x0000 0000

0x0B6C

0x2811 2B6C

SCR2_REG12_RATE_LIMIT

RW

32

0x0000 0000

0x0B70

0x2811 2B70

SCR2_REG13_RATE_LIMIT

RW

32

0x0000 0000

0x0B74

0x2811 2B74

SCR2_REG14_RATE_LIMIT

RW

32

0x0000 0000

0x0B78

0x2811 2B78

SCR2_REG15_RATE_LIMIT

RW

32

0x0000 0000

0x0B7C

0x2811 2B7C

SCR2_RATE_STATUS

RO

32

0x0000 0000

0x0B80

0x2811 2B80

ASF_INT_STATUS

RW

32

0x0000 0000

0x0E00

0x2811 2E00

ASF_INT_RAW_STATUS

RW

32

0x0000 0000

0x0E04

0x2811 2E04

ASF_INT_MASK

RW

32

0x0000 0030

0x0E08

0x2811 2E08

ASF_INT_TEST

RW

32

0x0000 0000

0x0E0C

0x2811 2E0C

ASF_FATAL_NONFATAL_SELECT

RW

32

0x0000 0030

0x0E10

0x2811 2E10

ASF_TRANS_TO_FAULT_MASK

RW

32

0x0000 000F

0x0E34

0x2811 2E34

ASF_TRANS_TO_FAULT_STATUS

RW

32

0x0000 0000

0x0E38

0x2811 2E38

ASF_PROTOCOL_FAULT_MASK

RW

32

0x003F 01FF

0x0E40

0x2811 2E40

ASF_PROTOCOL_FAULT_STATUS

RW

32

0x0000 0000

0x0E44

0x2811 2E44

 

gem_gximicrosemi Register Descriptions

gem_gximicrosemi : NETWORK_CONTROL

Address offset

0x0000

Physical address

0x2011 0000

Instance

GEM_A_LO

0x2011 2000

GEM_B_LO

0x2811 0000

GEM_A_HI

0x2811 2000

GEM_B_HI

Description

The network control register contains general MAC control functions for both receiver and transmitter.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

reserved_31

 

RO

0

30

ifg_eats_qav_credit

 

RW

0

29

two_pt_five_gig

MAC_x_SPEED_MODE_M2F [3] indicates the value of the two_pt_five_-gig bit 29 of the network control register

RW

0

28

sel_mii_on_rgmii

 

RW

0

27

oss_correction_field

 

RW

0

26

ext_rxq_sel_en

 

RW

0

25

reserved_25

 

RO

0

24

one_step_sync_mode

 

RW

0

23

reserved_23

 

RO

0

22

store_udp_offset

 

RW

0

21

reserved_21

 

RW

0

20

ptp_unicast_ena

 

RW

0

19

tx_lpi_en

 

RW

0

18

flush_rx_pkt_pclk

 

WO

0

17

transmit_pfc_priority_based_pause_frame

 

WO

0

16

pfc_enable

 

RW

0

15

store_rx_ts

 

RW

0

14:13

reserved_14_13

 

RO

0x0

12

tx_pause_frame_zero

 

WO

0

11

tx_pause_frame_req

 

WO

0

10

transmit_halt

 

WO

0

9

transmit_start

 

WO

0

8

back_pressure

 

RW

0

7

stats_write_en

 

RW

0

6

inc_all_stats_regs

 

WO

0

5

clear_all_stats_regs

 

WO

0

4

man_port_en

 

RW

0

3

enable_transmit

 

RW

0

2

enable_receive

 

RW

0

1

loopback_local

 

RW

0

0

loopback

 

RW

0

 

gem_gximicrosemi : NETWORK_CONFIG

Address offset

0x0004

Physical address

0x2011 0004

Instance

GEM_A_LO

0x2011 2004

GEM_B_LO

0x2811 0004

GEM_A_HI

0x2811 2004

GEM_B_HI

Description

The network configuration register contains functions for setting the mode of operation for the Gigabit Ethernet MAC.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

reserved_31

 

RW

0

30

ignore_ipg_rx_er

 

RW

0

29

nsp_change

 

RW

0

28

ipg_stretch_enable

 

RW

0

27

reserved_27

 

RW

0

26

ignore_rx_fcs

 

RW

0

25

en_half_duplex_rx

 

RW

0

24

receive_checksum_offload_enable

 

RW

0

23

disable_copy_of_pause_frames

 

RW

0

22:21

data_bus_width

 

RW

0x0

20:18

mdc_clock_division

 

RW

0x2

17

fcs_remove

 

RW

0

16

length_field_error_frame_discard

 

RW

0

15:14

receive_buffer_offset

 

RW

0x0

13

pause_enable

 

RW

0

12

retry_test

 

RW

0

11

reserved_11

MAC_x_SPEED_MODE_M2F [2] indicates the value of the reserved_11 bit 11 of the network config register

RW

0

10

gigabit_mode_enable

MAC_x_SPEED_MODE_M2F [1] indicates the value of the gigabit_mode_enable bit 10 of the network config register

RW

0

9

external_address_match_enable

 

RW

0

8

receive_1536_byte_frames

 

RW

0

7

unicast_hash_enable

 

RW

0

6

multicast_hash_enable

 

RW

0

5

no_broadcast

 

RW

0

4

copy_all_frames

 

RW

0

3

jumbo_frames

 

RW

0

2

discard_non_vlan_frames

 

RW

0

1

full_duplex

 

RW

0

0

speed

MAC_x_SPEED_MODE_M2F [0] indicates the value of the speed bit 0 of the network config register

RW

0

 

gem_gximicrosemi : NETWORK_STATUS

Address offset

0x0008

Physical address

0x2011 0008

Instance

GEM_A_LO

0x2011 2008

GEM_B_LO

0x2811 0008

GEM_A_HI

0x2811 2008

GEM_B_HI

Description

The network status register returns status information with respect to the PHY management MDIO interface, the PCS, priority flow control, LPI and other status.

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:11

reserved_31_11

 

RO

0x00 0000

10:9

link_fault_indication

 

RO

0x0

8

axi_xaction_outstanding

 

RO

0

7

lpi_indicate_pclk

 

RO

0

6

pfc_negotiate_pclk

 

RO

0

5:4

reserved_5_4

 

RO

0x0

3

reserved_3

 

RO

0

2

man_done

 

RO

1

1

mdio_in

 

RO

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : DMA_CONFIG

Address offset

0x0010

Physical address

0x2011 0010

Instance

GEM_A_LO

0x2011 2010

GEM_B_LO

0x2811 0010

GEM_A_HI

0x2811 2010

GEM_B_HI

Description

DMA Configuration Register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

reserved_31

 

RO

0

30

dma_addr_bus_width_1

 

RW

0

29

tx_bd_extended_mode_en

 

RW

0

28

rx_bd_extended_mode_en

 

RW

0

27

reserved_27

 

RO

0

26

force_max_amba_burst_tx

 

RW

0

25

force_max_amba_burst_rx

 

RW

0

24

force_discard_on_err

 

RW

0

23:16

rx_buf_size

 

RW

0x02

15:14

reserved_15_14

 

RO

0x0

13

crc_error_report

 

RW

0

12

infinite_last_dbuf_size_en

 

RW

0

11

tx_pbuf_tcp_en

 

RW

0

10

tx_pbuf_size

 

RW

1

9:8

rx_pbuf_size

 

RW

0x3

7

endian_swap_packet

 

RW

1

6

endian_swap_management

 

RW

1

5

hdr_data_splitting_en

 

RW

0

4:0

amba_burst_length

 

RW

0x04

 

gem_gximicrosemi : TRANSMIT_STATUS

Address offset

0x0014

Physical address

0x2011 0014

Instance

GEM_A_LO

0x2011 2014

GEM_B_LO

0x2811 0014

GEM_A_HI

0x2811 2014

GEM_B_HI

Description

This register, when read, provides details of the status of the transmit path. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:11

reserved_31_11

 

RO

0x00 0000

10

tx_dma_lockup_detected

 

RW
W1toClr

0

9

tx_mac_lockup_detected

 

RW
W1toClr

0

8

resp_not_ok

 

RW
W1toClr

0

7

late_collision_occurred

 

RW
W1toClr

0

6

transmit_under_run

 

RW
W1toClr

0

5

transmit_complete

 

RW
W1toClr

0

4

amba_error

 

RW
W1toClr

0

3

transmit_go

 

RO

0

2

retry_limit_exceeded

 

RW
W1toClr

0

1

collision_occurred

 

RW
W1toClr

0

0

used_bit_read

 

RW
W1toClr

0

 

gem_gximicrosemi : RECEIVE_Q_PTR

Address offset

0x0018

Physical address

0x2011 0018

Instance

GEM_A_LO

0x2011 2018

GEM_B_LO

0x2811 0018

GEM_A_HI

0x2811 2018

GEM_B_HI

Description

This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the network control register. Once reception is enabled, any write to the receive buffer queue base address register is ignored. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the used bits. In terms of AMBA (AHB/AXI) operation, the receive descriptors are read from memory using a single 32bit AHB/AXI access. When the datapath is configured at 64bit or 128bit, the receive descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is written to using a single 64bit AHB/AXI access. For 32bit datapaths, the receive descriptors should be aligned at 32-bit boundaries and are written to using two individual non sequential 32-bit accesses.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

dma_rx_q_ptr

 

RW

0x0000 0000

1

reserved_1

 

RO

0

0

dma_rx_dis_q

 

RW

0

 

gem_gximicrosemi : TRANSMIT_Q_PTR

Address offset

0x001C

Physical address

0x2011 001C

Instance

GEM_A_LO

0x2011 201C

GEM_B_LO

0x2811 001C

GEM_A_HI

0x2811 201C

GEM_B_HI

Description

This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AHB/AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit or 128bit, the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AHB/AXI access. For 32bit datapaths, the descriptors should be aligned at 32-bit boundaries and the descriptors are read from memory using two individual 32-bit non sequential accesses.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

dma_tx_q_ptr

 

RW

0x0000 0000

1

reserved_1

 

RO

0

0

dma_tx_dis_q

 

RW

0

 

gem_gximicrosemi : RECEIVE_STATUS

Address offset

0x0020

Physical address

0x2011 0020

Instance

GEM_A_LO

0x2011 2020

GEM_B_LO

0x2811 0020

GEM_A_HI

0x2811 2020

GEM_B_HI

Description

This register, when read provides details of the status of the receive path. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:6

reserved_31_6

 

RO

0x000 0000

5

rx_dma_lockup_detected

 

RW
W1toClr

0

4

rx_mac_lockup_detected

 

RW
W1toClr

0

3

resp_not_ok

 

RW
W1toClr

0

2

receive_overrun

 

RW
W1toClr

0

1

frame_received

 

RW
W1toClr

0

0

buffer_not_available

 

RW
W1toClr

0

 

gem_gximicrosemi : INT_STATUS

Address offset

0x0024

Physical address

0x2011 0024

Instance

GEM_A_LO

0x2011 2024

GEM_B_LO

0x2811 0024

GEM_A_HI

0x2811 2024

GEM_B_HI

Description

If not configured for priority queuing, the GEM generates a single interrupt. This register indicates the source of this interrupt. The corresponding bit in the mask register must be clear for a bit to be set. If any bit is set in this register the ethernet_int signal will be asserted. For test purposes each bit can be set or reset by writing to the interrupt mask register. The default configuration is shown below whereby all bits are reset to zero on read. Changing the validity of the `gem_irq_read_clear define will instead require a one to be written to the appropriate bit in order to clear it. In this mode reading has no effect on the status of the bit.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

tx_lockup_detected

 

RW
W1toClr

0

30

rx_lockup_detected

 

RW
W1toClr

0

29

tsu_timer_comparison_interrupt

 

RW
W1toClr

0

28

wol_interrupt

 

RW
W1toClr

0

27

receive_lpi_indication_status_bit_change

 

RW
W1toClr

0

26

tsu_seconds_register_increment

 

RW
W1toClr

0

25

ptp_pdelay_resp_frame_transmitted

 

RW
W1toClr

0

24

ptp_pdelay_req_frame_transmitted

 

RW
W1toClr

0

23

ptp_pdelay_resp_frame_received

 

RW
W1toClr

0

22

ptp_pdelay_req_frame_received

 

RW
W1toClr

0

21

ptp_sync_frame_transmitted

 

RW
W1toClr

0

20

ptp_delay_req_frame_transmitted

 

RW
W1toClr

0

19

ptp_sync_frame_received

 

RW
W1toClr

0

18

ptp_delay_req_frame_received

 

RW
W1toClr

0

17

reserved_17

 

RO

0

16

reserved_16

 

RO

0

15

external_interrupt

 

RW
W1toClr

0

14

pause_frame_transmitted

 

RW
W1toClr

0

13

pause_time_elapsed

 

RW
W1toClr

0

12

pause_frame_with_non_zero_pause_quantum_received

 

RW
W1toClr

0

11

resp_not_ok

 

RW
W1toClr

0

10

receive_overrun

 

RW
W1toClr

0

9

reserved_9

 

RO

0

8

reserved_8

 

RO

0

7

transmit_complete

 

RW
W1toClr

0

6

amba_error

 

RW
W1toClr

0

5

retry_limit_exceeded_or_late_collision

 

RW
W1toClr

0

4

transmit_under_run

 

RW
W1toClr

0

3

tx_used_bit_read

 

RW
W1toClr

0

2

rx_used_bit_read

 

RW
W1toClr

0

1

receive_complete

 

RW
W1toClr

0

0

management_frame_sent

 

RW
W1toClr

0

 

gem_gximicrosemi : INT_ENABLE

Address offset

0x0028

Physical address

0x2011 0028

Instance

GEM_A_LO

0x2011 2028

GEM_B_LO

0x2811 0028

GEM_A_HI

0x2811 2028

GEM_B_HI

Description

At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

enable_tx_lockup_detected_interrupt

 

WO

0

30

enable_rx_lockup_detected_interrupt

 

WO

0

29

enable_tsu_timer_comparison_interrupt

 

WO

0

28

enable_wol_event_received_interrupt

 

WO

0

27

enable_rx_lpi_indication_interrupt

 

WO

0

26

enable_tsu_seconds_register_increment

 

WO

0

25

enable_ptp_pdelay_resp_frame_transmitted

 

WO

0

24

enable_ptp_pdelay_req_frame_transmitted

 

WO

0

23

enable_ptp_pdelay_resp_frame_received

 

WO

0

22

enable_ptp_pdelay_req_frame_received

 

WO

0

21

enable_ptp_sync_frame_transmitted

 

WO

0

20

enable_ptp_delay_req_frame_transmitted

 

WO

0

19

enable_ptp_sync_frame_received

 

WO

0

18

enable_ptp_delay_req_frame_received

 

WO

0

17

reserved_17

 

RO

0

16

reserved_16

 

RO

0

15

enable_external_interrupt

 

WO

0

14

enable_pause_frame_transmitted_interrupt

 

WO

0

13

enable_pause_time_zero_interrupt

 

WO

0

12

enable_pause_frame_with_non_zero_pause_quantum_interrupt

 

WO

0

11

enable_resp_not_ok_interrupt

 

WO

0

10

enable_receive_overrun_interrupt

 

WO

0

9

reserved_9

 

RO

0

8

reserved_8

 

RO

0

7

enable_transmit_complete_interrupt

 

WO

0

6

enable_transmit_frame_corruption_due_to_amba_error_interrupt

 

WO

0

5

enable_retry_limit_exceeded_or_late_collision_interrupt

 

WO

0

4

enable_transmit_buffer_under_run_interrupt

 

WO

0

3

enable_transmit_used_bit_read_interrupt

 

WO

0

2

enable_receive_used_bit_read_interrupt

 

WO

0

1

enable_receive_complete_interrupt

 

WO

0

0

enable_management_done_interrupt

 

WO

0

 

gem_gximicrosemi : INT_DISABLE

Address offset

0x002C

Physical address

0x2011 002C

Instance

GEM_A_LO

0x2011 202C

GEM_B_LO

0x2811 002C

GEM_A_HI

0x2811 202C

GEM_B_HI

Description

Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

disable_tx_lockup_detected_interrupt

 

WO

0

30

disable_rx_lockup_detected_interrupt

 

WO

0

29

disable_tsu_timer_comparison_interrupt

 

WO

0

28

disable_wol_event_received_interrupt

 

WO

0

27

disable_rx_lpi_indication_interrupt

 

WO

0

26

disable_tsu_seconds_register_increment

 

WO

0

25

disable_ptp_pdelay_resp_frame_transmitted

 

WO

0

24

disable_ptp_pdelay_req_frame_transmitted

 

WO

0

23

disable_ptp_pdelay_resp_frame_received

 

WO

0

22

disable_ptp_pdelay_req_frame_received

 

WO

0

21

disable_ptp_sync_frame_transmitted

 

WO

0

20

disable_ptp_delay_req_frame_transmitted

 

WO

0

19

disable_ptp_sync_frame_received

 

WO

0

18

disable_ptp_delay_req_frame_received

 

WO

0

17

reserved_17

 

RO

0

16

reserved_16

 

RO

0

15

disable_external_interrupt

 

WO

0

14

disable_pause_frame_transmitted_interrupt

 

WO

0

13

disable_pause_time_zero_interrupt

 

WO

0

12

disable_pause_frame_with_non_zero_pause_quantum_interrupt

 

WO

0

11

disable_resp_not_ok_interrupt

 

WO

0

10

disable_receive_overrun_interrupt

 

WO

0

9

reserved_9

 

RO

0

8

reserved_8

 

RO

0

7

disable_transmit_complete_interrupt

 

WO

0

6

disable_transmit_frame_corruption_due_to_amba_error_interrupt

 

WO

0

5

disable_retry_limit_exceeded_or_late_collision_interrupt

 

WO

0

4

disable_transmit_buffer_under_run_interrupt

 

WO

0

3

disable_transmit_used_bit_read_interrupt

 

WO

0

2

disable_receive_used_bit_read_interrupt

 

WO

0

1

disable_receive_complete_interrupt

 

WO

0

0

disable_management_done_interrupt

 

WO

0

 

gem_gximicrosemi : INT_MASK

Address offset

0x0030

Physical address

0x2011 0030

Instance

GEM_A_LO

0x2011 2030

GEM_B_LO

0x2811 0030

GEM_A_HI

0x2811 2030

GEM_B_HI

Description

The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register.

Type

RO

 

Bits

Field Name

Description

Type

Reset

31

tx_lockup_detected_mask

 

RO

1

30

rx_lockup_detected_mask

 

RO

1

29

tsu_timer_comparison_mask

 

RO

1

28

wol_event_received_mask

 

RO

1

27

rx_lpi_indication_mask

 

RO

1

26

tsu_seconds_register_increment_mask

 

RO

1

25

ptp_pdelay_resp_frame_transmitted_mask

 

RO

1

24

ptp_pdelay_req_frame_transmitted_mask

 

RO

1

23

ptp_pdelay_resp_frame_received_mask

 

RO

1

22

ptp_pdelay_req_frame_received_mask

 

RO

1

21

ptp_sync_frame_transmitted_mask

 

RO

1

20

ptp_delay_req_frame_transmitted_mask

 

RO

1

19

ptp_sync_frame_received_mask

 

RO

1

18

ptp_delay_req_frame_received_mask

 

RO

1

17

reserved_17

 

RO

0

16

reserved_16

 

RO

0

15

external_interrupt_mask

 

RO

1

14

pause_frame_transmitted_interrupt_mask

 

RO

1

13

pause_time_zero_interrupt_mask

 

RO

1

12

pause_frame_with_non_zero_pause_quantum_interrupt_mask

 

RO

1

11

resp_not_ok_interrupt_mask

 

RO

1

10

receive_overrun_interrupt_mask

 

RO

1

9

reserved_9

 

RO

0

8

reserved_8

 

RO

0

7

transmit_complete_interrupt_mask

 

RO

1

6

amba_error_interrupt_mask

 

RO

1

5

retry_limit_exceeded_or_late_collision_mask

 

RO

1

4

transmit_buffer_under_run_interrupt_mask

 

RO

1

3

transmit_used_bit_read_interrupt_mask

 

RO

1

2

receive_used_bit_read_interrupt_mask

 

RO

1

1

receive_complete_interrupt_mask

 

RO

1

0

management_done_interrupt_mask

 

RO

1

 

gem_gximicrosemi : PHY_MANAGEMENT

Address offset

0x0034

Physical address

0x2011 0034

Instance

GEM_A_LO

0x2011 2034

GEM_B_LO

0x2811 0034

GEM_A_HI

0x2811 2034

GEM_B_HI

Description

The PHY management register is implemented as a shift register. Writing to the register starts a shift operation which is signalled as complete when bit-2 is set in the network status register. It takes about 2000 pclk cycles to complete, when MDC is set for pclk divide by 32 in the network configuration register. An interrupt is generated upon completion. During this time, the MSB of the register is output on the MDIO pin and the LSB updated from the MDIO pin with each MDC cycle. This causes transmission of a PHY management frame on MDIO. See Section 22.2.4.5 of the IEEE 802.3 standard. Reading during the shift operation will return the current contents of the shift register. At the end of management operation, the bits will have shifted back to their original locations. For a read operation, the data bits will be updated with data read from the PHY. It is important to write the correct values to the register to ensure a valid PHY management frame is produced. The MDIO interface can read IEEE 802.3 clause 45 PHYs as well as clause 22 PHYs. To read clause 45 PHYs, bit 30 should be written with a 0 rather than a 1. For a description of MDC generation, see Network Configuration Register.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

write0

 

RW

0

30

write1

 

RW

0

29:28

operation

 

RW

0x0

27:23

phy_address

 

RW

0x00

22:18

register_address

 

RW

0x00

17:16

write10

 

RW

0x0

15:0

phy_write_read_data

 

RW

0x0000

 

gem_gximicrosemi : PAUSE_TIME

Address offset

0x0038

Physical address

0x2011 0038

Instance

GEM_A_LO

0x2011 2038

GEM_B_LO

0x2811 0038

GEM_A_HI

0x2811 2038

GEM_B_HI

Description

Received Pause Quantum Register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:16

reserved_31_16

 

RO

0x0000

15:0

quantum

 

RO

0x0000

 

gem_gximicrosemi : TX_PAUSE_QUANTUM

Address offset

0x003C

Physical address

0x2011 003C

Instance

GEM_A_LO

0x2011 203C

GEM_B_LO

0x2811 003C

GEM_A_HI

0x2811 203C

GEM_B_HI

Description

Transmit Pause Quantum Register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

reserved_31_16

 

RO

0x0000

15:0

quantum

 

RW

0xFFFF

 

gem_gximicrosemi : PBUF_TXCUTTHRU

Address offset

0x0040

Physical address

0x2011 0040

Instance

GEM_A_LO

0x2011 2040

GEM_B_LO

0x2811 0040

GEM_A_HI

0x2811 2040

GEM_B_HI

Description

Transmit Partial Store and Forward Register. Partial store and forward is only applicable when using the DMA configured in SRAM based packet buffer mode. It is also not available when using multi buffer frames. This register contains the enable bit and watermark value for transmit cut-through operation.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

dma_tx_cutthru

 

RW

0

30:13

reserved

 

RO

0x0 0000

12:0

dma_tx_cutthru_threshold

 

RW

0x1FFF

 

gem_gximicrosemi : PBUF_RXCUTTHRU

Address offset

0x0044

Physical address

0x2011 0044

Instance

GEM_A_LO

0x2011 2044

GEM_B_LO

0x2811 0044

GEM_A_HI

0x2811 2044

GEM_B_HI

Description

Receive Partial Store and Forward Register. Partial store and forward is only applicable when using the DMA configured in SRAM based packet buffer mode. It is also not available when using multi buffer frames. This register contains the enable bit and watermark value for receive cut-through operation.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

dma_rx_cutthru

 

RW

0

30:11

reserved

 

RO

0x0 0000

10:0

dma_rx_cutthru_threshold

 

RW

0x7FF

 

gem_gximicrosemi : JUMBO_MAX_LENGTH

Address offset

0x0048

Physical address

0x2011 0048

Instance

GEM_A_LO

0x2011 2048

GEM_B_LO

0x2811 0048

GEM_A_HI

0x2811 2048

GEM_B_HI

Description

Maximum Jumbo Frame Size.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:14

reserved_31_14

 

RO

0x0 0000

13:0

jumbo_max_length

 

RW

0x3FFF

 

gem_gximicrosemi : AXI_MAX_PIPELINE

Address offset

0x0054

Physical address

0x2011 0054

Instance

GEM_A_LO

0x2011 2054

GEM_B_LO

0x2811 0054

GEM_A_HI

0x2811 2054

GEM_B_HI

Description

Used to set the maximum amount of outstanding transactions on the AXI bus between AR / R channels and AW / W channels. Cannot be more than the depth of the configured AXI pipeline FIFO (defined in verilog defs.v)

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:17

reserved

 

RO

0x0000

16

use_aw2b_fill

 

RW

0

15:8

aw2w_max_pipeline

 

RW

0x01

7:0

ar2r_max_pipeline

 

RW

0x01

 

gem_gximicrosemi : RSC_CONTROL

Address offset

0x0058

Physical address

0x2011 0058

Instance

GEM_A_LO

0x2011 2058

GEM_B_LO

0x2811 0058

GEM_A_HI

0x2811 2058

GEM_B_HI

Description

Used to enable Receive side coalescing on queues 1-15

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:17

reserved_31_17

 

RO

0x0000

16

rsc_clr_mask

 

RW

0

15:1

rsc_control

 

RW

0x0000

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_MODERATION

Address offset

0x005C

Physical address

0x2011 005C

Instance

GEM_A_LO

0x2011 205C

GEM_B_LO

0x2811 005C

GEM_A_HI

0x2811 205C

GEM_B_HI

Description

Used to moderate the number of transmit and receive complete interrupts issued. With interrupt moderation enabled receive and transmit interrupts are not generated immediately a frame is transmitted or received. Instead when a receive or transmit event occurs a timer is started and the interrupt is asserted after it times out. This limits the frequency with which the CPU receives interrupts. When interrupt moderation is enabled interrupt status bit one is always used for receive and bit 7 is always used for transmit even when priority queuing is enabled. With interrupt moderation 800ns periods are counted. GEM determines what constitutes an 800ns period by looking at the tbi (bit 11), gigabit bit (10) and speed (bit 0) bits in the network configuration register and counting tx_clk cycles. Bit 0 needs to be set to 1 for 100M operation., :From release 1p11 onwards a frame threshold value may also be used to moderate interrupts. If both time based and frame threshold moderation is enabled the interrupt will be asserted as soon as the first moderation method expires.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:24

tx_int_mod_thresh

 

RW

0x00

23:16

tx_int_moderation

 

RW

0x00

15:8

rx_int_mod_thresh

 

RW

0x00

7:0

rx_int_moderation

 

RW

0x00

 

gem_gximicrosemi : SYS_WAKE_TIME

Address offset

0x0060

Physical address

0x2011 0060

Instance

GEM_A_LO

0x2011 2060

GEM_B_LO

0x2811 0060

GEM_A_HI

0x2811 2060

GEM_B_HI

Description

Used to pause transmission after deassertion of tx_lpi_en. Each unit in this register corresponds to 25.6ns in 2.5G mode, 64ns in gigabit mode, 320ns in 100M mode and 3200ns at 10M. After tx_lpi_en is deasserted transmission will pause for the set time.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

reserved_31_16

 

RO

0x0000

15:0

sys_wake_time

 

RW

0x0000

 

gem_gximicrosemi : LOCKUP_CONFIG

Address offset

0x0068

Physical address

0x2011 0068

Instance

GEM_A_LO

0x2011 2068

GEM_B_LO

0x2811 0068

GEM_A_HI

0x2811 2068

GEM_B_HI

Description

The lockup detection and recovery configuration register.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

tx_dma_lockup_mon_en

 

RW

0

30

tx_mac_lockup_mon_en

 

RW

0

29

rx_dma_lockup_mon_en

 

RW

0

28

rx_mac_lockup_mon_en

 

RW

0

27

lockup_recovery_en

 

RW

0

26:16

dma_lockup_time

 

RW

0x7FF

15:0

prescaler_value

 

RW

0xFFFF

 

gem_gximicrosemi : MAC_LOCKUP_TIME

Address offset

0x006C

Physical address

0x2011 006C

Instance

GEM_A_LO

0x2011 206C

GEM_B_LO

0x2811 006C

GEM_A_HI

0x2811 206C

GEM_B_HI

Description

MAC lockup detection time register. For receive this register specifies the maximum time between received frames. If no valid EOP is seen at the receive FIFO interface within the timer period then a lockup is considered to have occurred in the receive MAC. For transmit the MAC lockup time is simply the time it takes for data to be seen on the MII output pins after entering on the MAC FIFO interface.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:27

reserved_31_27

 

RO

0x00

26:16

tx_mac_lockup_time

 

RW

0x7FF

15:0

rx_mac_lockup_time

 

RW

0xFFFF

 

gem_gximicrosemi : LOCKUP_CONFIG3

Address offset

0x0070

Physical address

0x2011 0070

Instance

GEM_A_LO

0x2011 2070

GEM_B_LO

0x2811 0070

GEM_A_HI

0x2811 2070

GEM_B_HI

Description

DMA TX Lockup Enable Control Register. This register enables the lockup timer for each individual queue. If this is set to 0, the number of outstanding packets are still counted but the actual timer does not run.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

reserved_31_16

 

RO

0x0000

15

dma_tx_lockup_en_q_15

 

RW

0

14

dma_tx_lockup_en_q_14

 

RW

0

13

dma_tx_lockup_en_q_13

 

RW

0

12

dma_tx_lockup_en_q_12

 

RW

0

11

dma_tx_lockup_en_q_11

 

RW

0

10

dma_tx_lockup_en_q_10

 

RW

0

9

dma_tx_lockup_en_q_9

 

RW

0

8

dma_tx_lockup_en_q_8

 

RW

0

7

dma_tx_lockup_en_q_7

 

RW

0

6

dma_tx_lockup_en_q_6

 

RW

0

5

dma_tx_lockup_en_q_5

 

RW

0

4

dma_tx_lockup_en_q_4

 

RW

0

3

dma_tx_lockup_en_q_3

 

RW

0

2

dma_tx_lockup_en_q_2

 

RW

0

1

dma_tx_lockup_en_q_1

 

RW

0

0

dma_tx_lockup_en_q_0

 

RW

0

 

gem_gximicrosemi : RX_WATER_MARK

Address offset

0x007C

Physical address

0x2011 007C

Instance

GEM_A_LO

0x2011 207C

GEM_B_LO

0x2811 007C

GEM_A_HI

0x2811 207C

GEM_B_HI

Description

rx_water_mark - Receive water mark register. This register contains the high and low water-marks for automatic transmission of pause frames. The water-marks are compared against the internal signal rx_dpram_fill_lvl which is readable in the dpram_fill_dbg register; rx_dpram_fill_lvl indicates the number of words used in the receive SRAM (word length is configuration dependent and may be 4, 8 and 16 bytes). A value of zero in a field disables the corresponding functionality.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

rx_low_watermark

 

RW

0x0000

15:0

rx_high_watermark

 

RW

0x0000

 

gem_gximicrosemi : HASH_BOTTOM

Address offset

0x0080

Physical address

0x2011 0080

Instance

GEM_A_LO

0x2011 2080

GEM_B_LO

0x2811 0080

GEM_A_HI

0x2811 2080

GEM_B_HI

Description

The unicast hash enable and the multicast hash enable bits in the network configuration register enable the reception of hash matched frames. Hash Register Bottom 31:0.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

address

 

RW

0x0000 0000

 

gem_gximicrosemi : HASH_TOP

Address offset

0x0084

Physical address

0x2011 0084

Instance

GEM_A_LO

0x2011 2084

GEM_B_LO

0x2811 0084

GEM_A_HI

0x2811 2084

GEM_B_HI

Description

Hash Register Top 63:32

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

address

 

RW

0x0000 0000

 

gem_gximicrosemi : SPEC_ADD1_BOTTOM

Address offset

0x0088

Physical address

0x2011 0088

Instance

GEM_A_LO

0x2011 2088

GEM_B_LO

0x2811 0088

GEM_A_HI

0x2811 2088

GEM_B_HI

Description

The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

address

 

RW

0x0000 0000

 

gem_gximicrosemi : SPEC_ADD1_TOP

Address offset

0x008C

Physical address

0x2011 008C

Instance

GEM_A_LO

0x2011 208C

GEM_B_LO

0x2811 008C

GEM_A_HI

0x2811 208C

GEM_B_HI

Description

Specific Address Top

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:17

reserved_31_17

 

RO

0x0000

16

filter_type

 

RW

0

15:0

address

 

RW

0x0000

 

gem_gximicrosemi : SPEC_ADD2_BOTTOM

Address offset

0x0090

Physical address

0x2011 0090

Instance

GEM_A_LO

0x2011 2090

GEM_B_LO

0x2811 0090

GEM_A_HI

0x2811 2090

GEM_B_HI

Description

The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

address

 

RW

0x0000 0000

 

gem_gximicrosemi : SPEC_ADD2_TOP

Address offset

0x0094

Physical address

0x2011 0094

Instance

GEM_A_LO

0x2011 2094

GEM_B_LO

0x2811 0094

GEM_A_HI

0x2811 2094

GEM_B_HI

Description

Specific Address Top

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:30

reserved_31_30

 

RO

0x0

29:24

filter_byte_mask

 

RW

0x00

23:17

reserved_23_17

 

RO

0x00

16

filter_type

 

RW

0

15:0

address

 

RW

0x0000

 

gem_gximicrosemi : SPEC_ADD3_BOTTOM

Address offset

0x0098

Physical address

0x2011 0098

Instance

GEM_A_LO

0x2011 2098

GEM_B_LO

0x2811 0098

GEM_A_HI

0x2811 2098

GEM_B_HI

Description

The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

address

 

RW

0x0000 0000

 

gem_gximicrosemi : SPEC_ADD3_TOP

Address offset

0x009C

Physical address

0x2011 009C

Instance

GEM_A_LO

0x2011 209C

GEM_B_LO

0x2811 009C

GEM_A_HI

0x2811 209C

GEM_B_HI

Description

Specific Address Top

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:30

reserved_31_30

 

RO

0x0

29:24

filter_byte_mask

 

RW

0x00

23:17

reserved_23_17

 

RO

0x00

16

filter_type

 

RW

0

15:0

address

 

RW

0x0000

 

gem_gximicrosemi : SPEC_ADD4_BOTTOM

Address offset

0x00A0

Physical address

0x2011 00A0

Instance

GEM_A_LO

0x2011 20A0

GEM_B_LO

0x2811 00A0

GEM_A_HI

0x2811 20A0

GEM_B_HI

Description

The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

address

 

RW

0x0000 0000

 

gem_gximicrosemi : SPEC_ADD4_TOP

Address offset

0x00A4

Physical address

0x2011 00A4

Instance

GEM_A_LO

0x2011 20A4

GEM_B_LO

0x2811 00A4

GEM_A_HI

0x2811 20A4

GEM_B_HI

Description

Specific Address Top

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:30

reserved_31_30

 

RO

0x0

29:24

filter_byte_mask

 

RW

0x00

23:17

reserved_23_17

 

RO

0x00

16

filter_type

 

RW

0

15:0

address

 

RW

0x0000

 

gem_gximicrosemi : SPEC_TYPE1

Address offset

0x00A8

Physical address

0x2011 00A8

Instance

GEM_A_LO

0x2011 20A8

GEM_B_LO

0x2811 00A8

GEM_A_HI

0x2811 20A8

GEM_B_HI

Description

Type ID Match 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

enable_copy

 

RW

0

30:16

reserved_30_16

 

RO

0x0000

15:0

match

 

RW

0x0000

 

gem_gximicrosemi : SPEC_TYPE2

Address offset

0x00AC

Physical address

0x2011 00AC

Instance

GEM_A_LO

0x2011 20AC

GEM_B_LO

0x2811 00AC

GEM_A_HI

0x2811 20AC

GEM_B_HI

Description

Type ID Match 2

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

enable_copy

 

RW

0

30:16

reserved_30_16

 

RO

0x0000

15:0

match

 

RW

0x0000

 

gem_gximicrosemi : SPEC_TYPE3

Address offset

0x00B0

Physical address

0x2011 00B0

Instance

GEM_A_LO

0x2011 20B0

GEM_B_LO

0x2811 00B0

GEM_A_HI

0x2811 20B0

GEM_B_HI

Description

Type ID Match 3

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

enable_copy

 

RW

0

30:16

reserved_30_16

 

RO

0x0000

15:0

match

 

RW

0x0000

 

gem_gximicrosemi : SPEC_TYPE4

Address offset

0x00B4

Physical address

0x2011 00B4

Instance

GEM_A_LO

0x2011 20B4

GEM_B_LO

0x2811 00B4

GEM_A_HI

0x2811 20B4

GEM_B_HI

Description

Type ID Match 4

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

enable_copy

 

RW

0

30:16

reserved_30_16

 

RO

0x0000

15:0

match

 

RW

0x0000

 

gem_gximicrosemi : WOL_REGISTER

Address offset

0x00B8

Physical address

0x2011 00B8

Instance

GEM_A_LO

0x2011 20B8

GEM_B_LO

0x2811 00B8

GEM_A_HI

0x2811 20B8

GEM_B_HI

Description

Wake on LAN Register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:20

reserved_31_20

 

RO

0x000

19

wol_mask_3

 

RW

0

18

wol_mask_2

 

RW

0

17

wol_mask_1

 

RW

0

16

wol_mask_0

 

RW

0

15:0

addr

 

RW

0x0000

 

gem_gximicrosemi : STRETCH_RATIO

Address offset

0x00BC

Physical address

0x2011 00BC

Instance

GEM_A_LO

0x2011 20BC

GEM_B_LO

0x2811 00BC

GEM_A_HI

0x2811 20BC

GEM_B_HI

Description

IPG stretch register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

reserved_31_16

 

RO

0x0000

15:0

ipg_stretch

 

RW

0x0000

 

gem_gximicrosemi : STACKED_VLAN

Address offset

0x00C0

Physical address

0x2011 00C0

Instance

GEM_A_LO

0x2011 20C0

GEM_B_LO

0x2811 00C0

GEM_A_HI

0x2811 20C0

GEM_B_HI

Description

Stacked VLAN Register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

enable_processing

 

RW

0

30:16

reserved_30_16

 

RO

0x0000

15:0

match

 

RW

0x0000

 

gem_gximicrosemi : TX_PFC_PAUSE

Address offset

0x00C4

Physical address

0x2011 00C4

Instance

GEM_A_LO

0x2011 20C4

GEM_B_LO

0x2811 00C4

GEM_A_HI

0x2811 20C4

GEM_B_HI

Description

Transmit PFC Pause Register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

reserved_31_16

 

RO

0x0000

15:8

vector

 

RW

0x00

7:0

vector_enable

 

RW

0x00

 

gem_gximicrosemi : MASK_ADD1_BOTTOM

Address offset

0x00C8

Physical address

0x2011 00C8

Instance

GEM_A_LO

0x2011 20C8

GEM_B_LO

0x2811 00C8

GEM_A_HI

0x2811 20C8

GEM_B_HI

Description

Specific Address Mask 1 Bottom 31:0

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

address_mask

 

RW

0x0000 0000

 

gem_gximicrosemi : MASK_ADD1_TOP

Address offset

0x00CC

Physical address

0x2011 00CC

Instance

GEM_A_LO

0x2011 20CC

GEM_B_LO

0x2811 00CC

GEM_A_HI

0x2811 20CC

GEM_B_HI

Description

Specific Address Mask 1 Top 47:32

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

reserved_31_16

 

RO

0x0000

15:0

address_mask

 

RW

0x0000

 

gem_gximicrosemi : DMA_ADDR_OR_MASK

Address offset

0x00D0

Physical address

0x2011 00D0

Instance

GEM_A_LO

0x2011 20D0

GEM_B_LO

0x2811 00D0

GEM_A_HI

0x2811 20D0

GEM_B_HI

Description

Receive DMA Data Buffer Address Mask - only applies to AHB operation

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:28

mask_value

 

RW

0x0

27:4

reserved_27_4

 

RO

0x00 0000

3:0

mask_enable

 

RW

0x0

 

gem_gximicrosemi : RX_PTP_UNICAST

Address offset

0x00D4

Physical address

0x2011 00D4

Instance

GEM_A_LO

0x2011 20D4

GEM_B_LO

0x2811 00D4

GEM_A_HI

0x2811 20D4

GEM_B_HI

Description

PTP RX unicast IP destination address

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

address

 

RW

0x0000 0000

 

gem_gximicrosemi : TX_PTP_UNICAST

Address offset

0x00D8

Physical address

0x2011 00D8

Instance

GEM_A_LO

0x2011 20D8

GEM_B_LO

0x2811 00D8

GEM_A_HI

0x2811 20D8

GEM_B_HI

Description

PTP TX unicast IP destination address

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

address

 

RW

0x0000 0000

 

gem_gximicrosemi : TSU_NSEC_CMP

Address offset

0x00DC

Physical address

0x2011 00DC

Instance

GEM_A_LO

0x2011 20DC

GEM_B_LO

0x2811 00DC

GEM_A_HI

0x2811 20DC

GEM_B_HI

Description

TSU timer comparison value nanoseconds

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:22

reserved_31_22

 

RO

0x000

21:0

comparison_value

 

RW

0x00 0000

 

gem_gximicrosemi : TSU_SEC_CMP

Address offset

0x00E0

Physical address

0x2011 00E0

Instance

GEM_A_LO

0x2011 20E0

GEM_B_LO

0x2811 00E0

GEM_A_HI

0x2811 20E0

GEM_B_HI

Description

TSU timer comparison value seconds 31:0

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

comparison_value

 

RW

0x0000 0000

 

gem_gximicrosemi : TSU_MSB_SEC_CMP

Address offset

0x00E4

Physical address

0x2011 00E4

Instance

GEM_A_LO

0x2011 20E4

GEM_B_LO

0x2811 00E4

GEM_A_HI

0x2811 20E4

GEM_B_HI

Description

TSU timer comparison value seconds 47:32

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

reserved_31_16

 

RO

0x0000

15:0

comparison_value

 

RW

0x0000

 

gem_gximicrosemi : TSU_PTP_TX_MSB_SEC

Address offset

0x00E8

Physical address

0x2011 00E8

Instance

GEM_A_LO

0x2011 20E8

GEM_B_LO

0x2811 00E8

GEM_A_HI

0x2811 20E8

GEM_B_HI

Description

PTP Event Frame Transmitted Seconds Register 47:32

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:16

reserved_31_16

 

RO

0x0000

15:0

timer_seconds

 

RO

0x0000

 

gem_gximicrosemi : TSU_PTP_RX_MSB_SEC

Address offset

0x00EC

Physical address

0x2011 00EC

Instance

GEM_A_LO

0x2011 20EC

GEM_B_LO

0x2811 00EC

GEM_A_HI

0x2811 20EC

GEM_B_HI

Description

PTP Event Frame Received Seconds Register 47:32

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:16

reserved_31_16

 

RO

0x0000

15:0

timer_seconds

 

RO

0x0000

 

gem_gximicrosemi : TSU_PEER_TX_MSB_SEC

Address offset

0x00F0

Physical address

0x2011 00F0

Instance

GEM_A_LO

0x2011 20F0

GEM_B_LO

0x2811 00F0

GEM_A_HI

0x2811 20F0

GEM_B_HI

Description

PTP Peer Event Frame Transmitted Seconds Register 47:32

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:16

reserved_31_16

 

RO

0x0000

15:0

timer_seconds

 

RO

0x0000

 

gem_gximicrosemi : TSU_PEER_RX_MSB_SEC

Address offset

0x00F4

Physical address

0x2011 00F4

Instance

GEM_A_LO

0x2011 20F4

GEM_B_LO

0x2811 00F4

GEM_A_HI

0x2811 20F4

GEM_B_HI

Description

PTP Peer Event Frame Received Seconds Register 47:32

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:16

reserved_31_16

 

RO

0x0000

15:0

timer_seconds

 

RO

0x0000

 

gem_gximicrosemi : DPRAM_FILL_DBG

Address offset

0x00F8

Physical address

0x2011 00F8

Instance

GEM_A_LO

0x2011 20F8

GEM_B_LO

0x2811 00F8

GEM_A_HI

0x2811 20F8

GEM_B_HI

Description

The fill levels for the TX and RX packet buffer SRAMs can be read using this register, including the fill level for each queue in the TX direction. The fill level is reported as the number of word locations used. The number of bytes will depend on the SRAM data width.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

dma_tx_rx_fill_level

 

RO

0x0000

15:8

reserved_15_8

 

RO

0x00

7:4

dma_tx_q_fill_level_select

 

RW

0x0

3:1

reserved_3_1

 

RO

0x0

0

dma_tx_rx_fill_level_select

 

RW

0

 

gem_gximicrosemi : REVISION_REG

Address offset

0x00FC

Physical address

0x2011 00FC

Instance

GEM_A_LO

0x2011 20FC

GEM_B_LO

0x2811 00FC

GEM_A_HI

0x2811 20FC

GEM_B_HI

Description

This register indicates a Cadence module identification number and module revision. The value of this register is read only as defined by `gem_revision_reg_value

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:28

fix_number

 

RO

0x0

27:16

module_identification_number

 

RO

0x107

15:0

module_revision

 

RO

0x010C

 

gem_gximicrosemi : OCTETS_TXED_BOTTOM

Address offset

0x0100

Physical address

0x2011 0100

Instance

GEM_A_LO

0x2011 2100

GEM_B_LO

0x2811 0100

GEM_A_HI

0x2811 2100

GEM_B_HI

Description

These registers reset to zero on a read and stick at all ones when they count to their maximum value. They should be read frequently enough to prevent loss of data. In order to reduce overall design area, the statistics registers may be optionally removed in the configuration file if they are deemed unnecessary for a particular design. The receive statistics registers are only incremented when the receive enable bit is set in the network control register. The statistics registers optionally have a snapshot capability which, when exercised, will simultaneously store and clear the current values of all the statistics registers into a snapshot register set in order to allow a consistent set of statistics to be read by the processor. The snapshot is controlled using bit 13 of the network control register. The read snapshot control indicated by bit 14 of the network control register determines whether the processor reads the snapshot registers (logic 1) or the incrementing registers (logic 0). The default GEM configuration does not support the snapshot capability. See Parameterization section under Implementation Application Notes for an explanation of how to enable this function. All the statistics registers are read only. For test purposes they may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes. Once a statistics register has been read, it is automatically cleared. When reading the octets transmitted and octets received registers, bits 31:0 should be read prior to bits 47:32 to ensure reliable operation. The statistics register block contains the following registers. Octets Transmitted [31:0]

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

count

 

RO
RtoClr

0x0000 0000

 

gem_gximicrosemi : OCTETS_TXED_TOP

Address offset

0x0104

Physical address

0x2011 0104

Instance

GEM_A_LO

0x2011 2104

GEM_B_LO

0x2811 0104

GEM_A_HI

0x2811 2104

GEM_B_HI

Description

Octets Transmitted 47:32

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:16

reserved_31_16

 

RO

0x0000

15:0

count

 

RO
RtoClr

0x0000

 

gem_gximicrosemi : FRAMES_TXED_OK

Address offset

0x0108

Physical address

0x2011 0108

Instance

GEM_A_LO

0x2011 2108

GEM_B_LO

0x2811 0108

GEM_A_HI

0x2811 2108

GEM_B_HI

Description

Frames Transmitted

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

count

 

RO
RtoClr

0x0000 0000

 

gem_gximicrosemi : BROADCAST_TXED

Address offset

0x010C

Physical address

0x2011 010C

Instance

GEM_A_LO

0x2011 210C

GEM_B_LO

0x2811 010C

GEM_A_HI

0x2811 210C

GEM_B_HI

Description

Broadcast Frames Transmitted

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

count

 

RO
RtoClr

0x0000 0000

 

gem_gximicrosemi : MULTICAST_TXED

Address offset

0x0110

Physical address

0x2011 0110

Instance

GEM_A_LO

0x2011 2110

GEM_B_LO

0x2811 0110

GEM_A_HI

0x2811 2110

GEM_B_HI

Description

Multicast Frames Transmitted

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

count

 

RO
RtoClr

0x0000 0000

 

gem_gximicrosemi : PAUSE_FRAMES_TXED

Address offset

0x0114

Physical address

0x2011 0114

Instance

GEM_A_LO

0x2011 2114

GEM_B_LO

0x2811 0114

GEM_A_HI

0x2811 2114

GEM_B_HI

Description

Pause Frames Transmitted

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:16

reserved_31_16

 

RO

0x0000

15:0

count

 

RO
RtoClr

0x0000

 

gem_gximicrosemi : FRAMES_TXED_64

Address offset

0x0118

Physical address

0x2011 0118

Instance

GEM_A_LO

0x2011 2118

GEM_B_LO

0x2811 0118

GEM_A_HI

0x2811 2118

GEM_B_HI

Description

64 Byte Frames Transmitted

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

count

 

RO
RtoClr

0x0000 0000

 

gem_gximicrosemi : FRAMES_TXED_65

Address offset

0x011C

Physical address

0x2011 011C

Instance

GEM_A_LO

0x2011 211C

GEM_B_LO

0x2811 011C

GEM_A_HI

0x2811 211C

GEM_B_HI

Description

65 to 127 Byte Frames Transmitted

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

count

 

RO
RtoClr

0x0000 0000

 

gem_gximicrosemi : FRAMES_TXED_128

Address offset

0x0120

Physical address

0x2011 0120

Instance

GEM_A_LO

0x2011 2120

GEM_B_LO

0x2811 0120

GEM_A_HI

0x2811 2120

GEM_B_HI

Description

128 to 255 Byte Frames Transmitted

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

count

 

RO
RtoClr

0x0000 0000

 

gem_gximicrosemi : FRAMES_TXED_256

Address offset

0x0124

Physical address

0x2011 0124

Instance

GEM_A_LO

0x2011 2124

GEM_B_LO

0x2811 0124

GEM_A_HI

0x2811 2124

GEM_B_HI

Description

256 to 511 Byte Frames Transmitted

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

count

 

RO
RtoClr

0x0000 0000

 

gem_gximicrosemi : FRAMES_TXED_512

Address offset

0x0128

Physical address

0x2011 0128

Instance

GEM_A_LO

0x2011 2128

GEM_B_LO

0x2811 0128

GEM_A_HI

0x2811 2128

GEM_B_HI

Description

512 to 1023 Byte Frames Transmitted

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

count

 

RO
RtoClr

0x0000 0000

 

gem_gximicrosemi : FRAMES_TXED_1024

Address offset

0x012C

Physical address

0x2011 012C

Instance

GEM_A_LO

0x2011 212C

GEM_B_LO

0x2811 012C

GEM_A_HI

0x2811 212C

GEM_B_HI

Description

1024 to 1518 Byte Frames Transmitted

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

count

 

RO
RtoClr

0x0000 0000

 

gem_gximicrosemi : FRAMES_TXED_1519

Address offset

0x0130

Physical address

0x2011 0130

Instance

GEM_A_LO

0x2011 2130

GEM_B_LO

0x2811 0130

GEM_A_HI

0x2811 2130

GEM_B_HI

Description

Greater Than 1518 Byte Frames Transmitted

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

count

 

RO
RtoClr

0x0000 0000

 

gem_gximicrosemi : TX_UNDERRUNS

Address offset

0x0134

Physical address

0x2011 0134

Instance

GEM_A_LO

0x2011 2134

GEM_B_LO

0x2811 0134

GEM_A_HI

0x2811 2134

GEM_B_HI

Description

Transmit Under Runs

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:10

reserved_31_10

 

RO

0x00 0000

9:0

count

 

RO
RtoClr

0x000

 

gem_gximicrosemi : SINGLE_COLLISIONS

Address offset

0x0138

Physical address

0x2011 0138

Instance

GEM_A_LO

0x2011 2138

GEM_B_LO

0x2811 0138

GEM_A_HI

0x2811 2138

GEM_B_HI

Description

Single Collision Frames

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:18

reserved_31_18

 

RO

0x0000

17:0

count

 

RO
RtoClr

0x0 0000

 

gem_gximicrosemi : MULTIPLE_COLLISIONS

Address offset

0x013C

Physical address

0x2011 013C

Instance

GEM_A_LO

0x2011 213C

GEM_B_LO

0x2811 013C

GEM_A_HI

0x2811 213C

GEM_B_HI

Description

Multiple Collision Frames

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:18

reserved_31_18

 

RO

0x0000

17:0

count

 

RO
RtoClr

0x0 0000

 

gem_gximicrosemi : EXCESSIVE_COLLISIONS

Address offset

0x0140

Physical address

0x2011 0140

Instance

GEM_A_LO

0x2011 2140

GEM_B_LO

0x2811 0140

GEM_A_HI

0x2811 2140

GEM_B_HI

Description

Excessive Collisions

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:10

reserved_31_10

 

RO

0x00 0000

9:0

count

 

RO
RtoClr

0x000

 

gem_gximicrosemi : LATE_COLLISIONS

Address offset

0x0144

Physical address

0x2011 0144

Instance

GEM_A_LO

0x2011 2144

GEM_B_LO

0x2811 0144

GEM_A_HI

0x2811 2144

GEM_B_HI

Description

Late Collisions

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:10

reserved_31_10

 

RO

0x00 0000

9:0

count

 

RO
RtoClr

0x000

 

gem_gximicrosemi : DEFERRED_FRAMES

Address offset

0x0148

Physical address

0x2011 0148

Instance

GEM_A_LO

0x2011 2148

GEM_B_LO

0x2811 0148

GEM_A_HI

0x2811 2148

GEM_B_HI

Description

Deferred Transmission Frames

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:18

reserved_31_18

 

RO

0x0000

17:0

count

 

RO
RtoClr

0x0 0000

 

gem_gximicrosemi : CRS_ERRORS

Address offset

0x014C

Physical address

0x2011 014C

Instance

GEM_A_LO

0x2011 214C

GEM_B_LO

0x2811 014C

GEM_A_HI

0x2811 214C

GEM_B_HI

Description

Carrier Sense Errors

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:10

reserved_31_10

 

RO

0x00 0000

9:0

count

 

RO
RtoClr

0x000

 

gem_gximicrosemi : OCTETS_RXED_BOTTOM

Address offset

0x0150

Physical address

0x2011 0150

Instance

GEM_A_LO

0x2011 2150

GEM_B_LO

0x2811 0150

GEM_A_HI

0x2811 2150

GEM_B_HI

Description

Octets Received 31:0

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

count

 

RO
RtoClr

0x0000 0000

 

gem_gximicrosemi : OCTETS_RXED_TOP

Address offset

0x0154

Physical address

0x2011 0154

Instance

GEM_A_LO

0x2011 2154

GEM_B_LO

0x2811 0154

GEM_A_HI

0x2811 2154

GEM_B_HI

Description

Octets Received 47:32

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:16

reserved_31_16

 

RO

0x0000

15:0

count

 

RO
RtoClr

0x0000

 

gem_gximicrosemi : FRAMES_RXED_OK

Address offset

0x0158

Physical address

0x2011 0158

Instance

GEM_A_LO

0x2011 2158

GEM_B_LO

0x2811 0158

GEM_A_HI

0x2811 2158

GEM_B_HI

Description

Frames Received

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

count

 

RO
RtoClr

0x0000 0000

 

gem_gximicrosemi : BROADCAST_RXED

Address offset

0x015C

Physical address

0x2011 015C

Instance

GEM_A_LO

0x2011 215C

GEM_B_LO

0x2811 015C

GEM_A_HI

0x2811 215C

GEM_B_HI

Description

Broadcast Frames Received

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

count

 

RO
RtoClr

0x0000 0000

 

gem_gximicrosemi : MULTICAST_RXED

Address offset

0x0160

Physical address

0x2011 0160

Instance

GEM_A_LO

0x2011 2160

GEM_B_LO

0x2811 0160

GEM_A_HI

0x2811 2160

GEM_B_HI

Description

Multicast Frames Received

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

count

 

RO
RtoClr

0x0000 0000

 

gem_gximicrosemi : PAUSE_FRAMES_RXED

Address offset

0x0164

Physical address

0x2011 0164

Instance

GEM_A_LO

0x2011 2164

GEM_B_LO

0x2811 0164

GEM_A_HI

0x2811 2164

GEM_B_HI

Description

Pause Frames Received

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:16

reserved_31_16

 

RO

0x0000

15:0

count

 

RO
RtoClr

0x0000

 

gem_gximicrosemi : FRAMES_RXED_64

Address offset

0x0168

Physical address

0x2011 0168

Instance

GEM_A_LO

0x2011 2168

GEM_B_LO

0x2811 0168

GEM_A_HI

0x2811 2168

GEM_B_HI

Description

64 Byte Frames Received

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

count

 

RO
RtoClr

0x0000 0000

 

gem_gximicrosemi : FRAMES_RXED_65

Address offset

0x016C

Physical address

0x2011 016C

Instance

GEM_A_LO

0x2011 216C

GEM_B_LO

0x2811 016C

GEM_A_HI

0x2811 216C

GEM_B_HI

Description

65 to 127 Byte Frames Received

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

count

 

RO
RtoClr

0x0000 0000

 

gem_gximicrosemi : FRAMES_RXED_128

Address offset

0x0170

Physical address

0x2011 0170

Instance

GEM_A_LO

0x2011 2170

GEM_B_LO

0x2811 0170

GEM_A_HI

0x2811 2170

GEM_B_HI

Description

128 to 255 Byte Frames Received

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

count

 

RO
RtoClr

0x0000 0000

 

gem_gximicrosemi : FRAMES_RXED_256

Address offset

0x0174

Physical address

0x2011 0174

Instance

GEM_A_LO

0x2011 2174

GEM_B_LO

0x2811 0174

GEM_A_HI

0x2811 2174

GEM_B_HI

Description

256 to 511 Byte Frames Received

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

count

 

RO
RtoClr

0x0000 0000

 

gem_gximicrosemi : FRAMES_RXED_512

Address offset

0x0178

Physical address

0x2011 0178

Instance

GEM_A_LO

0x2011 2178

GEM_B_LO

0x2811 0178

GEM_A_HI

0x2811 2178

GEM_B_HI

Description

512 to 1023 Byte Frames Received

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

count

 

RO
RtoClr

0x0000 0000

 

gem_gximicrosemi : FRAMES_RXED_1024

Address offset

0x017C

Physical address

0x2011 017C

Instance

GEM_A_LO

0x2011 217C

GEM_B_LO

0x2811 017C

GEM_A_HI

0x2811 217C

GEM_B_HI

Description

1024 to 1518 Byte Frames Received

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

count

 

RO
RtoClr

0x0000 0000

 

gem_gximicrosemi : FRAMES_RXED_1519

Address offset

0x0180

Physical address

0x2011 0180

Instance

GEM_A_LO

0x2011 2180

GEM_B_LO

0x2811 0180

GEM_A_HI

0x2811 2180

GEM_B_HI

Description

1519 to maximum Byte Frames Received

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

count

 

RO
RtoClr

0x0000 0000

 

gem_gximicrosemi : UNDERSIZE_FRAMES

Address offset

0x0184

Physical address

0x2011 0184

Instance

GEM_A_LO

0x2011 2184

GEM_B_LO

0x2811 0184

GEM_A_HI

0x2811 2184

GEM_B_HI

Description

Undersized Frames Received

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:10

reserved_31_10

 

RO

0x00 0000

9:0

count

 

RO
RtoClr

0x000

 

gem_gximicrosemi : EXCESSIVE_RX_LENGTH

Address offset

0x0188

Physical address

0x2011 0188

Instance

GEM_A_LO

0x2011 2188

GEM_B_LO

0x2811 0188

GEM_A_HI

0x2811 2188

GEM_B_HI

Description

Oversize Frames Received

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:10

reserved_31_10

 

RO

0x00 0000

9:0

count

 

RO
RtoClr

0x000

 

gem_gximicrosemi : RX_JABBERS

Address offset

0x018C

Physical address

0x2011 018C

Instance

GEM_A_LO

0x2011 218C

GEM_B_LO

0x2811 018C

GEM_A_HI

0x2811 218C

GEM_B_HI

Description

Jabbers Received

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:10

reserved_31_10

 

RO

0x00 0000

9:0

count

 

RO
RtoClr

0x000

 

gem_gximicrosemi : FCS_ERRORS

Address offset

0x0190

Physical address

0x2011 0190

Instance

GEM_A_LO

0x2011 2190

GEM_B_LO

0x2811 0190

GEM_A_HI

0x2811 2190

GEM_B_HI

Description

Frame Check Sequence Errors

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:10

reserved_31_10

 

RO

0x00 0000

9:0

count

 

RO
RtoClr

0x000

 

gem_gximicrosemi : RX_LENGTH_ERRORS

Address offset

0x0194

Physical address

0x2011 0194

Instance

GEM_A_LO

0x2011 2194

GEM_B_LO

0x2811 0194

GEM_A_HI

0x2811 2194

GEM_B_HI

Description

Length Field Frame Errors

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:10

reserved_31_10

 

RO

0x00 0000

9:0

count

 

RO
RtoClr

0x000

 

gem_gximicrosemi : RX_SYMBOL_ERRORS

Address offset

0x0198

Physical address

0x2011 0198

Instance

GEM_A_LO

0x2011 2198

GEM_B_LO

0x2811 0198

GEM_A_HI

0x2811 2198

GEM_B_HI

Description

Receive Symbol Errors

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:10

reserved_31_10

 

RO

0x00 0000

9:0

count

 

RO
RtoClr

0x000

 

gem_gximicrosemi : ALIGNMENT_ERRORS

Address offset

0x019C

Physical address

0x2011 019C

Instance

GEM_A_LO

0x2011 219C

GEM_B_LO

0x2811 019C

GEM_A_HI

0x2811 219C

GEM_B_HI

Description

Alignment Errors

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:10

reserved_31_10

 

RO

0x00 0000

9:0

count

 

RO
RtoClr

0x000

 

gem_gximicrosemi : RX_RESOURCE_ERRORS

Address offset

0x01A0

Physical address

0x2011 01A0

Instance

GEM_A_LO

0x2011 21A0

GEM_B_LO

0x2811 01A0

GEM_A_HI

0x2811 21A0

GEM_B_HI

Description

Receive Resource Errors

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:18

reserved_31_18

 

RO

0x0000

17:0

count

 

RO
RtoClr

0x0 0000

 

gem_gximicrosemi : RX_OVERRUNS

Address offset

0x01A4

Physical address

0x2011 01A4

Instance

GEM_A_LO

0x2011 21A4

GEM_B_LO

0x2811 01A4

GEM_A_HI

0x2811 21A4

GEM_B_HI

Description

Receive Overruns

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:10

reserved_31_10

 

RO

0x00 0000

9:0

count

 

RO
RtoClr

0x000

 

gem_gximicrosemi : RX_IP_CK_ERRORS

Address offset

0x01A8

Physical address

0x2011 01A8

Instance

GEM_A_LO

0x2011 21A8

GEM_B_LO

0x2811 01A8

GEM_A_HI

0x2811 21A8

GEM_B_HI

Description

IP Header Checksum Errors

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:8

reserved_31_8

 

RO

0x00 0000

7:0

count

 

RO
RtoClr

0x00

 

gem_gximicrosemi : RX_TCP_CK_ERRORS

Address offset

0x01AC

Physical address

0x2011 01AC

Instance

GEM_A_LO

0x2011 21AC

GEM_B_LO

0x2811 01AC

GEM_A_HI

0x2811 21AC

GEM_B_HI

Description

TCP Checksum Errors

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:8

reserved_31_8

 

RO

0x00 0000

7:0

count

 

RO
RtoClr

0x00

 

gem_gximicrosemi : RX_UDP_CK_ERRORS

Address offset

0x01B0

Physical address

0x2011 01B0

Instance

GEM_A_LO

0x2011 21B0

GEM_B_LO

0x2811 01B0

GEM_A_HI

0x2811 21B0

GEM_B_HI

Description

UDP Checksum Errors

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:8

reserved_31_8

 

RO

0x00 0000

7:0

count

 

RO
RtoClr

0x00

 

gem_gximicrosemi : AUTO_FLUSHED_PKTS

Address offset

0x01B4

Physical address

0x2011 01B4

Instance

GEM_A_LO

0x2011 21B4

GEM_B_LO

0x2811 01B4

GEM_A_HI

0x2811 21B4

GEM_B_HI

Description

Receive DMA Flushed Packets

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:16

reserved_31_16

 

RO

0x0000

15:0

count

 

RO
RtoClr

0x0000

 

gem_gximicrosemi : TSU_TIMER_INCR_SUB_NSEC

Address offset

0x01BC

Physical address

0x2011 01BC

Instance

GEM_A_LO

0x2011 21BC

GEM_B_LO

0x2811 01BC

GEM_A_HI

0x2811 21BC

GEM_B_HI

Description

1588 Timer Increment Register sub nsec. From release 1p08f1 onwards this register must be written before the tsu_timer_incr register and the value written will not take effect until the tsu_timer_incr register is written to.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:24

sub_ns_incr_lsb

 

RW

0x00

23:16

reserved_23_16

 

RO

0x00

15:0

sub_ns_incr

 

RW

0x0000

 

gem_gximicrosemi : TSU_TIMER_MSB_SEC

Address offset

0x01C0

Physical address

0x2011 01C0

Instance

GEM_A_LO

0x2011 21C0

GEM_B_LO

0x2811 01C0

GEM_A_HI

0x2811 21C0

GEM_B_HI

Description

1588 Timer Seconds Register 47:32

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

reserved_31_16

 

RO

0x0000

15:0

timer

 

RW

0x0000

 

gem_gximicrosemi : TSU_STROBE_MSB_SEC

Address offset

0x01C4

Physical address

0x2011 01C4

Instance

GEM_A_LO

0x2011 21C4

GEM_B_LO

0x2811 01C4

GEM_A_HI

0x2811 21C4

GEM_B_HI

Description

1588 Timer Sync Strobe Seconds Register 47:32

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:16

reserved_31_16

 

RO

0x0000

15:0

strobe

 

RO

0x0000

 

gem_gximicrosemi : TSU_STROBE_SEC

Address offset

0x01C8

Physical address

0x2011 01C8

Instance

GEM_A_LO

0x2011 21C8

GEM_B_LO

0x2811 01C8

GEM_A_HI

0x2811 21C8

GEM_B_HI

Description

1588 Timer Sync Strobe Seconds Register 31:0

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

strobe

 

RO

0x0000 0000

 

gem_gximicrosemi : TSU_STROBE_NSEC

Address offset

0x01CC

Physical address

0x2011 01CC

Instance

GEM_A_LO

0x2011 21CC

GEM_B_LO

0x2811 01CC

GEM_A_HI

0x2811 21CC

GEM_B_HI

Description

1588 Timer Sync Strobe Nanoseconds Register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:30

reserved_31_30

 

RO

0x0

29:0

strobe

 

RO

0x0000 0000

 

gem_gximicrosemi : TSU_TIMER_SEC

Address offset

0x01D0

Physical address

0x2011 01D0

Instance

GEM_A_LO

0x2011 21D0

GEM_B_LO

0x2811 01D0

GEM_A_HI

0x2811 21D0

GEM_B_HI

Description

1588 Timer Seconds Register 31:0

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

timer

 

RW

0x0000 0000

 

gem_gximicrosemi : TSU_TIMER_NSEC

Address offset

0x01D4

Physical address

0x2011 01D4

Instance

GEM_A_LO

0x2011 21D4

GEM_B_LO

0x2811 01D4

GEM_A_HI

0x2811 21D4

GEM_B_HI

Description

1588 Timer Nanoseconds Register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:30

reserved_31_30

 

RO

0x0

29:0

timer

 

RW

0x0000 0000

 

gem_gximicrosemi : TSU_TIMER_ADJUST

Address offset

0x01D8

Physical address

0x2011 01D8

Instance

GEM_A_LO

0x2011 21D8

GEM_B_LO

0x2811 01D8

GEM_A_HI

0x2811 21D8

GEM_B_HI

Description

This register is used to adjust the value of the timer in the TSU. It allows an integral number of nanoseconds to be added or subtracted from the timer in a one-off operation. This register returns all zeroes when read.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

add_subtract

 

WO

0

30

reserved_30

 

RO

0

29:0

increment_value

 

WO

0x0000 0000

 

gem_gximicrosemi : TSU_TIMER_INCR

Address offset

0x01DC

Physical address

0x2011 01DC

Instance

GEM_A_LO

0x2011 21DC

GEM_B_LO

0x2811 01DC

GEM_A_HI

0x2811 21DC

GEM_B_HI

Description

1588 Timer Increment Register. From release 1p08f1 onwards this register must be written after the tsu_timer_incr_sub_ns register and the write operation will cause the value written to the tsu_timer_incr_sub_ns register to take effect.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:24

reserved_31_24

 

RO

0x00

23:16

num_incs

 

RW

0x00

15:8

alt_ns_incr

 

RW

0x00

7:0

ns_increment

 

RW

0x00

 

gem_gximicrosemi : TSU_PTP_TX_SEC

Address offset

0x01E0

Physical address

0x2011 01E0

Instance

GEM_A_LO

0x2011 21E0

GEM_B_LO

0x2811 01E0

GEM_A_HI

0x2811 21E0

GEM_B_HI

Description

PTP Event Frame Transmitted Seconds Register 31:0

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

timer

 

RO

0x0000 0000

 

gem_gximicrosemi : TSU_PTP_TX_NSEC

Address offset

0x01E4

Physical address

0x2011 01E4

Instance

GEM_A_LO

0x2011 21E4

GEM_B_LO

0x2811 01E4

GEM_A_HI

0x2811 21E4

GEM_B_HI

Description

PTP Event Frame Transmitted Nanoseconds Register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:30

reserved_31_30

 

RO

0x0

29:0

timer

 

RO

0x0000 0000

 

gem_gximicrosemi : TSU_PTP_RX_SEC

Address offset

0x01E8

Physical address

0x2011 01E8

Instance

GEM_A_LO

0x2011 21E8

GEM_B_LO

0x2811 01E8

GEM_A_HI

0x2811 21E8

GEM_B_HI

Description

PTP Event Frame Received Seconds Register 31:0

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

timer

 

RO

0x0000 0000

 

gem_gximicrosemi : TSU_PTP_RX_NSEC

Address offset

0x01EC

Physical address

0x2011 01EC

Instance

GEM_A_LO

0x2011 21EC

GEM_B_LO

0x2811 01EC

GEM_A_HI

0x2811 21EC

GEM_B_HI

Description

PTP Event Frame Received Nanoseconds Register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:30

reserved_31_30

 

RO

0x0

29:0

timer

 

RO

0x0000 0000

 

gem_gximicrosemi : TSU_PEER_TX_SEC

Address offset

0x01F0

Physical address

0x2011 01F0

Instance

GEM_A_LO

0x2011 21F0

GEM_B_LO

0x2811 01F0

GEM_A_HI

0x2811 21F0

GEM_B_HI

Description

PTP Peer Event Frame Transmitted Seconds Register 31:0

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

timer

 

RO

0x0000 0000

 

gem_gximicrosemi : TSU_PEER_TX_NSEC

Address offset

0x01F4

Physical address

0x2011 01F4

Instance

GEM_A_LO

0x2011 21F4

GEM_B_LO

0x2811 01F4

GEM_A_HI

0x2811 21F4

GEM_B_HI

Description

PTP Peer Event Frame Transmitted Nanoseconds Register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:30

reserved_31_30

 

RO

0x0

29:0

timer

 

RO

0x0000 0000

 

gem_gximicrosemi : TSU_PEER_RX_SEC

Address offset

0x01F8

Physical address

0x2011 01F8

Instance

GEM_A_LO

0x2011 21F8

GEM_B_LO

0x2811 01F8

GEM_A_HI

0x2811 21F8

GEM_B_HI

Description

PTP Peer Event Frame Received Seconds Register 31:0

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

timer

 

RO

0x0000 0000

 

gem_gximicrosemi : TSU_PEER_RX_NSEC

Address offset

0x01FC

Physical address

0x2011 01FC

Instance

GEM_A_LO

0x2011 21FC

GEM_B_LO

0x2811 01FC

GEM_A_HI

0x2811 21FC

GEM_B_HI

Description

PTP Peer Event Frame Received Nanoseconds Register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:30

reserved_31_30

 

RO

0x0

29:0

timer

 

RO

0x0000 0000

 

gem_gximicrosemi : PFC_STATUS

Address offset

0x026C

Physical address

0x2011 026C

Instance

GEM_A_LO

0x2011 226C

GEM_B_LO

0x2811 026C

GEM_A_HI

0x2811 226C

GEM_B_HI

Description

Priority Flow Control status register - indicates whether PFC has been negotiated and the current state of the PFC counters for each priority.

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:9

reserved_31_9

 

RO

0x00 0000

8

pfc_negotiate_pclk

 

RO

0

7:0

rx_pfc_paused

 

RO

0x00

 

gem_gximicrosemi : RX_LPI

Address offset

0x0270

Physical address

0x2011 0270

Instance

GEM_A_LO

0x2011 2270

GEM_B_LO

0x2811 0270

GEM_A_HI

0x2811 2270

GEM_B_HI

Description

Received LPI transitions

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:16

reserved_31_16

 

RO

0x0000

15:0

count

 

RO
RtoClr

0x0000

 

gem_gximicrosemi : RX_LPI_TIME

Address offset

0x0274

Physical address

0x2011 0274

Instance

GEM_A_LO

0x2011 2274

GEM_B_LO

0x2811 0274

GEM_A_HI

0x2811 2274

GEM_B_HI

Description

Received LPI time

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:24

reserved_31_24

 

RO

0x00

23:0

lpi_time

 

RO
RtoClr

0x00 0000

 

gem_gximicrosemi : TX_LPI

Address offset

0x0278

Physical address

0x2011 0278

Instance

GEM_A_LO

0x2011 2278

GEM_B_LO

0x2811 0278

GEM_A_HI

0x2811 2278

GEM_B_HI

Description

Transmit LPI transitions

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:16

reserved_31_16

 

RO

0x0000

15:0

count

 

RO
RtoClr

0x0000

 

gem_gximicrosemi : TX_LPI_TIME

Address offset

0x027C

Physical address

0x2011 027C

Instance

GEM_A_LO

0x2011 227C

GEM_B_LO

0x2811 027C

GEM_A_HI

0x2811 227C

GEM_B_HI

Description

Transmit LPI time

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:24

reserved_31_24

 

RO

0x00

23:0

lpi_time

 

RO
RtoClr

0x00 0000

 

gem_gximicrosemi : DESIGNCFG_DEBUG1

Address offset

0x0280

Physical address

0x2011 0280

Instance

GEM_A_LO

0x2011 2280

GEM_B_LO

0x2811 0280

GEM_A_HI

0x2811 2280

GEM_B_HI

Description

Design Configuration Register 1 - The GEM has many parameterisation options to configure the IP during compilation stage. This is achieved using Verilog define compiler directives in an include file called gem_defs.v. This configuration is readable through APB addressable designcfg_debug registers.

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:28

axi_cache_value

 

RO

0x0

27:25

dma_bus_width

 

RO

0x4

24

exclude_cbs

 

RO

0

23

irq_read_clear

 

RO

0

22

no_snapshot

 

RO

1

21

no_stats

 

RO

0

20

reserved_20

 

RO

1

19:15

user_in_width

 

RO

0x01

14:10

user_out_width

 

RO

0x01

9

user_io

 

RO

0

8

reserved_8

 

RO

1

7

reserved_7

 

RO

0

6

ext_fifo_interface

 

RO

0

5

reserved_5

 

RO

0

4

int_loopback

 

RO

1

3:2

reserved_3_2

 

RO

0x0

1

exclude_qbv

 

RO

0

0

no_pcs

 

RO

1

 

gem_gximicrosemi : DESIGNCFG_DEBUG2

Address offset

0x0284

Physical address

0x2011 0284

Instance

GEM_A_LO

0x2011 2284

GEM_B_LO

0x2811 0284

GEM_A_HI

0x2811 2284

GEM_B_HI

Description

Design Configuration Register 2

Type

RO

 

Bits

Field Name

Description

Type

Reset

31

spram

 

RO

0

30

axi

 

RO

1

29:26

tx_pbuf_addr

 

RO

0xD

25:22

rx_pbuf_addr

 

RO

0xB

21

tx_pkt_buffer

 

RO

1

20

rx_pkt_buffer

 

RO

1

19:16

hprot_value

 

RO

0x1

15:14

reserved_15_14

 

RO

0x0

13:0

jumbo_max_length

 

RO

0x3FFF

 

gem_gximicrosemi : DESIGNCFG_DEBUG3

Address offset

0x0288

Physical address

0x2011 0288

Instance

GEM_A_LO

0x2011 2288

GEM_B_LO

0x2811 0288

GEM_A_HI

0x2811 2288

GEM_B_HI

Description

Design Configuration Register 3

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:30

reserved_31_30

 

RO

0x0

29:24

num_spec_add_filters

 

RO

0x04

23:21

reserved_23_21

 

RO

0x0

20:0

reserved_20_0

 

RO

0x00 0000

 

gem_gximicrosemi : DESIGNCFG_DEBUG4

Address offset

0x028C

Physical address

0x2011 028C

Instance

GEM_A_LO

0x2011 228C

GEM_B_LO

0x2811 028C

GEM_A_HI

0x2811 228C

GEM_B_HI

Description

Design Configuration Register 4

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:20

reserved_31_20

 

RO

0x000

19:0

reserved_19_0

 

RO

0x0 0000

 

gem_gximicrosemi : DESIGNCFG_DEBUG5

Address offset

0x0290

Physical address

0x2011 0290

Instance

GEM_A_LO

0x2011 2290

GEM_B_LO

0x2811 0290

GEM_A_HI

0x2811 2290

GEM_B_HI

Description

Design Configuration Register 5

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:29

axi_prot_value

 

RO

0x2

28

tsu_clk

 

RO

0

27:20

rx_buffer_length_def

 

RO

0x02

19

tx_pbuf_size_def

 

RO

1

18:17

rx_pbuf_size_def

 

RO

0x3

16:15

endian_swap_def

 

RO

0x3

14:12

mdc_clock_div

 

RO

0x2

11:10

dma_bus_width_def

 

RO

0x0

9

phy_ident

 

RO

1

8

tsu

 

RO

1

7:4

tx_fifo_cnt_width

 

RO

0x4

3:0

rx_fifo_cnt_width

 

RO

0x5

 

gem_gximicrosemi : DESIGNCFG_DEBUG6

Address offset

0x0294

Physical address

0x2011 0294

Instance

GEM_A_LO

0x2011 2294

GEM_B_LO

0x2811 0294

GEM_A_HI

0x2811 2294

GEM_B_HI

Description

Design Configuration Register 6

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:28

reserved_31_28

 

RO

0x0

27

pbuf_lso

 

RO

1

26

pbuf_rsc

 

RO

1

25

pbuf_cutthru

 

RO

0

24

pfc_multi_quantum

 

RO

0

23

dma_addr_width_is_64b

 

RO

1

22

host_if_soft_select

 

RO

0

21

tx_add_fifo_if

 

RO

0

20

ext_tsu_timer

 

RO

0

19:16

tx_pbuf_queue_segment_size

 

RO

0x4

15

dma_priority_queue15

 

RO

1

14

dma_priority_queue14

 

RO

1

13

dma_priority_queue13

 

RO

1

12

dma_priority_queue12

 

RO

1

11

dma_priority_queue11

 

RO

1

10

dma_priority_queue10

 

RO

1

9

dma_priority_queue9

 

RO

1

8

dma_priority_queue8

 

RO

1

7

dma_priority_queue7

 

RO

1

6

dma_priority_queue6

 

RO

1

5

dma_priority_queue5

 

RO

1

4

dma_priority_queue4

 

RO

1

3

dma_priority_queue3

 

RO

1

2

dma_priority_queue2

 

RO

1

1

dma_priority_queue1

 

RO

1

0

reserved_0

 

RO

0

 

gem_gximicrosemi : DESIGNCFG_DEBUG7

Address offset

0x0298

Physical address

0x2011 0298

Instance

GEM_A_LO

0x2011 2298

GEM_B_LO

0x2811 0298

GEM_A_HI

0x2811 2298

GEM_B_HI

Description

Design Configuration Register 7

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:28

tx_pbuf_num_segments_q7

 

RO

0x0

27:24

tx_pbuf_num_segments_q6

 

RO

0x0

23:20

tx_pbuf_num_segments_q5

 

RO

0x0

19:16

tx_pbuf_num_segments_q4

 

RO

0x0

15:12

tx_pbuf_num_segments_q3

 

RO

0x0

11:8

tx_pbuf_num_segments_q2

 

RO

0x0

7:4

tx_pbuf_num_segments_q1

 

RO

0x0

3:0

tx_pbuf_num_segments_q0

 

RO

0x0

 

gem_gximicrosemi : DESIGNCFG_DEBUG8

Address offset

0x029C

Physical address

0x2011 029C

Instance

GEM_A_LO

0x2011 229C

GEM_B_LO

0x2811 029C

GEM_A_HI

0x2811 229C

GEM_B_HI

Description

Design Configuration Register 8

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:24

num_type1_screeners

 

RO

0x10

23:16

num_type2_screeners

 

RO

0x10

15:8

num_scr2_ethtype_regs

 

RO

0x08

7:0

num_scr2_compare_regs

 

RO

0x20

 

gem_gximicrosemi : DESIGNCFG_DEBUG9

Address offset

0x02A0

Physical address

0x2011 02A0

Instance

GEM_A_LO

0x2011 22A0

GEM_B_LO

0x2811 02A0

GEM_A_HI

0x2811 22A0

GEM_B_HI

Description

Design Configuration Register 9

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:28

tx_pbuf_num_segments_q15

 

RO

0x0

27:24

tx_pbuf_num_segments_q14

 

RO

0x0

23:20

tx_pbuf_num_segments_q13

 

RO

0x0

19:16

tx_pbuf_num_segments_q12

 

RO

0x0

15:12

tx_pbuf_num_segments_q11

 

RO

0x0

11:8

tx_pbuf_num_segments_q10

 

RO

0x0

7:4

tx_pbuf_num_segments_q9

 

RO

0x0

3:0

tx_pbuf_num_segments_q8

 

RO

0x0

 

gem_gximicrosemi : DESIGNCFG_DEBUG10

Address offset

0x02A4

Physical address

0x2011 02A4

Instance

GEM_A_LO

0x2011 22A4

GEM_B_LO

0x2811 02A4

GEM_A_HI

0x2811 22A4

GEM_B_HI

Description

Design Configuration Register 10

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:28

emac_bus_width

 

RO

0x2

27:24

tx_pbuf_data

 

RO

0x4

23:20

rx_pbuf_data

 

RO

0x4

19:16

axi_access_pipeline_bits

 

RO

0x4

15:12

axi_tx_descr_rd_buff_bits

 

RO

0x4

11:8

axi_rx_descr_rd_buff_bits

 

RO

0x4

7:4

axi_tx_descr_wr_buff_bits

 

RO

0x4

3:0

axi_rx_descr_wr_buff_bits

 

RO

0x2

 

gem_gximicrosemi : DESIGNCFG_DEBUG11

Address offset

0x02A8

Physical address

0x2011 02A8

Instance

GEM_A_LO

0x2011 22A8

GEM_B_LO

0x2811 02A8

GEM_A_HI

0x2811 22A8

GEM_B_HI

Description

Design Configuration Register 11

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:8

reserved_31_8

 

RO

0x00 0000

7

asf_prot_tx_sched

 

RO

0

6

asf_host_par

 

RO

0

5

asf_trans_to_prot

 

RO

0

4

asf_integrity_prot

 

RO

0

3

protect_tsu

 

RO

0

2

csr_protection

 

RO

0

1

dap_protection

 

RO

0

0

ecc_sram

 

RO

0

 

gem_gximicrosemi : DESIGNCFG_DEBUG12

Address offset

0x02AC

Physical address

0x2011 02AC

Instance

GEM_A_LO

0x2011 22AC

GEM_B_LO

0x2811 02AC

GEM_A_HI

0x2811 22AC

GEM_B_HI

Description

Design Configuration Register 12

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:26

reserved_31_26

 

RO

0x00

25

gem_has_802p3_br

 

RO

0

24:21

emac_tx_pbuf_addr

 

RO

0xA

20:17

emac_rx_pbuf_addr

 

RO

0xA

16

gem_has_cb

 

RO

0

15:8

gem_cb_history_len

 

RO

0x40

7:0

gem_num_cb_streams

 

RO

0x01

 

gem_gximicrosemi : AXI_QOS_CFG_0

Address offset

0x02E0

Physical address

0x2011 02E0

Instance

GEM_A_LO

0x2011 22E0

GEM_B_LO

0x2811 02E0

GEM_A_HI

0x2811 22E0

GEM_B_HI

Description

AXI Quality of Service register 0. This register is only present if AXI is configured. This register contains 8-bits per queue to control driving of the ARQOS and AWQOS outputs (4-bits each). For each queue the lower four bits are for data accesses and the upper four bits are for descriptor accesses.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:28

q_3_descr_qos

 

RW

0x0

27:24

q_3_data_qos

 

RW

0x0

23:20

q_2_descr_qos

 

RW

0x0

19:16

q_2_data_qos

 

RW

0x0

15:12

q_1_descr_qos

 

RW

0x0

11:8

q_1_data_qos

 

RW

0x0

7:4

q_0_descr_qos

 

RW

0x0

3:0

q_0_data_qos

 

RW

0x0

 

gem_gximicrosemi : AXI_QOS_CFG_1

Address offset

0x02E4

Physical address

0x2011 02E4

Instance

GEM_A_LO

0x2011 22E4

GEM_B_LO

0x2811 02E4

GEM_A_HI

0x2811 22E4

GEM_B_HI

Description

AXI Quality of Service register 1. This register is only present if AXI is configured. This register contains 8-bits per queue to control driving of the ARQOS and AWQOS outputs (4-bits each). For each queue the lower four bits are for data accesses and the upper four bits are for descriptor accesses.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:28

q_7_descr_qos

 

RW

0x0

27:24

q_7_data_qos

 

RW

0x0

23:20

q_6_descr_qos

 

RW

0x0

19:16

q_6_data_qos

 

RW

0x0

15:12

q_5_descr_qos

 

RW

0x0

11:8

q_5_data_qos

 

RW

0x0

7:4

q_4_descr_qos

 

RW

0x0

3:0

q_4_data_qos

 

RW

0x0

 

gem_gximicrosemi : AXI_QOS_CFG_2

Address offset

0x02E8

Physical address

0x2011 02E8

Instance

GEM_A_LO

0x2011 22E8

GEM_B_LO

0x2811 02E8

GEM_A_HI

0x2811 22E8

GEM_B_HI

Description

AXI Quality of Service register 2. This register is only present if AXI is configured. This register contains 8-bits per queue to control driving of the ARQOS and AWQOS outputs (4-bits each). For each queue the lower four bits are for data accesses and the upper four bits are for descriptor accesses.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:28

q_11_descr_qos

 

RW

0x0

27:24

q_11_data_qos

 

RW

0x0

23:20

q_10_descr_qos

 

RW

0x0

19:16

q_10_data_qos

 

RW

0x0

15:12

q_9_descr_qos

 

RW

0x0

11:8

q_9_data_qos

 

RW

0x0

7:4

q_8_descr_qos

 

RW

0x0

3:0

q_8_data_qos

 

RW

0x0

 

gem_gximicrosemi : AXI_QOS_CFG_3

Address offset

0x02EC

Physical address

0x2011 02EC

Instance

GEM_A_LO

0x2011 22EC

GEM_B_LO

0x2811 02EC

GEM_A_HI

0x2811 22EC

GEM_B_HI

Description

AXI Quality of Service register 3. This register is only present if AXI is configured. This register contains 8-bits per queue to control driving of the ARQOS and AWQOS outputs (4-bits each). For each queue the lower four bits are for data accesses and the upper four bits are for descriptor accesses.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:28

q_15_descr_qos

 

RW

0x0

27:24

q_15_data_qos

 

RW

0x0

23:20

q_14_descr_qos

 

RW

0x0

19:16

q_14_data_qos

 

RW

0x0

15:12

q_13_descr_qos

 

RW

0x0

11:8

q_13_data_qos

 

RW

0x0

7:4

q_12_descr_qos

 

RW

0x0

3:0

q_12_data_qos

 

RW

0x0

 

gem_gximicrosemi : INT_Q1_STATUS

Address offset

0x0400

Physical address

0x2011 0400

Instance

GEM_A_LO

0x2011 2400

GEM_B_LO

0x2811 0400

GEM_A_HI

0x2811 2400

GEM_B_HI

Description

Priority Queue Interrupt Status Register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

resp_not_ok

 

RW
W1toClr

0

10:8

reserved_10_8

 

RO

0x0

7

transmit_complete

 

RW
W1toClr

0

6

amba_error

 

RW
W1toClr

0

5

retry_limit_exceeded_or_late_collision

 

RW
W1toClr

0

4:3

reserved_4_3

 

RO

0x0

2

rx_used_bit_read

 

RW
W1toClr

0

1

receive_complete

 

RW
W1toClr

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q2_STATUS

Address offset

0x0404

Physical address

0x2011 0404

Instance

GEM_A_LO

0x2011 2404

GEM_B_LO

0x2811 0404

GEM_A_HI

0x2811 2404

GEM_B_HI

Description

Priority Queue Interrupt Status Register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

resp_not_ok

 

RW
W1toClr

0

10:8

reserved_10_8

 

RO

0x0

7

transmit_complete

 

RW
W1toClr

0

6

amba_error

 

RW
W1toClr

0

5

retry_limit_exceeded_or_late_collision

 

RW
W1toClr

0

4:3

reserved_4_3

 

RO

0x0

2

rx_used_bit_read

 

RW
W1toClr

0

1

receive_complete

 

RW
W1toClr

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q3_STATUS

Address offset

0x0408

Physical address

0x2011 0408

Instance

GEM_A_LO

0x2011 2408

GEM_B_LO

0x2811 0408

GEM_A_HI

0x2811 2408

GEM_B_HI

Description

Priority Queue Interrupt Status Register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

resp_not_ok

 

RW
W1toClr

0

10:8

reserved_10_8

 

RO

0x0

7

transmit_complete

 

RW
W1toClr

0

6

amba_error

 

RW
W1toClr

0

5

retry_limit_exceeded_or_late_collision

 

RW
W1toClr

0

4:3

reserved_4_3

 

RO

0x0

2

rx_used_bit_read

 

RW
W1toClr

0

1

receive_complete

 

RW
W1toClr

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q4_STATUS

Address offset

0x040C

Physical address

0x2011 040C

Instance

GEM_A_LO

0x2011 240C

GEM_B_LO

0x2811 040C

GEM_A_HI

0x2811 240C

GEM_B_HI

Description

Priority Queue Interrupt Status Register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

resp_not_ok

 

RW
W1toClr

0

10:8

reserved_10_8

 

RO

0x0

7

transmit_complete

 

RW
W1toClr

0

6

amba_error

 

RW
W1toClr

0

5

retry_limit_exceeded_or_late_collision

 

RW
W1toClr

0

4:3

reserved_4_3

 

RO

0x0

2

rx_used_bit_read

 

RW
W1toClr

0

1

receive_complete

 

RW
W1toClr

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q5_STATUS

Address offset

0x0410

Physical address

0x2011 0410

Instance

GEM_A_LO

0x2011 2410

GEM_B_LO

0x2811 0410

GEM_A_HI

0x2811 2410

GEM_B_HI

Description

Priority Queue Interrupt Status Register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

resp_not_ok

 

RW
W1toClr

0

10:8

reserved_10_8

 

RO

0x0

7

transmit_complete

 

RW
W1toClr

0

6

amba_error

 

RW
W1toClr

0

5

retry_limit_exceeded_or_late_collision

 

RW
W1toClr

0

4:3

reserved_4_3

 

RO

0x0

2

rx_used_bit_read

 

RW
W1toClr

0

1

receive_complete

 

RW
W1toClr

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q6_STATUS

Address offset

0x0414

Physical address

0x2011 0414

Instance

GEM_A_LO

0x2011 2414

GEM_B_LO

0x2811 0414

GEM_A_HI

0x2811 2414

GEM_B_HI

Description

Priority Queue Interrupt Status Register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

resp_not_ok

 

RW
W1toClr

0

10:8

reserved_10_8

 

RO

0x0

7

transmit_complete

 

RW
W1toClr

0

6

amba_error

 

RW
W1toClr

0

5

retry_limit_exceeded_or_late_collision

 

RW
W1toClr

0

4:3

reserved_4_3

 

RO

0x0

2

rx_used_bit_read

 

RW
W1toClr

0

1

receive_complete

 

RW
W1toClr

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q7_STATUS

Address offset

0x0418

Physical address

0x2011 0418

Instance

GEM_A_LO

0x2011 2418

GEM_B_LO

0x2811 0418

GEM_A_HI

0x2811 2418

GEM_B_HI

Description

Priority Queue Interrupt Status Register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

resp_not_ok

 

RW
W1toClr

0

10:8

reserved_10_8

 

RO

0x0

7

transmit_complete

 

RW
W1toClr

0

6

amba_error

 

RW
W1toClr

0

5

retry_limit_exceeded_or_late_collision

 

RW
W1toClr

0

4:3

reserved_4_3

 

RO

0x0

2

rx_used_bit_read

 

RW
W1toClr

0

1

receive_complete

 

RW
W1toClr

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q8_STATUS

Address offset

0x041C

Physical address

0x2011 041C

Instance

GEM_A_LO

0x2011 241C

GEM_B_LO

0x2811 041C

GEM_A_HI

0x2811 241C

GEM_B_HI

Description

Priority Queue Interrupt Status Register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

resp_not_ok

 

RW
W1toClr

0

10:8

reserved_10_8

 

RO

0x0

7

transmit_complete

 

RW
W1toClr

0

6

amba_error

 

RW
W1toClr

0

5

retry_limit_exceeded_or_late_collision

 

RW
W1toClr

0

4:3

reserved_4_3

 

RO

0x0

2

rx_used_bit_read

 

RW
W1toClr

0

1

receive_complete

 

RW
W1toClr

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q9_STATUS

Address offset

0x0420

Physical address

0x2011 0420

Instance

GEM_A_LO

0x2011 2420

GEM_B_LO

0x2811 0420

GEM_A_HI

0x2811 2420

GEM_B_HI

Description

Priority Queue Interrupt Status Register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

resp_not_ok

 

RW
W1toClr

0

10:8

reserved_10_8

 

RO

0x0

7

transmit_complete

 

RW
W1toClr

0

6

amba_error

 

RW
W1toClr

0

5

retry_limit_exceeded_or_late_collision

 

RW
W1toClr

0

4:3

reserved_4_3

 

RO

0x0

2

rx_used_bit_read

 

RW
W1toClr

0

1

receive_complete

 

RW
W1toClr

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q10_STATUS

Address offset

0x0424

Physical address

0x2011 0424

Instance

GEM_A_LO

0x2011 2424

GEM_B_LO

0x2811 0424

GEM_A_HI

0x2811 2424

GEM_B_HI

Description

Priority Queue Interrupt Status Register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

resp_not_ok

 

RW
W1toClr

0

10:8

reserved_10_8

 

RO

0x0

7

transmit_complete

 

RW
W1toClr

0

6

amba_error

 

RW
W1toClr

0

5

retry_limit_exceeded_or_late_collision

 

RW
W1toClr

0

4:3

reserved_4_3

 

RO

0x0

2

rx_used_bit_read

 

RW
W1toClr

0

1

receive_complete

 

RW
W1toClr

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q11_STATUS

Address offset

0x0428

Physical address

0x2011 0428

Instance

GEM_A_LO

0x2011 2428

GEM_B_LO

0x2811 0428

GEM_A_HI

0x2811 2428

GEM_B_HI

Description

Priority Queue Interrupt Status Register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

resp_not_ok

 

RW
W1toClr

0

10:8

reserved_10_8

 

RO

0x0

7

transmit_complete

 

RW
W1toClr

0

6

amba_error

 

RW
W1toClr

0

5

retry_limit_exceeded_or_late_collision

 

RW
W1toClr

0

4:3

reserved_4_3

 

RO

0x0

2

rx_used_bit_read

 

RW
W1toClr

0

1

receive_complete

 

RW
W1toClr

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q12_STATUS

Address offset

0x042C

Physical address

0x2011 042C

Instance

GEM_A_LO

0x2011 242C

GEM_B_LO

0x2811 042C

GEM_A_HI

0x2811 242C

GEM_B_HI

Description

Priority Queue Interrupt Status Register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

resp_not_ok

 

RW
W1toClr

0

10:8

reserved_10_8

 

RO

0x0

7

transmit_complete

 

RW
W1toClr

0

6

amba_error

 

RW
W1toClr

0

5

retry_limit_exceeded_or_late_collision

 

RW
W1toClr

0

4:3

reserved_4_3

 

RO

0x0

2

rx_used_bit_read

 

RW
W1toClr

0

1

receive_complete

 

RW
W1toClr

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q13_STATUS

Address offset

0x0430

Physical address

0x2011 0430

Instance

GEM_A_LO

0x2011 2430

GEM_B_LO

0x2811 0430

GEM_A_HI

0x2811 2430

GEM_B_HI

Description

Priority Queue Interrupt Status Register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

resp_not_ok

 

RW
W1toClr

0

10:8

reserved_10_8

 

RO

0x0

7

transmit_complete

 

RW
W1toClr

0

6

amba_error

 

RW
W1toClr

0

5

retry_limit_exceeded_or_late_collision

 

RW
W1toClr

0

4:3

reserved_4_3

 

RO

0x0

2

rx_used_bit_read

 

RW
W1toClr

0

1

receive_complete

 

RW
W1toClr

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q14_STATUS

Address offset

0x0434

Physical address

0x2011 0434

Instance

GEM_A_LO

0x2011 2434

GEM_B_LO

0x2811 0434

GEM_A_HI

0x2811 2434

GEM_B_HI

Description

Priority Queue Interrupt Status Register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

resp_not_ok

 

RW
W1toClr

0

10:8

reserved_10_8

 

RO

0x0

7

transmit_complete

 

RW
W1toClr

0

6

amba_error

 

RW
W1toClr

0

5

retry_limit_exceeded_or_late_collision

 

RW
W1toClr

0

4:3

reserved_4_3

 

RO

0x0

2

rx_used_bit_read

 

RW
W1toClr

0

1

receive_complete

 

RW
W1toClr

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q15_STATUS

Address offset

0x0438

Physical address

0x2011 0438

Instance

GEM_A_LO

0x2011 2438

GEM_B_LO

0x2811 0438

GEM_A_HI

0x2811 2438

GEM_B_HI

Description

Priority Queue Interrupt Status Register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

resp_not_ok

 

RW
W1toClr

0

10:8

reserved_10_8

 

RO

0x0

7

transmit_complete

 

RW
W1toClr

0

6

amba_error

 

RW
W1toClr

0

5

retry_limit_exceeded_or_late_collision

 

RW
W1toClr

0

4:3

reserved_4_3

 

RO

0x0

2

rx_used_bit_read

 

RW
W1toClr

0

1

receive_complete

 

RW
W1toClr

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : TRANSMIT_Q1_PTR

Address offset

0x0440

Physical address

0x2011 0440

Instance

GEM_A_LO

0x2011 2440

GEM_B_LO

0x2811 0440

GEM_A_HI

0x2811 2440

GEM_B_HI

Description

This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AHB/AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit or 128bit, the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AHB/AXI access. For 32bit datapaths, the descriptors should be aligned at 32-bit boundaries and the descriptors are read from memory using two individual 32-bit non sequential accesses.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

dma_tx_q_ptr

 

RW

0x0000 0000

1

reserved_1

 

RO

0

0

dma_tx_dis_q

 

RW

0

 

gem_gximicrosemi : TRANSMIT_Q2_PTR

Address offset

0x0444

Physical address

0x2011 0444

Instance

GEM_A_LO

0x2011 2444

GEM_B_LO

0x2811 0444

GEM_A_HI

0x2811 2444

GEM_B_HI

Description

This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AHB/AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit or 128bit, the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AHB/AXI access. For 32bit datapaths, the descriptors should be aligned at 32-bit boundaries and the descriptors are read from memory using two individual 32-bit non sequential accesses.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

dma_tx_q_ptr

 

RW

0x0000 0000

1

reserved_1

 

RO

0

0

dma_tx_dis_q

 

RW

0

 

gem_gximicrosemi : TRANSMIT_Q3_PTR

Address offset

0x0448

Physical address

0x2011 0448

Instance

GEM_A_LO

0x2011 2448

GEM_B_LO

0x2811 0448

GEM_A_HI

0x2811 2448

GEM_B_HI

Description

This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AHB/AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit or 128bit, the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AHB/AXI access. For 32bit datapaths, the descriptors should be aligned at 32-bit boundaries and the descriptors are read from memory using two individual 32-bit non sequential accesses.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

dma_tx_q_ptr

 

RW

0x0000 0000

1

reserved_1

 

RO

0

0

dma_tx_dis_q

 

RW

0

 

gem_gximicrosemi : TRANSMIT_Q4_PTR

Address offset

0x044C

Physical address

0x2011 044C

Instance

GEM_A_LO

0x2011 244C

GEM_B_LO

0x2811 044C

GEM_A_HI

0x2811 244C

GEM_B_HI

Description

This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AHB/AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit or 128bit, the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AHB/AXI access. For 32bit datapaths, the descriptors should be aligned at 32-bit boundaries and the descriptors are read from memory using two individual 32-bit non sequential accesses.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

dma_tx_q_ptr

 

RW

0x0000 0000

1

reserved_1

 

RO

0

0

dma_tx_dis_q

 

RW

0

 

gem_gximicrosemi : TRANSMIT_Q5_PTR

Address offset

0x0450

Physical address

0x2011 0450

Instance

GEM_A_LO

0x2011 2450

GEM_B_LO

0x2811 0450

GEM_A_HI

0x2811 2450

GEM_B_HI

Description

This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AHB/AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit or 128bit, the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AHB/AXI access. For 32bit datapaths, the descriptors should be aligned at 32-bit boundaries and the descriptors are read from memory using two individual 32-bit non sequential accesses.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

dma_tx_q_ptr

 

RW

0x0000 0000

1

reserved_1

 

RO

0

0

dma_tx_dis_q

 

RW

0

 

gem_gximicrosemi : TRANSMIT_Q6_PTR

Address offset

0x0454

Physical address

0x2011 0454

Instance

GEM_A_LO

0x2011 2454

GEM_B_LO

0x2811 0454

GEM_A_HI

0x2811 2454

GEM_B_HI

Description

This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AHB/AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit or 128bit, the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AHB/AXI access. For 32bit datapaths, the descriptors should be aligned at 32-bit boundaries and the descriptors are read from memory using two individual 32-bit non sequential accesses.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

dma_tx_q_ptr

 

RW

0x0000 0000

1

reserved_1

 

RO

0

0

dma_tx_dis_q

 

RW

0

 

gem_gximicrosemi : TRANSMIT_Q7_PTR

Address offset

0x0458

Physical address

0x2011 0458

Instance

GEM_A_LO

0x2011 2458

GEM_B_LO

0x2811 0458

GEM_A_HI

0x2811 2458

GEM_B_HI

Description

This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AHB/AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit or 128bit, the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AHB/AXI access. For 32bit datapaths, the descriptors should be aligned at 32-bit boundaries and the descriptors are read from memory using two individual 32-bit non sequential accesses.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

dma_tx_q_ptr

 

RW

0x0000 0000

1

reserved_1

 

RO

0

0

dma_tx_dis_q

 

RW

0

 

gem_gximicrosemi : TRANSMIT_Q8_PTR

Address offset

0x045C

Physical address

0x2011 045C

Instance

GEM_A_LO

0x2011 245C

GEM_B_LO

0x2811 045C

GEM_A_HI

0x2811 245C

GEM_B_HI

Description

This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AHB/AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit or 128bit, the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AHB/AXI access. For 32bit datapaths, the descriptors should be aligned at 32-bit boundaries and the descriptors are read from memory using two individual 32-bit non sequential accesses.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

dma_tx_q_ptr

 

RW

0x0000 0000

1

reserved_1

 

RO

0

0

dma_tx_dis_q

 

RW

0

 

gem_gximicrosemi : TRANSMIT_Q9_PTR

Address offset

0x0460

Physical address

0x2011 0460

Instance

GEM_A_LO

0x2011 2460

GEM_B_LO

0x2811 0460

GEM_A_HI

0x2811 2460

GEM_B_HI

Description

This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AHB/AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit or 128bit, the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AHB/AXI access. For 32bit datapaths, the descriptors should be aligned at 32-bit boundaries and the descriptors are read from memory using two individual 32-bit non sequential accesses.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

dma_tx_q_ptr

 

RW

0x0000 0000

1

reserved_1

 

RO

0

0

dma_tx_dis_q

 

RW

0

 

gem_gximicrosemi : TRANSMIT_Q10_PTR

Address offset

0x0464

Physical address

0x2011 0464

Instance

GEM_A_LO

0x2011 2464

GEM_B_LO

0x2811 0464

GEM_A_HI

0x2811 2464

GEM_B_HI

Description

This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AHB/AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit or 128bit, the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AHB/AXI access. For 32bit datapaths, the descriptors should be aligned at 32-bit boundaries and the descriptors are read from memory using two individual 32-bit non sequential accesses.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

dma_tx_q_ptr

 

RW

0x0000 0000

1

reserved_1

 

RO

0

0

dma_tx_dis_q

 

RW

0

 

gem_gximicrosemi : TRANSMIT_Q11_PTR

Address offset

0x0468

Physical address

0x2011 0468

Instance

GEM_A_LO

0x2011 2468

GEM_B_LO

0x2811 0468

GEM_A_HI

0x2811 2468

GEM_B_HI

Description

This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AHB/AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit or 128bit, the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AHB/AXI access. For 32bit datapaths, the descriptors should be aligned at 32-bit boundaries and the descriptors are read from memory using two individual 32-bit non sequential accesses.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

dma_tx_q_ptr

 

RW

0x0000 0000

1

reserved_1

 

RO

0

0

dma_tx_dis_q

 

RW

0

 

gem_gximicrosemi : TRANSMIT_Q12_PTR

Address offset

0x046C

Physical address

0x2011 046C

Instance

GEM_A_LO

0x2011 246C

GEM_B_LO

0x2811 046C

GEM_A_HI

0x2811 246C

GEM_B_HI

Description

This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AHB/AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit or 128bit, the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AHB/AXI access. For 32bit datapaths, the descriptors should be aligned at 32-bit boundaries and the descriptors are read from memory using two individual 32-bit non sequential accesses.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

dma_tx_q_ptr

 

RW

0x0000 0000

1

reserved_1

 

RO

0

0

dma_tx_dis_q

 

RW

0

 

gem_gximicrosemi : TRANSMIT_Q13_PTR

Address offset

0x0470

Physical address

0x2011 0470

Instance

GEM_A_LO

0x2011 2470

GEM_B_LO

0x2811 0470

GEM_A_HI

0x2811 2470

GEM_B_HI

Description

This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AHB/AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit or 128bit, the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AHB/AXI access. For 32bit datapaths, the descriptors should be aligned at 32-bit boundaries and the descriptors are read from memory using two individual 32-bit non sequential accesses.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

dma_tx_q_ptr

 

RW

0x0000 0000

1

reserved_1

 

RO

0

0

dma_tx_dis_q

 

RW

0

 

gem_gximicrosemi : TRANSMIT_Q14_PTR

Address offset

0x0474

Physical address

0x2011 0474

Instance

GEM_A_LO

0x2011 2474

GEM_B_LO

0x2811 0474

GEM_A_HI

0x2811 2474

GEM_B_HI

Description

This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AHB/AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit or 128bit, the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AHB/AXI access. For 32bit datapaths, the descriptors should be aligned at 32-bit boundaries and the descriptors are read from memory using two individual 32-bit non sequential accesses.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

dma_tx_q_ptr

 

RW

0x0000 0000

1

reserved_1

 

RO

0

0

dma_tx_dis_q

 

RW

0

 

gem_gximicrosemi : TRANSMIT_Q15_PTR

Address offset

0x0478

Physical address

0x2011 0478

Instance

GEM_A_LO

0x2011 2478

GEM_B_LO

0x2811 0478

GEM_A_HI

0x2811 2478

GEM_B_HI

Description

This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AHB/AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit or 128bit, the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AHB/AXI access. For 32bit datapaths, the descriptors should be aligned at 32-bit boundaries and the descriptors are read from memory using two individual 32-bit non sequential accesses.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

dma_tx_q_ptr

 

RW

0x0000 0000

1

reserved_1

 

RO

0

0

dma_tx_dis_q

 

RW

0

 

gem_gximicrosemi : RECEIVE_Q1_PTR

Address offset

0x0480

Physical address

0x2011 0480

Instance

GEM_A_LO

0x2011 2480

GEM_B_LO

0x2811 0480

GEM_A_HI

0x2811 2480

GEM_B_HI

Description

This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the network control register. Once reception is enabled, any write to the receive buffer queue base address register is ignored. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the used bits. In terms of AMBA (AHB/AXI) operation, the receive descriptors are read from memory using a single 32bit AHB/AXI access. When the datapath is configured at 64bit or 128bit, the receive descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is written to using a single 64bit AHB/AXI access. For 32bit datapaths, the receive descriptors should be aligned at 32-bit boundaries and are written to using two individual non sequential 32-bit accesses.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

dma_rx_q_ptr

 

RW

0x0000 0000

1

reserved_1

 

RO

0

0

dma_rx_dis_q

 

RW

0

 

gem_gximicrosemi : RECEIVE_Q2_PTR

Address offset

0x0484

Physical address

0x2011 0484

Instance

GEM_A_LO

0x2011 2484

GEM_B_LO

0x2811 0484

GEM_A_HI

0x2811 2484

GEM_B_HI

Description

This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the network control register. Once reception is enabled, any write to the receive buffer queue base address register is ignored. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the used bits. In terms of AMBA (AHB/AXI) operation, the receive descriptors are read from memory using a single 32bit AHB/AXI access. When the datapath is configured at 64bit or 128bit, the receive descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is written to using a single 64bit AHB/AXI access. For 32bit datapaths, the receive descriptors should be aligned at 32-bit boundaries and are written to using two individual non sequential 32-bit accesses.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

dma_rx_q_ptr

 

RW

0x0000 0000

1

reserved_1

 

RO

0

0

dma_rx_dis_q

 

RW

0

 

gem_gximicrosemi : RECEIVE_Q3_PTR

Address offset

0x0488

Physical address

0x2011 0488

Instance

GEM_A_LO

0x2011 2488

GEM_B_LO

0x2811 0488

GEM_A_HI

0x2811 2488

GEM_B_HI

Description

This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the network control register. Once reception is enabled, any write to the receive buffer queue base address register is ignored. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the used bits. In terms of AMBA (AHB/AXI) operation, the receive descriptors are read from memory using a single 32bit AHB/AXI access. When the datapath is configured at 64bit or 128bit, the receive descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is written to using a single 64bit AHB/AXI access. For 32bit datapaths, the receive descriptors should be aligned at 32-bit boundaries and are written to using two individual non sequential 32-bit accesses.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

dma_rx_q_ptr

 

RW

0x0000 0000

1

reserved_1

 

RO

0

0

dma_rx_dis_q

 

RW

0

 

gem_gximicrosemi : RECEIVE_Q4_PTR

Address offset

0x048C

Physical address

0x2011 048C

Instance

GEM_A_LO

0x2011 248C

GEM_B_LO

0x2811 048C

GEM_A_HI

0x2811 248C

GEM_B_HI

Description

This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the network control register. Once reception is enabled, any write to the receive buffer queue base address register is ignored. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the used bits. In terms of AMBA (AHB/AXI) operation, the receive descriptors are read from memory using a single 32bit AHB/AXI access. When the datapath is configured at 64bit or 128bit, the receive descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is written to using a single 64bit AHB/AXI access. For 32bit datapaths, the receive descriptors should be aligned at 32-bit boundaries and are written to using two individual non sequential 32-bit accesses.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

dma_rx_q_ptr

 

RW

0x0000 0000

1

reserved_1

 

RO

0

0

dma_rx_dis_q

 

RW

0

 

gem_gximicrosemi : RECEIVE_Q5_PTR

Address offset

0x0490

Physical address

0x2011 0490

Instance

GEM_A_LO

0x2011 2490

GEM_B_LO

0x2811 0490

GEM_A_HI

0x2811 2490

GEM_B_HI

Description

This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the network control register. Once reception is enabled, any write to the receive buffer queue base address register is ignored. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the used bits. In terms of AMBA (AHB/AXI) operation, the receive descriptors are read from memory using a single 32bit AHB/AXI access. When the datapath is configured at 64bit or 128bit, the receive descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is written to using a single 64bit AHB/AXI access. For 32bit datapaths, the receive descriptors should be aligned at 32-bit boundaries and are written to using two individual non sequential 32-bit accesses.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

dma_rx_q_ptr

 

RW

0x0000 0000

1

reserved_1

 

RO

0

0

dma_rx_dis_q

 

RW

0

 

gem_gximicrosemi : RECEIVE_Q6_PTR

Address offset

0x0494

Physical address

0x2011 0494

Instance

GEM_A_LO

0x2011 2494

GEM_B_LO

0x2811 0494

GEM_A_HI

0x2811 2494

GEM_B_HI

Description

This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the network control register. Once reception is enabled, any write to the receive buffer queue base address register is ignored. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the used bits. In terms of AMBA (AHB/AXI) operation, the receive descriptors are read from memory using a single 32bit AHB/AXI access. When the datapath is configured at 64bit or 128bit, the receive descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is written to using a single 64bit AHB/AXI access. For 32bit datapaths, the receive descriptors should be aligned at 32-bit boundaries and are written to using two individual non sequential 32-bit accesses.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

dma_rx_q_ptr

 

RW

0x0000 0000

1

reserved_1

 

RO

0

0

dma_rx_dis_q

 

RW

0

 

gem_gximicrosemi : RECEIVE_Q7_PTR

Address offset

0x0498

Physical address

0x2011 0498

Instance

GEM_A_LO

0x2011 2498

GEM_B_LO

0x2811 0498

GEM_A_HI

0x2811 2498

GEM_B_HI

Description

This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the network control register. Once reception is enabled, any write to the receive buffer queue base address register is ignored. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the used bits. In terms of AMBA (AHB/AXI) operation, the receive descriptors are read from memory using a single 32bit AHB/AXI access. When the datapath is configured at 64bit or 128bit, the receive descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is written to using a single 64bit AHB/AXI access. For 32bit datapaths, the receive descriptors should be aligned at 32-bit boundaries and are written to using two individual non sequential 32-bit accesses.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

dma_rx_q_ptr

 

RW

0x0000 0000

1

reserved_1

 

RO

0

0

dma_rx_dis_q

 

RW

0

 

gem_gximicrosemi : DMA_RXBUF_SIZE_Q1

Address offset

0x04A0

Physical address

0x2011 04A0

Instance

GEM_A_LO

0x2011 24A0

GEM_B_LO

0x2811 04A0

GEM_A_HI

0x2811 24A0

GEM_B_HI

Description

Receive Buffer Size

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:8

reserved_31_8

 

RO

0x00 0000

7:0

dma_rx_q_buf_size

 

RW

0x02

 

gem_gximicrosemi : DMA_RXBUF_SIZE_Q2

Address offset

0x04A4

Physical address

0x2011 04A4

Instance

GEM_A_LO

0x2011 24A4

GEM_B_LO

0x2811 04A4

GEM_A_HI

0x2811 24A4

GEM_B_HI

Description

Receive Buffer Size

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:8

reserved_31_8

 

RO

0x00 0000

7:0

dma_rx_q_buf_size

 

RW

0x02

 

gem_gximicrosemi : DMA_RXBUF_SIZE_Q3

Address offset

0x04A8

Physical address

0x2011 04A8

Instance

GEM_A_LO

0x2011 24A8

GEM_B_LO

0x2811 04A8

GEM_A_HI

0x2811 24A8

GEM_B_HI

Description

Receive Buffer Size

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:8

reserved_31_8

 

RO

0x00 0000

7:0

dma_rx_q_buf_size

 

RW

0x02

 

gem_gximicrosemi : DMA_RXBUF_SIZE_Q4

Address offset

0x04AC

Physical address

0x2011 04AC

Instance

GEM_A_LO

0x2011 24AC

GEM_B_LO

0x2811 04AC

GEM_A_HI

0x2811 24AC

GEM_B_HI

Description

Receive Buffer Size

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:8

reserved_31_8

 

RO

0x00 0000

7:0

dma_rx_q_buf_size

 

RW

0x02

 

gem_gximicrosemi : DMA_RXBUF_SIZE_Q5

Address offset

0x04B0

Physical address

0x2011 04B0

Instance

GEM_A_LO

0x2011 24B0

GEM_B_LO

0x2811 04B0

GEM_A_HI

0x2811 24B0

GEM_B_HI

Description

Receive Buffer Size

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:8

reserved_31_8

 

RO

0x00 0000

7:0

dma_rx_q_buf_size

 

RW

0x02

 

gem_gximicrosemi : DMA_RXBUF_SIZE_Q6

Address offset

0x04B4

Physical address

0x2011 04B4

Instance

GEM_A_LO

0x2011 24B4

GEM_B_LO

0x2811 04B4

GEM_A_HI

0x2811 24B4

GEM_B_HI

Description

Receive Buffer Size

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:8

reserved_31_8

 

RO

0x00 0000

7:0

dma_rx_q_buf_size

 

RW

0x02

 

gem_gximicrosemi : DMA_RXBUF_SIZE_Q7

Address offset

0x04B8

Physical address

0x2011 04B8

Instance

GEM_A_LO

0x2011 24B8

GEM_B_LO

0x2811 04B8

GEM_A_HI

0x2811 24B8

GEM_B_HI

Description

Receive Buffer Size

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:8

reserved_31_8

 

RO

0x00 0000

7:0

dma_rx_q_buf_size

 

RW

0x02

 

gem_gximicrosemi : CBS_CONTROL

Address offset

0x04BC

Physical address

0x2011 04BC

Instance

GEM_A_LO

0x2011 24BC

GEM_B_LO

0x2811 04BC

GEM_A_HI

0x2811 24BC

GEM_B_HI

Description

The IdleSlope value is defined as the rate of change of credit when a packet is waiting to be sent. This must not exceed the portTransmitRate which is dependent on the speed of operation, eg, portTransmitRate: 1Gb/s = 32'h07735940 (125 Mbytes/s), 100Mb/sec = 32'h017D7840 (25 Mnibbles/s), 10Mb/sec = 32'h002625A0 (2.5 Mnibbles/s). If 50% of bandwidth was to be allocated to a particular queue in 1Gb/sec mode then the IdleSlope value for that queue would be calculated as 32'h07735940/2. Note: Credit-Based Shaping should be disabled prior to updating the IdleSlope values. As another example, for a 1722 audio packet with a payload of 6 samples per channel, the packet size would be: 7 (preamble) + 1 (SFD) + 50 (packet header) + 6x4x2(payload) + 4 (CRC) = 110 bytes. For a rate of 8000 packets per second, the desired rate would 110 x 8000 bytes per second, so the programmed idleSlope value would be 880000 for a 1Gb/s connection, or 1760000 for a 100Mb/s or 10Mbs connection. See Figure 6.3 in the IEEE 1722 standard. In practice, the actual transmission rate will be vary slightly from that calculated. In this case, the idleSlope value should be recalibrated based on the variance between the measured and expected rate, and in this case very accurate transmission rates can be achieved. (The idleslope value is scaled by 2.5 in 2.5G operation and so the port transmit rate is the same for 1G and 2.5G.)

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

reserved_31_2

 

RO

0x0000 0000

1

cbs_enable_queue_b

 

RW

0

0

cbs_enable_queue_a

 

RW

0

 

gem_gximicrosemi : CBS_IDLESLOPE_Q_A

Address offset

0x04C0

Physical address

0x2011 04C0

Instance

GEM_A_LO

0x2011 24C0

GEM_B_LO

0x2811 04C0

GEM_A_HI

0x2811 24C0

GEM_B_HI

Description

Queue A is the highest priority queue. This is the highest indexed active queue, e.g. For a system with Q0 to Q7, this would be Q7 if all queues were active.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

idleslope_a

 

RW

0x0000 0000

 

gem_gximicrosemi : CBS_IDLESLOPE_Q_B

Address offset

0x04C4

Physical address

0x2011 04C4

Instance

GEM_A_LO

0x2011 24C4

GEM_B_LO

0x2811 04C4

GEM_A_HI

0x2811 24C4

GEM_B_HI

Description

Queue B is the 2nd highest priority queue. This is the second highest indexed active queue, e.g. For a system with Q0 to Q7, this would be Q6 if all queues were active.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

idleslope_b

 

RW

0x0000 0000

 

gem_gximicrosemi : UPPER_TX_Q_BASE_ADDR

Address offset

0x04C8

Physical address

0x2011 04C8

Instance

GEM_A_LO

0x2011 24C8

GEM_B_LO

0x2811 04C8

GEM_A_HI

0x2811 24C8

GEM_B_HI

Description

Upper 32 bits of transmit buffer descriptor queue base address.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

upper_tx_q_base_addr

 

RW

0x0000 0000

 

gem_gximicrosemi : TX_BD_CONTROL

Address offset

0x04CC

Physical address

0x2011 04CC

Instance

GEM_A_LO

0x2011 24CC

GEM_B_LO

0x2811 04CC

GEM_A_HI

0x2811 24CC

GEM_B_HI

Description

Transmit buffer descriptor control register - this register determines which transmit frames, with time stamps reported in the buffer descriptor status field in extended buffer descriptor mode, set bit 23 in transmit buffer descriptor word 1.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:6

reserved_31_6

 

RO

0x000 0000

5:4

tx_bd_ts_mode

 

RW

0x0

3:0

reserved_3_0

 

RO

0x0

 

gem_gximicrosemi : RX_BD_CONTROL

Address offset

0x04D0

Physical address

0x2011 04D0

Instance

GEM_A_LO

0x2011 24D0

GEM_B_LO

0x2811 04D0

GEM_A_HI

0x2811 24D0

GEM_B_HI

Description

Receive buffer descriptor control register - this register determines which receive frames have time stamps reported in the buffer descriptor status field

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:6

reserved_31_6

 

RO

0x000 0000

5:4

rx_bd_ts_mode

 

RW

0x0

3:0

reserved_3_0

 

RO

0x0

 

gem_gximicrosemi : UPPER_RX_Q_BASE_ADDR

Address offset

0x04D4

Physical address

0x2011 04D4

Instance

GEM_A_LO

0x2011 24D4

GEM_B_LO

0x2811 04D4

GEM_A_HI

0x2811 24D4

GEM_B_HI

Description

Upper 32 bits of receive buffer descriptor queue base address.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

upper_rx_q_base_addr

 

RW

0x0000 0000

 

gem_gximicrosemi : WD_COUNTER

Address offset

0x04EC

Physical address

0x2011 04EC

Instance

GEM_A_LO

0x2011 24EC

GEM_B_LO

0x2811 04EC

GEM_A_HI

0x2811 24EC

GEM_B_HI

Description

Hidden control register - do not alter

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:4

reserved_31_4

 

RO

0x000 0000

3:0

rx_bd_reread_timer

 

RW

0x7

 

gem_gximicrosemi : AXI_TX_FULL_THRESH0

Address offset

0x04F8

Physical address

0x2011 04F8

Instance

GEM_A_LO

0x2011 24F8

GEM_B_LO

0x2811 04F8

GEM_A_HI

0x2811 24F8

GEM_B_HI

Description

Hidden control register - do not alter

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:24

reserved_31_24

 

RO

0x00

23:16

axi_tx_full_adj_0

 

RW

0x06

15:8

reserved_15_8

 

RO

0x00

7:0

axi_tx_full_adj_1

 

RW

0x08

 

gem_gximicrosemi : AXI_TX_FULL_THRESH1

Address offset

0x04FC

Physical address

0x2011 04FC

Instance

GEM_A_LO

0x2011 24FC

GEM_B_LO

0x2811 04FC

GEM_A_HI

0x2811 24FC

GEM_B_HI

Description

Hidden control register - do not alter

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:24

reserved_31_24

 

RO

0x00

23:16

axi_tx_full_adj_2

 

RW

0x00

15:8

reserved_15_8

 

RO

0x00

7:0

axi_tx_full_adj_3

 

RW

0x00

 

gem_gximicrosemi : SCREENING_TYPE_1_REGISTER_0

Address offset

0x0500

Physical address

0x2011 0500

Instance

GEM_A_LO

0x2011 2500

GEM_B_LO

0x2811 0500

GEM_A_HI

0x2811 2500

GEM_B_HI

Description

Screening type 1 registers are used to allocate up to 16 priority queues to received frames based on certain IP or UDP fields of incoming frames. Firstly, when DS/TC match enable is set (bit 28), the DS (Differentiated Services) field of the received IPv4 header or TC field (traffic class) of IPv6 headers are matched against bits 11:4. Secondly, when UDP port match enable is set (bit 29), the UDP Destination Port of the received UDP frame is matched against bits 27:12. Both UDP and DS/TC matching can be enabled simultaneously or individually. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 1 screening registers is configured in the gem defines file. Up to 16 type 1 screening registers have been allocated APB address space between 0x500 and 0x53C. The bit mappings for these registers are as follows:

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

reserved_31

 

RO

0

30

drop_on_match

 

RW

0

29

udp_port_match_enable

 

RW

0

28

dstc_enable

 

RW

0

27:12

udp_port_match

 

RW

0x0000

11:4

dstc_match

 

RW

0x00

3:0

queue_number

 

RW

0x0

 

gem_gximicrosemi : SCREENING_TYPE_1_REGISTER_1

Address offset

0x0504

Physical address

0x2011 0504

Instance

GEM_A_LO

0x2011 2504

GEM_B_LO

0x2811 0504

GEM_A_HI

0x2811 2504

GEM_B_HI

Description

Screening type 1 registers are used to allocate up to 16 priority queues to received frames based on certain IP or UDP fields of incoming frames. Firstly, when DS/TC match enable is set (bit 28), the DS (Differentiated Services) field of the received IPv4 header or TC field (traffic class) of IPv6 headers are matched against bits 11:4. Secondly, when UDP port match enable is set (bit 29), the UDP Destination Port of the received UDP frame is matched against bits 27:12. Both UDP and DS/TC matching can be enabled simultaneously or individually. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 1 screening registers is configured in the gem defines file. Up to 16 type 1 screening registers have been allocated APB address space between 0x500 and 0x53C. The bit mappings for these registers are as follows:

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

reserved_31

 

RO

0

30

drop_on_match

 

RW

0

29

udp_port_match_enable

 

RW

0

28

dstc_enable

 

RW

0

27:12

udp_port_match

 

RW

0x0000

11:4

dstc_match

 

RW

0x00

3:0

queue_number

 

RW

0x0

 

gem_gximicrosemi : SCREENING_TYPE_1_REGISTER_2

Address offset

0x0508

Physical address

0x2011 0508

Instance

GEM_A_LO

0x2011 2508

GEM_B_LO

0x2811 0508

GEM_A_HI

0x2811 2508

GEM_B_HI

Description

Screening type 1 registers are used to allocate up to 16 priority queues to received frames based on certain IP or UDP fields of incoming frames. Firstly, when DS/TC match enable is set (bit 28), the DS (Differentiated Services) field of the received IPv4 header or TC field (traffic class) of IPv6 headers are matched against bits 11:4. Secondly, when UDP port match enable is set (bit 29), the UDP Destination Port of the received UDP frame is matched against bits 27:12. Both UDP and DS/TC matching can be enabled simultaneously or individually. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 1 screening registers is configured in the gem defines file. Up to 16 type 1 screening registers have been allocated APB address space between 0x500 and 0x53C. The bit mappings for these registers are as follows:

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

reserved_31

 

RO

0

30

drop_on_match

 

RW

0

29

udp_port_match_enable

 

RW

0

28

dstc_enable

 

RW

0

27:12

udp_port_match

 

RW

0x0000

11:4

dstc_match

 

RW

0x00

3:0

queue_number

 

RW

0x0

 

gem_gximicrosemi : SCREENING_TYPE_1_REGISTER_3

Address offset

0x050C

Physical address

0x2011 050C

Instance

GEM_A_LO

0x2011 250C

GEM_B_LO

0x2811 050C

GEM_A_HI

0x2811 250C

GEM_B_HI

Description

Screening type 1 registers are used to allocate up to 16 priority queues to received frames based on certain IP or UDP fields of incoming frames. Firstly, when DS/TC match enable is set (bit 28), the DS (Differentiated Services) field of the received IPv4 header or TC field (traffic class) of IPv6 headers are matched against bits 11:4. Secondly, when UDP port match enable is set (bit 29), the UDP Destination Port of the received UDP frame is matched against bits 27:12. Both UDP and DS/TC matching can be enabled simultaneously or individually. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 1 screening registers is configured in the gem defines file. Up to 16 type 1 screening registers have been allocated APB address space between 0x500 and 0x53C. The bit mappings for these registers are as follows:

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

reserved_31

 

RO

0

30

drop_on_match

 

RW

0

29

udp_port_match_enable

 

RW

0

28

dstc_enable

 

RW

0

27:12

udp_port_match

 

RW

0x0000

11:4

dstc_match

 

RW

0x00

3:0

queue_number

 

RW

0x0

 

gem_gximicrosemi : SCREENING_TYPE_1_REGISTER_4

Address offset

0x0510

Physical address

0x2011 0510

Instance

GEM_A_LO

0x2011 2510

GEM_B_LO

0x2811 0510

GEM_A_HI

0x2811 2510

GEM_B_HI

Description

Screening type 1 registers are used to allocate up to 16 priority queues to received frames based on certain IP or UDP fields of incoming frames. Firstly, when DS/TC match enable is set (bit 28), the DS (Differentiated Services) field of the received IPv4 header or TC field (traffic class) of IPv6 headers are matched against bits 11:4. Secondly, when UDP port match enable is set (bit 29), the UDP Destination Port of the received UDP frame is matched against bits 27:12. Both UDP and DS/TC matching can be enabled simultaneously or individually. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 1 screening registers is configured in the gem defines file. Up to 16 type 1 screening registers have been allocated APB address space between 0x500 and 0x53C. The bit mappings for these registers are as follows:

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

reserved_31

 

RO

0

30

drop_on_match

 

RW

0

29

udp_port_match_enable

 

RW

0

28

dstc_enable

 

RW

0

27:12

udp_port_match

 

RW

0x0000

11:4

dstc_match

 

RW

0x00

3:0

queue_number

 

RW

0x0

 

gem_gximicrosemi : SCREENING_TYPE_1_REGISTER_5

Address offset

0x0514

Physical address

0x2011 0514

Instance

GEM_A_LO

0x2011 2514

GEM_B_LO

0x2811 0514

GEM_A_HI

0x2811 2514

GEM_B_HI

Description

Screening type 1 registers are used to allocate up to 16 priority queues to received frames based on certain IP or UDP fields of incoming frames. Firstly, when DS/TC match enable is set (bit 28), the DS (Differentiated Services) field of the received IPv4 header or TC field (traffic class) of IPv6 headers are matched against bits 11:4. Secondly, when UDP port match enable is set (bit 29), the UDP Destination Port of the received UDP frame is matched against bits 27:12. Both UDP and DS/TC matching can be enabled simultaneously or individually. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 1 screening registers is configured in the gem defines file. Up to 16 type 1 screening registers have been allocated APB address space between 0x500 and 0x53C. The bit mappings for these registers are as follows:

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

reserved_31

 

RO

0

30

drop_on_match

 

RW

0

29

udp_port_match_enable

 

RW

0

28

dstc_enable

 

RW

0

27:12

udp_port_match

 

RW

0x0000

11:4

dstc_match

 

RW

0x00

3:0

queue_number

 

RW

0x0

 

gem_gximicrosemi : SCREENING_TYPE_1_REGISTER_6

Address offset

0x0518

Physical address

0x2011 0518

Instance

GEM_A_LO

0x2011 2518

GEM_B_LO

0x2811 0518

GEM_A_HI

0x2811 2518

GEM_B_HI

Description

Screening type 1 registers are used to allocate up to 16 priority queues to received frames based on certain IP or UDP fields of incoming frames. Firstly, when DS/TC match enable is set (bit 28), the DS (Differentiated Services) field of the received IPv4 header or TC field (traffic class) of IPv6 headers are matched against bits 11:4. Secondly, when UDP port match enable is set (bit 29), the UDP Destination Port of the received UDP frame is matched against bits 27:12. Both UDP and DS/TC matching can be enabled simultaneously or individually. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 1 screening registers is configured in the gem defines file. Up to 16 type 1 screening registers have been allocated APB address space between 0x500 and 0x53C. The bit mappings for these registers are as follows:

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

reserved_31

 

RO

0

30

drop_on_match

 

RW

0

29

udp_port_match_enable

 

RW

0

28

dstc_enable

 

RW

0

27:12

udp_port_match

 

RW

0x0000

11:4

dstc_match

 

RW

0x00

3:0

queue_number

 

RW

0x0

 

gem_gximicrosemi : SCREENING_TYPE_1_REGISTER_7

Address offset

0x051C

Physical address

0x2011 051C

Instance

GEM_A_LO

0x2011 251C

GEM_B_LO

0x2811 051C

GEM_A_HI

0x2811 251C

GEM_B_HI

Description

Screening type 1 registers are used to allocate up to 16 priority queues to received frames based on certain IP or UDP fields of incoming frames. Firstly, when DS/TC match enable is set (bit 28), the DS (Differentiated Services) field of the received IPv4 header or TC field (traffic class) of IPv6 headers are matched against bits 11:4. Secondly, when UDP port match enable is set (bit 29), the UDP Destination Port of the received UDP frame is matched against bits 27:12. Both UDP and DS/TC matching can be enabled simultaneously or individually. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 1 screening registers is configured in the gem defines file. Up to 16 type 1 screening registers have been allocated APB address space between 0x500 and 0x53C. The bit mappings for these registers are as follows:

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

reserved_31

 

RO

0

30

drop_on_match

 

RW

0

29

udp_port_match_enable

 

RW

0

28

dstc_enable

 

RW

0

27:12

udp_port_match

 

RW

0x0000

11:4

dstc_match

 

RW

0x00

3:0

queue_number

 

RW

0x0

 

gem_gximicrosemi : SCREENING_TYPE_1_REGISTER_8

Address offset

0x0520

Physical address

0x2011 0520

Instance

GEM_A_LO

0x2011 2520

GEM_B_LO

0x2811 0520

GEM_A_HI

0x2811 2520

GEM_B_HI

Description

Screening type 1 registers are used to allocate up to 16 priority queues to received frames based on certain IP or UDP fields of incoming frames. Firstly, when DS/TC match enable is set (bit 28), the DS (Differentiated Services) field of the received IPv4 header or TC field (traffic class) of IPv6 headers are matched against bits 11:4. Secondly, when UDP port match enable is set (bit 29), the UDP Destination Port of the received UDP frame is matched against bits 27:12. Both UDP and DS/TC matching can be enabled simultaneously or individually. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 1 screening registers is configured in the gem defines file. Up to 16 type 1 screening registers have been allocated APB address space between 0x500 and 0x53C. The bit mappings for these registers are as follows:

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

reserved_31

 

RO

0

30

drop_on_match

 

RW

0

29

udp_port_match_enable

 

RW

0

28

dstc_enable

 

RW

0

27:12

udp_port_match

 

RW

0x0000

11:4

dstc_match

 

RW

0x00

3:0

queue_number

 

RW

0x0

 

gem_gximicrosemi : SCREENING_TYPE_1_REGISTER_9

Address offset

0x0524

Physical address

0x2011 0524

Instance

GEM_A_LO

0x2011 2524

GEM_B_LO

0x2811 0524

GEM_A_HI

0x2811 2524

GEM_B_HI

Description

Screening type 1 registers are used to allocate up to 16 priority queues to received frames based on certain IP or UDP fields of incoming frames. Firstly, when DS/TC match enable is set (bit 28), the DS (Differentiated Services) field of the received IPv4 header or TC field (traffic class) of IPv6 headers are matched against bits 11:4. Secondly, when UDP port match enable is set (bit 29), the UDP Destination Port of the received UDP frame is matched against bits 27:12. Both UDP and DS/TC matching can be enabled simultaneously or individually. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 1 screening registers is configured in the gem defines file. Up to 16 type 1 screening registers have been allocated APB address space between 0x500 and 0x53C. The bit mappings for these registers are as follows:

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

reserved_31

 

RO

0

30

drop_on_match

 

RW

0

29

udp_port_match_enable

 

RW

0

28

dstc_enable

 

RW

0

27:12

udp_port_match

 

RW

0x0000

11:4

dstc_match

 

RW

0x00

3:0

queue_number

 

RW

0x0

 

gem_gximicrosemi : SCREENING_TYPE_1_REGISTER_10

Address offset

0x0528

Physical address

0x2011 0528

Instance

GEM_A_LO

0x2011 2528

GEM_B_LO

0x2811 0528

GEM_A_HI

0x2811 2528

GEM_B_HI

Description

Screening type 1 registers are used to allocate up to 16 priority queues to received frames based on certain IP or UDP fields of incoming frames. Firstly, when DS/TC match enable is set (bit 28), the DS (Differentiated Services) field of the received IPv4 header or TC field (traffic class) of IPv6 headers are matched against bits 11:4. Secondly, when UDP port match enable is set (bit 29), the UDP Destination Port of the received UDP frame is matched against bits 27:12. Both UDP and DS/TC matching can be enabled simultaneously or individually. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 1 screening registers is configured in the gem defines file. Up to 16 type 1 screening registers have been allocated APB address space between 0x500 and 0x53C. The bit mappings for these registers are as follows:

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

reserved_31

 

RO

0

30

drop_on_match

 

RW

0

29

udp_port_match_enable

 

RW

0

28

dstc_enable

 

RW

0

27:12

udp_port_match

 

RW

0x0000

11:4

dstc_match

 

RW

0x00

3:0

queue_number

 

RW

0x0

 

gem_gximicrosemi : SCREENING_TYPE_1_REGISTER_11

Address offset

0x052C

Physical address

0x2011 052C

Instance

GEM_A_LO

0x2011 252C

GEM_B_LO

0x2811 052C

GEM_A_HI

0x2811 252C

GEM_B_HI

Description

Screening type 1 registers are used to allocate up to 16 priority queues to received frames based on certain IP or UDP fields of incoming frames. Firstly, when DS/TC match enable is set (bit 28), the DS (Differentiated Services) field of the received IPv4 header or TC field (traffic class) of IPv6 headers are matched against bits 11:4. Secondly, when UDP port match enable is set (bit 29), the UDP Destination Port of the received UDP frame is matched against bits 27:12. Both UDP and DS/TC matching can be enabled simultaneously or individually. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 1 screening registers is configured in the gem defines file. Up to 16 type 1 screening registers have been allocated APB address space between 0x500 and 0x53C. The bit mappings for these registers are as follows:

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

reserved_31

 

RO

0

30

drop_on_match

 

RW

0

29

udp_port_match_enable

 

RW

0

28

dstc_enable

 

RW

0

27:12

udp_port_match

 

RW

0x0000

11:4

dstc_match

 

RW

0x00

3:0

queue_number

 

RW

0x0

 

gem_gximicrosemi : SCREENING_TYPE_1_REGISTER_12

Address offset

0x0530

Physical address

0x2011 0530

Instance

GEM_A_LO

0x2011 2530

GEM_B_LO

0x2811 0530

GEM_A_HI

0x2811 2530

GEM_B_HI

Description

Screening type 1 registers are used to allocate up to 16 priority queues to received frames based on certain IP or UDP fields of incoming frames. Firstly, when DS/TC match enable is set (bit 28), the DS (Differentiated Services) field of the received IPv4 header or TC field (traffic class) of IPv6 headers are matched against bits 11:4. Secondly, when UDP port match enable is set (bit 29), the UDP Destination Port of the received UDP frame is matched against bits 27:12. Both UDP and DS/TC matching can be enabled simultaneously or individually. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 1 screening registers is configured in the gem defines file. Up to 16 type 1 screening registers have been allocated APB address space between 0x500 and 0x53C. The bit mappings for these registers are as follows:

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

reserved_31

 

RO

0

30

drop_on_match

 

RW

0

29

udp_port_match_enable

 

RW

0

28

dstc_enable

 

RW

0

27:12

udp_port_match

 

RW

0x0000

11:4

dstc_match

 

RW

0x00

3:0

queue_number

 

RW

0x0

 

gem_gximicrosemi : SCREENING_TYPE_1_REGISTER_13

Address offset

0x0534

Physical address

0x2011 0534

Instance

GEM_A_LO

0x2011 2534

GEM_B_LO

0x2811 0534

GEM_A_HI

0x2811 2534

GEM_B_HI

Description

Screening type 1 registers are used to allocate up to 16 priority queues to received frames based on certain IP or UDP fields of incoming frames. Firstly, when DS/TC match enable is set (bit 28), the DS (Differentiated Services) field of the received IPv4 header or TC field (traffic class) of IPv6 headers are matched against bits 11:4. Secondly, when UDP port match enable is set (bit 29), the UDP Destination Port of the received UDP frame is matched against bits 27:12. Both UDP and DS/TC matching can be enabled simultaneously or individually. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 1 screening registers is configured in the gem defines file. Up to 16 type 1 screening registers have been allocated APB address space between 0x500 and 0x53C. The bit mappings for these registers are as follows:

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

reserved_31

 

RO

0

30

drop_on_match

 

RW

0

29

udp_port_match_enable

 

RW

0

28

dstc_enable

 

RW

0

27:12

udp_port_match

 

RW

0x0000

11:4

dstc_match

 

RW

0x00

3:0

queue_number

 

RW

0x0

 

gem_gximicrosemi : SCREENING_TYPE_1_REGISTER_14

Address offset

0x0538

Physical address

0x2011 0538

Instance

GEM_A_LO

0x2011 2538

GEM_B_LO

0x2811 0538

GEM_A_HI

0x2811 2538

GEM_B_HI

Description

Screening type 1 registers are used to allocate up to 16 priority queues to received frames based on certain IP or UDP fields of incoming frames. Firstly, when DS/TC match enable is set (bit 28), the DS (Differentiated Services) field of the received IPv4 header or TC field (traffic class) of IPv6 headers are matched against bits 11:4. Secondly, when UDP port match enable is set (bit 29), the UDP Destination Port of the received UDP frame is matched against bits 27:12. Both UDP and DS/TC matching can be enabled simultaneously or individually. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 1 screening registers is configured in the gem defines file. Up to 16 type 1 screening registers have been allocated APB address space between 0x500 and 0x53C. The bit mappings for these registers are as follows:

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

reserved_31

 

RO

0

30

drop_on_match

 

RW

0

29

udp_port_match_enable

 

RW

0

28

dstc_enable

 

RW

0

27:12

udp_port_match

 

RW

0x0000

11:4

dstc_match

 

RW

0x00

3:0

queue_number

 

RW

0x0

 

gem_gximicrosemi : SCREENING_TYPE_1_REGISTER_15

Address offset

0x053C

Physical address

0x2011 053C

Instance

GEM_A_LO

0x2011 253C

GEM_B_LO

0x2811 053C

GEM_A_HI

0x2811 253C

GEM_B_HI

Description

Screening type 1 registers are used to allocate up to 16 priority queues to received frames based on certain IP or UDP fields of incoming frames. Firstly, when DS/TC match enable is set (bit 28), the DS (Differentiated Services) field of the received IPv4 header or TC field (traffic class) of IPv6 headers are matched against bits 11:4. Secondly, when UDP port match enable is set (bit 29), the UDP Destination Port of the received UDP frame is matched against bits 27:12. Both UDP and DS/TC matching can be enabled simultaneously or individually. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 1 screening registers is configured in the gem defines file. Up to 16 type 1 screening registers have been allocated APB address space between 0x500 and 0x53C. The bit mappings for these registers are as follows:

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

reserved_31

 

RO

0

30

drop_on_match

 

RW

0

29

udp_port_match_enable

 

RW

0

28

dstc_enable

 

RW

0

27:12

udp_port_match

 

RW

0x0000

11:4

dstc_match

 

RW

0x00

3:0

queue_number

 

RW

0x0

 

gem_gximicrosemi : SCREENING_TYPE_2_REGISTER_0

Address offset

0x0540

Physical address

0x2011 0540

Instance

GEM_A_LO

0x2011 2540

GEM_B_LO

0x2811 0540

GEM_A_HI

0x2811 2540

GEM_B_HI

Description

Screener Type 2 match registers allow a screen to be configured that is the combination of all or any of the following comparisons:, :1) An enabled VLAN Priority. A VLAN Priority match will be performed if the VLAN priority enable is set. The extracted priority field in the VLAN header is compared against 3 bits within the screener type 2 register itself., :2) An enabled EtherType., :3) An enabled Field Compare A. , :4) An enabled Field Compare B. , :5) An enabled Field Compare C. , :All enabled comparisons are ANDed together to form the overall type 2 screener match. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 2 screening registers is configured in the gem defines file. Up to 16 type 2 screening registers have been allocated APB address space between 0x540 and 0x57C. The bit mappings for these registers are as follows:

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

drop_on_match

 

RW

0

30

compare_c_enable

 

RW

0

29:25

compare_c

 

RW

0x00

24

compare_b_enable

 

RW

0

23:19

compare_b

 

RW

0x00

18

compare_a_enable

 

RW

0

17:13

compare_a

 

RW

0x00

12

ethertype_enable

 

RW

0

11:9

ethertype_reg_index

 

RW

0x0

8

vlan_enable

 

RW

0

7

reserved_7

 

RW

0

6:4

vlan_priority

 

RW

0x0

3:0

queue_number

 

RW

0x0

 

gem_gximicrosemi : SCREENING_TYPE_2_REGISTER_1

Address offset

0x0544

Physical address

0x2011 0544

Instance

GEM_A_LO

0x2011 2544

GEM_B_LO

0x2811 0544

GEM_A_HI

0x2811 2544

GEM_B_HI

Description

Screener Type 2 match registers allow a screen to be configured that is the combination of all or any of the following comparisons:, :1) An enabled VLAN Priority. A VLAN Priority match will be performed if the VLAN priority enable is set. The extracted priority field in the VLAN header is compared against 3 bits within the screener type 2 register itself., :2) An enabled EtherType., :3) An enabled Field Compare A. , :4) An enabled Field Compare B. , :5) An enabled Field Compare C. , :All enabled comparisons are ANDed together to form the overall type 2 screener match. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 2 screening registers is configured in the gem defines file. Up to 16 type 2 screening registers have been allocated APB address space between 0x540 and 0x57C. The bit mappings for these registers are as follows:

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

drop_on_match

 

RW

0

30

compare_c_enable

 

RW

0

29:25

compare_c

 

RW

0x00

24

compare_b_enable

 

RW

0

23:19

compare_b

 

RW

0x00

18

compare_a_enable

 

RW

0

17:13

compare_a

 

RW

0x00

12

ethertype_enable

 

RW

0

11:9

ethertype_reg_index

 

RW

0x0

8

vlan_enable

 

RW

0

7

reserved_7

 

RW

0

6:4

vlan_priority

 

RW

0x0

3:0

queue_number

 

RW

0x0

 

gem_gximicrosemi : SCREENING_TYPE_2_REGISTER_2

Address offset

0x0548

Physical address

0x2011 0548

Instance

GEM_A_LO

0x2011 2548

GEM_B_LO

0x2811 0548

GEM_A_HI

0x2811 2548

GEM_B_HI

Description

Screener Type 2 match registers allow a screen to be configured that is the combination of all or any of the following comparisons:, :1) An enabled VLAN Priority. A VLAN Priority match will be performed if the VLAN priority enable is set. The extracted priority field in the VLAN header is compared against 3 bits within the screener type 2 register itself., :2) An enabled EtherType., :3) An enabled Field Compare A. , :4) An enabled Field Compare B. , :5) An enabled Field Compare C. , :All enabled comparisons are ANDed together to form the overall type 2 screener match. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 2 screening registers is configured in the gem defines file. Up to 16 type 2 screening registers have been allocated APB address space between 0x540 and 0x57C. The bit mappings for these registers are as follows:

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

drop_on_match

 

RW

0

30

compare_c_enable

 

RW

0

29:25

compare_c

 

RW

0x00

24

compare_b_enable

 

RW

0

23:19

compare_b

 

RW

0x00

18

compare_a_enable

 

RW

0

17:13

compare_a

 

RW

0x00

12

ethertype_enable

 

RW

0

11:9

ethertype_reg_index

 

RW

0x0

8

vlan_enable

 

RW

0

7

reserved_7

 

RW

0

6:4

vlan_priority

 

RW

0x0

3:0

queue_number

 

RW

0x0

 

gem_gximicrosemi : SCREENING_TYPE_2_REGISTER_3

Address offset

0x054C

Physical address

0x2011 054C

Instance

GEM_A_LO

0x2011 254C

GEM_B_LO

0x2811 054C

GEM_A_HI

0x2811 254C

GEM_B_HI

Description

Screener Type 2 match registers allow a screen to be configured that is the combination of all or any of the following comparisons:, :1) An enabled VLAN Priority. A VLAN Priority match will be performed if the VLAN priority enable is set. The extracted priority field in the VLAN header is compared against 3 bits within the screener type 2 register itself., :2) An enabled EtherType., :3) An enabled Field Compare A. , :4) An enabled Field Compare B. , :5) An enabled Field Compare C. , :All enabled comparisons are ANDed together to form the overall type 2 screener match. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 2 screening registers is configured in the gem defines file. Up to 16 type 2 screening registers have been allocated APB address space between 0x540 and 0x57C. The bit mappings for these registers are as follows:

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

drop_on_match

 

RW

0

30

compare_c_enable

 

RW

0

29:25

compare_c

 

RW

0x00

24

compare_b_enable

 

RW

0

23:19

compare_b

 

RW

0x00

18

compare_a_enable

 

RW

0

17:13

compare_a

 

RW

0x00

12

ethertype_enable

 

RW

0

11:9

ethertype_reg_index

 

RW

0x0

8

vlan_enable

 

RW

0

7

reserved_7

 

RW

0

6:4

vlan_priority

 

RW

0x0

3:0

queue_number

 

RW

0x0

 

gem_gximicrosemi : SCREENING_TYPE_2_REGISTER_4

Address offset

0x0550

Physical address

0x2011 0550

Instance

GEM_A_LO

0x2011 2550

GEM_B_LO

0x2811 0550

GEM_A_HI

0x2811 2550

GEM_B_HI

Description

Screener Type 2 match registers allow a screen to be configured that is the combination of all or any of the following comparisons:, :1) An enabled VLAN Priority. A VLAN Priority match will be performed if the VLAN priority enable is set. The extracted priority field in the VLAN header is compared against 3 bits within the screener type 2 register itself., :2) An enabled EtherType., :3) An enabled Field Compare A. , :4) An enabled Field Compare B. , :5) An enabled Field Compare C. , :All enabled comparisons are ANDed together to form the overall type 2 screener match. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 2 screening registers is configured in the gem defines file. Up to 16 type 2 screening registers have been allocated APB address space between 0x540 and 0x57C. The bit mappings for these registers are as follows:

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

drop_on_match

 

RW

0

30

compare_c_enable

 

RW

0

29:25

compare_c

 

RW

0x00

24

compare_b_enable

 

RW

0

23:19

compare_b

 

RW

0x00

18

compare_a_enable

 

RW

0

17:13

compare_a

 

RW

0x00

12

ethertype_enable

 

RW

0

11:9

ethertype_reg_index

 

RW

0x0

8

vlan_enable

 

RW

0

7

reserved_7

 

RW

0

6:4

vlan_priority

 

RW

0x0

3:0

queue_number

 

RW

0x0

 

gem_gximicrosemi : SCREENING_TYPE_2_REGISTER_5

Address offset

0x0554

Physical address

0x2011 0554

Instance

GEM_A_LO

0x2011 2554

GEM_B_LO

0x2811 0554

GEM_A_HI

0x2811 2554

GEM_B_HI

Description

Screener Type 2 match registers allow a screen to be configured that is the combination of all or any of the following comparisons:, :1) An enabled VLAN Priority. A VLAN Priority match will be performed if the VLAN priority enable is set. The extracted priority field in the VLAN header is compared against 3 bits within the screener type 2 register itself., :2) An enabled EtherType., :3) An enabled Field Compare A. , :4) An enabled Field Compare B. , :5) An enabled Field Compare C. , :All enabled comparisons are ANDed together to form the overall type 2 screener match. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 2 screening registers is configured in the gem defines file. Up to 16 type 2 screening registers have been allocated APB address space between 0x540 and 0x57C. The bit mappings for these registers are as follows:

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

drop_on_match

 

RW

0

30

compare_c_enable

 

RW

0

29:25

compare_c

 

RW

0x00

24

compare_b_enable

 

RW

0

23:19

compare_b

 

RW

0x00

18

compare_a_enable

 

RW

0

17:13

compare_a

 

RW

0x00

12

ethertype_enable

 

RW

0

11:9

ethertype_reg_index

 

RW

0x0

8

vlan_enable

 

RW

0

7

reserved_7

 

RW

0

6:4

vlan_priority

 

RW

0x0

3:0

queue_number

 

RW

0x0

 

gem_gximicrosemi : SCREENING_TYPE_2_REGISTER_6

Address offset

0x0558

Physical address

0x2011 0558

Instance

GEM_A_LO

0x2011 2558

GEM_B_LO

0x2811 0558

GEM_A_HI

0x2811 2558

GEM_B_HI

Description

Screener Type 2 match registers allow a screen to be configured that is the combination of all or any of the following comparisons:, :1) An enabled VLAN Priority. A VLAN Priority match will be performed if the VLAN priority enable is set. The extracted priority field in the VLAN header is compared against 3 bits within the screener type 2 register itself., :2) An enabled EtherType., :3) An enabled Field Compare A. , :4) An enabled Field Compare B. , :5) An enabled Field Compare C. , :All enabled comparisons are ANDed together to form the overall type 2 screener match. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 2 screening registers is configured in the gem defines file. Up to 16 type 2 screening registers have been allocated APB address space between 0x540 and 0x57C. The bit mappings for these registers are as follows:

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

drop_on_match

 

RW

0

30

compare_c_enable

 

RW

0

29:25

compare_c

 

RW

0x00

24

compare_b_enable

 

RW

0

23:19

compare_b

 

RW

0x00

18

compare_a_enable

 

RW

0

17:13

compare_a

 

RW

0x00

12

ethertype_enable

 

RW

0

11:9

ethertype_reg_index

 

RW

0x0

8

vlan_enable

 

RW

0

7

reserved_7

 

RW

0

6:4

vlan_priority

 

RW

0x0

3:0

queue_number

 

RW

0x0

 

gem_gximicrosemi : SCREENING_TYPE_2_REGISTER_7

Address offset

0x055C

Physical address

0x2011 055C

Instance

GEM_A_LO

0x2011 255C

GEM_B_LO

0x2811 055C

GEM_A_HI

0x2811 255C

GEM_B_HI

Description

Screener Type 2 match registers allow a screen to be configured that is the combination of all or any of the following comparisons:, :1) An enabled VLAN Priority. A VLAN Priority match will be performed if the VLAN priority enable is set. The extracted priority field in the VLAN header is compared against 3 bits within the screener type 2 register itself., :2) An enabled EtherType., :3) An enabled Field Compare A. , :4) An enabled Field Compare B. , :5) An enabled Field Compare C. , :All enabled comparisons are ANDed together to form the overall type 2 screener match. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 2 screening registers is configured in the gem defines file. Up to 16 type 2 screening registers have been allocated APB address space between 0x540 and 0x57C. The bit mappings for these registers are as follows:

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

drop_on_match

 

RW

0

30

compare_c_enable

 

RW

0

29:25

compare_c

 

RW

0x00

24

compare_b_enable

 

RW

0

23:19

compare_b

 

RW

0x00

18

compare_a_enable

 

RW

0

17:13

compare_a

 

RW

0x00

12

ethertype_enable

 

RW

0

11:9

ethertype_reg_index

 

RW

0x0

8

vlan_enable

 

RW

0

7

reserved_7

 

RW

0

6:4

vlan_priority

 

RW

0x0

3:0

queue_number

 

RW

0x0

 

gem_gximicrosemi : SCREENING_TYPE_2_REGISTER_8

Address offset

0x0560

Physical address

0x2011 0560

Instance

GEM_A_LO

0x2011 2560

GEM_B_LO

0x2811 0560

GEM_A_HI

0x2811 2560

GEM_B_HI

Description

Screener Type 2 match registers allow a screen to be configured that is the combination of all or any of the following comparisons:, :1) An enabled VLAN Priority. A VLAN Priority match will be performed if the VLAN priority enable is set. The extracted priority field in the VLAN header is compared against 3 bits within the screener type 2 register itself., :2) An enabled EtherType., :3) An enabled Field Compare A. , :4) An enabled Field Compare B. , :5) An enabled Field Compare C. , :All enabled comparisons are ANDed together to form the overall type 2 screener match. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 2 screening registers is configured in the gem defines file. Up to 16 type 2 screening registers have been allocated APB address space between 0x540 and 0x57C. The bit mappings for these registers are as follows:

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

drop_on_match

 

RW

0

30

compare_c_enable

 

RW

0

29:25

compare_c

 

RW

0x00

24

compare_b_enable

 

RW

0

23:19

compare_b

 

RW

0x00

18

compare_a_enable

 

RW

0

17:13

compare_a

 

RW

0x00

12

ethertype_enable

 

RW

0

11:9

ethertype_reg_index

 

RW

0x0

8

vlan_enable

 

RW

0

7

reserved_7

 

RW

0

6:4

vlan_priority

 

RW

0x0

3:0

queue_number

 

RW

0x0

 

gem_gximicrosemi : SCREENING_TYPE_2_REGISTER_9

Address offset

0x0564

Physical address

0x2011 0564

Instance

GEM_A_LO

0x2011 2564

GEM_B_LO

0x2811 0564

GEM_A_HI

0x2811 2564

GEM_B_HI

Description

Screener Type 2 match registers allow a screen to be configured that is the combination of all or any of the following comparisons:, :1) An enabled VLAN Priority. A VLAN Priority match will be performed if the VLAN priority enable is set. The extracted priority field in the VLAN header is compared against 3 bits within the screener type 2 register itself., :2) An enabled EtherType., :3) An enabled Field Compare A. , :4) An enabled Field Compare B. , :5) An enabled Field Compare C. , :All enabled comparisons are ANDed together to form the overall type 2 screener match. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 2 screening registers is configured in the gem defines file. Up to 16 type 2 screening registers have been allocated APB address space between 0x540 and 0x57C. The bit mappings for these registers are as follows:

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

drop_on_match

 

RW

0

30

compare_c_enable

 

RW

0

29:25

compare_c

 

RW

0x00

24

compare_b_enable

 

RW

0

23:19

compare_b

 

RW

0x00

18

compare_a_enable

 

RW

0

17:13

compare_a

 

RW

0x00

12

ethertype_enable

 

RW

0

11:9

ethertype_reg_index

 

RW

0x0

8

vlan_enable

 

RW

0

7

reserved_7

 

RW

0

6:4

vlan_priority

 

RW

0x0

3:0

queue_number

 

RW

0x0

 

gem_gximicrosemi : SCREENING_TYPE_2_REGISTER_10

Address offset

0x0568

Physical address

0x2011 0568

Instance

GEM_A_LO

0x2011 2568

GEM_B_LO

0x2811 0568

GEM_A_HI

0x2811 2568

GEM_B_HI

Description

Screener Type 2 match registers allow a screen to be configured that is the combination of all or any of the following comparisons:, :1) An enabled VLAN Priority. A VLAN Priority match will be performed if the VLAN priority enable is set. The extracted priority field in the VLAN header is compared against 3 bits within the screener type 2 register itself., :2) An enabled EtherType., :3) An enabled Field Compare A. , :4) An enabled Field Compare B. , :5) An enabled Field Compare C. , :All enabled comparisons are ANDed together to form the overall type 2 screener match. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 2 screening registers is configured in the gem defines file. Up to 16 type 2 screening registers have been allocated APB address space between 0x540 and 0x57C. The bit mappings for these registers are as follows:

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

drop_on_match

 

RW

0

30

compare_c_enable

 

RW

0

29:25

compare_c

 

RW

0x00

24

compare_b_enable

 

RW

0

23:19

compare_b

 

RW

0x00

18

compare_a_enable

 

RW

0

17:13

compare_a

 

RW

0x00

12

ethertype_enable

 

RW

0

11:9

ethertype_reg_index

 

RW

0x0

8

vlan_enable

 

RW

0

7

reserved_7

 

RW

0

6:4

vlan_priority

 

RW

0x0

3:0

queue_number

 

RW

0x0

 

gem_gximicrosemi : SCREENING_TYPE_2_REGISTER_11

Address offset

0x056C

Physical address

0x2011 056C

Instance

GEM_A_LO

0x2011 256C

GEM_B_LO

0x2811 056C

GEM_A_HI

0x2811 256C

GEM_B_HI

Description

Screener Type 2 match registers allow a screen to be configured that is the combination of all or any of the following comparisons:, :1) An enabled VLAN Priority. A VLAN Priority match will be performed if the VLAN priority enable is set. The extracted priority field in the VLAN header is compared against 3 bits within the screener type 2 register itself., :2) An enabled EtherType., :3) An enabled Field Compare A. , :4) An enabled Field Compare B. , :5) An enabled Field Compare C. , :All enabled comparisons are ANDed together to form the overall type 2 screener match. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 2 screening registers is configured in the gem defines file. Up to 16 type 2 screening registers have been allocated APB address space between 0x540 and 0x57C. The bit mappings for these registers are as follows:

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

drop_on_match

 

RW

0

30

compare_c_enable

 

RW

0

29:25

compare_c

 

RW

0x00

24

compare_b_enable

 

RW

0

23:19

compare_b

 

RW

0x00

18

compare_a_enable

 

RW

0

17:13

compare_a

 

RW

0x00

12

ethertype_enable

 

RW

0

11:9

ethertype_reg_index

 

RW

0x0

8

vlan_enable

 

RW

0

7

reserved_7

 

RW

0

6:4

vlan_priority

 

RW

0x0

3:0

queue_number

 

RW

0x0

 

gem_gximicrosemi : SCREENING_TYPE_2_REGISTER_12

Address offset

0x0570

Physical address

0x2011 0570

Instance

GEM_A_LO

0x2011 2570

GEM_B_LO

0x2811 0570

GEM_A_HI

0x2811 2570

GEM_B_HI

Description

Screener Type 2 match registers allow a screen to be configured that is the combination of all or any of the following comparisons:, :1) An enabled VLAN Priority. A VLAN Priority match will be performed if the VLAN priority enable is set. The extracted priority field in the VLAN header is compared against 3 bits within the screener type 2 register itself., :2) An enabled EtherType., :3) An enabled Field Compare A. , :4) An enabled Field Compare B. , :5) An enabled Field Compare C. , :All enabled comparisons are ANDed together to form the overall type 2 screener match. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 2 screening registers is configured in the gem defines file. Up to 16 type 2 screening registers have been allocated APB address space between 0x540 and 0x57C. The bit mappings for these registers are as follows:

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

drop_on_match

 

RW

0

30

compare_c_enable

 

RW

0

29:25

compare_c

 

RW

0x00

24

compare_b_enable

 

RW

0

23:19

compare_b

 

RW

0x00

18

compare_a_enable

 

RW

0

17:13

compare_a

 

RW

0x00

12

ethertype_enable

 

RW

0

11:9

ethertype_reg_index

 

RW

0x0

8

vlan_enable

 

RW

0

7

reserved_7

 

RW

0

6:4

vlan_priority

 

RW

0x0

3:0

queue_number

 

RW

0x0

 

gem_gximicrosemi : SCREENING_TYPE_2_REGISTER_13

Address offset

0x0574

Physical address

0x2011 0574

Instance

GEM_A_LO

0x2011 2574

GEM_B_LO

0x2811 0574

GEM_A_HI

0x2811 2574

GEM_B_HI

Description

Screener Type 2 match registers allow a screen to be configured that is the combination of all or any of the following comparisons:, :1) An enabled VLAN Priority. A VLAN Priority match will be performed if the VLAN priority enable is set. The extracted priority field in the VLAN header is compared against 3 bits within the screener type 2 register itself., :2) An enabled EtherType., :3) An enabled Field Compare A. , :4) An enabled Field Compare B. , :5) An enabled Field Compare C. , :All enabled comparisons are ANDed together to form the overall type 2 screener match. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 2 screening registers is configured in the gem defines file. Up to 16 type 2 screening registers have been allocated APB address space between 0x540 and 0x57C. The bit mappings for these registers are as follows:

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

drop_on_match

 

RW

0

30

compare_c_enable

 

RW

0

29:25

compare_c

 

RW

0x00

24

compare_b_enable

 

RW

0

23:19

compare_b

 

RW

0x00

18

compare_a_enable

 

RW

0

17:13

compare_a

 

RW

0x00

12

ethertype_enable

 

RW

0

11:9

ethertype_reg_index

 

RW

0x0

8

vlan_enable

 

RW

0

7

reserved_7

 

RW

0

6:4

vlan_priority

 

RW

0x0

3:0

queue_number

 

RW

0x0

 

gem_gximicrosemi : SCREENING_TYPE_2_REGISTER_14

Address offset

0x0578

Physical address

0x2011 0578

Instance

GEM_A_LO

0x2011 2578

GEM_B_LO

0x2811 0578

GEM_A_HI

0x2811 2578

GEM_B_HI

Description

Screener Type 2 match registers allow a screen to be configured that is the combination of all or any of the following comparisons:, :1) An enabled VLAN Priority. A VLAN Priority match will be performed if the VLAN priority enable is set. The extracted priority field in the VLAN header is compared against 3 bits within the screener type 2 register itself., :2) An enabled EtherType., :3) An enabled Field Compare A. , :4) An enabled Field Compare B. , :5) An enabled Field Compare C. , :All enabled comparisons are ANDed together to form the overall type 2 screener match. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 2 screening registers is configured in the gem defines file. Up to 16 type 2 screening registers have been allocated APB address space between 0x540 and 0x57C. The bit mappings for these registers are as follows:

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

drop_on_match

 

RW

0

30

compare_c_enable

 

RW

0

29:25

compare_c

 

RW

0x00

24

compare_b_enable

 

RW

0

23:19

compare_b

 

RW

0x00

18

compare_a_enable

 

RW

0

17:13

compare_a

 

RW

0x00

12

ethertype_enable

 

RW

0

11:9

ethertype_reg_index

 

RW

0x0

8

vlan_enable

 

RW

0

7

reserved_7

 

RW

0

6:4

vlan_priority

 

RW

0x0

3:0

queue_number

 

RW

0x0

 

gem_gximicrosemi : SCREENING_TYPE_2_REGISTER_15

Address offset

0x057C

Physical address

0x2011 057C

Instance

GEM_A_LO

0x2011 257C

GEM_B_LO

0x2811 057C

GEM_A_HI

0x2811 257C

GEM_B_HI

Description

Screener Type 2 match registers allow a screen to be configured that is the combination of all or any of the following comparisons:, :1) An enabled VLAN Priority. A VLAN Priority match will be performed if the VLAN priority enable is set. The extracted priority field in the VLAN header is compared against 3 bits within the screener type 2 register itself., :2) An enabled EtherType., :3) An enabled Field Compare A. , :4) An enabled Field Compare B. , :5) An enabled Field Compare C. , :All enabled comparisons are ANDed together to form the overall type 2 screener match. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 2 screening registers is configured in the gem defines file. Up to 16 type 2 screening registers have been allocated APB address space between 0x540 and 0x57C. The bit mappings for these registers are as follows:

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

drop_on_match

 

RW

0

30

compare_c_enable

 

RW

0

29:25

compare_c

 

RW

0x00

24

compare_b_enable

 

RW

0

23:19

compare_b

 

RW

0x00

18

compare_a_enable

 

RW

0

17:13

compare_a

 

RW

0x00

12

ethertype_enable

 

RW

0

11:9

ethertype_reg_index

 

RW

0x0

8

vlan_enable

 

RW

0

7

reserved_7

 

RW

0

6:4

vlan_priority

 

RW

0x0

3:0

queue_number

 

RW

0x0

 

gem_gximicrosemi : TX_SCHED_CTRL

Address offset

0x0580

Physical address

0x2011 0580

Instance

GEM_A_LO

0x2011 2580

GEM_B_LO

0x2811 0580

GEM_A_HI

0x2811 2580

GEM_B_HI

Description

This register controls the transmit scheduling algorithm the user can select for each active transmit queue. By default all queues are initialized to fixed priority, with the top indexed queue having overall priority.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:30

tx_sched_q15

 

RW

0x0

29:28

tx_sched_q14

 

RW

0x0

27:26

tx_sched_q13

 

RW

0x0

25:24

tx_sched_q12

 

RW

0x0

23:22

tx_sched_q11

 

RW

0x0

21:20

tx_sched_q10

 

RW

0x0

19:18

tx_sched_q9

 

RW

0x0

17:16

tx_sched_q8

 

RW

0x0

15:14

tx_sched_q7

 

RW

0x0

13:12

tx_sched_q6

 

RW

0x0

11:10

tx_sched_q5

 

RW

0x0

9:8

tx_sched_q4

 

RW

0x0

7:6

tx_sched_q3

 

RW

0x0

5:4

tx_sched_q2

 

RW

0x0

3:2

tx_sched_q1

 

RW

0x0

1:0

tx_sched_q0

 

RW

0x0

 

gem_gximicrosemi : BW_RATE_LIMIT_Q0TO3

Address offset

0x0590

Physical address

0x2011 0590

Instance

GEM_A_LO

0x2011 2590

GEM_B_LO

0x2811 0590

GEM_A_HI

0x2811 2590

GEM_B_HI

Description

This register holds the DWRR weighting value or the ETS bandwidth percentage value used by the transmit scheduler for queues 0 to 3.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:24

dwrr_ets_weight_q3

 

RW

0x00

23:16

dwrr_ets_weight_q2

 

RW

0x00

15:8

dwrr_ets_weight_q1

 

RW

0x00

7:0

dwrr_ets_weight_q0

 

RW

0x00

 

gem_gximicrosemi : BW_RATE_LIMIT_Q4TO7

Address offset

0x0594

Physical address

0x2011 0594

Instance

GEM_A_LO

0x2011 2594

GEM_B_LO

0x2811 0594

GEM_A_HI

0x2811 2594

GEM_B_HI

Description

This register holds the DWRR weighting value or the ETS bandwidth percentage value used by the transmit scheduler for queues 4 to 7.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:24

dwrr_ets_weight_q7

 

RW

0x00

23:16

dwrr_ets_weight_q6

 

RW

0x00

15:8

dwrr_ets_weight_q5

 

RW

0x00

7:0

dwrr_ets_weight_q4

 

RW

0x00

 

gem_gximicrosemi : BW_RATE_LIMIT_Q8TO11

Address offset

0x0598

Physical address

0x2011 0598

Instance

GEM_A_LO

0x2011 2598

GEM_B_LO

0x2811 0598

GEM_A_HI

0x2811 2598

GEM_B_HI

Description

This register holds the DWRR weighting value or the ETS bandwidth percentage value used by the transmit scheduler for queues 8 to 11.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:24

dwrr_ets_weight_q11

 

RW

0x00

23:16

dwrr_ets_weight_q10

 

RW

0x00

15:8

dwrr_ets_weight_q9

 

RW

0x00

7:0

dwrr_ets_weight_q8

 

RW

0x00

 

gem_gximicrosemi : BW_RATE_LIMIT_Q12TO15

Address offset

0x059C

Physical address

0x2011 059C

Instance

GEM_A_LO

0x2011 259C

GEM_B_LO

0x2811 059C

GEM_A_HI

0x2811 259C

GEM_B_HI

Description

This register holds the DWRR weighting value or the ETS bandwidth percentage value used by the transmit scheduler for queues 12 to 15.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:24

dwrr_ets_weight_q15

 

RW

0x00

23:16

dwrr_ets_weight_q14

 

RW

0x00

15:8

dwrr_ets_weight_q13

 

RW

0x00

7:0

dwrr_ets_weight_q12

 

RW

0x00

 

gem_gximicrosemi : TX_Q_SEG_ALLOC_Q_LOWER

Address offset

0x05A0

Physical address

0x2011 05A0

Instance

GEM_A_LO

0x2011 25A0

GEM_B_LO

0x2811 05A0

GEM_A_HI

0x2811 25A0

GEM_B_HI

Description

This register allows the user to distribute the Transmit SRAM used by the DMA across the priority queues, for queues 0 to 7. The SRAM itself is split into a number of evenly sized segments (this is defined in the verilog configuration defs file - for the configuration used to generate this register description, the total number of segments was set to '16'). Those segments can then be freely distributed across the active queues, in powers of 2. I.e. a value of 0 would mean 1 segment has been allocated to the queue. A value of 1 would mean 2 segments, a value of 2 means 4 segments and so on. The reset values of these registers are defined in the configuration defs file.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

reserved_31_31

 

RO

0

30:28

segment_alloc_q7

 

RW

0x0

27

reserved_27_27

 

RO

0

26:24

segment_alloc_q6

 

RW

0x0

23

reserved_23_23

 

RO

0

22:20

segment_alloc_q5

 

RW

0x0

19

reserved_19_19

 

RO

0

18:16

segment_alloc_q4

 

RW

0x0

15

reserved_15_15

 

RO

0

14:12

segment_alloc_q3

 

RW

0x0

11

reserved_11_11

 

RO

0

10:8

segment_alloc_q2

 

RW

0x0

7

reserved_7_7

 

RO

0

6:4

segment_alloc_q1

 

RW

0x0

3

reserved_3_3

 

RO

0

2:0

segment_alloc_q0

 

RW

0x0

 

gem_gximicrosemi : TX_Q_SEG_ALLOC_Q_UPPER

Address offset

0x05A4

Physical address

0x2011 05A4

Instance

GEM_A_LO

0x2011 25A4

GEM_B_LO

0x2811 05A4

GEM_A_HI

0x2811 25A4

GEM_B_HI

Description

This register allows the user to distribute the Transmit SRAM used by the DMA across the priority queues, for queues 8 to 15. The SRAM itself is split into a number of evenly sized segments (this is defined in the verilog configuration defs file - for the configuration used to generate this register description, the total number of segments was set to '16'). Those segments can then be freely distributed across the active queues, in powers of 2. I.e. a value of 0 would mean 1 segment has been allocated to the queue. A value of 1 would mean 2 segments, a value of 2 means 4 segments and so on. The reset values of these registers are defined in the configuration defs file.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

reserved_31_31

 

RO

0

30:28

segment_alloc_q15

 

RW

0x0

27

reserved_27_27

 

RO

0

26:24

segment_alloc_q14

 

RW

0x0

23

reserved_23_23

 

RO

0

22:20

segment_alloc_q13

 

RW

0x0

19

reserved_19_19

 

RO

0

18:16

segment_alloc_q12

 

RW

0x0

15

reserved_15_15

 

RO

0

14:12

segment_alloc_q11

 

RW

0x0

11

reserved_11_11

 

RO

0

10:8

segment_alloc_q10

 

RW

0x0

7

reserved_7_7

 

RO

0

6:4

segment_alloc_q9

 

RW

0x0

3

reserved_3_3

 

RO

0

2:0

segment_alloc_q8

 

RW

0x0

 

gem_gximicrosemi : RECEIVE_Q8_PTR

Address offset

0x05C0

Physical address

0x2011 05C0

Instance

GEM_A_LO

0x2011 25C0

GEM_B_LO

0x2811 05C0

GEM_A_HI

0x2811 25C0

GEM_B_HI

Description

This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the network control register. Once reception is enabled, any write to the receive buffer queue base address register is ignored. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the used bits. In terms of AMBA (AHB/AXI) operation, the receive descriptors are read from memory using a single 32bit AHB/AXI access. When the datapath is configured at 64bit or 128bit, the receive descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is written to using a single 64bit AHB/AXI access. For 32bit datapaths, the receive descriptors should be aligned at 32-bit boundaries and are written to using two individual non sequential 32-bit accesses.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

dma_rx_q_ptr

 

RW

0x0000 0000

1

reserved_1

 

RO

0

0

dma_rx_dis_q

 

RW

0

 

gem_gximicrosemi : RECEIVE_Q9_PTR

Address offset

0x05C4

Physical address

0x2011 05C4

Instance

GEM_A_LO

0x2011 25C4

GEM_B_LO

0x2811 05C4

GEM_A_HI

0x2811 25C4

GEM_B_HI

Description

This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the network control register. Once reception is enabled, any write to the receive buffer queue base address register is ignored. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the used bits. In terms of AMBA (AHB/AXI) operation, the receive descriptors are read from memory using a single 32bit AHB/AXI access. When the datapath is configured at 64bit or 128bit, the receive descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is written to using a single 64bit AHB/AXI access. For 32bit datapaths, the receive descriptors should be aligned at 32-bit boundaries and are written to using two individual non sequential 32-bit accesses.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

dma_rx_q_ptr

 

RW

0x0000 0000

1

reserved_1

 

RO

0

0

dma_rx_dis_q

 

RW

0

 

gem_gximicrosemi : RECEIVE_Q10_PTR

Address offset

0x05C8

Physical address

0x2011 05C8

Instance

GEM_A_LO

0x2011 25C8

GEM_B_LO

0x2811 05C8

GEM_A_HI

0x2811 25C8

GEM_B_HI

Description

This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the network control register. Once reception is enabled, any write to the receive buffer queue base address register is ignored. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the used bits. In terms of AMBA (AHB/AXI) operation, the receive descriptors are read from memory using a single 32bit AHB/AXI access. When the datapath is configured at 64bit or 128bit, the receive descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is written to using a single 64bit AHB/AXI access. For 32bit datapaths, the receive descriptors should be aligned at 32-bit boundaries and are written to using two individual non sequential 32-bit accesses.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

dma_rx_q_ptr

 

RW

0x0000 0000

1

reserved_1

 

RO

0

0

dma_rx_dis_q

 

RW

0

 

gem_gximicrosemi : RECEIVE_Q11_PTR

Address offset

0x05CC

Physical address

0x2011 05CC

Instance

GEM_A_LO

0x2011 25CC

GEM_B_LO

0x2811 05CC

GEM_A_HI

0x2811 25CC

GEM_B_HI

Description

This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the network control register. Once reception is enabled, any write to the receive buffer queue base address register is ignored. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the used bits. In terms of AMBA (AHB/AXI) operation, the receive descriptors are read from memory using a single 32bit AHB/AXI access. When the datapath is configured at 64bit or 128bit, the receive descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is written to using a single 64bit AHB/AXI access. For 32bit datapaths, the receive descriptors should be aligned at 32-bit boundaries and are written to using two individual non sequential 32-bit accesses.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

dma_rx_q_ptr

 

RW

0x0000 0000

1

reserved_1

 

RO

0

0

dma_rx_dis_q

 

RW

0

 

gem_gximicrosemi : RECEIVE_Q12_PTR

Address offset

0x05D0

Physical address

0x2011 05D0

Instance

GEM_A_LO

0x2011 25D0

GEM_B_LO

0x2811 05D0

GEM_A_HI

0x2811 25D0

GEM_B_HI

Description

This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the network control register. Once reception is enabled, any write to the receive buffer queue base address register is ignored. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the used bits. In terms of AMBA (AHB/AXI) operation, the receive descriptors are read from memory using a single 32bit AHB/AXI access. When the datapath is configured at 64bit or 128bit, the receive descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is written to using a single 64bit AHB/AXI access. For 32bit datapaths, the receive descriptors should be aligned at 32-bit boundaries and are written to using two individual non sequential 32-bit accesses.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

dma_rx_q_ptr

 

RW

0x0000 0000

1

reserved_1

 

RO

0

0

dma_rx_dis_q

 

RW

0

 

gem_gximicrosemi : RECEIVE_Q13_PTR

Address offset

0x05D4

Physical address

0x2011 05D4

Instance

GEM_A_LO

0x2011 25D4

GEM_B_LO

0x2811 05D4

GEM_A_HI

0x2811 25D4

GEM_B_HI

Description

This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the network control register. Once reception is enabled, any write to the receive buffer queue base address register is ignored. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the used bits. In terms of AMBA (AHB/AXI) operation, the receive descriptors are read from memory using a single 32bit AHB/AXI access. When the datapath is configured at 64bit or 128bit, the receive descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is written to using a single 64bit AHB/AXI access. For 32bit datapaths, the receive descriptors should be aligned at 32-bit boundaries and are written to using two individual non sequential 32-bit accesses.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

dma_rx_q_ptr

 

RW

0x0000 0000

1

reserved_1

 

RO

0

0

dma_rx_dis_q

 

RW

0

 

gem_gximicrosemi : RECEIVE_Q14_PTR

Address offset

0x05D8

Physical address

0x2011 05D8

Instance

GEM_A_LO

0x2011 25D8

GEM_B_LO

0x2811 05D8

GEM_A_HI

0x2811 25D8

GEM_B_HI

Description

This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the network control register. Once reception is enabled, any write to the receive buffer queue base address register is ignored. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the used bits. In terms of AMBA (AHB/AXI) operation, the receive descriptors are read from memory using a single 32bit AHB/AXI access. When the datapath is configured at 64bit or 128bit, the receive descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is written to using a single 64bit AHB/AXI access. For 32bit datapaths, the receive descriptors should be aligned at 32-bit boundaries and are written to using two individual non sequential 32-bit accesses.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

dma_rx_q_ptr

 

RW

0x0000 0000

1

reserved_1

 

RO

0

0

dma_rx_dis_q

 

RW

0

 

gem_gximicrosemi : RECEIVE_Q15_PTR

Address offset

0x05DC

Physical address

0x2011 05DC

Instance

GEM_A_LO

0x2011 25DC

GEM_B_LO

0x2811 05DC

GEM_A_HI

0x2811 25DC

GEM_B_HI

Description

This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the network control register. Once reception is enabled, any write to the receive buffer queue base address register is ignored. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the used bits. In terms of AMBA (AHB/AXI) operation, the receive descriptors are read from memory using a single 32bit AHB/AXI access. When the datapath is configured at 64bit or 128bit, the receive descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is written to using a single 64bit AHB/AXI access. For 32bit datapaths, the receive descriptors should be aligned at 32-bit boundaries and are written to using two individual non sequential 32-bit accesses.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

dma_rx_q_ptr

 

RW

0x0000 0000

1

reserved_1

 

RO

0

0

dma_rx_dis_q

 

RW

0

 

gem_gximicrosemi : DMA_RXBUF_SIZE_Q8

Address offset

0x05E0

Physical address

0x2011 05E0

Instance

GEM_A_LO

0x2011 25E0

GEM_B_LO

0x2811 05E0

GEM_A_HI

0x2811 25E0

GEM_B_HI

Description

Receive Buffer Size

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:8

reserved_31_8

 

RO

0x00 0000

7:0

dma_rx_q_buf_size

 

RW

0x02

 

gem_gximicrosemi : DMA_RXBUF_SIZE_Q9

Address offset

0x05E4

Physical address

0x2011 05E4

Instance

GEM_A_LO

0x2011 25E4

GEM_B_LO

0x2811 05E4

GEM_A_HI

0x2811 25E4

GEM_B_HI

Description

Receive Buffer Size

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:8

reserved_31_8

 

RO

0x00 0000

7:0

dma_rx_q_buf_size

 

RW

0x02

 

gem_gximicrosemi : DMA_RXBUF_SIZE_Q10

Address offset

0x05E8

Physical address

0x2011 05E8

Instance

GEM_A_LO

0x2011 25E8

GEM_B_LO

0x2811 05E8

GEM_A_HI

0x2811 25E8

GEM_B_HI

Description

Receive Buffer Size

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:8

reserved_31_8

 

RO

0x00 0000

7:0

dma_rx_q_buf_size

 

RW

0x02

 

gem_gximicrosemi : DMA_RXBUF_SIZE_Q11

Address offset

0x05EC

Physical address

0x2011 05EC

Instance

GEM_A_LO

0x2011 25EC

GEM_B_LO

0x2811 05EC

GEM_A_HI

0x2811 25EC

GEM_B_HI

Description

Receive Buffer Size

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:8

reserved_31_8

 

RO

0x00 0000

7:0

dma_rx_q_buf_size

 

RW

0x02

 

gem_gximicrosemi : DMA_RXBUF_SIZE_Q12

Address offset

0x05F0

Physical address

0x2011 05F0

Instance

GEM_A_LO

0x2011 25F0

GEM_B_LO

0x2811 05F0

GEM_A_HI

0x2811 25F0

GEM_B_HI

Description

Receive Buffer Size

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:8

reserved_31_8

 

RO

0x00 0000

7:0

dma_rx_q_buf_size

 

RW

0x02

 

gem_gximicrosemi : DMA_RXBUF_SIZE_Q13

Address offset

0x05F4

Physical address

0x2011 05F4

Instance

GEM_A_LO

0x2011 25F4

GEM_B_LO

0x2811 05F4

GEM_A_HI

0x2811 25F4

GEM_B_HI

Description

Receive Buffer Size

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:8

reserved_31_8

 

RO

0x00 0000

7:0

dma_rx_q_buf_size

 

RW

0x02

 

gem_gximicrosemi : DMA_RXBUF_SIZE_Q14

Address offset

0x05F8

Physical address

0x2011 05F8

Instance

GEM_A_LO

0x2011 25F8

GEM_B_LO

0x2811 05F8

GEM_A_HI

0x2811 25F8

GEM_B_HI

Description

Receive Buffer Size

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:8

reserved_31_8

 

RO

0x00 0000

7:0

dma_rx_q_buf_size

 

RW

0x02

 

gem_gximicrosemi : DMA_RXBUF_SIZE_Q15

Address offset

0x05FC

Physical address

0x2011 05FC

Instance

GEM_A_LO

0x2011 25FC

GEM_B_LO

0x2811 05FC

GEM_A_HI

0x2811 25FC

GEM_B_HI

Description

Receive Buffer Size

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:8

reserved_31_8

 

RO

0x00 0000

7:0

dma_rx_q_buf_size

 

RW

0x02

 

gem_gximicrosemi : INT_Q1_ENABLE

Address offset

0x0600

Physical address

0x2011 0600

Instance

GEM_A_LO

0x2011 2600

GEM_B_LO

0x2811 0600

GEM_A_HI

0x2811 2600

GEM_B_HI

Description

At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

enable_resp_not_ok_interrupt

 

WO

0

10:8

reserved_10_8

 

RO

0x0

7

enable_transmit_complete_interrupt

 

WO

0

6

enable_transmit_frame_corruption_due_to_amba_error_interrupt

 

WO

0

5

enable_retry_limit_exceeded_or_late_collision_interrupt

 

WO

0

4:3

reserved_4_3

 

RO

0x0

2

enable_rx_used_bit_read_interrupt

 

WO

0

1

enable_receive_complete_interrupt

 

WO

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q2_ENABLE

Address offset

0x0604

Physical address

0x2011 0604

Instance

GEM_A_LO

0x2011 2604

GEM_B_LO

0x2811 0604

GEM_A_HI

0x2811 2604

GEM_B_HI

Description

At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

enable_resp_not_ok_interrupt

 

WO

0

10:8

reserved_10_8

 

RO

0x0

7

enable_transmit_complete_interrupt

 

WO

0

6

enable_transmit_frame_corruption_due_to_amba_error_interrupt

 

WO

0

5

enable_retry_limit_exceeded_or_late_collision_interrupt

 

WO

0

4:3

reserved_4_3

 

RO

0x0

2

enable_rx_used_bit_read_interrupt

 

WO

0

1

enable_receive_complete_interrupt

 

WO

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q3_ENABLE

Address offset

0x0608

Physical address

0x2011 0608

Instance

GEM_A_LO

0x2011 2608

GEM_B_LO

0x2811 0608

GEM_A_HI

0x2811 2608

GEM_B_HI

Description

At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

enable_resp_not_ok_interrupt

 

WO

0

10:8

reserved_10_8

 

RO

0x0

7

enable_transmit_complete_interrupt

 

WO

0

6

enable_transmit_frame_corruption_due_to_amba_error_interrupt

 

WO

0

5

enable_retry_limit_exceeded_or_late_collision_interrupt

 

WO

0

4:3

reserved_4_3

 

RO

0x0

2

enable_rx_used_bit_read_interrupt

 

WO

0

1

enable_receive_complete_interrupt

 

WO

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q4_ENABLE

Address offset

0x060C

Physical address

0x2011 060C

Instance

GEM_A_LO

0x2011 260C

GEM_B_LO

0x2811 060C

GEM_A_HI

0x2811 260C

GEM_B_HI

Description

At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

enable_resp_not_ok_interrupt

 

WO

0

10:8

reserved_10_8

 

RO

0x0

7

enable_transmit_complete_interrupt

 

WO

0

6

enable_transmit_frame_corruption_due_to_amba_error_interrupt

 

WO

0

5

enable_retry_limit_exceeded_or_late_collision_interrupt

 

WO

0

4:3

reserved_4_3

 

RO

0x0

2

enable_rx_used_bit_read_interrupt

 

WO

0

1

enable_receive_complete_interrupt

 

WO

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q5_ENABLE

Address offset

0x0610

Physical address

0x2011 0610

Instance

GEM_A_LO

0x2011 2610

GEM_B_LO

0x2811 0610

GEM_A_HI

0x2811 2610

GEM_B_HI

Description

At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

enable_resp_not_ok_interrupt

 

WO

0

10:8

reserved_10_8

 

RO

0x0

7

enable_transmit_complete_interrupt

 

WO

0

6

enable_transmit_frame_corruption_due_to_amba_error_interrupt

 

WO

0

5

enable_retry_limit_exceeded_or_late_collision_interrupt

 

WO

0

4:3

reserved_4_3

 

RO

0x0

2

enable_rx_used_bit_read_interrupt

 

WO

0

1

enable_receive_complete_interrupt

 

WO

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q6_ENABLE

Address offset

0x0614

Physical address

0x2011 0614

Instance

GEM_A_LO

0x2011 2614

GEM_B_LO

0x2811 0614

GEM_A_HI

0x2811 2614

GEM_B_HI

Description

At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

enable_resp_not_ok_interrupt

 

WO

0

10:8

reserved_10_8

 

RO

0x0

7

enable_transmit_complete_interrupt

 

WO

0

6

enable_transmit_frame_corruption_due_to_amba_error_interrupt

 

WO

0

5

enable_retry_limit_exceeded_or_late_collision_interrupt

 

WO

0

4:3

reserved_4_3

 

RO

0x0

2

enable_rx_used_bit_read_interrupt

 

WO

0

1

enable_receive_complete_interrupt

 

WO

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q7_ENABLE

Address offset

0x0618

Physical address

0x2011 0618

Instance

GEM_A_LO

0x2011 2618

GEM_B_LO

0x2811 0618

GEM_A_HI

0x2811 2618

GEM_B_HI

Description

At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

enable_resp_not_ok_interrupt

 

WO

0

10:8

reserved_10_8

 

RO

0x0

7

enable_transmit_complete_interrupt

 

WO

0

6

enable_transmit_frame_corruption_due_to_amba_error_interrupt

 

WO

0

5

enable_retry_limit_exceeded_or_late_collision_interrupt

 

WO

0

4:3

reserved_4_3

 

RO

0x0

2

enable_rx_used_bit_read_interrupt

 

WO

0

1

enable_receive_complete_interrupt

 

WO

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q1_DISABLE

Address offset

0x0620

Physical address

0x2011 0620

Instance

GEM_A_LO

0x2011 2620

GEM_B_LO

0x2811 0620

GEM_A_HI

0x2811 2620

GEM_B_HI

Description

Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

disable_resp_not_ok_interrupt

 

WO

0

10:8

reserved_10_8

 

RO

0x0

7

disable_transmit_complete_interrupt

 

WO

0

6

disable_transmit_frame_corruption_due_to_amba_error_interrupt

 

WO

0

5

disable_retry_limit_exceeded_or_late_collision_interrupt

 

WO

0

4:3

reserved_4_3

 

RO

0x0

2

disable_rx_used_bit_read_interrupt

 

WO

0

1

disable_receive_complete_interrupt

 

WO

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q2_DISABLE

Address offset

0x0624

Physical address

0x2011 0624

Instance

GEM_A_LO

0x2011 2624

GEM_B_LO

0x2811 0624

GEM_A_HI

0x2811 2624

GEM_B_HI

Description

Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

disable_resp_not_ok_interrupt

 

WO

0

10:8

reserved_10_8

 

RO

0x0

7

disable_transmit_complete_interrupt

 

WO

0

6

disable_transmit_frame_corruption_due_to_amba_error_interrupt

 

WO

0

5

disable_retry_limit_exceeded_or_late_collision_interrupt

 

WO

0

4:3

reserved_4_3

 

RO

0x0

2

disable_rx_used_bit_read_interrupt

 

WO

0

1

disable_receive_complete_interrupt

 

WO

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q3_DISABLE

Address offset

0x0628

Physical address

0x2011 0628

Instance

GEM_A_LO

0x2011 2628

GEM_B_LO

0x2811 0628

GEM_A_HI

0x2811 2628

GEM_B_HI

Description

Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

disable_resp_not_ok_interrupt

 

WO

0

10:8

reserved_10_8

 

RO

0x0

7

disable_transmit_complete_interrupt

 

WO

0

6

disable_transmit_frame_corruption_due_to_amba_error_interrupt

 

WO

0

5

disable_retry_limit_exceeded_or_late_collision_interrupt

 

WO

0

4:3

reserved_4_3

 

RO

0x0

2

disable_rx_used_bit_read_interrupt

 

WO

0

1

disable_receive_complete_interrupt

 

WO

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q4_DISABLE

Address offset

0x062C

Physical address

0x2011 062C

Instance

GEM_A_LO

0x2011 262C

GEM_B_LO

0x2811 062C

GEM_A_HI

0x2811 262C

GEM_B_HI

Description

Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

disable_resp_not_ok_interrupt

 

WO

0

10:8

reserved_10_8

 

RO

0x0

7

disable_transmit_complete_interrupt

 

WO

0

6

disable_transmit_frame_corruption_due_to_amba_error_interrupt

 

WO

0

5

disable_retry_limit_exceeded_or_late_collision_interrupt

 

WO

0

4:3

reserved_4_3

 

RO

0x0

2

disable_rx_used_bit_read_interrupt

 

WO

0

1

disable_receive_complete_interrupt

 

WO

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q5_DISABLE

Address offset

0x0630

Physical address

0x2011 0630

Instance

GEM_A_LO

0x2011 2630

GEM_B_LO

0x2811 0630

GEM_A_HI

0x2811 2630

GEM_B_HI

Description

Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

disable_resp_not_ok_interrupt

 

WO

0

10:8

reserved_10_8

 

RO

0x0

7

disable_transmit_complete_interrupt

 

WO

0

6

disable_transmit_frame_corruption_due_to_amba_error_interrupt

 

WO

0

5

disable_retry_limit_exceeded_or_late_collision_interrupt

 

WO

0

4:3

reserved_4_3

 

RO

0x0

2

disable_rx_used_bit_read_interrupt

 

WO

0

1

disable_receive_complete_interrupt

 

WO

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q6_DISABLE

Address offset

0x0634

Physical address

0x2011 0634

Instance

GEM_A_LO

0x2011 2634

GEM_B_LO

0x2811 0634

GEM_A_HI

0x2811 2634

GEM_B_HI

Description

Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

disable_resp_not_ok_interrupt

 

WO

0

10:8

reserved_10_8

 

RO

0x0

7

disable_transmit_complete_interrupt

 

WO

0

6

disable_transmit_frame_corruption_due_to_amba_error_interrupt

 

WO

0

5

disable_retry_limit_exceeded_or_late_collision_interrupt

 

WO

0

4:3

reserved_4_3

 

RO

0x0

2

disable_rx_used_bit_read_interrupt

 

WO

0

1

disable_receive_complete_interrupt

 

WO

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q7_DISABLE

Address offset

0x0638

Physical address

0x2011 0638

Instance

GEM_A_LO

0x2011 2638

GEM_B_LO

0x2811 0638

GEM_A_HI

0x2811 2638

GEM_B_HI

Description

Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

disable_resp_not_ok_interrupt

 

WO

0

10:8

reserved_10_8

 

RO

0x0

7

disable_transmit_complete_interrupt

 

WO

0

6

disable_transmit_frame_corruption_due_to_amba_error_interrupt

 

WO

0

5

disable_retry_limit_exceeded_or_late_collision_interrupt

 

WO

0

4:3

reserved_4_3

 

RO

0x0

2

disable_rx_used_bit_read_interrupt

 

WO

0

1

disable_receive_complete_interrupt

 

WO

0

0

reserved_0

 

RO

0

 

G5SOC_MSS_REGMAP : gem_gximicrosemi : INT_Q1_MASK

Address offset

0x0640

Physical address

0x2011 0640

Instance

GEM_A_LO

0x2011 2640

GEM_B_LO

0x2811 0640

GEM_A_HI

0x2811 2640

GEM_B_HI

Description

The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register.

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

resp_not_ok_interrupt_mask

 

RO

1

10:8

reserved_10_8

 

RO

0x0

7

transmit_complete_interrupt_mask

 

RO

1

6

amba_error_interrupt_mask

 

RO

1

5

retry_limit_exceeded_or_late_collision_interrupt_mask

 

RO

1

4:3

reserved_4_3

 

RO

0x0

2

rx_used_interrupt_mask

 

RO

1

1

receive_complete_interrupt_mask

 

RO

1

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q2_MASK

Address offset

0x0644

Physical address

0x2011 0644

Instance

GEM_A_LO

0x2011 2644

GEM_B_LO

0x2811 0644

GEM_A_HI

0x2811 2644

GEM_B_HI

Description

The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register.

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

resp_not_ok_interrupt_mask

 

RO

1

10:8

reserved_10_8

 

RO

0x0

7

transmit_complete_interrupt_mask

 

RO

1

6

amba_error_interrupt_mask

 

RO

1

5

retry_limit_exceeded_or_late_collision_interrupt_mask

 

RO

1

4:3

reserved_4_3

 

RO

0x0

2

rx_used_interrupt_mask

 

RO

1

1

receive_complete_interrupt_mask

 

RO

1

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q3_MASK

Address offset

0x0648

Physical address

0x2011 0648

Instance

GEM_A_LO

0x2011 2648

GEM_B_LO

0x2811 0648

GEM_A_HI

0x2811 2648

GEM_B_HI

Description

The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register.

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

resp_not_ok_interrupt_mask

 

RO

1

10:8

reserved_10_8

 

RO

0x0

7

transmit_complete_interrupt_mask

 

RO

1

6

amba_error_interrupt_mask

 

RO

1

5

retry_limit_exceeded_or_late_collision_interrupt_mask

 

RO

1

4:3

reserved_4_3

 

RO

0x0

2

rx_used_interrupt_mask

 

RO

1

1

receive_complete_interrupt_mask

 

RO

1

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q4_MASK

Address offset

0x064C

Physical address

0x2011 064C

Instance

GEM_A_LO

0x2011 264C

GEM_B_LO

0x2811 064C

GEM_A_HI

0x2811 264C

GEM_B_HI

Description

The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register.

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

resp_not_ok_interrupt_mask

 

RO

1

10:8

reserved_10_8

 

RO

0x0

7

transmit_complete_interrupt_mask

 

RO

1

6

amba_error_interrupt_mask

 

RO

1

5

retry_limit_exceeded_or_late_collision_interrupt_mask

 

RO

1

4:3

reserved_4_3

 

RO

0x0

2

rx_used_interrupt_mask

 

RO

1

1

receive_complete_interrupt_mask

 

RO

1

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q5_MASK

Address offset

0x0650

Physical address

0x2011 0650

Instance

GEM_A_LO

0x2011 2650

GEM_B_LO

0x2811 0650

GEM_A_HI

0x2811 2650

GEM_B_HI

Description

The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register.

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

resp_not_ok_interrupt_mask

 

RO

1

10:8

reserved_10_8

 

RO

0x0

7

transmit_complete_interrupt_mask

 

RO

1

6

amba_error_interrupt_mask

 

RO

1

5

retry_limit_exceeded_or_late_collision_interrupt_mask

 

RO

1

4:3

reserved_4_3

 

RO

0x0

2

rx_used_interrupt_mask

 

RO

1

1

receive_complete_interrupt_mask

 

RO

1

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q6_MASK

Address offset

0x0654

Physical address

0x2011 0654

Instance

GEM_A_LO

0x2011 2654

GEM_B_LO

0x2811 0654

GEM_A_HI

0x2811 2654

GEM_B_HI

Description

The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register.

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

resp_not_ok_interrupt_mask

 

RO

1

10:8

reserved_10_8

 

RO

0x0

7

transmit_complete_interrupt_mask

 

RO

1

6

amba_error_interrupt_mask

 

RO

1

5

retry_limit_exceeded_or_late_collision_interrupt_mask

 

RO

1

4:3

reserved_4_3

 

RO

0x0

2

rx_used_interrupt_mask

 

RO

1

1

receive_complete_interrupt_mask

 

RO

1

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q7_MASK

Address offset

0x0658

Physical address

0x2011 0658

Instance

GEM_A_LO

0x2011 2658

GEM_B_LO

0x2811 0658

GEM_A_HI

0x2811 2658

GEM_B_HI

Description

The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register.

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

resp_not_ok_interrupt_mask

 

RO

1

10:8

reserved_10_8

 

RO

0x0

7

transmit_complete_interrupt_mask

 

RO

1

6

amba_error_interrupt_mask

 

RO

1

5

retry_limit_exceeded_or_late_collision_interrupt_mask

 

RO

1

4:3

reserved_4_3

 

RO

0x0

2

rx_used_interrupt_mask

 

RO

1

1

receive_complete_interrupt_mask

 

RO

1

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q8_ENABLE

Address offset

0x0660

Physical address

0x2011 0660

Instance

GEM_A_LO

0x2011 2660

GEM_B_LO

0x2811 0660

GEM_A_HI

0x2811 2660

GEM_B_HI

Description

At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

enable_resp_not_ok_interrupt

 

WO

0

10:8

reserved_10_8

 

RO

0x0

7

enable_transmit_complete_interrupt

 

WO

0

6

enable_transmit_frame_corruption_due_to_amba_error_interrupt

 

WO

0

5

enable_retry_limit_exceeded_or_late_collision_interrupt

 

WO

0

4:3

reserved_4_3

 

RO

0x0

2

enable_rx_used_bit_read_interrupt

 

WO

0

1

enable_receive_complete_interrupt

 

WO

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q9_ENABLE

Address offset

0x0664

Physical address

0x2011 0664

Instance

GEM_A_LO

0x2011 2664

GEM_B_LO

0x2811 0664

GEM_A_HI

0x2811 2664

GEM_B_HI

Description

At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

enable_resp_not_ok_interrupt

 

WO

0

10:8

reserved_10_8

 

RO

0x0

7

enable_transmit_complete_interrupt

 

WO

0

6

enable_transmit_frame_corruption_due_to_amba_error_interrupt

 

WO

0

5

enable_retry_limit_exceeded_or_late_collision_interrupt

 

WO

0

4:3

reserved_4_3

 

RO

0x0

2

enable_rx_used_bit_read_interrupt

 

WO

0

1

enable_receive_complete_interrupt

 

WO

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q10_ENABLE

Address offset

0x0668

Physical address

0x2011 0668

Instance

GEM_A_LO

0x2011 2668

GEM_B_LO

0x2811 0668

GEM_A_HI

0x2811 2668

GEM_B_HI

Description

At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

enable_resp_not_ok_interrupt

 

WO

0

10:8

reserved_10_8

 

RO

0x0

7

enable_transmit_complete_interrupt

 

WO

0

6

enable_transmit_frame_corruption_due_to_amba_error_interrupt

 

WO

0

5

enable_retry_limit_exceeded_or_late_collision_interrupt

 

WO

0

4:3

reserved_4_3

 

RO

0x0

2

enable_rx_used_bit_read_interrupt

 

WO

0

1

enable_receive_complete_interrupt

 

WO

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q11_ENABLE

Address offset

0x066C

Physical address

0x2011 066C

Instance

GEM_A_LO

0x2011 266C

GEM_B_LO

0x2811 066C

GEM_A_HI

0x2811 266C

GEM_B_HI

Description

At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

enable_resp_not_ok_interrupt

 

WO

0

10:8

reserved_10_8

 

RO

0x0

7

enable_transmit_complete_interrupt

 

WO

0

6

enable_transmit_frame_corruption_due_to_amba_error_interrupt

 

WO

0

5

enable_retry_limit_exceeded_or_late_collision_interrupt

 

WO

0

4:3

reserved_4_3

 

RO

0x0

2

enable_rx_used_bit_read_interrupt

 

WO

0

1

enable_receive_complete_interrupt

 

WO

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q12_ENABLE

Address offset

0x0670

Physical address

0x2011 0670

Instance

GEM_A_LO

0x2011 2670

GEM_B_LO

0x2811 0670

GEM_A_HI

0x2811 2670

GEM_B_HI

Description

At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

enable_resp_not_ok_interrupt

 

WO

0

10:8

reserved_10_8

 

RO

0x0

7

enable_transmit_complete_interrupt

 

WO

0

6

enable_transmit_frame_corruption_due_to_amba_error_interrupt

 

WO

0

5

enable_retry_limit_exceeded_or_late_collision_interrupt

 

WO

0

4:3

reserved_4_3

 

RO

0x0

2

enable_rx_used_bit_read_interrupt

 

WO

0

1

enable_receive_complete_interrupt

 

WO

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q13_ENABLE

Address offset

0x0674

Physical address

0x2011 0674

Instance

GEM_A_LO

0x2011 2674

GEM_B_LO

0x2811 0674

GEM_A_HI

0x2811 2674

GEM_B_HI

Description

At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

enable_resp_not_ok_interrupt

 

WO

0

10:8

reserved_10_8

 

RO

0x0

7

enable_transmit_complete_interrupt

 

WO

0

6

enable_transmit_frame_corruption_due_to_amba_error_interrupt

 

WO

0

5

enable_retry_limit_exceeded_or_late_collision_interrupt

 

WO

0

4:3

reserved_4_3

 

RO

0x0

2

enable_rx_used_bit_read_interrupt

 

WO

0

1

enable_receive_complete_interrupt

 

WO

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q14_ENABLE

Address offset

0x0678

Physical address

0x2011 0678

Instance

GEM_A_LO

0x2011 2678

GEM_B_LO

0x2811 0678

GEM_A_HI

0x2811 2678

GEM_B_HI

Description

At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

enable_resp_not_ok_interrupt

 

WO

0

10:8

reserved_10_8

 

RO

0x0

7

enable_transmit_complete_interrupt

 

WO

0

6

enable_transmit_frame_corruption_due_to_amba_error_interrupt

 

WO

0

5

enable_retry_limit_exceeded_or_late_collision_interrupt

 

WO

0

4:3

reserved_4_3

 

RO

0x0

2

enable_rx_used_bit_read_interrupt

 

WO

0

1

enable_receive_complete_interrupt

 

WO

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q15_ENABLE

Address offset

0x067C

Physical address

0x2011 067C

Instance

GEM_A_LO

0x2011 267C

GEM_B_LO

0x2811 067C

GEM_A_HI

0x2811 267C

GEM_B_HI

Description

At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

enable_resp_not_ok_interrupt

 

WO

0

10:8

reserved_10_8

 

RO

0x0

7

enable_transmit_complete_interrupt

 

WO

0

6

enable_transmit_frame_corruption_due_to_amba_error_interrupt

 

WO

0

5

enable_retry_limit_exceeded_or_late_collision_interrupt

 

WO

0

4:3

reserved_4_3

 

RO

0x0

2

enable_rx_used_bit_read_interrupt

 

WO

0

1

enable_receive_complete_interrupt

 

WO

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q8_DISABLE

Address offset

0x0680

Physical address

0x2011 0680

Instance

GEM_A_LO

0x2011 2680

GEM_B_LO

0x2811 0680

GEM_A_HI

0x2811 2680

GEM_B_HI

Description

Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

disable_resp_not_ok_interrupt

 

WO

0

10:8

reserved_10_8

 

RO

0x0

7

disable_transmit_complete_interrupt

 

WO

0

6

disable_transmit_frame_corruption_due_to_amba_error_interrupt

 

WO

0

5

disable_retry_limit_exceeded_or_late_collision_interrupt

 

WO

0

4:3

reserved_4_3

 

RO

0x0

2

disable_rx_used_bit_read_interrupt

 

WO

0

1

disable_receive_complete_interrupt

 

WO

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q9_DISABLE

Address offset

0x0684

Physical address

0x2011 0684

Instance

GEM_A_LO

0x2011 2684

GEM_B_LO

0x2811 0684

GEM_A_HI

0x2811 2684

GEM_B_HI

Description

Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

disable_resp_not_ok_interrupt

 

WO

0

10:8

reserved_10_8

 

RO

0x0

7

disable_transmit_complete_interrupt

 

WO

0

6

disable_transmit_frame_corruption_due_to_amba_error_interrupt

 

WO

0

5

disable_retry_limit_exceeded_or_late_collision_interrupt

 

WO

0

4:3

reserved_4_3

 

RO

0x0

2

disable_rx_used_bit_read_interrupt

 

WO

0

1

disable_receive_complete_interrupt

 

WO

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q10_DISABLE

Address offset

0x0688

Physical address

0x2011 0688

Instance

GEM_A_LO

0x2011 2688

GEM_B_LO

0x2811 0688

GEM_A_HI

0x2811 2688

GEM_B_HI

Description

Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

disable_resp_not_ok_interrupt

 

WO

0

10:8

reserved_10_8

 

RO

0x0

7

disable_transmit_complete_interrupt

 

WO

0

6

disable_transmit_frame_corruption_due_to_amba_error_interrupt

 

WO

0

5

disable_retry_limit_exceeded_or_late_collision_interrupt

 

WO

0

4:3

reserved_4_3

 

RO

0x0

2

disable_rx_used_bit_read_interrupt

 

WO

0

1

disable_receive_complete_interrupt

 

WO

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q11_DISABLE

Address offset

0x068C

Physical address

0x2011 068C

Instance

GEM_A_LO

0x2011 268C

GEM_B_LO

0x2811 068C

GEM_A_HI

0x2811 268C

GEM_B_HI

Description

Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

disable_resp_not_ok_interrupt

 

WO

0

10:8

reserved_10_8

 

RO

0x0

7

disable_transmit_complete_interrupt

 

WO

0

6

disable_transmit_frame_corruption_due_to_amba_error_interrupt

 

WO

0

5

disable_retry_limit_exceeded_or_late_collision_interrupt

 

WO

0

4:3

reserved_4_3

 

RO

0x0

2

disable_rx_used_bit_read_interrupt

 

WO

0

1

disable_receive_complete_interrupt

 

WO

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q12_DISABLE

Address offset

0x0690

Physical address

0x2011 0690

Instance

GEM_A_LO

0x2011 2690

GEM_B_LO

0x2811 0690

GEM_A_HI

0x2811 2690

GEM_B_HI

Description

Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

disable_resp_not_ok_interrupt

 

WO

0

10:8

reserved_10_8

 

RO

0x0

7

disable_transmit_complete_interrupt

 

WO

0

6

disable_transmit_frame_corruption_due_to_amba_error_interrupt

 

WO

0

5

disable_retry_limit_exceeded_or_late_collision_interrupt

 

WO

0

4:3

reserved_4_3

 

RO

0x0

2

disable_rx_used_bit_read_interrupt

 

WO

0

1

disable_receive_complete_interrupt

 

WO

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q13_DISABLE

Address offset

0x0694

Physical address

0x2011 0694

Instance

GEM_A_LO

0x2011 2694

GEM_B_LO

0x2811 0694

GEM_A_HI

0x2811 2694

GEM_B_HI

Description

Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

disable_resp_not_ok_interrupt

 

WO

0

10:8

reserved_10_8

 

RO

0x0

7

disable_transmit_complete_interrupt

 

WO

0

6

disable_transmit_frame_corruption_due_to_amba_error_interrupt

 

WO

0

5

disable_retry_limit_exceeded_or_late_collision_interrupt

 

WO

0

4:3

reserved_4_3

 

RO

0x0

2

disable_rx_used_bit_read_interrupt

 

WO

0

1

disable_receive_complete_interrupt

 

WO

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q14_DISABLE

Address offset

0x0698

Physical address

0x2011 0698

Instance

GEM_A_LO

0x2011 2698

GEM_B_LO

0x2811 0698

GEM_A_HI

0x2811 2698

GEM_B_HI

Description

Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

disable_resp_not_ok_interrupt

 

WO

0

10:8

reserved_10_8

 

RO

0x0

7

disable_transmit_complete_interrupt

 

WO

0

6

disable_transmit_frame_corruption_due_to_amba_error_interrupt

 

WO

0

5

disable_retry_limit_exceeded_or_late_collision_interrupt

 

WO

0

4:3

reserved_4_3

 

RO

0x0

2

disable_rx_used_bit_read_interrupt

 

WO

0

1

disable_receive_complete_interrupt

 

WO

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q15_DISABLE

Address offset

0x069C

Physical address

0x2011 069C

Instance

GEM_A_LO

0x2011 269C

GEM_B_LO

0x2811 069C

GEM_A_HI

0x2811 269C

GEM_B_HI

Description

Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

disable_resp_not_ok_interrupt

 

WO

0

10:8

reserved_10_8

 

RO

0x0

7

disable_transmit_complete_interrupt

 

WO

0

6

disable_transmit_frame_corruption_due_to_amba_error_interrupt

 

WO

0

5

disable_retry_limit_exceeded_or_late_collision_interrupt

 

WO

0

4:3

reserved_4_3

 

RO

0x0

2

disable_rx_used_bit_read_interrupt

 

WO

0

1

disable_receive_complete_interrupt

 

WO

0

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q8_MASK

Address offset

0x06A0

Physical address

0x2011 06A0

Instance

GEM_A_LO

0x2011 26A0

GEM_B_LO

0x2811 06A0

GEM_A_HI

0x2811 26A0

GEM_B_HI

Description

The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register.

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

resp_not_ok_interrupt_mask

 

RO

1

10:8

reserved_10_8

 

RO

0x0

7

transmit_complete_interrupt_mask

 

RO

1

6

amba_error_interrupt_mask

 

RO

1

5

retry_limit_exceeded_or_late_collision_interrupt_mask

 

RO

1

4:3

reserved_4_3

 

RO

0x0

2

rx_used_interrupt_mask

 

RO

1

1

receive_complete_interrupt_mask

 

RO

1

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q9_MASK

Address offset

0x06A4

Physical address

0x2011 06A4

Instance

GEM_A_LO

0x2011 26A4

GEM_B_LO

0x2811 06A4

GEM_A_HI

0x2811 26A4

GEM_B_HI

Description

The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register.

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

resp_not_ok_interrupt_mask

 

RO

1

10:8

reserved_10_8

 

RO

0x0

7

transmit_complete_interrupt_mask

 

RO

1

6

amba_error_interrupt_mask

 

RO

1

5

retry_limit_exceeded_or_late_collision_interrupt_mask

 

RO

1

4:3

reserved_4_3

 

RO

0x0

2

rx_used_interrupt_mask

 

RO

1

1

receive_complete_interrupt_mask

 

RO

1

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q10_MASK

Address offset

0x06A8

Physical address

0x2011 06A8

Instance

GEM_A_LO

0x2011 26A8

GEM_B_LO

0x2811 06A8

GEM_A_HI

0x2811 26A8

GEM_B_HI

Description

The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register.

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

resp_not_ok_interrupt_mask

 

RO

1

10:8

reserved_10_8

 

RO

0x0

7

transmit_complete_interrupt_mask

 

RO

1

6

amba_error_interrupt_mask

 

RO

1

5

retry_limit_exceeded_or_late_collision_interrupt_mask

 

RO

1

4:3

reserved_4_3

 

RO

0x0

2

rx_used_interrupt_mask

 

RO

1

1

receive_complete_interrupt_mask

 

RO

1

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q11_MASK

Address offset

0x06AC

Physical address

0x2011 06AC

Instance

GEM_A_LO

0x2011 26AC

GEM_B_LO

0x2811 06AC

GEM_A_HI

0x2811 26AC

GEM_B_HI

Description

The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register.

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

resp_not_ok_interrupt_mask

 

RO

1

10:8

reserved_10_8

 

RO

0x0

7

transmit_complete_interrupt_mask

 

RO

1

6

amba_error_interrupt_mask

 

RO

1

5

retry_limit_exceeded_or_late_collision_interrupt_mask

 

RO

1

4:3

reserved_4_3

 

RO

0x0

2

rx_used_interrupt_mask

 

RO

1

1

receive_complete_interrupt_mask

 

RO

1

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q12_MASK

Address offset

0x06B0

Physical address

0x2011 06B0

Instance

GEM_A_LO

0x2011 26B0

GEM_B_LO

0x2811 06B0

GEM_A_HI

0x2811 26B0

GEM_B_HI

Description

The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register.

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

resp_not_ok_interrupt_mask

 

RO

1

10:8

reserved_10_8

 

RO

0x0

7

transmit_complete_interrupt_mask

 

RO

1

6

amba_error_interrupt_mask

 

RO

1

5

retry_limit_exceeded_or_late_collision_interrupt_mask

 

RO

1

4:3

reserved_4_3

 

RO

0x0

2

rx_used_interrupt_mask

 

RO

1

1

receive_complete_interrupt_mask

 

RO

1

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q13_MASK

Address offset

0x06B4

Physical address

0x2011 06B4

Instance

GEM_A_LO

0x2011 26B4

GEM_B_LO

0x2811 06B4

GEM_A_HI

0x2811 26B4

GEM_B_HI

Description

The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register.

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

resp_not_ok_interrupt_mask

 

RO

1

10:8

reserved_10_8

 

RO

0x0

7

transmit_complete_interrupt_mask

 

RO

1

6

amba_error_interrupt_mask

 

RO

1

5

retry_limit_exceeded_or_late_collision_interrupt_mask

 

RO

1

4:3

reserved_4_3

 

RO

0x0

2

rx_used_interrupt_mask

 

RO

1

1

receive_complete_interrupt_mask

 

RO

1

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q14_MASK

Address offset

0x06B8

Physical address

0x2011 06B8

Instance

GEM_A_LO

0x2011 26B8

GEM_B_LO

0x2811 06B8

GEM_A_HI

0x2811 26B8

GEM_B_HI

Description

The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register.

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

resp_not_ok_interrupt_mask

 

RO

1

10:8

reserved_10_8

 

RO

0x0

7

transmit_complete_interrupt_mask

 

RO

1

6

amba_error_interrupt_mask

 

RO

1

5

retry_limit_exceeded_or_late_collision_interrupt_mask

 

RO

1

4:3

reserved_4_3

 

RO

0x0

2

rx_used_interrupt_mask

 

RO

1

1

receive_complete_interrupt_mask

 

RO

1

0

reserved_0

 

RO

0

 

gem_gximicrosemi : INT_Q15_MASK

Address offset

0x06BC

Physical address

0x2011 06BC

Instance

GEM_A_LO

0x2011 26BC

GEM_B_LO

0x2811 06BC

GEM_A_HI

0x2811 26BC

GEM_B_HI

Description

The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register.

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:12

reserved_31_12

 

RO

0x0 0000

11

resp_not_ok_interrupt_mask

 

RO

1

10:8

reserved_10_8

 

RO

0x0

7

transmit_complete_interrupt_mask

 

RO

1

6

amba_error_interrupt_mask

 

RO

1

5

retry_limit_exceeded_or_late_collision_interrupt_mask

 

RO

1

4:3

reserved_4_3

 

RO

0x0

2

rx_used_interrupt_mask

 

RO

1

1

receive_complete_interrupt_mask

 

RO

1

0

reserved_0

 

RO

0

 

gem_gximicrosemi : SCREENING_TYPE_2_ETHERTYPE_REG_0

Address offset

0x06E0

Physical address

0x2011 06E0

Instance

GEM_A_LO

0x2011 26E0

GEM_B_LO

0x2811 06E0

GEM_A_HI

0x2811 26E0

GEM_B_HI

Description

EtherType Register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

reserved_31_16

 

RO

0x0000

15:0

compare_value

 

RW

0x0000

 

gem_gximicrosemi : SCREENING_TYPE_2_ETHERTYPE_REG_1

Address offset

0x06E4

Physical address

0x2011 06E4

Instance

GEM_A_LO

0x2011 26E4

GEM_B_LO

0x2811 06E4

GEM_A_HI

0x2811 26E4

GEM_B_HI

Description

EtherType Register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

reserved_31_16

 

RO

0x0000

15:0

compare_value

 

RW

0x0000

 

gem_gximicrosemi : SCREENING_TYPE_2_ETHERTYPE_REG_2

Address offset

0x06E8

Physical address

0x2011 06E8

Instance

GEM_A_LO

0x2011 26E8

GEM_B_LO

0x2811 06E8

GEM_A_HI

0x2811 26E8

GEM_B_HI

Description

EtherType Register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

reserved_31_16

 

RO

0x0000

15:0

compare_value

 

RW

0x0000

 

gem_gximicrosemi : SCREENING_TYPE_2_ETHERTYPE_REG_3

Address offset

0x06EC

Physical address

0x2011 06EC

Instance

GEM_A_LO

0x2011 26EC

GEM_B_LO

0x2811 06EC

GEM_A_HI

0x2811 26EC

GEM_B_HI

Description

EtherType Register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

reserved_31_16

 

RO

0x0000

15:0

compare_value

 

RW

0x0000

 

gem_gximicrosemi : SCREENING_TYPE_2_ETHERTYPE_REG_4

Address offset

0x06F0

Physical address

0x2011 06F0

Instance

GEM_A_LO

0x2011 26F0

GEM_B_LO

0x2811 06F0

GEM_A_HI

0x2811 26F0

GEM_B_HI

Description

EtherType Register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

reserved_31_16

 

RO

0x0000

15:0

compare_value

 

RW

0x0000

 

gem_gximicrosemi : SCREENING_TYPE_2_ETHERTYPE_REG_5

Address offset

0x06F4

Physical address

0x2011 06F4

Instance

GEM_A_LO

0x2011 26F4

GEM_B_LO

0x2811 06F4

GEM_A_HI

0x2811 26F4

GEM_B_HI

Description

EtherType Register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

reserved_31_16

 

RO

0x0000

15:0

compare_value

 

RW

0x0000

 

gem_gximicrosemi : SCREENING_TYPE_2_ETHERTYPE_REG_6

Address offset

0x06F8

Physical address

0x2011 06F8

Instance

GEM_A_LO

0x2011 26F8

GEM_B_LO

0x2811 06F8

GEM_A_HI

0x2811 26F8

GEM_B_HI

Description

EtherType Register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

reserved_31_16

 

RO

0x0000

15:0

compare_value

 

RW

0x0000

 

gem_gximicrosemi : SCREENING_TYPE_2_ETHERTYPE_REG_7

Address offset

0x06FC

Physical address

0x2011 06FC

Instance

GEM_A_LO

0x2011 26FC

GEM_B_LO

0x2811 06FC

GEM_A_HI

0x2811 26FC

GEM_B_HI

Description

EtherType Register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

reserved_31_16

 

RO

0x0000

15:0

compare_value

 

RW

0x0000

 

gem_gximicrosemi : TYPE2_COMPARE_0_WORD_0

Address offset

0x0700

Physical address

0x2011 0700

Instance

GEM_A_LO

0x2011 2700

GEM_B_LO

0x2811 0700

GEM_A_HI

0x2811 2700

GEM_B_HI

Description

Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

compare_value

 

RW

0x0000

15:0

mask_value

 

RW

0x0000

 

gem_gximicrosemi : TYPE2_COMPARE_0_WORD_1

Address offset

0x0704

Physical address

0x2011 0704

Instance

GEM_A_LO

0x2011 2704

GEM_B_LO

0x2811 0704

GEM_A_HI

0x2811 2704

GEM_B_HI

Description

Type2 Compare Word 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:11

reserved_31_11

 

RO

0x00 0000

10

compare_vlan_id

 

RW

0

9

disable_mask

 

RW

0

8:7

compare_offset

 

RW

0x0

6:0

offset_value

 

RW

0x00

 

gem_gximicrosemi : TYPE2_COMPARE_1_WORD_0

Address offset

0x0708

Physical address

0x2011 0708

Instance

GEM_A_LO

0x2011 2708

GEM_B_LO

0x2811 0708

GEM_A_HI

0x2811 2708

GEM_B_HI

Description

Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

compare_value

 

RW

0x0000

15:0

mask_value

 

RW

0x0000

 

gem_gximicrosemi : TYPE2_COMPARE_1_WORD_1

Address offset

0x070C

Physical address

0x2011 070C

Instance

GEM_A_LO

0x2011 270C

GEM_B_LO

0x2811 070C

GEM_A_HI

0x2811 270C

GEM_B_HI

Description

Type2 Compare Word 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:11

reserved_31_11

 

RO

0x00 0000

10

compare_vlan_id

 

RW

0

9

disable_mask

 

RW

0

8:7

compare_offset

 

RW

0x0

6:0

offset_value

 

RW

0x00

 

gem_gximicrosemi : TYPE2_COMPARE_2_WORD_0

Address offset

0x0710

Physical address

0x2011 0710

Instance

GEM_A_LO

0x2011 2710

GEM_B_LO

0x2811 0710

GEM_A_HI

0x2811 2710

GEM_B_HI

Description

Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

compare_value

 

RW

0x0000

15:0

mask_value

 

RW

0x0000

 

gem_gximicrosemi : TYPE2_COMPARE_2_WORD_1

Address offset

0x0714

Physical address

0x2011 0714

Instance

GEM_A_LO

0x2011 2714

GEM_B_LO

0x2811 0714

GEM_A_HI

0x2811 2714

GEM_B_HI

Description

Type2 Compare Word 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:11

reserved_31_11

 

RO

0x00 0000

10

compare_vlan_id

 

RW

0

9

disable_mask

 

RW

0

8:7

compare_offset

 

RW

0x0

6:0

offset_value

 

RW

0x00

 

gem_gximicrosemi : TYPE2_COMPARE_3_WORD_0

Address offset

0x0718

Physical address

0x2011 0718

Instance

GEM_A_LO

0x2011 2718

GEM_B_LO

0x2811 0718

GEM_A_HI

0x2811 2718

GEM_B_HI

Description

Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

compare_value

 

RW

0x0000

15:0

mask_value

 

RW

0x0000

 

gem_gximicrosemi : TYPE2_COMPARE_3_WORD_1

Address offset

0x071C

Physical address

0x2011 071C

Instance

GEM_A_LO

0x2011 271C

GEM_B_LO

0x2811 071C

GEM_A_HI

0x2811 271C

GEM_B_HI

Description

Type2 Compare Word 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:11

reserved_31_11

 

RO

0x00 0000

10

compare_vlan_id

 

RW

0

9

disable_mask

 

RW

0

8:7

compare_offset

 

RW

0x0

6:0

offset_value

 

RW

0x00

 

gem_gximicrosemi : TYPE2_COMPARE_4_WORD_0

Address offset

0x0720

Physical address

0x2011 0720

Instance

GEM_A_LO

0x2011 2720

GEM_B_LO

0x2811 0720

GEM_A_HI

0x2811 2720

GEM_B_HI

Description

Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

compare_value

 

RW

0x0000

15:0

mask_value

 

RW

0x0000

 

gem_gximicrosemi : TYPE2_COMPARE_4_WORD_1

Address offset

0x0724

Physical address

0x2011 0724

Instance

GEM_A_LO

0x2011 2724

GEM_B_LO

0x2811 0724

GEM_A_HI

0x2811 2724

GEM_B_HI

Description

Type2 Compare Word 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:11

reserved_31_11

 

RO

0x00 0000

10

compare_vlan_id

 

RW

0

9

disable_mask

 

RW

0

8:7

compare_offset

 

RW

0x0

6:0

offset_value

 

RW

0x00

 

gem_gximicrosemi : TYPE2_COMPARE_5_WORD_0

Address offset

0x0728

Physical address

0x2011 0728

Instance

GEM_A_LO

0x2011 2728

GEM_B_LO

0x2811 0728

GEM_A_HI

0x2811 2728

GEM_B_HI

Description

Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

compare_value

 

RW

0x0000

15:0

mask_value

 

RW

0x0000

 

gem_gximicrosemi : TYPE2_COMPARE_5_WORD_1

Address offset

0x072C

Physical address

0x2011 072C

Instance

GEM_A_LO

0x2011 272C

GEM_B_LO

0x2811 072C

GEM_A_HI

0x2811 272C

GEM_B_HI

Description

Type2 Compare Word 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:11

reserved_31_11

 

RO

0x00 0000

10

compare_vlan_id

 

RW

0

9

disable_mask

 

RW

0

8:7

compare_offset

 

RW

0x0

6:0

offset_value

 

RW

0x00

 

gem_gximicrosemi : TYPE2_COMPARE_6_WORD_0

Address offset

0x0730

Physical address

0x2011 0730

Instance

GEM_A_LO

0x2011 2730

GEM_B_LO

0x2811 0730

GEM_A_HI

0x2811 2730

GEM_B_HI

Description

Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

compare_value

 

RW

0x0000

15:0

mask_value

 

RW

0x0000

 

gem_gximicrosemi : TYPE2_COMPARE_6_WORD_1

Address offset

0x0734

Physical address

0x2011 0734

Instance

GEM_A_LO

0x2011 2734

GEM_B_LO

0x2811 0734

GEM_A_HI

0x2811 2734

GEM_B_HI

Description

Type2 Compare Word 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:11

reserved_31_11

 

RO

0x00 0000

10

compare_vlan_id

 

RW

0

9

disable_mask

 

RW

0

8:7

compare_offset

 

RW

0x0

6:0

offset_value

 

RW

0x00

 

gem_gximicrosemi : TYPE2_COMPARE_7_WORD_0

Address offset

0x0738

Physical address

0x2011 0738

Instance

GEM_A_LO

0x2011 2738

GEM_B_LO

0x2811 0738

GEM_A_HI

0x2811 2738

GEM_B_HI

Description

Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

compare_value

 

RW

0x0000

15:0

mask_value

 

RW

0x0000

 

gem_gximicrosemi : TYPE2_COMPARE_7_WORD_1

Address offset

0x073C

Physical address

0x2011 073C

Instance

GEM_A_LO

0x2011 273C

GEM_B_LO

0x2811 073C

GEM_A_HI

0x2811 273C

GEM_B_HI

Description

Type2 Compare Word 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:11

reserved_31_11

 

RO

0x00 0000

10

compare_vlan_id

 

RW

0

9

disable_mask

 

RW

0

8:7

compare_offset

 

RW

0x0

6:0

offset_value

 

RW

0x00

 

gem_gximicrosemi : TYPE2_COMPARE_8_WORD_0

Address offset

0x0740

Physical address

0x2011 0740

Instance

GEM_A_LO

0x2011 2740

GEM_B_LO

0x2811 0740

GEM_A_HI

0x2811 2740

GEM_B_HI

Description

Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

compare_value

 

RW

0x0000

15:0

mask_value

 

RW

0x0000

 

gem_gximicrosemi : TYPE2_COMPARE_8_WORD_1

Address offset

0x0744

Physical address

0x2011 0744

Instance

GEM_A_LO

0x2011 2744

GEM_B_LO

0x2811 0744

GEM_A_HI

0x2811 2744

GEM_B_HI

Description

Type2 Compare Word 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:11

reserved_31_11

 

RO

0x00 0000

10

compare_vlan_id

 

RW

0

9

disable_mask

 

RW

0

8:7

compare_offset

 

RW

0x0

6:0

offset_value

 

RW

0x00

 

gem_gximicrosemi : TYPE2_COMPARE_9_WORD_0

Address offset

0x0748

Physical address

0x2011 0748

Instance

GEM_A_LO

0x2011 2748

GEM_B_LO

0x2811 0748

GEM_A_HI

0x2811 2748

GEM_B_HI

Description

Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

compare_value

 

RW

0x0000

15:0

mask_value

 

RW

0x0000

 

gem_gximicrosemi : TYPE2_COMPARE_9_WORD_1

Address offset

0x074C

Physical address

0x2011 074C

Instance

GEM_A_LO

0x2011 274C

GEM_B_LO

0x2811 074C

GEM_A_HI

0x2811 274C

GEM_B_HI

Description

Type2 Compare Word 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:11

reserved_31_11

 

RO

0x00 0000

10

compare_vlan_id

 

RW

0

9

disable_mask

 

RW

0

8:7

compare_offset

 

RW

0x0

6:0

offset_value

 

RW

0x00

 

gem_gximicrosemi : TYPE2_COMPARE_10_WORD_0

Address offset

0x0750

Physical address

0x2011 0750

Instance

GEM_A_LO

0x2011 2750

GEM_B_LO

0x2811 0750

GEM_A_HI

0x2811 2750

GEM_B_HI

Description

Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

compare_value

 

RW

0x0000

15:0

mask_value

 

RW

0x0000

 

gem_gximicrosemi : TYPE2_COMPARE_10_WORD_1

Address offset

0x0754

Physical address

0x2011 0754

Instance

GEM_A_LO

0x2011 2754

GEM_B_LO

0x2811 0754

GEM_A_HI

0x2811 2754

GEM_B_HI

Description

Type2 Compare Word 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:11

reserved_31_11

 

RO

0x00 0000

10

compare_vlan_id

 

RW

0

9

disable_mask

 

RW

0

8:7

compare_offset

 

RW

0x0

6:0

offset_value

 

RW

0x00

 

gem_gximicrosemi : TYPE2_COMPARE_11_WORD_0

Address offset

0x0758

Physical address

0x2011 0758

Instance

GEM_A_LO

0x2011 2758

GEM_B_LO

0x2811 0758

GEM_A_HI

0x2811 2758

GEM_B_HI

Description

Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

compare_value

 

RW

0x0000

15:0

mask_value

 

RW

0x0000

 

gem_gximicrosemi : TYPE2_COMPARE_11_WORD_1

Address offset

0x075C

Physical address

0x2011 075C

Instance

GEM_A_LO

0x2011 275C

GEM_B_LO

0x2811 075C

GEM_A_HI

0x2811 275C

GEM_B_HI

Description

Type2 Compare Word 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:11

reserved_31_11

 

RO

0x00 0000

10

compare_vlan_id

 

RW

0

9

disable_mask

 

RW

0

8:7

compare_offset

 

RW

0x0

6:0

offset_value

 

RW

0x00

 

gem_gximicrosemi : TYPE2_COMPARE_12_WORD_0

Address offset

0x0760

Physical address

0x2011 0760

Instance

GEM_A_LO

0x2011 2760

GEM_B_LO

0x2811 0760

GEM_A_HI

0x2811 2760

GEM_B_HI

Description

Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

compare_value

 

RW

0x0000

15:0

mask_value

 

RW

0x0000

 

gem_gximicrosemi : TYPE2_COMPARE_12_WORD_1

Address offset

0x0764

Physical address

0x2011 0764

Instance

GEM_A_LO

0x2011 2764

GEM_B_LO

0x2811 0764

GEM_A_HI

0x2811 2764

GEM_B_HI

Description

Type2 Compare Word 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:11

reserved_31_11

 

RO

0x00 0000

10

compare_vlan_id

 

RW

0

9

disable_mask

 

RW

0

8:7

compare_offset

 

RW

0x0

6:0

offset_value

 

RW

0x00

 

gem_gximicrosemi : TYPE2_COMPARE_13_WORD_0

Address offset

0x0768

Physical address

0x2011 0768

Instance

GEM_A_LO

0x2011 2768

GEM_B_LO

0x2811 0768

GEM_A_HI

0x2811 2768

GEM_B_HI

Description

Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

compare_value

 

RW

0x0000

15:0

mask_value

 

RW

0x0000

 

gem_gximicrosemi : TYPE2_COMPARE_13_WORD_1

Address offset

0x076C

Physical address

0x2011 076C

Instance

GEM_A_LO

0x2011 276C

GEM_B_LO

0x2811 076C

GEM_A_HI

0x2811 276C

GEM_B_HI

Description

Type2 Compare Word 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:11

reserved_31_11

 

RO

0x00 0000

10

compare_vlan_id

 

RW

0

9

disable_mask

 

RW

0

8:7

compare_offset

 

RW

0x0

6:0

offset_value

 

RW

0x00

 

gem_gximicrosemi : TYPE2_COMPARE_14_WORD_0

Address offset

0x0770

Physical address

0x2011 0770

Instance

GEM_A_LO

0x2011 2770

GEM_B_LO

0x2811 0770

GEM_A_HI

0x2811 2770

GEM_B_HI

Description

Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

compare_value

 

RW

0x0000

15:0

mask_value

 

RW

0x0000

 

gem_gximicrosemi : TYPE2_COMPARE_14_WORD_1

Address offset

0x0774

Physical address

0x2011 0774

Instance

GEM_A_LO

0x2011 2774

GEM_B_LO

0x2811 0774

GEM_A_HI

0x2811 2774

GEM_B_HI

Description

Type2 Compare Word 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:11

reserved_31_11

 

RO

0x00 0000

10

compare_vlan_id

 

RW

0

9

disable_mask

 

RW

0

8:7

compare_offset

 

RW

0x0

6:0

offset_value

 

RW

0x00

 

gem_gximicrosemi : TYPE2_COMPARE_15_WORD_0

Address offset

0x0778

Physical address

0x2011 0778

Instance

GEM_A_LO

0x2011 2778

GEM_B_LO

0x2811 0778

GEM_A_HI

0x2811 2778

GEM_B_HI

Description

Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

compare_value

 

RW

0x0000

15:0

mask_value

 

RW

0x0000

 

gem_gximicrosemi : TYPE2_COMPARE_15_WORD_1

Address offset

0x077C

Physical address

0x2011 077C

Instance

GEM_A_LO

0x2011 277C

GEM_B_LO

0x2811 077C

GEM_A_HI

0x2811 277C

GEM_B_HI

Description

Type2 Compare Word 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:11

reserved_31_11

 

RO

0x00 0000

10

compare_vlan_id

 

RW

0

9

disable_mask

 

RW

0

8:7

compare_offset

 

RW

0x0

6:0

offset_value

 

RW

0x00

 

gem_gximicrosemi : TYPE2_COMPARE_16_WORD_0

Address offset

0x0780

Physical address

0x2011 0780

Instance

GEM_A_LO

0x2011 2780

GEM_B_LO

0x2811 0780

GEM_A_HI

0x2811 2780

GEM_B_HI

Description

Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

compare_value

 

RW

0x0000

15:0

mask_value

 

RW

0x0000

 

gem_gximicrosemi : TYPE2_COMPARE_16_WORD_1

Address offset

0x0784

Physical address

0x2011 0784

Instance

GEM_A_LO

0x2011 2784

GEM_B_LO

0x2811 0784

GEM_A_HI

0x2811 2784

GEM_B_HI

Description

Type2 Compare Word 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:11

reserved_31_11

 

RO

0x00 0000

10

compare_vlan_id

 

RW

0

9

disable_mask

 

RW

0

8:7

compare_offset

 

RW

0x0

6:0

offset_value

 

RW

0x00

 

gem_gximicrosemi : TYPE2_COMPARE_17_WORD_0

Address offset

0x0788

Physical address

0x2011 0788

Instance

GEM_A_LO

0x2011 2788

GEM_B_LO

0x2811 0788

GEM_A_HI

0x2811 2788

GEM_B_HI

Description

Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

compare_value

 

RW

0x0000

15:0

mask_value

 

RW

0x0000

 

gem_gximicrosemi : TYPE2_COMPARE_17_WORD_1

Address offset

0x078C

Physical address

0x2011 078C

Instance

GEM_A_LO

0x2011 278C

GEM_B_LO

0x2811 078C

GEM_A_HI

0x2811 278C

GEM_B_HI

Description

Type2 Compare Word 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:11

reserved_31_11

 

RO

0x00 0000

10

compare_vlan_id

 

RW

0

9

disable_mask

 

RW

0

8:7

compare_offset

 

RW

0x0

6:0

offset_value

 

RW

0x00

 

gem_gximicrosemi : TYPE2_COMPARE_18_WORD_0

Address offset

0x0790

Physical address

0x2011 0790

Instance

GEM_A_LO

0x2011 2790

GEM_B_LO

0x2811 0790

GEM_A_HI

0x2811 2790

GEM_B_HI

Description

Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

compare_value

 

RW

0x0000

15:0

mask_value

 

RW

0x0000

 

gem_gximicrosemi : TYPE2_COMPARE_18_WORD_1

Address offset

0x0794

Physical address

0x2011 0794

Instance

GEM_A_LO

0x2011 2794

GEM_B_LO

0x2811 0794

GEM_A_HI

0x2811 2794

GEM_B_HI

Description

Type2 Compare Word 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:11

reserved_31_11

 

RO

0x00 0000

10

compare_vlan_id

 

RW

0

9

disable_mask

 

RW

0

8:7

compare_offset

 

RW

0x0

6:0

offset_value

 

RW

0x00

 

gem_gximicrosemi : TYPE2_COMPARE_19_WORD_0

Address offset

0x0798

Physical address

0x2011 0798

Instance

GEM_A_LO

0x2011 2798

GEM_B_LO

0x2811 0798

GEM_A_HI

0x2811 2798

GEM_B_HI

Description

Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

compare_value

 

RW

0x0000

15:0

mask_value

 

RW

0x0000

 

gem_gximicrosemi : TYPE2_COMPARE_19_WORD_1

Address offset

0x079C

Physical address

0x2011 079C

Instance

GEM_A_LO

0x2011 279C

GEM_B_LO

0x2811 079C

GEM_A_HI

0x2811 279C

GEM_B_HI

Description

Type2 Compare Word 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:11

reserved_31_11

 

RO

0x00 0000

10

compare_vlan_id

 

RW

0

9

disable_mask

 

RW

0

8:7

compare_offset

 

RW

0x0

6:0

offset_value

 

RW

0x00

 

gem_gximicrosemi : TYPE2_COMPARE_20_WORD_0

Address offset

0x07A0

Physical address

0x2011 07A0

Instance

GEM_A_LO

0x2011 27A0

GEM_B_LO

0x2811 07A0

GEM_A_HI

0x2811 27A0

GEM_B_HI

Description

Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

compare_value

 

RW

0x0000

15:0

mask_value

 

RW

0x0000

 

gem_gximicrosemi : TYPE2_COMPARE_20_WORD_1

Address offset

0x07A4

Physical address

0x2011 07A4

Instance

GEM_A_LO

0x2011 27A4

GEM_B_LO

0x2811 07A4

GEM_A_HI

0x2811 27A4

GEM_B_HI

Description

Type2 Compare Word 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:11

reserved_31_11

 

RO

0x00 0000

10

compare_vlan_id

 

RW

0

9

disable_mask

 

RW

0

8:7

compare_offset

 

RW

0x0

6:0

offset_value

 

RW

0x00

 

gem_gximicrosemi : TYPE2_COMPARE_21_WORD_0

Address offset

0x07A8

Physical address

0x2011 07A8

Instance

GEM_A_LO

0x2011 27A8

GEM_B_LO

0x2811 07A8

GEM_A_HI

0x2811 27A8

GEM_B_HI

Description

Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

compare_value

 

RW

0x0000

15:0

mask_value

 

RW

0x0000

 

gem_gximicrosemi : TYPE2_COMPARE_21_WORD_1

Address offset

0x07AC

Physical address

0x2011 07AC

Instance

GEM_A_LO

0x2011 27AC

GEM_B_LO

0x2811 07AC

GEM_A_HI

0x2811 27AC

GEM_B_HI

Description

Type2 Compare Word 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:11

reserved_31_11

 

RO

0x00 0000

10

compare_vlan_id

 

RW

0

9

disable_mask

 

RW

0

8:7

compare_offset

 

RW

0x0

6:0

offset_value

 

RW

0x00

 

gem_gximicrosemi : TYPE2_COMPARE_22_WORD_0

Address offset

0x07B0

Physical address

0x2011 07B0

Instance

GEM_A_LO

0x2011 27B0

GEM_B_LO

0x2811 07B0

GEM_A_HI

0x2811 27B0

GEM_B_HI

Description

Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

compare_value

 

RW

0x0000

15:0

mask_value

 

RW

0x0000

 

gem_gximicrosemi : TYPE2_COMPARE_22_WORD_1

Address offset

0x07B4

Physical address

0x2011 07B4

Instance

GEM_A_LO

0x2011 27B4

GEM_B_LO

0x2811 07B4

GEM_A_HI

0x2811 27B4

GEM_B_HI

Description

Type2 Compare Word 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:11

reserved_31_11

 

RO

0x00 0000

10

compare_vlan_id

 

RW

0

9

disable_mask

 

RW

0

8:7

compare_offset

 

RW

0x0

6:0

offset_value

 

RW

0x00

 

gem_gximicrosemi : TYPE2_COMPARE_23_WORD_0

Address offset

0x07B8

Physical address

0x2011 07B8

Instance

GEM_A_LO

0x2011 27B8

GEM_B_LO

0x2811 07B8

GEM_A_HI

0x2811 27B8

GEM_B_HI

Description

Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

compare_value

 

RW

0x0000

15:0

mask_value

 

RW

0x0000

 

gem_gximicrosemi : TYPE2_COMPARE_23_WORD_1

Address offset

0x07BC

Physical address

0x2011 07BC

Instance

GEM_A_LO

0x2011 27BC

GEM_B_LO

0x2811 07BC

GEM_A_HI

0x2811 27BC

GEM_B_HI

Description

Type2 Compare Word 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:11

reserved_31_11

 

RO

0x00 0000

10

compare_vlan_id

 

RW

0

9

disable_mask

 

RW

0

8:7

compare_offset

 

RW

0x0

6:0

offset_value

 

RW

0x00

 

gem_gximicrosemi : TYPE2_COMPARE_24_WORD_0

Address offset

0x07C0

Physical address

0x2011 07C0

Instance

GEM_A_LO

0x2011 27C0

GEM_B_LO

0x2811 07C0

GEM_A_HI

0x2811 27C0

GEM_B_HI

Description

Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

compare_value

 

RW

0x0000

15:0

mask_value

 

RW

0x0000

 

gem_gximicrosemi : TYPE2_COMPARE_24_WORD_1

Address offset

0x07C4

Physical address

0x2011 07C4

Instance

GEM_A_LO

0x2011 27C4

GEM_B_LO

0x2811 07C4

GEM_A_HI

0x2811 27C4

GEM_B_HI

Description

Type2 Compare Word 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:11

reserved_31_11

 

RO

0x00 0000

10

compare_vlan_id

 

RW

0

9

disable_mask

 

RW

0

8:7

compare_offset

 

RW

0x0

6:0

offset_value

 

RW

0x00

 

gem_gximicrosemi : TYPE2_COMPARE_25_WORD_0

Address offset

0x07C8

Physical address

0x2011 07C8

Instance

GEM_A_LO

0x2011 27C8

GEM_B_LO

0x2811 07C8

GEM_A_HI

0x2811 27C8

GEM_B_HI

Description

Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

compare_value

 

RW

0x0000

15:0

mask_value

 

RW

0x0000

 

gem_gximicrosemi : TYPE2_COMPARE_25_WORD_1

Address offset

0x07CC

Physical address

0x2011 07CC

Instance

GEM_A_LO

0x2011 27CC

GEM_B_LO

0x2811 07CC

GEM_A_HI

0x2811 27CC

GEM_B_HI

Description

Type2 Compare Word 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:11

reserved_31_11

 

RO

0x00 0000

10

compare_vlan_id

 

RW

0

9

disable_mask

 

RW

0

8:7

compare_offset

 

RW

0x0

6:0

offset_value

 

RW

0x00

 

gem_gximicrosemi : TYPE2_COMPARE_26_WORD_0

Address offset

0x07D0

Physical address

0x2011 07D0

Instance

GEM_A_LO

0x2011 27D0

GEM_B_LO

0x2811 07D0

GEM_A_HI

0x2811 27D0

GEM_B_HI

Description

Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

compare_value

 

RW

0x0000

15:0

mask_value

 

RW

0x0000

 

gem_gximicrosemi : TYPE2_COMPARE_26_WORD_1

Address offset

0x07D4

Physical address

0x2011 07D4

Instance

GEM_A_LO

0x2011 27D4

GEM_B_LO

0x2811 07D4

GEM_A_HI

0x2811 27D4

GEM_B_HI

Description

Type2 Compare Word 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:11

reserved_31_11

 

RO

0x00 0000

10

compare_vlan_id

 

RW

0

9

disable_mask

 

RW

0

8:7

compare_offset

 

RW

0x0

6:0

offset_value

 

RW

0x00

 

gem_gximicrosemi : TYPE2_COMPARE_27_WORD_0

Address offset

0x07D8

Physical address

0x2011 07D8

Instance

GEM_A_LO

0x2011 27D8

GEM_B_LO

0x2811 07D8

GEM_A_HI

0x2811 27D8

GEM_B_HI

Description

Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

compare_value

 

RW

0x0000

15:0

mask_value

 

RW

0x0000

 

gem_gximicrosemi : TYPE2_COMPARE_27_WORD_1

Address offset

0x07DC

Physical address

0x2011 07DC

Instance

GEM_A_LO

0x2011 27DC

GEM_B_LO

0x2811 07DC

GEM_A_HI

0x2811 27DC

GEM_B_HI

Description

Type2 Compare Word 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:11

reserved_31_11

 

RO

0x00 0000

10

compare_vlan_id

 

RW

0

9

disable_mask

 

RW

0

8:7

compare_offset

 

RW

0x0

6:0

offset_value

 

RW

0x00

 

gem_gximicrosemi : TYPE2_COMPARE_28_WORD_0

Address offset

0x07E0

Physical address

0x2011 07E0

Instance

GEM_A_LO

0x2011 27E0

GEM_B_LO

0x2811 07E0

GEM_A_HI

0x2811 27E0

GEM_B_HI

Description

Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

compare_value

 

RW

0x0000

15:0

mask_value

 

RW

0x0000

 

gem_gximicrosemi : TYPE2_COMPARE_28_WORD_1

Address offset

0x07E4

Physical address

0x2011 07E4

Instance

GEM_A_LO

0x2011 27E4

GEM_B_LO

0x2811 07E4

GEM_A_HI

0x2811 27E4

GEM_B_HI

Description

Type2 Compare Word 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:11

reserved_31_11

 

RO

0x00 0000

10

compare_vlan_id

 

RW

0

9

disable_mask

 

RW

0

8:7

compare_offset

 

RW

0x0

6:0

offset_value

 

RW

0x00

 

gem_gximicrosemi : TYPE2_COMPARE_29_WORD_0

Address offset

0x07E8

Physical address

0x2011 07E8

Instance

GEM_A_LO

0x2011 27E8

GEM_B_LO

0x2811 07E8

GEM_A_HI

0x2811 27E8

GEM_B_HI

Description

Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

compare_value

 

RW

0x0000

15:0

mask_value

 

RW

0x0000

 

gem_gximicrosemi : TYPE2_COMPARE_29_WORD_1

Address offset

0x07EC

Physical address

0x2011 07EC

Instance

GEM_A_LO

0x2011 27EC

GEM_B_LO

0x2811 07EC

GEM_A_HI

0x2811 27EC

GEM_B_HI

Description

Type2 Compare Word 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:11

reserved_31_11

 

RO

0x00 0000

10

compare_vlan_id

 

RW

0

9

disable_mask

 

RW

0

8:7

compare_offset

 

RW

0x0

6:0

offset_value

 

RW

0x00

 

gem_gximicrosemi : TYPE2_COMPARE_30_WORD_0

Address offset

0x07F0

Physical address

0x2011 07F0

Instance

GEM_A_LO

0x2011 27F0

GEM_B_LO

0x2811 07F0

GEM_A_HI

0x2811 27F0

GEM_B_HI

Description

Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

compare_value

 

RW

0x0000

15:0

mask_value

 

RW

0x0000

 

gem_gximicrosemi : TYPE2_COMPARE_30_WORD_1

Address offset

0x07F4

Physical address

0x2011 07F4

Instance

GEM_A_LO

0x2011 27F4

GEM_B_LO

0x2811 07F4

GEM_A_HI

0x2811 27F4

GEM_B_HI

Description

Type2 Compare Word 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:11

reserved_31_11

 

RO

0x00 0000

10

compare_vlan_id

 

RW

0

9

disable_mask

 

RW

0

8:7

compare_offset

 

RW

0x0

6:0

offset_value

 

RW

0x00

 

gem_gximicrosemi : TYPE2_COMPARE_31_WORD_0

Address offset

0x07F8

Physical address

0x2011 07F8

Instance

GEM_A_LO

0x2011 27F8

GEM_B_LO

0x2811 07F8

GEM_A_HI

0x2811 27F8

GEM_B_HI

Description

Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

compare_value

 

RW

0x0000

15:0

mask_value

 

RW

0x0000

 

gem_gximicrosemi : TYPE2_COMPARE_31_WORD_1

Address offset

0x07FC

Physical address

0x2011 07FC

Instance

GEM_A_LO

0x2011 27FC

GEM_B_LO

0x2811 07FC

GEM_A_HI

0x2811 27FC

GEM_B_HI

Description

Type2 Compare Word 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:11

reserved_31_11

 

RO

0x00 0000

10

compare_vlan_id

 

RW

0

9

disable_mask

 

RW

0

8:7

compare_offset

 

RW

0x0

6:0

offset_value

 

RW

0x00

 

gem_gximicrosemi : ENST_START_TIME_Q8

Address offset

0x0800

Physical address

0x2011 0800

Instance

GEM_A_LO

0x2011 2800

GEM_B_LO

0x2811 0800

GEM_A_HI

0x2811 2800

GEM_B_HI

Description

This register sets the absolute time at which queue q8 starts EnST transmit scheduling

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:30

start_time_sec

 

RW

0x0

29:0

start_time_nsec

 

RW

0x0000 0000

 

gem_gximicrosemi : ENST_START_TIME_Q9

Address offset

0x0804

Physical address

0x2011 0804

Instance

GEM_A_LO

0x2011 2804

GEM_B_LO

0x2811 0804

GEM_A_HI

0x2811 2804

GEM_B_HI

Description

This register sets the absolute time at which queue q9 starts EnST transmit scheduling

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:30

start_time_sec

 

RW

0x0

29:0

start_time_nsec

 

RW

0x0000 0000

 

gem_gximicrosemi : ENST_START_TIME_Q10

Address offset

0x0808

Physical address

0x2011 0808

Instance

GEM_A_LO

0x2011 2808

GEM_B_LO

0x2811 0808

GEM_A_HI

0x2811 2808

GEM_B_HI

Description

This register sets the absolute time at which queue q10 starts EnST transmit scheduling

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:30

start_time_sec

 

RW

0x0

29:0

start_time_nsec

 

RW

0x0000 0000

 

gem_gximicrosemi : ENST_START_TIME_Q11

Address offset

0x080C

Physical address

0x2011 080C

Instance

GEM_A_LO

0x2011 280C

GEM_B_LO

0x2811 080C

GEM_A_HI

0x2811 280C

GEM_B_HI

Description

This register sets the absolute time at which queue q11 starts EnST transmit scheduling

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:30

start_time_sec

 

RW

0x0

29:0

start_time_nsec

 

RW

0x0000 0000

 

gem_gximicrosemi : ENST_START_TIME_Q12

Address offset

0x0810

Physical address

0x2011 0810

Instance

GEM_A_LO

0x2011 2810

GEM_B_LO

0x2811 0810

GEM_A_HI

0x2811 2810

GEM_B_HI

Description

This register sets the absolute time at which queue q12 starts EnST transmit scheduling

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:30

start_time_sec

 

RW

0x0

29:0

start_time_nsec

 

RW

0x0000 0000

 

gem_gximicrosemi : ENST_START_TIME_Q13

Address offset

0x0814

Physical address

0x2011 0814

Instance

GEM_A_LO

0x2011 2814

GEM_B_LO

0x2811 0814

GEM_A_HI

0x2811 2814

GEM_B_HI

Description

This register sets the absolute time at which queue q13 starts EnST transmit scheduling

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:30

start_time_sec

 

RW

0x0

29:0

start_time_nsec

 

RW

0x0000 0000

 

gem_gximicrosemi : ENST_START_TIME_Q14

Address offset

0x0818

Physical address

0x2011 0818

Instance

GEM_A_LO

0x2011 2818

GEM_B_LO

0x2811 0818

GEM_A_HI

0x2811 2818

GEM_B_HI

Description

This register sets the absolute time at which queue q14 starts EnST transmit scheduling

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:30

start_time_sec

 

RW

0x0

29:0

start_time_nsec

 

RW

0x0000 0000

 

gem_gximicrosemi : ENST_START_TIME_Q15

Address offset

0x081C

Physical address

0x2011 081C

Instance

GEM_A_LO

0x2011 281C

GEM_B_LO

0x2811 081C

GEM_A_HI

0x2811 281C

GEM_B_HI

Description

This register sets the absolute time at which queue q15 starts EnST transmit scheduling

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:30

start_time_sec

 

RW

0x0

29:0

start_time_nsec

 

RW

0x0000 0000

 

gem_gximicrosemi : ENST_ON_TIME_Q8

Address offset

0x0820

Physical address

0x2011 0820

Instance

GEM_A_LO

0x2011 2820

GEM_B_LO

0x2811 0820

GEM_A_HI

0x2811 2820

GEM_B_HI

Description

This register sets the time period for which queue q8 is to be open, (on_time_nsec), this register has to be written according to the speed mode as:, : ||1Gbps or 2.5Gbps|| : on_time = on_time_nsec/8, : ||100Mbps|| : on_time = on_time_nsec/80, : ||10Mbps|| : on_time = on_time_nsec/800

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:17

reserved_31_17

 

RO

0x0000

16:0

on_time

 

RW

0x1 FFFF

 

G5SOC_MSS_REGMAP : gem_gximicrosemi : ENST_ON_TIME_Q9

Address offset

0x0824

Physical address

0x2011 0824

Instance

GEM_A_LO

0x2011 2824

GEM_B_LO

0x2811 0824

GEM_A_HI

0x2811 2824

GEM_B_HI

Description

This register sets the time period for which queue q9 is to be open, (on_time_nsec), this register has to be written according to the speed mode as:, : ||1Gbps or 2.5Gbps|| : on_time = on_time_nsec/8, : ||100Mbps|| : on_time = on_time_nsec/80, : ||10Mbps|| : on_time = on_time_nsec/800

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:17

reserved_31_17

 

RO

0x0000

16:0

on_time

 

RW

0x1 FFFF

 

gem_gximicrosemi : ENST_ON_TIME_Q10

Address offset

0x0828

Physical address

0x2011 0828

Instance

GEM_A_LO

0x2011 2828

GEM_B_LO

0x2811 0828

GEM_A_HI

0x2811 2828

GEM_B_HI

Description

This register sets the time period for which queue q10 is to be open, (on_time_nsec), this register has to be written according to the speed mode as:, : ||1Gbps or 2.5Gbps|| : on_time = on_time_nsec/8, : ||100Mbps|| : on_time = on_time_nsec/80, : ||10Mbps|| : on_time = on_time_nsec/800

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:17

reserved_31_17

 

RO

0x0000

16:0

on_time

 

RW

0x1 FFFF

 

gem_gximicrosemi : ENST_ON_TIME_Q11

Address offset

0x082C

Physical address

0x2011 082C

Instance

GEM_A_LO

0x2011 282C

GEM_B_LO

0x2811 082C

GEM_A_HI

0x2811 282C

GEM_B_HI

Description

This register sets the time period for which queue q11 is to be open, (on_time_nsec), this register has to be written according to the speed mode as:, : ||1Gbps or 2.5Gbps|| : on_time = on_time_nsec/8, : ||100Mbps|| : on_time = on_time_nsec/80, : ||10Mbps|| : on_time = on_time_nsec/800

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:17

reserved_31_17

 

RO

0x0000

16:0

on_time

 

RW

0x1 FFFF

 

gem_gximicrosemi : ENST_ON_TIME_Q12

Address offset

0x0830

Physical address

0x2011 0830

Instance

GEM_A_LO

0x2011 2830

GEM_B_LO

0x2811 0830

GEM_A_HI

0x2811 2830

GEM_B_HI

Description

This register sets the time period for which queue q12 is to be open, (on_time_nsec), this register has to be written according to the speed mode as:, : ||1Gbps or 2.5Gbps|| : on_time = on_time_nsec/8, : ||100Mbps|| : on_time = on_time_nsec/80, : ||10Mbps|| : on_time = on_time_nsec/800

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:17

reserved_31_17

 

RO

0x0000

16:0

on_time

 

RW

0x1 FFFF

 

gem_gximicrosemi : ENST_ON_TIME_Q13

Address offset

0x0834

Physical address

0x2011 0834

Instance

GEM_A_LO

0x2011 2834

GEM_B_LO

0x2811 0834

GEM_A_HI

0x2811 2834

GEM_B_HI

Description

This register sets the time period for which queue q13 is to be open, (on_time_nsec), this register has to be written according to the speed mode as:, : ||1Gbps or 2.5Gbps|| : on_time = on_time_nsec/8, : ||100Mbps|| : on_time = on_time_nsec/80, : ||10Mbps|| : on_time = on_time_nsec/800

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:17

reserved_31_17

 

RO

0x0000

16:0

on_time

 

RW

0x1 FFFF

 

gem_gximicrosemi : ENST_ON_TIME_Q14

Address offset

0x0838

Physical address

0x2011 0838

Instance

GEM_A_LO

0x2011 2838

GEM_B_LO

0x2811 0838

GEM_A_HI

0x2811 2838

GEM_B_HI

Description

This register sets the time period for which queue q14 is to be open, (on_time_nsec), this register has to be written according to the speed mode as:, : ||1Gbps or 2.5Gbps|| : on_time = on_time_nsec/8, : ||100Mbps|| : on_time = on_time_nsec/80, : ||10Mbps|| : on_time = on_time_nsec/800

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:17

reserved_31_17

 

RO

0x0000

16:0

on_time

 

RW

0x1 FFFF

 

gem_gximicrosemi : ENST_ON_TIME_Q15

Address offset

0x083C

Physical address

0x2011 083C

Instance

GEM_A_LO

0x2011 283C

GEM_B_LO

0x2811 083C

GEM_A_HI

0x2811 283C

GEM_B_HI

Description

This register sets the time period for which queue q15 is to be open, (on_time_nsec), this register has to be written according to the speed mode as:, : ||1Gbps or 2.5Gbps|| : on_time = on_time_nsec/8, : ||100Mbps|| : on_time = on_time_nsec/80, : ||10Mbps|| : on_time = on_time_nsec/800

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:17

reserved_31_17

 

RO

0x0000

16:0

on_time

 

RW

0x1 FFFF

 

gem_gximicrosemi : ENST_OFF_TIME_Q8

Address offset

0x0840

Physical address

0x2011 0840

Instance

GEM_A_LO

0x2011 2840

GEM_B_LO

0x2811 0840

GEM_A_HI

0x2811 2840

GEM_B_HI

Description

This register sets the time period for which queue q8 is to be blocked, (off_time_nsec), this register has to be written according to the speed mode as:, : ||1Gbps or 2.5Gbps|| => off_time = off_time_nsec/8, : ||100Mbps|| => off_time = off_time_nsec/80, : ||10Mbps|| => off_time = off_time_nsec/800

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:17

reserved_31_17

 

RO

0x0000

16:0

off_time

 

RW

0x0 0000

 

gem_gximicrosemi : ENST_OFF_TIME_Q9

Address offset

0x0844

Physical address

0x2011 0844

Instance

GEM_A_LO

0x2011 2844

GEM_B_LO

0x2811 0844

GEM_A_HI

0x2811 2844

GEM_B_HI

Description

This register sets the time period for which queue q9 is to be blocked, (off_time_nsec), this register has to be written according to the speed mode as:, : ||1Gbps or 2.5Gbps|| => off_time = off_time_nsec/8, : ||100Mbps|| => off_time = off_time_nsec/80, : ||10Mbps|| => off_time = off_time_nsec/800

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:17

reserved_31_17

 

RO

0x0000

16:0

off_time

 

RW

0x0 0000

 

gem_gximicrosemi : ENST_OFF_TIME_Q10

Address offset

0x0848

Physical address

0x2011 0848

Instance

GEM_A_LO

0x2011 2848

GEM_B_LO

0x2811 0848

GEM_A_HI

0x2811 2848

GEM_B_HI

Description

This register sets the time period for which queue q10 is to be blocked, (off_time_nsec), this register has to be written according to the speed mode as:, : ||1Gbps or 2.5Gbps|| => off_time = off_time_nsec/8, : ||100Mbps|| => off_time = off_time_nsec/80, : ||10Mbps|| => off_time = off_time_nsec/800

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:17

reserved_31_17

 

RO

0x0000

16:0

off_time

 

RW

0x0 0000

 

gem_gximicrosemi : ENST_OFF_TIME_Q11

Address offset

0x084C

Physical address

0x2011 084C

Instance

GEM_A_LO

0x2011 284C

GEM_B_LO

0x2811 084C

GEM_A_HI

0x2811 284C

GEM_B_HI

Description

This register sets the time period for which queue q11 is to be blocked, (off_time_nsec), this register has to be written according to the speed mode as:, : ||1Gbps or 2.5Gbps|| => off_time = off_time_nsec/8, : ||100Mbps|| => off_time = off_time_nsec/80, : ||10Mbps|| => off_time = off_time_nsec/800

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:17

reserved_31_17

 

RO

0x0000

16:0

off_time

 

RW

0x0 0000

 

gem_gximicrosemi : ENST_OFF_TIME_Q12

Address offset

0x0850

Physical address

0x2011 0850

Instance

GEM_A_LO

0x2011 2850

GEM_B_LO

0x2811 0850

GEM_A_HI

0x2811 2850

GEM_B_HI

Description

This register sets the time period for which queue q12 is to be blocked, (off_time_nsec), this register has to be written according to the speed mode as:, : ||1Gbps or 2.5Gbps|| => off_time = off_time_nsec/8, : ||100Mbps|| => off_time = off_time_nsec/80, : ||10Mbps|| => off_time = off_time_nsec/800

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:17

reserved_31_17

 

RO

0x0000

16:0

off_time

 

RW

0x0 0000

 

gem_gximicrosemi : ENST_OFF_TIME_Q13

Address offset

0x0854

Physical address

0x2011 0854

Instance

GEM_A_LO

0x2011 2854

GEM_B_LO

0x2811 0854

GEM_A_HI

0x2811 2854

GEM_B_HI

Description

This register sets the time period for which queue q13 is to be blocked, (off_time_nsec), this register has to be written according to the speed mode as:, : ||1Gbps or 2.5Gbps|| => off_time = off_time_nsec/8, : ||100Mbps|| => off_time = off_time_nsec/80, : ||10Mbps|| => off_time = off_time_nsec/800

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:17

reserved_31_17

 

RO

0x0000

16:0

off_time

 

RW

0x0 0000

 

gem_gximicrosemi : ENST_OFF_TIME_Q14

Address offset

0x0858

Physical address

0x2011 0858

Instance

GEM_A_LO

0x2011 2858

GEM_B_LO

0x2811 0858

GEM_A_HI

0x2811 2858

GEM_B_HI

Description

This register sets the time period for which queue q14 is to be blocked, (off_time_nsec), this register has to be written according to the speed mode as:, : ||1Gbps or 2.5Gbps|| => off_time = off_time_nsec/8, : ||100Mbps|| => off_time = off_time_nsec/80, : ||10Mbps|| => off_time = off_time_nsec/800

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:17

reserved_31_17

 

RO

0x0000

16:0

off_time

 

RW

0x0 0000

 

gem_gximicrosemi : ENST_OFF_TIME_Q15

Address offset

0x085C

Physical address

0x2011 085C

Instance

GEM_A_LO

0x2011 285C

GEM_B_LO

0x2811 085C

GEM_A_HI

0x2811 285C

GEM_B_HI

Description

This register sets the time period for which queue q15 is to be blocked, (off_time_nsec), this register has to be written according to the speed mode as:, : ||1Gbps or 2.5Gbps|| => off_time = off_time_nsec/8, : ||100Mbps|| => off_time = off_time_nsec/80, : ||10Mbps|| => off_time = off_time_nsec/800

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:17

reserved_31_17

 

RO

0x0000

16:0

off_time

 

RW

0x0 0000

 

gem_gximicrosemi : ENST_CONTROL

Address offset

0x0880

Physical address

0x2011 0880

Instance

GEM_A_LO

0x2011 2880

GEM_B_LO

0x2811 0880

GEM_A_HI

0x2811 2880

GEM_B_HI

Description

Enhancement for Scheduled Traffic control register. EnST scheduling can only be applied to a maximum number of 8 queues. If 802.3br operation has been configured and both an eMAC and pMAC are present then the eMAC only supports a single queue and EnST is enabled on the eMAC by writing to bit 0 of emac_enst_control.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:8

reserved_31_8

 

RO

0x00 0000

7

enst_enable_q15

 

RW

0

6

enst_enable_q14

 

RW

0

5

enst_enable_q13

 

RW

0

4

enst_enable_q12

 

RW

0

3

enst_enable_q11

 

RW

0

2

enst_enable_q10

 

RW

0

1

enst_enable_q9

 

RW

0

0

enst_enable_q8

 

RW

0

 

gem_gximicrosemi : RX_Q0_FLUSH

Address offset

0x0B00

Physical address

0x2011 0B00

Instance

GEM_A_LO

0x2011 2B00

GEM_B_LO

0x2811 0B00

GEM_A_HI

0x2811 2B00

GEM_B_HI

Description

Receive Queue flush register. This register defines the traffic policing mode of operation. Each mode can be set simultaneously with the exception of bits 2 and 3, which are exclusive. If bits 2 and 3 are both set then only bit 3 is treated as active.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

max_val

 

RW

0x0000

15:4

reserved_15_4

 

RO

0x000

3

limit_frame_size

 

RW

0

2

limit_num_bytes

 

RW

0

1

drop_on_resource_err

 

RW

0

0

drop_all_frames

 

RW

0

 

gem_gximicrosemi : RX_Q1_FLUSH

Address offset

0x0B04

Physical address

0x2011 0B04

Instance

GEM_A_LO

0x2011 2B04

GEM_B_LO

0x2811 0B04

GEM_A_HI

0x2811 2B04

GEM_B_HI

Description

Receive Queue flush register. This register defines the traffic policing mode of operation. Each mode can be set simultaneously with the exception of bits 2 and 3, which are exclusive. If bits 2 and 3 are both set then only bit 3 is treated as active.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

max_val

 

RW

0x0000

15:4

reserved_15_4

 

RO

0x000

3

limit_frame_size

 

RW

0

2

limit_num_bytes

 

RW

0

1

drop_on_resource_err

 

RW

0

0

drop_all_frames

 

RW

0

 

gem_gximicrosemi : RX_Q2_FLUSH

Address offset

0x0B08

Physical address

0x2011 0B08

Instance

GEM_A_LO

0x2011 2B08

GEM_B_LO

0x2811 0B08

GEM_A_HI

0x2811 2B08

GEM_B_HI

Description

Receive Queue flush register. This register defines the traffic policing mode of operation. Each mode can be set simultaneously with the exception of bits 2 and 3, which are exclusive. If bits 2 and 3 are both set then only bit 3 is treated as active.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

max_val

 

RW

0x0000

15:4

reserved_15_4

 

RO

0x000

3

limit_frame_size

 

RW

0

2

limit_num_bytes

 

RW

0

1

drop_on_resource_err

 

RW

0

0

drop_all_frames

 

RW

0

 

gem_gximicrosemi : RX_Q3_FLUSH

Address offset

0x0B0C

Physical address

0x2011 0B0C

Instance

GEM_A_LO

0x2011 2B0C

GEM_B_LO

0x2811 0B0C

GEM_A_HI

0x2811 2B0C

GEM_B_HI

Description

Receive Queue flush register. This register defines the traffic policing mode of operation. Each mode can be set simultaneously with the exception of bits 2 and 3, which are exclusive. If bits 2 and 3 are both set then only bit 3 is treated as active.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

max_val

 

RW

0x0000

15:4

reserved_15_4

 

RO

0x000

3

limit_frame_size

 

RW

0

2

limit_num_bytes

 

RW

0

1

drop_on_resource_err

 

RW

0

0

drop_all_frames

 

RW

0

 

gem_gximicrosemi : RX_Q4_FLUSH

Address offset

0x0B10

Physical address

0x2011 0B10

Instance

GEM_A_LO

0x2011 2B10

GEM_B_LO

0x2811 0B10

GEM_A_HI

0x2811 2B10

GEM_B_HI

Description

Receive Queue flush register. This register defines the traffic policing mode of operation. Each mode can be set simultaneously with the exception of bits 2 and 3, which are exclusive. If bits 2 and 3 are both set then only bit 3 is treated as active.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

max_val

 

RW

0x0000

15:4

reserved_15_4

 

RO

0x000

3

limit_frame_size

 

RW

0

2

limit_num_bytes

 

RW

0

1

drop_on_resource_err

 

RW

0

0

drop_all_frames

 

RW

0

 

gem_gximicrosemi : RX_Q5_FLUSH

Address offset

0x0B14

Physical address

0x2011 0B14

Instance

GEM_A_LO

0x2011 2B14

GEM_B_LO

0x2811 0B14

GEM_A_HI

0x2811 2B14

GEM_B_HI

Description

Receive Queue flush register. This register defines the traffic policing mode of operation. Each mode can be set simultaneously with the exception of bits 2 and 3, which are exclusive. If bits 2 and 3 are both set then only bit 3 is treated as active.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

max_val

 

RW

0x0000

15:4

reserved_15_4

 

RO

0x000

3

limit_frame_size

 

RW

0

2

limit_num_bytes

 

RW

0

1

drop_on_resource_err

 

RW

0

0

drop_all_frames

 

RW

0

 

gem_gximicrosemi : RX_Q6_FLUSH

Address offset

0x0B18

Physical address

0x2011 0B18

Instance

GEM_A_LO

0x2011 2B18

GEM_B_LO

0x2811 0B18

GEM_A_HI

0x2811 2B18

GEM_B_HI

Description

Receive Queue flush register. This register defines the traffic policing mode of operation. Each mode can be set simultaneously with the exception of bits 2 and 3, which are exclusive. If bits 2 and 3 are both set then only bit 3 is treated as active.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

max_val

 

RW

0x0000

15:4

reserved_15_4

 

RO

0x000

3

limit_frame_size

 

RW

0

2

limit_num_bytes

 

RW

0

1

drop_on_resource_err

 

RW

0

0

drop_all_frames

 

RW

0

 

gem_gximicrosemi : RX_Q7_FLUSH

Address offset

0x0B1C

Physical address

0x2011 0B1C

Instance

GEM_A_LO

0x2011 2B1C

GEM_B_LO

0x2811 0B1C

GEM_A_HI

0x2811 2B1C

GEM_B_HI

Description

Receive Queue flush register. This register defines the traffic policing mode of operation. Each mode can be set simultaneously with the exception of bits 2 and 3, which are exclusive. If bits 2 and 3 are both set then only bit 3 is treated as active.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

max_val

 

RW

0x0000

15:4

reserved_15_4

 

RO

0x000

3

limit_frame_size

 

RW

0

2

limit_num_bytes

 

RW

0

1

drop_on_resource_err

 

RW

0

0

drop_all_frames

 

RW

0

 

gem_gximicrosemi : RX_Q8_FLUSH

Address offset

0x0B20

Physical address

0x2011 0B20

Instance

GEM_A_LO

0x2011 2B20

GEM_B_LO

0x2811 0B20

GEM_A_HI

0x2811 2B20

GEM_B_HI

Description

Receive Queue flush register. This register defines the traffic policing mode of operation. Each mode can be set simultaneously with the exception of bits 2 and 3, which are exclusive. If bits 2 and 3 are both set then only bit 3 is treated as active.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

max_val

 

RW

0x0000

15:4

reserved_15_4

 

RO

0x000

3

limit_frame_size

 

RW

0

2

limit_num_bytes

 

RW

0

1

drop_on_resource_err

 

RW

0

0

drop_all_frames

 

RW

0

 

gem_gximicrosemi : RX_Q9_FLUSH

Address offset

0x0B24

Physical address

0x2011 0B24

Instance

GEM_A_LO

0x2011 2B24

GEM_B_LO

0x2811 0B24

GEM_A_HI

0x2811 2B24

GEM_B_HI

Description

Receive Queue flush register. This register defines the traffic policing mode of operation. Each mode can be set simultaneously with the exception of bits 2 and 3, which are exclusive. If bits 2 and 3 are both set then only bit 3 is treated as active.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

max_val

 

RW

0x0000

15:4

reserved_15_4

 

RO

0x000

3

limit_frame_size

 

RW

0

2

limit_num_bytes

 

RW

0

1

drop_on_resource_err

 

RW

0

0

drop_all_frames

 

RW

0

 

gem_gximicrosemi : RX_Q10_FLUSH

Address offset

0x0B28

Physical address

0x2011 0B28

Instance

GEM_A_LO

0x2011 2B28

GEM_B_LO

0x2811 0B28

GEM_A_HI

0x2811 2B28

GEM_B_HI

Description

Receive Queue flush register. This register defines the traffic policing mode of operation. Each mode can be set simultaneously with the exception of bits 2 and 3, which are exclusive. If bits 2 and 3 are both set then only bit 3 is treated as active.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

max_val

 

RW

0x0000

15:4

reserved_15_4

 

RO

0x000

3

limit_frame_size

 

RW

0

2

limit_num_bytes

 

RW

0

1

drop_on_resource_err

 

RW

0

0

drop_all_frames

 

RW

0

 

gem_gximicrosemi : RX_Q11_FLUSH

Address offset

0x0B2C

Physical address

0x2011 0B2C

Instance

GEM_A_LO

0x2011 2B2C

GEM_B_LO

0x2811 0B2C

GEM_A_HI

0x2811 2B2C

GEM_B_HI

Description

Receive Queue flush register. This register defines the traffic policing mode of operation. Each mode can be set simultaneously with the exception of bits 2 and 3, which are exclusive. If bits 2 and 3 are both set then only bit 3 is treated as active.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

max_val

 

RW

0x0000

15:4

reserved_15_4

 

RO

0x000

3

limit_frame_size

 

RW

0

2

limit_num_bytes

 

RW

0

1

drop_on_resource_err

 

RW

0

0

drop_all_frames

 

RW

0

 

gem_gximicrosemi : RX_Q12_FLUSH

Address offset

0x0B30

Physical address

0x2011 0B30

Instance

GEM_A_LO

0x2011 2B30

GEM_B_LO

0x2811 0B30

GEM_A_HI

0x2811 2B30

GEM_B_HI

Description

Receive Queue flush register. This register defines the traffic policing mode of operation. Each mode can be set simultaneously with the exception of bits 2 and 3, which are exclusive. If bits 2 and 3 are both set then only bit 3 is treated as active.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

max_val

 

RW

0x0000

15:4

reserved_15_4

 

RO

0x000

3

limit_frame_size

 

RW

0

2

limit_num_bytes

 

RW

0

1

drop_on_resource_err

 

RW

0

0

drop_all_frames

 

RW

0

 

gem_gximicrosemi : RX_Q13_FLUSH

Address offset

0x0B34

Physical address

0x2011 0B34

Instance

GEM_A_LO

0x2011 2B34

GEM_B_LO

0x2811 0B34

GEM_A_HI

0x2811 2B34

GEM_B_HI

Description

Receive Queue flush register. This register defines the traffic policing mode of operation. Each mode can be set simultaneously with the exception of bits 2 and 3, which are exclusive. If bits 2 and 3 are both set then only bit 3 is treated as active.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

max_val

 

RW

0x0000

15:4

reserved_15_4

 

RO

0x000

3

limit_frame_size

 

RW

0

2

limit_num_bytes

 

RW

0

1

drop_on_resource_err

 

RW

0

0

drop_all_frames

 

RW

0

 

gem_gximicrosemi : RX_Q14_FLUSH

Address offset

0x0B38

Physical address

0x2011 0B38

Instance

GEM_A_LO

0x2011 2B38

GEM_B_LO

0x2811 0B38

GEM_A_HI

0x2811 2B38

GEM_B_HI

Description

Receive Queue flush register. This register defines the traffic policing mode of operation. Each mode can be set simultaneously with the exception of bits 2 and 3, which are exclusive. If bits 2 and 3 are both set then only bit 3 is treated as active.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

max_val

 

RW

0x0000

15:4

reserved_15_4

 

RO

0x000

3

limit_frame_size

 

RW

0

2

limit_num_bytes

 

RW

0

1

drop_on_resource_err

 

RW

0

0

drop_all_frames

 

RW

0

 

gem_gximicrosemi : RX_Q15_FLUSH

Address offset

0x0B3C

Physical address

0x2011 0B3C

Instance

GEM_A_LO

0x2011 2B3C

GEM_B_LO

0x2811 0B3C

GEM_A_HI

0x2811 2B3C

GEM_B_HI

Description

Receive Queue flush register. This register defines the traffic policing mode of operation. Each mode can be set simultaneously with the exception of bits 2 and 3, which are exclusive. If bits 2 and 3 are both set then only bit 3 is treated as active.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

max_val

 

RW

0x0000

15:4

reserved_15_4

 

RO

0x000

3

limit_frame_size

 

RW

0

2

limit_num_bytes

 

RW

0

1

drop_on_resource_err

 

RW

0

0

drop_all_frames

 

RW

0

 

gem_gximicrosemi : SCR2_REG0_RATE_LIMIT

Address offset

0x0B40

Physical address

0x2011 0B40

Instance

GEM_A_LO

0x2011 2B40

GEM_B_LO

0x2811 0B40

GEM_A_HI

0x2811 2B40

GEM_B_HI

Description

Screener type 2 maximum rate register. This register defines the maximum receive rate for the corresponding type 2 screener. This is a traffic policing function and is relevant to the 802.1Qci standard. If the maximum rate is exceeded all frames matched by the corresponding type 2 screener will be discarded until the receive rate falls below the specified value.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

max_rate_val

 

RW

0x0000

15:0

interval_time

 

RW

0x0000

 

gem_gximicrosemi : SCR2_REG1_RATE_LIMIT

Address offset

0x0B44

Physical address

0x2011 0B44

Instance

GEM_A_LO

0x2011 2B44

GEM_B_LO

0x2811 0B44

GEM_A_HI

0x2811 2B44

GEM_B_HI

Description

Screener type 2 maximum rate register. This register defines the maximum receive rate for the corresponding type 2 screener. This is a traffic policing function and is relevant to the 802.1Qci standard. If the maximum rate is exceeded all frames matched by the corresponding type 2 screener will be discarded until the receive rate falls below the specified value.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

max_rate_val

 

RW

0x0000

15:0

interval_time

 

RW

0x0000

 

gem_gximicrosemi : SCR2_REG2_RATE_LIMIT

Address offset

0x0B48

Physical address

0x2011 0B48

Instance

GEM_A_LO

0x2011 2B48

GEM_B_LO

0x2811 0B48

GEM_A_HI

0x2811 2B48

GEM_B_HI

Description

Screener type 2 maximum rate register. This register defines the maximum receive rate for the corresponding type 2 screener. This is a traffic policing function and is relevant to the 802.1Qci standard. If the maximum rate is exceeded all frames matched by the corresponding type 2 screener will be discarded until the receive rate falls below the specified value.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

max_rate_val

 

RW

0x0000

15:0

interval_time

 

RW

0x0000

 

gem_gximicrosemi : SCR2_REG3_RATE_LIMIT

Address offset

0x0B4C

Physical address

0x2011 0B4C

Instance

GEM_A_LO

0x2011 2B4C

GEM_B_LO

0x2811 0B4C

GEM_A_HI

0x2811 2B4C

GEM_B_HI

Description

Screener type 2 maximum rate register. This register defines the maximum receive rate for the corresponding type 2 screener. This is a traffic policing function and is relevant to the 802.1Qci standard. If the maximum rate is exceeded all frames matched by the corresponding type 2 screener will be discarded until the receive rate falls below the specified value.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

max_rate_val

 

RW

0x0000

15:0

interval_time

 

RW

0x0000

 

gem_gximicrosemi : SCR2_REG4_RATE_LIMIT

Address offset

0x0B50

Physical address

0x2011 0B50

Instance

GEM_A_LO

0x2011 2B50

GEM_B_LO

0x2811 0B50

GEM_A_HI

0x2811 2B50

GEM_B_HI

Description

Screener type 2 maximum rate register. This register defines the maximum receive rate for the corresponding type 2 screener. This is a traffic policing function and is relevant to the 802.1Qci standard. If the maximum rate is exceeded all frames matched by the corresponding type 2 screener will be discarded until the receive rate falls below the specified value.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

max_rate_val

 

RW

0x0000

15:0

interval_time

 

RW

0x0000

 

gem_gximicrosemi : SCR2_REG5_RATE_LIMIT

Address offset

0x0B54

Physical address

0x2011 0B54

Instance

GEM_A_LO

0x2011 2B54

GEM_B_LO

0x2811 0B54

GEM_A_HI

0x2811 2B54

GEM_B_HI

Description

Screener type 2 maximum rate register. This register defines the maximum receive rate for the corresponding type 2 screener. This is a traffic policing function and is relevant to the 802.1Qci standard. If the maximum rate is exceeded all frames matched by the corresponding type 2 screener will be discarded until the receive rate falls below the specified value.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

max_rate_val

 

RW

0x0000

15:0

interval_time

 

RW

0x0000

 

gem_gximicrosemi : SCR2_REG6_RATE_LIMIT

Address offset

0x0B58

Physical address

0x2011 0B58

Instance

GEM_A_LO

0x2011 2B58

GEM_B_LO

0x2811 0B58

GEM_A_HI

0x2811 2B58

GEM_B_HI

Description

Screener type 2 maximum rate register. This register defines the maximum receive rate for the corresponding type 2 screener. This is a traffic policing function and is relevant to the 802.1Qci standard. If the maximum rate is exceeded all frames matched by the corresponding type 2 screener will be discarded until the receive rate falls below the specified value.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

max_rate_val

 

RW

0x0000

15:0

interval_time

 

RW

0x0000

 

gem_gximicrosemi : SCR2_REG7_RATE_LIMIT

Address offset

0x0B5C

Physical address

0x2011 0B5C

Instance

GEM_A_LO

0x2011 2B5C

GEM_B_LO

0x2811 0B5C

GEM_A_HI

0x2811 2B5C

GEM_B_HI

Description

Screener type 2 maximum rate register. This register defines the maximum receive rate for the corresponding type 2 screener. This is a traffic policing function and is relevant to the 802.1Qci standard. If the maximum rate is exceeded all frames matched by the corresponding type 2 screener will be discarded until the receive rate falls below the specified value.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

max_rate_val

 

RW

0x0000

15:0

interval_time

 

RW

0x0000

 

gem_gximicrosemi : SCR2_REG8_RATE_LIMIT

Address offset

0x0B60

Physical address

0x2011 0B60

Instance

GEM_A_LO

0x2011 2B60

GEM_B_LO

0x2811 0B60

GEM_A_HI

0x2811 2B60

GEM_B_HI

Description

Screener type 2 maximum rate register. This register defines the maximum receive rate for the corresponding type 2 screener. This is a traffic policing function and is relevant to the 802.1Qci standard. If the maximum rate is exceeded all frames matched by the corresponding type 2 screener will be discarded until the receive rate falls below the specified value.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

max_rate_val

 

RW

0x0000

15:0

interval_time

 

RW

0x0000

 

gem_gximicrosemi : SCR2_REG9_RATE_LIMIT

Address offset

0x0B64

Physical address

0x2011 0B64

Instance

GEM_A_LO

0x2011 2B64

GEM_B_LO

0x2811 0B64

GEM_A_HI

0x2811 2B64

GEM_B_HI

Description

Screener type 2 maximum rate register. This register defines the maximum receive rate for the corresponding type 2 screener. This is a traffic policing function and is relevant to the 802.1Qci standard. If the maximum rate is exceeded all frames matched by the corresponding type 2 screener will be discarded until the receive rate falls below the specified value.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

max_rate_val

 

RW

0x0000

15:0

interval_time

 

RW

0x0000

 

gem_gximicrosemi : SCR2_REG10_RATE_LIMIT

Address offset

0x0B68

Physical address

0x2011 0B68

Instance

GEM_A_LO

0x2011 2B68

GEM_B_LO

0x2811 0B68

GEM_A_HI

0x2811 2B68

GEM_B_HI

Description

Screener type 2 maximum rate register. This register defines the maximum receive rate for the corresponding type 2 screener. This is a traffic policing function and is relevant to the 802.1Qci standard. If the maximum rate is exceeded all frames matched by the corresponding type 2 screener will be discarded until the receive rate falls below the specified value.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

max_rate_val

 

RW

0x0000

15:0

interval_time

 

RW

0x0000

 

gem_gximicrosemi : SCR2_REG11_RATE_LIMIT

Address offset

0x0B6C

Physical address

0x2011 0B6C

Instance

GEM_A_LO

0x2011 2B6C

GEM_B_LO

0x2811 0B6C

GEM_A_HI

0x2811 2B6C

GEM_B_HI

Description

Screener type 2 maximum rate register. This register defines the maximum receive rate for the corresponding type 2 screener. This is a traffic policing function and is relevant to the 802.1Qci standard. If the maximum rate is exceeded all frames matched by the corresponding type 2 screener will be discarded until the receive rate falls below the specified value.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

max_rate_val

 

RW

0x0000

15:0

interval_time

 

RW

0x0000

 

gem_gximicrosemi : SCR2_REG12_RATE_LIMIT

Address offset

0x0B70

Physical address

0x2011 0B70

Instance

GEM_A_LO

0x2011 2B70

GEM_B_LO

0x2811 0B70

GEM_A_HI

0x2811 2B70

GEM_B_HI

Description

Screener type 2 maximum rate register. This register defines the maximum receive rate for the corresponding type 2 screener. This is a traffic policing function and is relevant to the 802.1Qci standard. If the maximum rate is exceeded all frames matched by the corresponding type 2 screener will be discarded until the receive rate falls below the specified value.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

max_rate_val

 

RW

0x0000

15:0

interval_time

 

RW

0x0000

 

gem_gximicrosemi : SCR2_REG13_RATE_LIMIT

Address offset

0x0B74

Physical address

0x2011 0B74

Instance

GEM_A_LO

0x2011 2B74

GEM_B_LO

0x2811 0B74

GEM_A_HI

0x2811 2B74

GEM_B_HI

Description

Screener type 2 maximum rate register. This register defines the maximum receive rate for the corresponding type 2 screener. This is a traffic policing function and is relevant to the 802.1Qci standard. If the maximum rate is exceeded all frames matched by the corresponding type 2 screener will be discarded until the receive rate falls below the specified value.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

max_rate_val

 

RW

0x0000

15:0

interval_time

 

RW

0x0000

 

gem_gximicrosemi : SCR2_REG14_RATE_LIMIT

Address offset

0x0B78

Physical address

0x2011 0B78

Instance

GEM_A_LO

0x2011 2B78

GEM_B_LO

0x2811 0B78

GEM_A_HI

0x2811 2B78

GEM_B_HI

Description

Screener type 2 maximum rate register. This register defines the maximum receive rate for the corresponding type 2 screener. This is a traffic policing function and is relevant to the 802.1Qci standard. If the maximum rate is exceeded all frames matched by the corresponding type 2 screener will be discarded until the receive rate falls below the specified value.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

max_rate_val

 

RW

0x0000

15:0

interval_time

 

RW

0x0000

 

gem_gximicrosemi : SCR2_REG15_RATE_LIMIT

Address offset

0x0B7C

Physical address

0x2011 0B7C

Instance

GEM_A_LO

0x2011 2B7C

GEM_B_LO

0x2811 0B7C

GEM_A_HI

0x2811 2B7C

GEM_B_HI

Description

Screener type 2 maximum rate register. This register defines the maximum receive rate for the corresponding type 2 screener. This is a traffic policing function and is relevant to the 802.1Qci standard. If the maximum rate is exceeded all frames matched by the corresponding type 2 screener will be discarded until the receive rate falls below the specified value.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

max_rate_val

 

RW

0x0000

15:0

interval_time

 

RW

0x0000

 

gem_gximicrosemi : SCR2_RATE_STATUS

Address offset

0x0B80

Physical address

0x2011 0B80

Instance

GEM_A_LO

0x2011 2B80

GEM_B_LO

0x2811 0B80

GEM_A_HI

0x2811 2B80

GEM_B_HI

Description

Screener rate limit exceeded status register. For each screener type 2 register configured a status bit will be set and cleared on read if the maximum receive rate is exceeded.

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:16

reserved_31_16

 

RO

0x0000

15

scr2_15_excess_rate

 

RO
RtoClr

0

14

scr2_14_excess_rate

 

RO
RtoClr

0

13

scr2_13_excess_rate

 

RO
RtoClr

0

12

scr2_12_excess_rate

 

RO
RtoClr

0

11

scr2_11_excess_rate

 

RO
RtoClr

0

10

scr2_10_excess_rate

 

RO
RtoClr

0

9

scr2_9_excess_rate

 

RO
RtoClr

0

8

scr2_8_excess_rate

 

RO
RtoClr

0

7

scr2_7_excess_rate

 

RO
RtoClr

0

6

scr2_6_excess_rate

 

RO
RtoClr

0

5

scr2_5_excess_rate

 

RO
RtoClr

0

4

scr2_4_excess_rate

 

RO
RtoClr

0

3

scr2_3_excess_rate

 

RO
RtoClr

0

2

scr2_2_excess_rate

 

RO
RtoClr

0

1

scr2_1_excess_rate

 

RO
RtoClr

0

0

scr2_0_excess_rate

 

RO
RtoClr

0

 

gem_gximicrosemi : ASF_INT_STATUS

Address offset

0x0E00

Physical address

0x2011 0E00

Instance

GEM_A_LO

0x2011 2E00

GEM_B_LO

0x2811 0E00

GEM_A_HI

0x2811 2E00

GEM_B_HI

Description

ASF Interrupt Status Register. This register indicates the source of ASF interrupts. The corresponding bit in the mask register must be clear for a bit to be set. If any bit is set in this register the asf_fatal or asf_nonfatal signal will be asserted. Writing to either raw or masked status registers, clear both registers. For test purposes, trigger signal interrupt event by writing to the ASF interrupt status test register.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:7

reserved_31_7

 

RO

0x000 0000

6

reserved_6

 

RO

0

5

asf_protocol_err

 

RW
W1toClr

0

4

asf_trans_to_err

 

RW
W1toClr

0

3

reserved_3

 

RO

0

2

reserved_2

 

RO

0

1:0

reserved_1_0

 

RO

0x0

 

gem_gximicrosemi : ASF_INT_RAW_STATUS

Address offset

0x0E04

Physical address

0x2011 0E04

Instance

GEM_A_LO

0x2011 2E04

GEM_B_LO

0x2811 0E04

GEM_A_HI

0x2811 2E04

GEM_B_HI

Description

ASF Interrupt Raw Status Register. A bit set in this raw register indicates a source of ASF fault in the corresponding feature. Writing to either raw or masked status registers, clear both registers. For test purposes, trigger signal interrupt event by writing to the ASF interrupt status test register.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:7

reserved_31_7

 

RO

0x000 0000

6

reserved_6

 

RO

0

5

asf_protocol_err

 

RW
W1toClr

0

4

asf_trans_to_err

 

RW
W1toClr

0

3

reserved_3

 

RO

0

2

reserved_2

 

RO

0

1:0

reserved_1_0

 

RO

0x0

 

gem_gximicrosemi : ASF_INT_MASK

Address offset

0x0E08

Physical address

0x2011 0E08

Instance

GEM_A_LO

0x2011 2E08

GEM_B_LO

0x2811 0E08

GEM_A_HI

0x2811 2E08

GEM_B_HI

Description

The ASF interrupt mask register indicating which interrupt bits in the ASF interrupt status register are masked. All bits are set at reset. Clear the individual bit to enable the corresponding interrupt.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:7

reserved_31_7

 

RO

0x000 0000

6

reserved_6

 

RO

0

5

asf_protocol_err_mask

 

RW

1

4

asf_trans_to_err_mask

 

RW

1

3

reserved_3

 

RO

0

2

reserved_2

 

RO

0

1:0

reserved_1_0

 

RO

0x0

 

gem_gximicrosemi : ASF_INT_TEST

Address offset

0x0E0C

Physical address

0x2011 0E0C

Instance

GEM_A_LO

0x2011 2E0C

GEM_B_LO

0x2811 0E0C

GEM_A_HI

0x2811 2E0C

GEM_B_HI

Description

The ASF interrupt test register emulate hardware even. Write one to individual bit to trigger single event in (masked and raw) status registers according to mask and will generate interrupt accordingly.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:7

reserved_31_7

 

RO

0x000 0000

6

reserved_6

 

RO

0

5

asf_protocol_err_test

 

WO

0

4

asf_trans_to_err_test

 

WO

0

3

reserved_3

 

RO

0

2

reserved_2

 

RO

0

1:0

reserved_1_0

 

RO

0x0

 

gem_gximicrosemi : ASF_FATAL_NONFATAL_SELECT

Address offset

0x0E10

Physical address

0x2011 0E10

Instance

GEM_A_LO

0x2011 2E10

GEM_B_LO

0x2811 0E10

GEM_A_HI

0x2811 2E10

GEM_B_HI

Description

The fatal or non-fatal interrupt register selects whether a fatal (asf_int_fatal) or non-fatal (asf_int_nonfatal) interrupt is triggered. If the bit of the event will be set to one then fatal interrupt (asf_int_fatal) will be triggered. Otherwise the non-fatal interrupt (asf_int_nonfatal) will be triggered.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:7

reserved_31_7

 

RO

0x000 0000

6

reserved_6

 

RO

0

5

asf_protocol_err

 

RW

1

4

asf_trans_to_err

 

RW

1

3

reserved_3

 

RO

0

2

reserved_2

 

RO

0

1:0

reserved_1_0

 

RO

0x0

 

gem_gximicrosemi : ASF_TRANS_TO_FAULT_MASK

Address offset

0x0E34

Physical address

0x2011 0E34

Instance

GEM_A_LO

0x2011 2E34

GEM_B_LO

0x2811 0E34

GEM_A_HI

0x2811 2E34

GEM_B_HI

Description

Control register to mask out ASF transaction timeout faults from triggering interrupts. On reset, all bits are set to mask out all sources. Clear the corresponding bit to enable the interrupt source.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:5

reserved_31_5

 

RO

0x000 0000

4

reserved_4

 

RO

0

3

dma_rx_to_mask

 

RW

1

2

dma_tx_to_mask

 

RW

1

1

mac_rx_to_mask

 

RW

1

0

mac_tx_to_mask

 

RW

1

 

gem_gximicrosemi : ASF_TRANS_TO_FAULT_STATUS

Address offset

0x0E38

Physical address

0x2011 0E38

Instance

GEM_A_LO

0x2011 2E38

GEM_B_LO

0x2811 0E38

GEM_A_HI

0x2811 2E38

GEM_B_HI

Description

Status register for transaction timeouts fault. If a fault occurs the revelant status bit will be set to 1. Each bit can be cleared by software writing 1 to each bit.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:5

reserved_31_5

 

RO

0x000 0000

4

reserved_4

 

RO

0

3

dma_rx_to_status

 

RW
W1toClr

0

2

dma_tx_to_status

 

RW
W1toClr

0

1

mac_rx_to_status

 

RW
W1toClr

0

0

mac_tx_to_status

 

RW
W1toClr

0

 

gem_gximicrosemi : ASF_PROTOCOL_FAULT_MASK

Address offset

0x0E40

Physical address

0x2011 0E40

Instance

GEM_A_LO

0x2011 2E40

GEM_B_LO

0x2811 0E40

GEM_A_HI

0x2811 2E40

GEM_B_HI

Description

Control register to mask out ASF Protocol faults from triggering interrupts. On reset, all bits are set to mask out all sources. Clear the corresponding bit to enable the interrupt source.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:22

reserved_31_22

 

RO

0x000

21

rx_dma_pkt_flush_mask

 

RW

1

20

rx_overflow_mask

 

RW

1

19

rx_hresp_err_mask

 

RW

1

18

tx_hresp_err_mask

 

RW

1

17

tx_buff_ex_mid_mask

 

RW

1

16

tx_underrun_mask

 

RW

1

15:9

reserved_15_9

 

RO

0x00

8

tx_too_many_retries_mask

 

RW

1

7

rx_udp_ck_err_mask

 

RW

1

6

rx_tcp_ck_err_mask

 

RW

1

5

rx_ip_ck_err_mask

 

RW

1

4

rx_length_err_mask

 

RW

1

3

rx_symbol_err_mask

 

RW

1

2

rx_long_err_mask

 

RW

1

1

rx_short_err_mask

 

RW

1

0

rx_crc_err_mask

 

RW

1

 

gem_gximicrosemi : ASF_PROTOCOL_FAULT_STATUS

Address offset

0x0E44

Physical address

0x2011 0E44

Instance

GEM_A_LO

0x2011 2E44

GEM_B_LO

0x2811 0E44

GEM_A_HI

0x2811 2E44

GEM_B_HI

Description

Status register for protocol faults. If a fault occurs the revelant status bit will be set to 1. Each bit can be cleared by software writing 1 to each bit

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:22

reserved_31_22

 

RO

0x000

21

rx_dma_pkt_flush_status

 

RW
W1toClr

0

20

rx_overflow_status

 

RW
W1toClr

0

19

rx_hresp_err_status

 

RW
W1toClr

0

18

tx_hresp_err_status

 

RW
W1toClr

0

17

tx_buff_ex_mid_status

 

RW
W1toClr

0

16

tx_underrun_status

 

RW
W1toClr

0

15:9

reserved_15_9

 

RO

0x00

8

tx_too_many_retries_status

 

RW
W1toClr

0

7

rx_udp_ck_err_status

 

RW
W1toClr

0

6

rx_tcp_ck_err_status

 

RW
W1toClr

0

5

rx_ip_ck_err_status

 

RW
W1toClr

0

4

rx_length_err_status

 

RW
W1toClr

0

3

rx_symbol_err_status

 

RW
W1toClr

0

2

rx_long_err_status

 

RW
W1toClr

0

1

rx_short_err_status

 

RW
W1toClr

0

0

rx_crc_err_status

 

RW
W1toClr

0

 

gem_gximicrosemi has no common memories.