Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

H2FINT_ENABLE

RW

32

0x0000 0000

0x000

H2FSTATUS

RO

32

0x0000 0000

0x004

PLSTATUS0

RO

32

0x0000 0000

0x010

PLSTATUS1

RO

32

0x0000 0000

0x014

PLSTATUS2

RO

32

0x0000 0000

0x018

PLSTATUS3

RO

32

0x0000 0000

0x01C

PLENABLE0

RW

32

0x0000 0000

0x020

PLENABLE1

RW

32

0x0000 0000

0x024

PLENABLE2

RW

32

0x0000 0000

0x028

PLENABLE3

RW

32

0x0000 0000

0x02C

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

H2FINT_ENABLE

RW

32

0x0000 0000

0x000

0x2012 6000

H2FSTATUS

RO

32

0x0000 0000

0x004

0x2012 6004

PLSTATUS0

RO

32

0x0000 0000

0x010

0x2012 6010

PLSTATUS1

RO

32

0x0000 0000

0x014

0x2012 6014

PLSTATUS2

RO

32

0x0000 0000

0x018

0x2012 6018

PLSTATUS3

RO

32

0x0000 0000

0x01C

0x2012 601C

PLENABLE0

RW

32

0x0000 0000

0x020

0x2012 6020

PLENABLE1

RW

32

0x0000 0000

0x024

0x2012 6024

PLENABLE2

RW

32

0x0000 0000

0x028

0x2012 6028

PLENABLE3

RW

32

0x0000 0000

0x02C

0x2012 602C

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

H2FINT_ENABLE

RW

32

0x0000 0000

0x000

0x2812 6000

H2FSTATUS

RO

32

0x0000 0000

0x004

0x2812 6004

PLSTATUS0

RO

32

0x0000 0000

0x010

0x2812 6010

PLSTATUS1

RO

32

0x0000 0000

0x014

0x2812 6014

PLSTATUS2

RO

32

0x0000 0000

0x018

0x2812 6018

PLSTATUS3

RO

32

0x0000 0000

0x01C

0x2812 601C

PLENABLE0

RW

32

0x0000 0000

0x020

0x2812 6020

PLENABLE1

RW

32

0x0000 0000

0x024

0x2812 6024

PLENABLE2

RW

32

0x0000 0000

0x028

0x2812 6028

PLENABLE3

RW

32

0x0000 0000

0x02C

0x2812 602C

Address offset

0x000

Physical address

0x2012 6000

Instance

H2FINT_LO

0x2812 6000

H2FINT_HI

Description

Type

RW

31:16

HENABLE

Enables individual H2F outputs

RW

0x0000

15:1

Reserved

RO
Rreturns0s

0x0000

0

GENABLE

Enables all the H2FINT outputs

RW

0

Address offset

0x004

Physical address

0x2012 6004

Instance

H2FINT_LO

0x2812 6004

H2FINT_HI

Description

Type

RO

31:16

Reserved

RO
Rreturns0s

0x0000

15:0

H2FSTATUS

Read back of the 16-bit H2F Interrupts before the H2F and global enable

RO

0x0000

Address offset

0x010

Physical address

0x2012 6010

Instance

H2FINT_LO

0x2812 6010

H2FINT_HI

Description

Type

RO

31:0

PLSTATUS0

Indicates that the PLINT interrupt is active before the PLINT enable i.e. direct read of the PLINT inputs [31:0]

RO

0x0000 0000

Address offset

0x014

Physical address

0x2012 6014

Instance

H2FINT_LO

0x2812 6014

H2FINT_HI

Description

Type

RO

31:0

PLSTATUS1

Indicates that the PLIT interrupt is active before the PLINT enable i.e. direct read of the PLINT inputs [63:32]

RO

0x0000 0000

Address offset

0x018

Physical address

0x2012 6018

Instance

H2FINT_LO

0x2812 6018

H2FINT_HI

Description

Type

RO

31:0

PLSTATUS2

Indicates that the PLIT interrupt is active before the PLINT enable i.e. direct read of the PLINT inputs [95:64]

RO

0x0000 0000

Address offset

0x01C

Physical address

0x2012 601C

Instance

H2FINT_LO

0x2812 601C

H2FINT_HI

Description

Type

RO

31:0

PLSTATUS3

Indicates that the PLINT interrupt is active before the PLINT enable i.e. direct read of the PLINT inputs [127:96]

RO

0x0000 0000

Address offset

0x020

Physical address

0x2012 6020

Instance

H2FINT_LO

0x2812 6020

H2FINT_HI

Description

Type

RW

31:0

PLENABLE0

Enables PLINT interrupts 31:0

RW

0x0000 0000

Address offset

0x024

Physical address

0x2012 6024

Instance

H2FINT_LO

0x2812 6024

H2FINT_HI

Description

Type

RW

31:0

PLENABLE1

Enables PLINT interrupts 63:32

RW

0x0000 0000

Address offset

0x028

Physical address

0x2012 6028

Instance

H2FINT_LO

0x2812 6028

H2FINT_HI

Description

Type

RW

31:0

PLENABLE2

Enables PLINT interrupts 95:64

RW

0x0000 0000

Address offset

0x02C

Physical address

0x2012 602C

Instance

H2FINT_LO

0x2812 602C

H2FINT_HI

Description

Type

RW

31:0

PLENABLE3

Enables PLINT interrupts 127:96

RW

0x0000 0000