This section
provides information on the MSRTC Module Instance. Each of the module registers
is described below.
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
RW |
32 |
0x0000 0000 |
0x000 |
|
RW |
32 |
0x0000 0000 |
0x004 |
|
RW |
32 |
0x0000 0000 |
0x008 |
|
RW |
32 |
0x0000 0000 |
0x00C |
|
RW |
32 |
0x0000 0000 |
0x010 |
|
RW |
32 |
0x0000 0000 |
0x014 |
|
RW |
32 |
0x0000 0000 |
0x018 |
|
RW |
32 |
0x0000 0000 |
0x020 |
|
RW |
32 |
0x0000 0000 |
0x024 |
|
RW |
32 |
0x0000 0000 |
0x030 |
|
RW |
32 |
0x0000 0000 |
0x034 |
|
RW |
32 |
0x0000 0000 |
0x038 |
|
RW |
32 |
0x0000 0000 |
0x03C |
|
RW |
32 |
0x0000 0000 |
0x040 |
|
RW |
32 |
0x0000 0000 |
0x044 |
|
RW |
32 |
0x0000 0000 |
0x048 |
|
RW |
32 |
0x0000 0000 |
0x04C |
|
RW |
32 |
0x0000 0000 |
0x050 |
|
RW |
32 |
0x0000 0000 |
0x054 |
|
RW |
32 |
0x0000 0000 |
0x058 |
|
RW |
32 |
0x0000 0000 |
0x05C |
|
RW |
32 |
0x0000 0000 |
0x060 |
|
RW |
32 |
0x0000 0000 |
0x064 |
|
RW |
32 |
0x0000 0000 |
0x068 |
|
RW |
32 |
0x0000 0000 |
0x06C |
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x000 |
0x2012 4000 |
|
RW |
32 |
0x0000 0000 |
0x004 |
0x2012 4004 |
|
RW |
32 |
0x0000 0000 |
0x008 |
0x2012 4008 |
|
RW |
32 |
0x0000 0000 |
0x00C |
0x2012 400C |
|
RW |
32 |
0x0000 0000 |
0x010 |
0x2012 4010 |
|
RW |
32 |
0x0000 0000 |
0x014 |
0x2012 4014 |
|
RW |
32 |
0x0000 0000 |
0x018 |
0x2012 4018 |
|
RW |
32 |
0x0000 0000 |
0x020 |
0x2012 4020 |
|
RW |
32 |
0x0000 0000 |
0x024 |
0x2012 4024 |
|
RW |
32 |
0x0000 0000 |
0x030 |
0x2012 4030 |
|
RW |
32 |
0x0000 0000 |
0x034 |
0x2012 4034 |
|
RW |
32 |
0x0000 0000 |
0x038 |
0x2012 4038 |
|
RW |
32 |
0x0000 0000 |
0x03C |
0x2012 403C |
|
RW |
32 |
0x0000 0000 |
0x040 |
0x2012 4040 |
|
RW |
32 |
0x0000 0000 |
0x044 |
0x2012 4044 |
|
RW |
32 |
0x0000 0000 |
0x048 |
0x2012 4048 |
|
RW |
32 |
0x0000 0000 |
0x04C |
0x2012 404C |
|
RW |
32 |
0x0000 0000 |
0x050 |
0x2012 4050 |
|
RW |
32 |
0x0000 0000 |
0x054 |
0x2012 4054 |
|
RW |
32 |
0x0000 0000 |
0x058 |
0x2012 4058 |
|
RW |
32 |
0x0000 0000 |
0x05C |
0x2012 405C |
|
RW |
32 |
0x0000 0000 |
0x060 |
0x2012 4060 |
|
RW |
32 |
0x0000 0000 |
0x064 |
0x2012 4064 |
|
RW |
32 |
0x0000 0000 |
0x068 |
0x2012 4068 |
|
RW |
32 |
0x0000 0000 |
0x06C |
0x2012 406C |
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x000 |
0x2812 4000 |
|
RW |
32 |
0x0000 0000 |
0x004 |
0x2812 4004 |
|
RW |
32 |
0x0000 0000 |
0x008 |
0x2812 4008 |
|
RW |
32 |
0x0000 0000 |
0x00C |
0x2812 400C |
|
RW |
32 |
0x0000 0000 |
0x010 |
0x2812 4010 |
|
RW |
32 |
0x0000 0000 |
0x014 |
0x2812 4014 |
|
RW |
32 |
0x0000 0000 |
0x018 |
0x2812 4018 |
|
RW |
32 |
0x0000 0000 |
0x020 |
0x2812 4020 |
|
RW |
32 |
0x0000 0000 |
0x024 |
0x2812 4024 |
|
RW |
32 |
0x0000 0000 |
0x030 |
0x2812 4030 |
|
RW |
32 |
0x0000 0000 |
0x034 |
0x2812 4034 |
|
RW |
32 |
0x0000 0000 |
0x038 |
0x2812 4038 |
|
RW |
32 |
0x0000 0000 |
0x03C |
0x2812 403C |
|
RW |
32 |
0x0000 0000 |
0x040 |
0x2812 4040 |
|
RW |
32 |
0x0000 0000 |
0x044 |
0x2812 4044 |
|
RW |
32 |
0x0000 0000 |
0x048 |
0x2812 4048 |
|
RW |
32 |
0x0000 0000 |
0x04C |
0x2812 404C |
|
RW |
32 |
0x0000 0000 |
0x050 |
0x2812 4050 |
|
RW |
32 |
0x0000 0000 |
0x054 |
0x2812 4054 |
|
RW |
32 |
0x0000 0000 |
0x058 |
0x2812 4058 |
|
RW |
32 |
0x0000 0000 |
0x05C |
0x2812 405C |
|
RW |
32 |
0x0000 0000 |
0x060 |
0x2812 4060 |
|
RW |
32 |
0x0000 0000 |
0x064 |
0x2812 4064 |
|
RW |
32 |
0x0000 0000 |
0x068 |
0x2812 4068 |
|
RW |
32 |
0x0000 0000 |
0x06C |
0x2812 406C |
Address offset |
0x000 |
||
Physical address |
0x2012 4000 |
Instance |
MSRTC_LO |
0x2812 4000 |
MSRTC_HI |
||
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:11 |
Reserved |
|
RO |
0x00 0000 |
10 |
Updated |
1:when RTC counter updates the RTC value.It is cleared by
the writing '1' to the bit |
RW |
0 |
9 |
Wakeup_set |
1:Assert the rtc_wakeup output and set the wakeup status
bit. |
WO |
0 |
8 |
Wakeup_clear |
Set every time a match occurs.1:wakeup_clear bit is
cleared. Once cleared it will not be set again until the next wakeup occurs |
RW |
0 |
7 |
Match |
RTC value matches with wakeup value. Indicates rtc_match
output value. |
RO |
0 |
6 |
Download |
1: Current RTC counter value to be downloaded |
WO |
0 |
5 |
Upload |
1: Date/time value loaded into date/time registers and
uploaded to the RTC counters |
RW |
0 |
4 |
Reset |
1:date/time value is reset and uploaded to RTC counters |
WO |
0 |
3 |
Alarm_off |
1:Alarm is disabled |
RW |
0 |
2 |
Alarm_on |
1:Alarm is enabled |
RW |
0 |
1 |
Stop |
When stop bit is written '1', RTC counter is stopped. Read
indicates that RTC is running |
RW |
0 |
0 |
Start |
When start bit is written '1',indicates that RTC counter
is started. Read indicates that RTC counter is running. |
RW |
0 |
Address offset |
0x004 |
||
Physical address |
0x2012 4004 |
Instance |
MSRTC_LO |
0x2812 4004 |
MSRTC_HI |
||
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:5 |
Reserved |
|
RO |
0x000 0000 |
4 |
Wake_reset_ps |
when a wakeup occurs reset the pre-scaler |
RW |
0 |
3 |
Wake_continue |
when a wakeup occurs continue counting |
RW |
0 |
2 |
Wake_reset |
when a wakeup occurs reset the RTC counters |
RW |
0 |
1 |
Wake_enable |
Enables the wakeup output |
RW |
0 |
0 |
Clock_mode |
0: Binary counter 1: date and time counting |
RW |
0 |
Address offset |
0x008 |
||
Physical address |
0x2012 4008 |
Instance |
MSRTC_LO |
0x2812 4008 |
MSRTC_HI |
||
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:26 |
Reserved |
|
RO |
0x00 |
25:0 |
Prescaler |
value to divide incoming rtc clock. It should be set to
achieve 1Hz from rtc_clk. Value must be greater than 1. Value = Clock
Frequency - 1Hz |
RW |
0x000 0000 |
Address offset |
0x00C |
||
Physical address |
0x2012 400C |
Instance |
MSRTC_LO |
0x2812 400C |
MSRTC_HI |
||
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
Alarm_lower |
Write: Sets the alarm wakeup time. Read: Returns the alarm
time. Binary count [31:0] |
RW |
0x0000 0000 |
Address offset |
0x010 |
||
Physical address |
0x2012 4010 |
Instance |
MSRTC_LO |
0x2812 4010 |
MSRTC_HI |
||
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:11 |
Reserved |
|
RW |
0x00 0000 |
10:0 |
Alarm_upper |
Write: sets the alarm wakeup time. Read: returns the alarm
time. Binary count [42:32] |
RW |
0x000 |
Address offset |
0x014 |
||
Physical address |
0x2012 4014 |
Instance |
MSRTC_LO |
0x2812 4014 |
MSRTC_HI |
||
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
Compare_lower |
Write: sets the compare bits on the alarm time. [7:0]:
Seconds, [15:8]: Minutres, [23:16]: Hours, [31:24]:Day. Read: Returns the
compare value. 0: Bit is ignored. 1: Bit is compared. |
RW |
0x0000 0000 |
Address offset |
0x018 |
||
Physical address |
0x2012 4018 |
Instance |
MSRTC_LO |
0x2812 4018 |
MSRTC_HI |
||
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:30 |
Reserved |
|
RW |
0x0 |
29:0 |
Compare_upper |
Write: sets the compare bits on the alarm time. [7:0]:
Month, [15:8]: Year, [23:16]: Weekday, [29:24]:Week. Read: Returns the
compare value. 0: Bit is ignored. 1: Bit is compared. |
RW |
0x0000 0000 |
Address offset |
0x020 |
||
Physical address |
0x2012 4020 |
Instance |
MSRTC_LO |
0x2812 4020 |
MSRTC_HI |
||
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
Datetime_Lower |
Writes: Data to be uploaded to counter. Read: returns the
current time. [7:0]: Seconds, [15:8]: Minutres, [23:16]: Hours, [31:24]:Day. |
RW |
0x0000 0000 |
Address offset |
0x024 |
||
Physical address |
0x2012 4024 |
Instance |
MSRTC_LO |
0x2812 4024 |
MSRTC_HI |
||
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:30 |
Reserved |
|
RW |
0x0 |
29:0 |
Datetime_Upper |
Writes: Data to be uploaded to counter. Read: returns the
upper time bits that are in alignment with the last read lower bits.[7:0]:
Month, [15:8]: Year, [23:16]: Weekday, [29:24]:Week. |
RW |
0x0000 0000 |
Address offset |
0x030 |
||
Physical address |
0x2012 4030 |
Instance |
MSRTC_LO |
0x2812 4030 |
MSRTC_HI |
||
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:6 |
Reserved |
|
RO |
0x000 0000 |
5:0 |
Seconds |
The complete RTC data is read and stored internally. For
writes all fields (0x30-x4c) must be written. The control register upload bit
will upload data to the RTC.These registers are for use when clock_mode=1 |
RW |
0x00 |
Address offset |
0x034 |
||
Physical address |
0x2012 4034 |
Instance |
MSRTC_LO |
0x2812 4034 |
MSRTC_HI |
||
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:6 |
Reserved |
|
RO |
0x000 0000 |
5:0 |
Minutes |
|
RW |
0x00 |
Address offset |
0x038 |
||
Physical address |
0x2012 4038 |
Instance |
MSRTC_LO |
0x2812 4038 |
MSRTC_HI |
||
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:5 |
Reserved |
|
RO |
0x000 0000 |
4:0 |
Hours |
|
RW |
0x00 |
Address offset |
0x03C |
||
Physical address |
0x2012 403C |
Instance |
MSRTC_LO |
0x2812 403C |
MSRTC_HI |
||
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:5 |
Reserved |
|
RO |
0x000 0000 |
4:0 |
Day |
|
RW |
0x00 |
Address offset |
0x040 |
||
Physical address |
0x2012 4040 |
Instance |
MSRTC_LO |
0x2812 4040 |
MSRTC_HI |
||
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
Reserved |
|
RO |
0x000 0000 |
3:0 |
Month |
|
RW |
0x0 |
Address offset |
0x044 |
||
Physical address |
0x2012 4044 |
Instance |
MSRTC_LO |
0x2812 4044 |
MSRTC_HI |
||
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
Reserved |
|
RO |
0x00 0000 |
7:0 |
Year |
|
RW |
0x00 |
Address offset |
0x048 |
||
Physical address |
0x2012 4048 |
Instance |
MSRTC_LO |
0x2812 4048 |
MSRTC_HI |
||
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
Reserved |
|
RO |
0x0000 0000 |
2:0 |
Weekday |
|
RW |
0x0 |
Address offset |
0x04C |
||
Physical address |
0x2012 404C |
Instance |
MSRTC_LO |
0x2812 404C |
MSRTC_HI |
||
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:6 |
Reserved |
|
RO |
0x000 0000 |
5:0 |
Week |
|
RW |
0x00 |
Address offset |
0x050 |
||
Physical address |
0x2012 4050 |
Instance |
MSRTC_LO |
0x2812 4050 |
MSRTC_HI |
||
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:6 |
Reserved |
|
RO |
0x000 0000 |
5:0 |
Seconds |
Each read returns the current date/time value. It is
possible that date/time may increament b/w reads. Write: All fields
(0x50-0x6c) must be writeen. The control register upload bit will upload the
data to RTC.These registers are for use when clock_mode=1 |
RW |
0x00 |
Address offset |
0x054 |
||
Physical address |
0x2012 4054 |
Instance |
MSRTC_LO |
0x2812 4054 |
MSRTC_HI |
||
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:6 |
Reserved |
|
RO |
0x000 0000 |
5:0 |
Minutes |
|
RW |
0x00 |
Address offset |
0x058 |
||
Physical address |
0x2012 4058 |
Instance |
MSRTC_LO |
0x2812 4058 |
MSRTC_HI |
||
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:5 |
Reserved |
|
RO |
0x000 0000 |
4:0 |
Hours |
|
RW |
0x00 |
Address offset |
0x05C |
||
Physical address |
0x2012 405C |
Instance |
MSRTC_LO |
0x2812 405C |
MSRTC_HI |
||
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:5 |
Reserved |
|
RO |
0x000 0000 |
4:0 |
Day |
|
RW |
0x00 |
Address offset |
0x060 |
||
Physical address |
0x2012 4060 |
Instance |
MSRTC_LO |
0x2812 4060 |
MSRTC_HI |
||
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
Reserved |
|
RO |
0x000 0000 |
3:0 |
Month |
|
RW |
0x0 |
Address offset |
0x064 |
||
Physical address |
0x2012 4064 |
Instance |
MSRTC_LO |
0x2812 4064 |
MSRTC_HI |
||
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
Reserved |
|
RO |
0x00 0000 |
7:0 |
Year |
|
RW |
0x00 |
Address offset |
0x068 |
||
Physical address |
0x2012 4068 |
Instance |
MSRTC_LO |
0x2812 4068 |
MSRTC_HI |
||
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
Reserved |
|
RO |
0x0000 0000 |
2:0 |
Weekday |
|
RW |
0x0 |
Address offset |
0x06C |
||
Physical address |
0x2012 406C |
Instance |
MSRTC_LO |
0x2812 406C |
MSRTC_HI |
||
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:6 |
Reserved |
|
RO |
0x000 0000 |
5:0 |
Week |
|
RW |
0x00 |
MSRTC has no common
memories.