pfsoc_mss_top_scb_regs

This section provides information on the pfsoc_mss_top_scb_regs Module Instance. Each of the module registers is described below.

Register Lock Bits can prevent the XCVR configuration registers from being overwritten by hosts that have access to these registers. The lock bits can be managed using the Configure Register Lock Bits utility in the Libero SoC. The following registers can be locked.

·         PFSOC_MSS_TOP_SCB_REGS_DLL0_CTRL0                  

·         PFSOC _MSS_TOP_SCB_REGS_DLL0_CTRL1                 

·         PFSOC _MSS_TOP_SCB_REGS_DLL0_STAT0                 

·         PFSOC _MSS_TOP_SCB_REGS_DLL1_CTRL0                 

·         PFSOC _MSS_TOP_SCB_REGS_DLL1_CTRL1                 

·         PFSOC _MSS_TOP_SCB_REGS_DLL1_STAT0                 

·         PFSOC _MSS_TOP_SCB_REGS_DLL2_CTRL0                 

·         PFSOC _MSS_TOP_SCB_REGS_DLL2_CTRL1                 

·         PFSOC _MSS_TOP_SCB_REGS_DLL2_STAT0                  

·         PFSOC _MSS_TOP_SCB_REGS_DLL3_CTRL0                 

·         PFSOC _MSS_TOP_SCB_REGS_DLL3_CTRL1                 

·         PFSOC _MSS_TOP_SCB_REGS_DLL3_STAT0                

 

Return to pfsoc_mss_regmap

PF_mss_top_scb_regs Register Mapping Summary

SYSREGSCB Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SOFT_RESET

RW

32

0x0720 0000

0x000

0x2000 3000

AXI_WSETUP

RW

32

0x0000 0000

0x010

0x2000 3010

AXI_WADDR

RW

32

0x0000 0000

0x014

0x2000 3014

AXI_WDATA

RW

32

0x0000 0000

0x018

0x2000 3018

AXI_RSETUP

RW

32

0x0000 0000

0x01C

0x2000 301C

AXI_RADDR

RW

32

0x0000 0000

0x020

0x2000 3020

AXI_RDATA

RW

32

0x0000 0000

0x024

0x2000 3024

AXI_STATUS

RW

32

0x0000 0000

0x028

0x2000 3028

AXI_CONTROL

RW

32

0x0000 0000

0x02C

0x2000 302C

REDUNDANCY

RW

32

0x0000 0002

0x030

0x2000 3030

BIST_CONFIG

RW

32

0x0000 0001

0x050

0x2000 3050

BIST_DATA

RW

32

0x0000 0000

0x054

0x2000 3054

BIST_COMMAND

RW

32

0x0000 2000

0x058

0x2000 3058

MSS_RESET_CR

RW

32

0x0000 0107

0x100

0x2000 3100

MSS_STATUS

RW

32

0x0000 0000

0x104

0x2000 3104

BOOT_ADDR0

RW

32

0x2000 3120

0x108

0x2000 3108

BOOT_ADDR1

RW

32

0x2000 3120

0x10C

0x2000 310C

BOOT_ADDR2

RW

32

0x2000 3120

0x110

0x2000 3110

BOOT_ADDR3

RW

32

0x2000 3120

0x114

0x2000 3114

BOOT_ADDR4

RW

32

0x2000 3120

0x118

0x2000 3118

BOOT_ROM0

RW

32

0x0000 0513

0x120

0x2000 3120

BOOT_ROM1

RW

32

0x3445 1073

0x124

0x2000 3124

BOOT_ROM2

RW

32

0x1050 0073

0x128

0x2000 3128

BOOT_ROM3

RW

32

0xFF5F F06F

0x12C

0x2000 312C

BOOT_ROM4

RW

32

0xFF1F F06F

0x130

0x2000 3130

BOOT_ROM5

RW

32

0xFEDF F06F

0x134

0x2000 3134

BOOT_ROM6

RW

32

0xFE9F F06F

0x138

0x2000 3138

BOOT_ROM7

RW

32

0xFE5F F06F

0x13C

0x2000 313C

FLASH_FREEZE

RW

32

0x0000 0000

0x180

0x2000 3180

PFCIO

RW

32

0x0000 0000

0x184

0x2000 3184

DEVICE_ID

RW

32

0x0000 0000

0x188

0x2000 3188

MESSAGE_INT

RW

32

0x0000 0000

0x18C

0x2000 318C

MESSAGE

RW

32

0x0000 0000

0x190

0x2000 3190

DEVRST_INT

RW

32

0x0000 0000

0x194

0x2000 3194

SCB_INTERRUPT

RW

32

0x0000 0000

0x198

0x2000 3198

MSS_INTERRUPT

RW

32

0x0000 0000

0x19C

0x2000 319C

DEVICE_CONFIG_CR

RW

32

0x0000 0004

0x1A0

0x2000 31A0

ATHENA_CR

RW

32

0x0000 0000

0x1A4

0x2000 31A4

ENVM_CR

RW

32

0x4005 0003

0x1A8

0x2000 31A8

ENVM_POWER_CR

RW

32

0x0000 007F

0x1AC

0x2000 31AC

RAM_SHUTDOWN_CR

RW

32

0x0000 3FFF

0x1B0

0x2000 31B0

RAM_MARGIN_CR

RW

32

0x0000 0000

0x1B4

0x2000 31B4

TRACE_CR

RW

32

0x0000 0000

0x1B8

0x2000 31B8

MSSIO_CONTROL_CR

RW

32

0x0000 0720

0x1BC

0x2000 31BC

MSS_IO_LOCKDOWN_CR

RO

32

0x0000 0000

0x1C0

0x2000 31C0

MSSIO_BANK2_CFG_CR

RW

32

0x0000 3F3F

0x1C4

0x2000 31C4

MSSIO_BANK4_CFG_CR

RW

32

0x0000 3F3F

0x1C8

0x2000 31C8

DLL0_CTRL0

RW

32

0x8800 000F

0x200

0x2000 3200

DLL0_CTRL1

RW

32

0x0000 0000

0x204

0x2000 3204

DLL0_STAT0

RW

32

0x0000 1003

0x208

0x2000 3208

DLL0_STAT1

RO

32

0x0001 0000

0x20C

0x2000 320C

DLL0_STAT2

RO

32

0x0000 0000

0x210

0x2000 3210

DLL0_TEST

RW

32

0x0000 0000

0x214

0x2000 3214

DLL1_CTRL0

RW

32

0x8800 000F

0x220

0x2000 3220

DLL1_CTRL1

RW

32

0x0000 0000

0x224

0x2000 3224

DLL1_STAT0

RW

32

0x0000 1003

0x228

0x2000 3228

DLL1_STAT1

RO

32

0x0001 0000

0x22C

0x2000 322C

DLL1_STAT2

RO

32

0x0000 0000

0x230

0x2000 3230

DLL1_TEST

RW

32

0x0000 0000

0x234

0x2000 3234

DLL2_CTRL0

RW

32

0x8800 000F

0x240

0x2000 3240

DLL2_CTRL1

RW

32

0x0000 0000

0x244

0x2000 3244

DLL2_STAT0

RW

32

0x0000 1003

0x248

0x2000 3248

DLL2_STAT1

RO

32

0x0001 0000

0x24C

0x2000 324C

DLL2_STAT2

RO

32

0x0000 0000

0x250

0x2000 3250

DLL2_TEST

RW

32

0x0000 0000

0x254

0x2000 3254

DLL3_CTRL0

RW

32

0x8800 000F

0x260

0x2000 3260

DLL3_CTRL1

RW

32

0x0000 0000

0x264

0x2000 3264

DLL3_STAT0

RW

32

0x0000 1003

0x268

0x2000 3268

DLL3_STAT1

RO

32

0x0001 0000

0x26C

0x2000 326C

DLL3_STAT2

RO

32

0x0000 0000

0x270

0x2000 3270

DLL3_TEST

RW

32

0x0000 0000

0x274

0x2000 3274

MSSIO_VB2_CFG

RW

32

0x0000 0828

0x278

0x2000 3278

MSSIO_VB4_CFG

RW

32

0x0000 0828

0x27C

0x2000 327C

 

pfsoc_mss_top_scb_regs Register Descriptions

pfsoc_mss_top_scb_regs : SOFT_RESET

Address offset

0x000

Physical address

0x2000 3000

Instance

SYSREGSCB

Description

System Reset Register. This MSS soft reset register is not readable or writeable by the MSS or user or DRI.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

BLOCKID

This returns the block type and chip location.

RO

0x0720

15:9

Reserved

 

RO
Rreturns0s

0x00

8

PERIPH

This asserts the functional reset of the block. It is asserted at power up, the bit self clears i.e. is similar to a W1P bit. This bit is activated global_periph_reset

WO

0

7:2

Reserved

 

RO
Rreturns0s

0x00

1

V_MAP

This when asserted resets all the register bits apart from the non-volatile registers, the bit self clears i.e. is similar to a W1P bit. This bit is activated global_map_reset.

WO

0

0

NV_MAP

This when asserted resets all the non-volatile register bits e.g. RW-P bits, the bit self clears i.e. is similar to a W1P bit. This bit is activated global_map_reset.

WO

0

 

pfsoc_mss_top_scb_regs : AXI_WSETUP

Address offset

0x010

Physical address

0x2000 3010

Instance

SYSREGSCB

Description

Axi Write Setup. Not accesible from MSS or user or DRI.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

SYSTEM

0: AXI transaction uses ID 0 and passes through MPU block
1: AXI transaction uses ID 1 and bypasses the MPU block

RW

0

30:27

QOS

Sets the AXI QOS value, higher values have higher priority in the switch

RW

0x0

26:24

PROT

Sets the AXI protection value

RW

0x0

23:20

CACHE

Sets the AXI Cache value

RW

0x0

19

LOCK

Sets the AXI lock

RW

0

18:16

SIZE

Set the AXI size (width)

RW

0x0

15:8

LENGTH

Sets the AXI burst length

RW

0x00

7:6

BURST

Sets the AXi burst type

RW

0x0

5:0

ADDR

Sets the upper 6-bits of the address bus

RW

0x00

 

pfsoc_mss_top_scb_regs : AXI_WADDR

Address offset

0x014

Physical address

0x2000 3014

Instance

SYSREGSCB

Description

AXI Write Address. Not accesible from MSS or user or DRI.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

ADDR

This sets the AXI write address. A write to this register triggers the AXI AW cycle

RW

0x0000 0000

 

pfsoc_mss_top_scb_regs : AXI_WDATA

Address offset

0x018

Physical address

0x2000 3018

Instance

SYSREGSCB

Description

AXI Write Data. This is write only register, reads will return zero. Not accesible from MSS or user or DRI.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

DATA

Write Data, when written will initiate a AHB write transfer through the write data FIFO.Data must be written using word operations. If AWSIZE<=2 then a AXI Write data cycle will be started every cycle, if AWSIZE=3 a AXI Write data cycle will be started every other cycle.

RW

0x0000 0000

 

pfsoc_mss_top_scb_regs : AXI_RSETUP

Address offset

0x01C

Physical address

0x2000 301C

Instance

SYSREGSCB

Description

AXI Read Setup. Not accesible from MSS or user or DRI.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

SYSTEM

0: AXI transaction uses ID 0 and passes through MPU block
1: AXI transaction uses ID 1 and bypasses the MPU block

RW

0

30:27

QOS

Sets the AXI QOS value, higher values have higher priority in the switch

RW

0x0

26:24

PROT

Sets the AXI protection value

RW

0x0

23:20

CACHE

Sets the AXI Cache value

RW

0x0

19

LOCK

Sets the AXI lock

RW

0

18:16

SIZE

Set the AXI size (width)

RW

0x0

15:8

LENGTH

Sets the AXI burst length

RW

0x00

7:6

BURST

Sets the AXi burst type

RW

0x0

5:0

ADDR

Sets the upper 6-bits of the address bus

RW

0x00

 

pfsoc_mss_top_scb_regs : AXI_RADDR

Address offset

0x020

Physical address

0x2000 3020

Instance

SYSREGSCB

Description

AXI Read Address. Not accesible from MSS or user or DRI.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

ADDR

This sets the AXI read address. A write to this register triggers the AXI AR cycle

RW

0x0000 0000

 

pfsoc_mss_top_scb_regs : AXI_RDATA

Address offset

0x024

Physical address

0x2000 3024

Instance

SYSREGSCB

Description

AHB Read data. This is a read only register, writes will be have no effect.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

DATA

Read data from the AXI read FIFO

RW

0x0000 0000

 

pfsoc_mss_top_scb_regs : AXI_STATUS

Address offset

0x028

Physical address

0x2000 3028

Instance

SYSREGSCB

Description

AXI Master Status. Not accessible from MSS or user or DRI. This register provides status information and writes only supported on bits 28:24

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:29

Reserved

 

RO
Rreturns0s

0x0

28

INT_ENABLE_SYSREG

Enable SCB interrupt from the SCB Interrupt register

RW

0

27

INT_ENABLE_WRESP

Enable SCB interrupt on write response error

RW

0

26

INT_ENABLE_RRESP

Enable SCB interrupt on read response error

RW

0

25

INT_ENABLE_WRITE_ORUN

Enable SCB interrupt on write overrun

RW

0

24

INT_ENABLE_READ_ORUN

Enable SCB interrupt on read overrun

RW

0

23:21

Reserved

 

RO
Rreturns0s

0x0

20

MSS_RESET

Indicates that the MSS has been reset and the SCB transfer may have failed. Is the internal MSS sticky_reset signal

RW

0

19:18

READ_RESPONSE

Indicates the read response. When a non-zero value is detected the register will hold the value until the read_error bit is cleared or abort asserted

RW

0x0

17:16

WRITE_RESPONSE

Indicates the write response. When a non-zero value is detected the register will hold the value until the write_error bit is cleared or abort asserted

RW

0x0

15

WRITE_OVERRUN

Indicates the SCB bus wrote the write FIFO when empty. Is cleared by writing a ‘1’

RW

0

14

READ_OVERRUN

Indicates the SCB bus read the read FIFO when empty. Is cleared by writing a ‘1’

RW

0

13:9

READ_COUNT

Indicates how many 32-bit words are stored in the read FIFO

RW

0x00

8:4

WRITE_COUNT

Indicates how many 32-bit words are stored in the write FIFO

RW

0x00

3

READ_ERROR

Set when a read error response is received. Is cleared by writing a ‘1’

RW

0

2

WRITE_ERROR

Set when a write error response is received. Is cleared by writing a ‘1’

RW

0

1

READ_BUSY

Set during arvalid cycle and cleared on the last read response

RW

0

0

WRITE_BUSY

Set during awvalid cycle and cleared on the write response

RW

0

 

pfsoc_mss_top_scb_regs : AXI_CONTROL

Address offset

0x02C

Physical address

0x2000 302C

Instance

SYSREGSCB

Description

AXI Cycle Controls. Not accesible from MSS or user or DRI.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:17

Reserved

 

RO
Rreturns0s

0x0000

16

START_WRITE

Starts AXI transfer when STALL_WRITE is set, reads as zero

RW

0

15:9

Reserved

 

RO
Rreturns0s

0x00

8

STALL_WRITE

When set prevents the logic initiating AW cycle automatically. Write is started by START_WRITE. Allows up to 16 words (32-bits) of data to be queued allowing AXI to run more efficiently.

RW

0

7:1

Reserved

 

RO
Rreturns0s

0x00

0

ABORT

Abort current transfer and reset the FSMS. May cause AXI protocol violations

RW

0

 

pfsoc_mss_top_scb_regs : REDUNDANCY

Address offset

0x030

Physical address

0x2000 3030

Instance

SYSREGSCB

Description

Used to program MSS RAM redundancy system during system startup

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2

NOCLOCK

When set stops the SCB clock creating the Redundancy clock. To allow for large recovery times on the redundancy ISOLATE and RESET inputs this bit should be set prior to toggling the reset/isolate bits and cleared afterwards.

RW

0

1

ISOLATE

Asserts the Redundacy isolate, interface isolated when 1 (can be accessed by MSS in factory mode)

RW

1

0

RESET

Asserts the Redundacy reset (can be accessed by MSS in factory mode)

RW

0

 

pfsoc_mss_top_scb_regs : BIST_CONFIG

Address offset

0x050

Physical address

0x2000 3050

Instance

SYSREGSCB

Description

Used to access the BIST systems

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:19

Reserved

 

RO
Rreturns0s

0x0000

18:16

margin

Set the BIST memory margin, factory mode only

RW

0x0

15:13

Reserved

 

RO
Rreturns0s

0x0

12:8

select

Select the BIST engine 0-15

RW

0x00

7:4

Reserved

 

RO
Rreturns0s

0x0

3

diag_select

Assert the DIAG select

RW

0

2

reset

Assert the BIST reset

RW

0

1

enable

Enable the CPU BIST system

RW

0

0

enabled

Indicates that CPU may use BIST system, UFS bit may disable this interface, available when factory mode set

RO

1

 

pfsoc_mss_top_scb_regs : BIST_DATA

Address offset

0x054

Physical address

0x2000 3054

Instance

SYSREGSCB

Description

Data value to be shifted into BIST system

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

data

Writes sets the data value to shifted, LSB shifted out first. Reads returns the shifted in value, MSB is last bit shifted in.

RW

0x0000 0000

 

pfsoc_mss_top_scb_regs : BIST_COMMAND

Address offset

0x058

Physical address

0x2000 3058

Instance

SYSREGSCB

Description

BIST Shift Controls

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:15

Reserved

 

RO
Rreturns0s

0x0 0000

14:8

length

Number of bits to shift 1-127. If set to >32 the outgoing shift data for bits 33 upwards will be zero. This allows MBIST with CSR registers greater than 32 to be started with valid data loaded into bits 23:0 off the CSR register as specified in the data register. When >32 incoming data is not captured in the shift register, if the read data is to extracted then each shift operation should be <=32 bits. To read a 88 bit register will require 3 shift operatiosn of 32, 32 and 24 bits

RW

0x20

7:4

Reserved

 

RO
Rreturns0s

0x0

3

busy

Indicates that the shift is in progress.

RO

0

2

shift

Perform the specified number off shift cycles.

RW
W1P

0

1

capture

Do a shift cycle, may be asserted at the same time as shift, capture is asserted before shift operations start.

RW
W1P

0

0

update

Do an update cycle

RW
W1P

0

 

pfsoc_mss_top_scb_regs : MSS_RESET_CR

Address offset

0x100

Physical address

0x2000 3100

Instance

SYSREGSCB

Description

MSS reset Controls

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:25

Reserved

 

RO
Rreturns0s

0x00

24:16

REASON

This provides a read off the main SYSREG reset reason register

RO

0x000

15:9

Reserved

 

RO
Rreturns0s

0x00

8

SGMII

Asserts a reset the SGMII block containing the MSS reference clock input.
Warning that setting this bit causes the external reference clock input to the MSS PLL to disappear.
It is advisable to use the SGMII channel soft resets in the PHY instead of this bit.
However if E51 software wants to set this bit, the MSS clock source should be switched over to the standby source in advance.

RW

1

7:4

Reserved

 

RO
Rreturns0s

0x0

3

REBOOT_REQUEST

Reading returns the value of reboot_request.
Writing 1 clears the reboot request and the fabric reset enable register

RW
W1toClr

0

2

CPUINRESET

Indicates that the CPU's are being help in reset. Will stay active for sixteen CPU clocks after the CPU resets are released

RO

1

1

MSS

Holds the MSS system (i.e. AXI/AHB/APB resets) in reset. When asserted the CPU's are also held in reset. The Trace UDB reset is not asserted by this bit.

RW

1

0

CPU

Holds the CPUS (corplex) in reset.

RW

1

 

pfsoc_mss_top_scb_regs : MSS_STATUS

Address offset

0x104

Physical address

0x2000 3104

Instance

SYSREGSCB

Description

MSS Status

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:17

Reserved

 

RO
Rreturns0s

0x0000

16

ecc_error_other

 

RO

0

15

ecc_error_l2

 

RO

0

14

halt_cpu4

 

RO

0

13

halt_cpu3

 

RO

0

12

halt_cpu2

 

RO

0

11

halt_cpu1

 

RO

0

10

halt_cpu0

 

RO

0

9

debug_active

 

RO

0

8:4

watchdog

 

RO

0x00

3:0

boot_status

 

RW

0x0

 

pfsoc_mss_top_scb_regs : BOOT_ADDR0

Address offset

0x108

Physical address

0x2000 3108

Instance

SYSREGSCB

Description

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

address

Boot Address i.e. reset vector for the coreplex

RW

0x2000 3120

 

pfsoc_mss_top_scb_regs : BOOT_ADDR1

Address offset

0x10C

Physical address

0x2000 310C

Instance

SYSREGSCB

Description

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

address

Boot Address i.e. reset vector for the coreplex

RW

0x2000 3120

 

pfsoc_mss_top_scb_regs : BOOT_ADDR2

Address offset

0x110

Physical address

0x2000 3110

Instance

SYSREGSCB

Description

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

address

Boot Address i.e. reset vector for the coreplex

RW

0x2000 3120

 

pfsoc_mss_top_scb_regs : BOOT_ADDR3

Address offset

0x114

Physical address

0x2000 3114

Instance

SYSREGSCB

Description

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

address

Boot Address i.e. reset vector for the coreplex

RW

0x2000 3120

 

pfsoc_mss_top_scb_regs : BOOT_ADDR4

Address offset

0x118

Physical address

0x2000 3118

Instance

SYSREGSCB

Description

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

address

Boot Address i.e. reset vector for the coreplex

RW

0x2000 3120

 

pfsoc_mss_top_scb_regs : BOOT_ROM0

Address offset

0x120

Physical address

0x2000 3120

Instance

SYSREGSCB

Description

32-byte ROM for CPU booting
Holds eight 32-bit Instructions

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

data

li a0,0

RW

0x0000 0513

 

pfsoc_mss_top_scb_regs : BOOT_ROM1

Address offset

0x124

Physical address

0x2000 3124

Instance

SYSREGSCB

Description

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

data

csrw mip,a0

RW

0x3445 1073

 

pfsoc_mss_top_scb_regs : BOOT_ROM2

Address offset

0x128

Physical address

0x2000 3128

Instance

SYSREGSCB

Description

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

data

wfi

RW

0x1050 0073

 

pfsoc_mss_top_scb_regs : BOOT_ROM3

Address offset

0x12C

Physical address

0x2000 312C

Instance

SYSREGSCB

Description

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

data

j 20003120 <_start>

RW

0xFF5F F06F

 

pfsoc_mss_top_scb_regs : BOOT_ROM4

Address offset

0x130

Physical address

0x2000 3130

Instance

SYSREGSCB

Description

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

data

j 20003120 <_start>

RW

0xFF1F F06F

 

pfsoc_mss_top_scb_regs : BOOT_ROM5

Address offset

0x134

Physical address

0x2000 3134

Instance

SYSREGSCB

Description

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

data

j 20003120 <_start>

RW

0xFEDF F06F

 

pfsoc_mss_top_scb_regs : BOOT_ROM6

Address offset

0x138

Physical address

0x2000 3138

Instance

SYSREGSCB

Description

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

data

j 20003120 <_start>

RW

0xFE9F F06F

 

pfsoc_mss_top_scb_regs : BOOT_ROM7

Address offset

0x13C

Physical address

0x2000 313C

Instance

SYSREGSCB

Description

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

data

j 20003120 <_start>

RW

0xFE5F F06F

 

pfsoc_mss_top_scb_regs : FLASH_FREEZE

Address offset

0x180

Physical address

0x2000 3180

Instance

SYSREGSCB

Description

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

in_progress

Set by PFC when FF in progress

RW

0

 

pfsoc_mss_top_scb_regs : PFCIO

Address offset

0x184

Physical address

0x2000 3184

Instance

SYSREGSCB

Description

Register bit that may drive IOMUX

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

ioout

Allows PFC to drive an IO pad[4] when IOMUX is configured in MISC mode. This is provided to aid device validation alloing an IO to be easily controlleed by PF-control.

RW

0

 

pfsoc_mss_top_scb_regs : DEVICE_ID

Address offset

0x188

Physical address

0x2000 3188

Instance

SYSREGSCB

Description

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:20

Reserved

 

RO
Rreturns0s

0x000

19:16

idv

 

RW

0x0

15:0

idp

 

RW

0x0000

 

pfsoc_mss_top_scb_regs : MESSAGE_INT

Address offset

0x18C

Physical address

0x2000 318C

Instance

SYSREGSCB

Description

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

active

Writing to this bit sets the PFc_message interrupt to the Coreplex, interrupt is cleared by coreplex writing a '0'. It is required that the MSS clears this bit proir to requesting a system service from PFC, on completion PFC will set the MESSAGE register and this bit casuing an interrupt to the MSS indicating the system service is complete.

RW

0

 

pfsoc_mss_top_scb_regs : MESSAGE

Address offset

0x190

Physical address

0x2000 3190

Instance

SYSREGSCB

Description

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

data

Data value associated with Message interrupt, used for system service return status

RW

0x0000 0000

 

pfsoc_mss_top_scb_regs : DEVRST_INT

Address offset

0x194

Physical address

0x2000 3194

Instance

SYSREGSCB

Description

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

active

Writing to this bit sets the DEVRST interrupt to the Coreplex via the maintence register, interrupt is cleared by coreplex writing a '0' to this bit

RW

0

 

pfsoc_mss_top_scb_regs : SCB_INTERRUPT

Address offset

0x198

Physical address

0x2000 3198

Instance

SYSREGSCB

Description

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

active

Writing to this bit sets the SCB interrupt signal, interrupt is cleared by PFC writing a '0' to this bit

RW

0

 

pfsoc_mss_top_scb_regs : MSS_INTERRUPT

Address offset

0x19C

Physical address

0x2000 319C

Instance

SYSREGSCB

Description

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

active

Writing to this bit sets the MSS to PFC interrupt, interrupt is cleared by PFC writing a '0' to this bit

RW

0

 

pfsoc_mss_top_scb_regs : DEVICE_CONFIG_CR

Address offset

0x1A0

Physical address

0x2000 31A0

Instance

SYSREGSCB

Description

This register configures the

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:17

Reserved

 

RO
Rreturns0s

0x0000

16

DISABLE_XIP

When set prevents the QSPI module from operating in XIP mode preventinmg direct execution from the QSPI device

RW

0

15:9

Reserved

 

RO
Rreturns0s

0x00

8

CPU_BIST_DISABLE

When set the CPU's may not initiate MBIST of the RAMS

RW

0

7:6

Reserved

 

RO
Rreturns0s

0x0

5

CPU_DISABLE

When '1' dissables the SIFIVE CPUs and holds them in reset.

RW

0

4

CPU_ALLOWED

When '1' allows the SIFIVE CPUs to operate. When '0' the CPUS (E51 and U54s) are held in reset. This bit is intended to be set via a factory configuration bit by PF-Control allowing the RiscV cores to be de-featured

RW

0

3

CAN_ALLOWED

When '1' indicates CAN is enabled When '0' the CAN block is held in reset. This bit is intended to be set via a factory configuration bit by PF-Control allowing the CAN core to be de-featured

RW

0

2

CRYPTO_DISABLE

When '1' disables the Crypto block and the Athena block is held in reset. This bit is intended to be set via a factory configuration bit by PF-Control allowing the CAN core to be de-featured

RW

1

1

Reserved

 

RO

0

0

FACTORY_TEST_MODE

Indicates the device is in manufacturing test mode.

RW

0

 

pfsoc_mss_top_scb_regs : ATHENA_CR

Address offset

0x1A4

Physical address

0x2000 31A4

Instance

SYSREGSCB

Description

Sets the Athena owners. Not writeable by the MSS or user

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:5

Reserved

 

RO
Rreturns0s

0x000 0000

4

stream_enable

Allow Streaming Interface to operate

RW

0

3

Reserved

 

RO
Rreturns0s

0

2:0

mss_mode

0xx: Crypto block not available to fabric or MSS
100: Only available to MSS
101: Only avaliable to fabric
110: Available to both, starts with MSS
111: Available to both, starts with fabric
If changed during operation then initial change must be to 3'b000.

RW

0x0

 

pfsoc_mss_top_scb_regs : ENVM_CR

Address offset

0x1A8

Physical address

0x2000 31A8

Instance

SYSREGSCB

Description

Applies to AHB Controllers when NVM override set

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:24

timer

Sets the duration of the timer used to detect a non response of slow response from the PNVM on C and R bus accesses.
Timer Duration = Value * 4ns.
0x00: Timer dissabled.
If the timer expires the AHB cycle is terminates using the HRESP protocol.
This field must be set before the PFC override is set and should not be changed whilst it is set.

RW

0x40

23:19

Reserved

 

RO
Rreturns0s

0x00

18

interrupt_enable

Enable the PNVM interrupt

RW

1

17

slowread

When '1' the controller will initate separate PNVM reads for all reads. No buffering or speculative operations will be carried out. When performing word reads incrementing through PNVM each location will be read twice (intended for test use)

RW

0

16

readahead

Enables "readahead" on the PNVM controller. The controller will automatically read the next PNVM location as soon as possible ahead of the AHB request. This will improve read performance when incrementing though memory as the NVM reads and AHB cycles are pipelined. When set non incrementing accesses will take longer as the controller may be in the process of reading the next address and the PNVM cycle needs to complete prior to starting the required read

RW

1

15:10

Reserved

 

RO
Rreturns0s

0x00

9

clock_suppress

When set suppresses clock edge between C-Bus access cycles so that they appear as consecutive access cycles.

RW

0

8

clock_continuous

When '1' the PNVM clock will be always generated, and not stopped between access cycles. Setting this will increase access latency but mean that the PNVM clock operates at a stable rate.

RW

0

7:6

Reserved

 

RO
Rreturns0s

0x0

5:0

clock_period

Sets the number of AHB cycles used to generate the PNVM clock,
Clock period = (Value+1) * 4ns (AHB clock at 250MHz)
Value must be 1 to 63 (0 defaults to 3)
e.g. 9 will generate a 40ns period 25MHz clock if the AHB clock is 250MHz
This field must be set before the PFC override is set and should not be changed whilst it is set.

RW

0x03

 

pfsoc_mss_top_scb_regs : ENVM_POWER_CR

Address offset

0x1AC

Physical address

0x2000 31AC

Instance

SYSREGSCB

Description

Applies to the eNVM controller

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:9

Reserved

 

RO
Rreturns0s

0x00 0000

8

override

Enable PFC overrides

RW

0

7

Reserved

 

RO
Rreturns0s

0

6

sleep

Controls the PNVM sleep input

RW

1

5

iso

Controls the PNVM iso (isolate) input

RW

1

4

pd4

Controls the PNVM pd4 (powerdown) input

RW

1

3

pd3

Controls the PNVM pd3 (powerdown) input

RW

1

2

pd2

Controls the PNVM pd2 (powerdown) input

RW

1

1

pd1

Controls the PNVM pd1 (powerdown) input

RW

1

0

reset

Asserts the PNVM reset input (inverted version to PNVM)

RW

1

 

pfsoc_mss_top_scb_regs : RAM_SHUTDOWN_CR

Address offset

0x1B0

Physical address

0x2000 31B0

Instance

SYSREGSCB

Description

Puts all the RAMS in that block into shut down mode. RAM contents not preserved. Powers down the RAM and periphery circuits.
At reset all RAMS powered down

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:14

Reserved

 

RO
Rreturns0s

0x0 0000

13

l2

 

RW

1

12

u54_4

 

RW

1

11

u54_3

 

RW

1

10

u54_2

 

RW

1

9

u54_1

 

RW

1

8

e51

 

RW

1

7

ddrc

 

RW

1

6

athena

 

RW

1

5

mmc

 

RW

1

4

gem1

 

RW

1

3

gem0

 

RW

1

2

usb

 

RW

1

1

can1

 

RW

1

0

can0

 

RW

1

 

pfsoc_mss_top_scb_regs : RAM_MARGIN_CR

Address offset

0x1B4

Physical address

0x2000 31B4

Instance

SYSREGSCB

Description

Controls the RAM margin inputs on the RAMS. Should not be changeld without explicity guidance from Silicon Engineering

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:27

Reserved

 

RO
Rreturns0s

0x00

26:25

l2

 

RW

0x0

24:23

u54_4

 

RW

0x0

22:21

u54_3

 

RW

0x0

20:19

u54_2

 

RW

0x0

18:17

u54_1

 

RW

0x0

16:15

e51

 

RW

0x0

14:13

ddrc

 

RW

0x0

12:11

mmc

 

RW

0x0

10:9

gem1

 

RW

0x0

8:7

gem0

 

RW

0x0

6:5

usb

 

RW

0x0

4:3

can1

 

RW

0x0

2:1

can0

 

RW

0x0

0

enable

 

RW

0

 

pfsoc_mss_top_scb_regs : TRACE_CR

Address offset

0x1B8

Physical address

0x2000 31B8

Instance

SYSREGSCB

Description

Configures the trace and debug connectivity

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:9

Reserved

 

RO
Rreturns0s

0x00 0000

8

ULTRASOC_FABRIC

When set the Utrasoc JTAG interface is connected to fabric EIP connections allowing the JTAG to be directly accessed through fabric IO pins. This also connects the RiscV debugger to the fabric as it passed through the UltraSoc JPAM module

RW

0

7:3

Reserved

 

RO
Rreturns0s

0x00

2

ULTRASOC_DISABLE_AXI

When set the Utrasoc module is dissabled and will not respond to AXI accesses from PF-Control or the fabric. The JTAG end point will be in bypass mode.

RW

0

1

ULTRASOC_DISABLE_JTAG

When set the Utrasoc module is dissabled and will not respond to JTAG accesses from PF-Control or the fabric. The JTAG end point will be in bypass mode.

RW

0

0

CPU_DEBUG_DISABLE

When set the RiscV debug module is dissabled and will not respond to JTAG accesses from either PF-Control or the fabric. The JTAG end point will be in bypass mode.

RW

0

 

pfsoc_mss_top_scb_regs : MSSIO_CONTROL_CR

Address offset

0x1BC

Physical address

0x2000 31BC

Instance

SYSREGSCB

Description

Controls the MSS Corner IO control signals

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

Reserved

 

RO
Rreturns0s

0x0000

15

mss_sel_hw_def

Sets the value driven out on mss_sel_hw_def_out

RW

0

14

mss_sel_hw_dyn

Sets the value driven out on mss_sel_hw_dyn_out

RW

0

13

mss_io_en

Sets the value driven out on mss_io_en (before gating)

RW

0

12

mss_flash_valid

Sets the value driven out on mss_flash_valid_out

RW

0

11

mss_core_up

Sets the value driven out on mss_core_up_out

RW

0

10:8

mss_dce

Sets the value driven out on mss_dce_out unless PFC asserts its overrides

RW

0x7

7

lp_stop_clocks_done_mss

Read back of lp_stop_clocks_done input of MSS Corner LP state control

RO

0

6

lp_stop_clocks_out_mss

Direct control of MSS Corner LP state control

RW

0

5

lp_pll_locked_mss

Direct control of MSS Corner LP state control

RW

1

4

lp_state_bypass_mss

Direct control of MSS Corner LP state control

RW

0

3

lp_state_persist_mss

Direct control of MSS Corner LP state control

RW

0

2

lp_state_op_mss

Direct control of MSS Corner LP state control

RW

0

1

lp_state_ip_mss

Direct control of MSS Corner LP state control

RW

0

0

lp_state_mss

Direct control of MSS Corner LP state control (before gating)

RW

0

 

pfsoc_mss_top_scb_regs : MSS_IO_LOCKDOWN_CR

Address offset

0x1C0

Physical address

0x2000 31C0

Instance

SYSREGSCB

Description

Controls the lockdown enable for the MSS-related IO banks

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:4

Reserved

 

RO
Rreturns0s

0x000 0000

3

ddr_io_lockdn_en

Enable lockdown of DDR-related IO if global lockdown asserted

RO

0

2

sgmii_io_lockdn_en

Enable lockdown of SGMII-related IO if global lockdown asserted

RO

0

1

mssio_b4_lockdn_en

Enable lockdown of MSSIO bank 4 if global lockdown asserted

RO

0

0

mssio_b2_lockdn_en

Enable lockdown of MSSIO bank 2 if global lockdown asserted

RO

0

 

pfsoc_mss_top_scb_regs : MSSIO_BANK2_CFG_CR

Address offset

0x1C4

Physical address

0x2000 31C4

Instance

SYSREGSCB

Description

Configures the MSSIO block

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:20

Reserved

 

RO
Rreturns0s

0x000

19:16

vs

Sets the voltage controls for bank 2

RW

0x0

15:14

Reserved

 

RO
Rreturns0s

0x0

13:8

bank_ncode

Sets the NCODE value for bank 2

RW

0x3F

7:6

Reserved

 

RO
Rreturns0s

0x0

5:0

bank_pcode

Sets the PCODE value for bank 2

RW

0x3F

 

pfsoc_mss_top_scb_regs : MSSIO_BANK4_CFG_CR

Address offset

0x1C8

Physical address

0x2000 31C8

Instance

SYSREGSCB

Description

Configures the MSSIO block

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:20

Reserved

 

RO
Rreturns0s

0x000

19:16

vs

Sets the voltage controls for bank 4

RW

0x0

15:14

Reserved

 

RO
Rreturns0s

0x0

13:8

bank_ncode

Sets the NCODE value for bank 4

RW

0x3F

7:6

Reserved

 

RO
Rreturns0s

0x0

5:0

bank_pcode

Sets the PCODE value for bank 4

RW

0x3F

 

pfsoc_mss_top_scb_regs : DLL0_CTRL0

Address offset

0x200

Physical address

0x2000 3200

Instance

SYSREGSCB

Description

DLL control register 0

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:28

lock_low

 

RW

0x8

27:24

lock_high

 

RW

0x8

23:22

Reserved

 

RO

0x0

21:20

lock_flt

 

RW

0x0

19

lock_frc

 

RW

0

18:16

Reserved

 

RO

0x0

15:14

alu_upd

 

RW

0x0

13:11

Reserved

 

RO

0x0

10

div_sel

 

RW

0

9

fb_sel

 

RW

0

8

ref_sel

 

RW

0

7:6

sel_s

 

RW

0x0

5:4

sel_p

 

RW

0x0

3:2

phase_s

 

RW

0x3

1:0

phase_p

All thes eregisters follow the standard allocation for DLL blocks used in PF. Please refer to the DLL SAC specification for details of register functions.

RW

0x3

 

pfsoc_mss_top_scb_regs : DLL0_CTRL1

Address offset

0x204

Physical address

0x2000 3204

Instance

SYSREGSCB

Description

DLL control register 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

Reserved

 

RO

0

30

relock_fast

 

RW

0

29:24

init_code

 

RW

0x00

23

test_ring

 

RW

0

22:16

Reserved

 

RO

0x00

15

test_s

 

RW

0

14:8

adj_del4

 

RW

0x00

7:0

set_alu

 

RW

0x00

 

pfsoc_mss_top_scb_regs : DLL0_STAT0

Address offset

0x208

Physical address

0x2000 3208

Instance

SYSREGSCB

Description

DLL status register 0

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:24

Reserved

 

RO

0x00

23:16

Reserved

 

RO

0x00

15:14

Reserved

 

RO

0x0

13

Reserved

 

RO

0

12

phase_move_clk

 

RW

1

11

Reserved

 

RO

0

10

Reserved

 

RO

0

9

Reserved

 

RO

0

8

Reserved

 

RO

0

7:5

Reserved

 

RO

0x0

4

Reserved

 

RO

0

3

Reserved

 

RO

0

2

Reserved

 

RO

0

1

bypass

 

RW

1

0

reset

 

RW

1

 

pfsoc_mss_top_scb_regs : DLL0_STAT1

Address offset

0x20C

Physical address

0x2000 320C

Instance

SYSREGSCB

Description

DLL status register 1

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:30

Reserved

 

RO

0x0

29:28

Reserved

 

RO

0x0

27:26

Reserved

 

RO

0x0

25

Reserved

 

RO

0

24:16

sro_alu_cnt

 

RO

0x001

15:8

Reserved

 

RO

0x00

7

Reserved

 

RO

0

6:0

sro_del4

 

RO

0x00

 

pfsoc_mss_top_scb_regs : DLL0_STAT2

Address offset

0x210

Physical address

0x2000 3210

Instance

SYSREGSCB

Description

DLL status register 2

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:24

Reserved

 

RO

0x00

23:16

Reserved

 

RO

0x00

15:7

Reserved

 

RO

0x000

6

Reserved

 

RO

0

5

Reserved

 

RO

0

4

Reserved

 

RO

0

3

Reserved

 

RO

0

2

sro_lock

 

RO

0

1

Reserved

 

RO

0

0

Reserved

 

RO

0

 

pfsoc_mss_top_scb_regs : DLL0_TEST

Address offset

0x214

Physical address

0x2000 3214

Instance

SYSREGSCB

Description

Enables test modes on the DLL

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:4

Reserved

 

RO
Rreturns0s

0x000 0000

3

reserved

To aid synthesis - reads as zero

RO

0

2

ref_select

When '1' the sb clock input is fed to the DLL reference

RW

0

1

cfm_select

Feeds the MBIST clock rather than DLL clock to the CFM block

RW

0

0

cfm_enable

When set enables the DLL output to the frequency meter inside the PF-Controller for test use

RW

0

 

pfsoc_mss_top_scb_regs : DLL1_CTRL0

Address offset

0x220

Physical address

0x2000 3220

Instance

SYSREGSCB

Description

DLL control register 0

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:28

lock_low

 

RW

0x8

27:24

lock_high

 

RW

0x8

23:22

Reserved

 

RO

0x0

21:20

lock_flt

 

RW

0x0

19

lock_frc

 

RW

0

18:16

Reserved

 

RO

0x0

15:14

alu_upd

 

RW

0x0

13:11

Reserved

 

RO

0x0

10

div_sel

 

RW

0

9

fb_sel

 

RW

0

8

ref_sel

 

RW

0

7:6

sel_s

 

RW

0x0

5:4

sel_p

 

RW

0x0

3:2

phase_s

 

RW

0x3

1:0

phase_p

All these registers follow the standard allocation for DLL blocks used in PF. Please refer to the DLL SAC specification for details of register functions.

RW

0x3

 

pfsoc_mss_top_scb_regs : DLL1_CTRL1

Address offset

0x224

Physical address

0x2000 3224

Instance

SYSREGSCB

Description

DLL control register 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

Reserved

 

RO

0

30

relock_fast

 

RW

0

29:24

init_code

 

RW

0x00

23

test_ring

 

RW

0

22:16

Reserved

 

RO

0x00

15

test_s

 

RW

0

14:8

adj_del4

 

RW

0x00

7:0

set_alu

 

RW

0x00

 

pfsoc_mss_top_scb_regs : DLL1_STAT0

Address offset

0x228

Physical address

0x2000 3228

Instance

SYSREGSCB

Description

DLL status register 0

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:24

Reserved

 

RO

0x00

23:16

Reserved

 

RO

0x00

15:14

Reserved

 

RO

0x0

13

Reserved

 

RO

0

12

phase_move_clk

 

RW

1

11

Reserved

 

RO

0

10

Reserved

 

RO

0

9

Reserved

 

RO

0

8

Reserved

 

RO

0

7:5

Reserved

 

RO

0x0

4

Reserved

 

RO

0

3

Reserved

 

RO

0

2

Reserved

 

RO

0

1

bypass

 

RW

1

0

reset

 

RW

1

 

pfsoc_mss_top_scb_regs : DLL1_STAT1

Address offset

0x22C

Physical address

0x2000 322C

Instance

SYSREGSCB

Description

DLL status register 1

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:30

Reserved

 

RO

0x0

29:28

Reserved

 

RO

0x0

27:26

Reserved

 

RO

0x0

25

Reserved

 

RO

0

24:16

sro_alu_cnt

 

RO

0x001

15:8

Reserved

 

RO

0x00

7

Reserved

 

RO

0

6:0

sro_del4

 

RO

0x00

 

pfsoc_mss_top_scb_regs : DLL1_STAT2

Address offset

0x230

Physical address

0x2000 3230

Instance

SYSREGSCB

Description

DLL status register 2

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:24

Reserved

 

RO

0x00

23:16

Reserved

 

RO

0x00

15:7

Reserved

 

RO

0x000

6

Reserved

 

RO

0

5

Reserved

 

RO

0

4

Reserved

 

RO

0

3

Reserved

 

RO

0

2

sro_lock

 

RO

0

1

Reserved

 

RO

0

0

Reserved

 

RO

0

 

pfsoc_mss_top_scb_regs : DLL1_TEST

Address offset

0x234

Physical address

0x2000 3234

Instance

SYSREGSCB

Description

Enables test modes on the DLL

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:4

Reserved

 

RO
Rreturns0s

0x000 0000

3

reserved

To aid synthesis - reads as zero

RO

0

2

ref_select

When '1' the sb clock input is fed to the DLL reference

RW

0

1

cfm_select

Feeds the MBIST clock rather than DLL clock to the CFM block

RW

0

0

cfm_enable

When set enables the DLL output to the frequency meter inside the PF-Controller for test use

RW

0

 

pfsoc_mss_top_scb_regs : DLL2_CTRL0

Address offset

0x240

Physical address

0x2000 3240

Instance

SYSREGSCB

Description

DLL control register 0

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:28

lock_low

 

RW

0x8

27:24

lock_high

 

RW

0x8

23:22

Reserved

 

RO

0x0

21:20

lock_flt

 

RW

0x0

19

lock_frc

 

RW

0

18:16

Reserved

 

RO

0x0

15:14

alu_upd

 

RW

0x0

13:11

Reserved

 

RO

0x0

10

div_sel

 

RW

0

9

fb_sel

 

RW

0

8

ref_sel

 

RW

0

7:6

sel_s

 

RW

0x0

5:4

sel_p

 

RW

0x0

3:2

phase_s

 

RW

0x3

1:0

phase_p

All these registers follow the standard allocation for DLL blocks used in PF. Please refer to the DLL SAC specification for details of register functions.

RW

0x3

 

pfsoc_mss_top_scb_regs : DLL2_CTRL1

Address offset

0x244

Physical address

0x2000 3244

Instance

SYSREGSCB

Description

DLL control register 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

Reserved

 

RO

0

30

relock_fast

 

RW

0

29:24

init_code

 

RW

0x00

23

test_ring

 

RW

0

22:16

Reserved

 

RO

0x00

15

test_s

 

RW

0

14:8

adj_del4

 

RW

0x00

7:0

set_alu

 

RW

0x00

 

pfsoc_mss_top_scb_regs : DLL2_STAT0

Address offset

0x248

Physical address

0x2000 3248

Instance

SYSREGSCB

Description

DLL status register 0

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:24

Reserved

 

RO

0x00

23:16

Reserved

 

RO

0x00

15:14

Reserved

 

RO

0x0

13

Reserved

 

RO

0

12

phase_move_clk

 

RW

1

11

Reserved

 

RO

0

10

Reserved

 

RO

0

9

Reserved

 

RO

0

8

Reserved

 

RO

0

7:5

Reserved

 

RO

0x0

4

Reserved

 

RO

0

3

Reserved

 

RO

0

2

Reserved

 

RO

0

1

bypass

 

RW

1

0

reset

 

RW

1

 

pfsoc_mss_top_scb_regs : DLL2_STAT1

Address offset

0x24C

Physical address

0x2000 324C

Instance

SYSREGSCB

Description

DLL status register 1

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:30

Reserved

 

RO

0x0

29:28

Reserved

 

RO

0x0

27:26

Reserved

 

RO

0x0

25

Reserved

 

RO

0

24:16

sro_alu_cnt

 

RO

0x001

15:8

Reserved

 

RO

0x00

7

Reserved

 

RO

0

6:0

sro_del4

 

RO

0x00

 

pfsoc_mss_top_scb_regs : DLL2_STAT2

Address offset

0x250

Physical address

0x2000 3250

Instance

SYSREGSCB

Description

DLL status register 2

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:24

Reserved

 

RO

0x00

23:16

Reserved

 

RO

0x00

15:7

Reserved

 

RO

0x000

6

Reserved

 

RO

0

5

Reserved

 

RO

0

4

Reserved

 

RO

0

3

Reserved

 

RO

0

2

sro_lock

 

RO

0

1

Reserved

 

RO

0

0

Reserved

 

RO

0

 

pfsoc_mss_top_scb_regs : DLL2_TEST

Address offset

0x254

Physical address

0x2000 3254

Instance

SYSREGSCB

Description

Enables test modes on the DLL

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:4

Reserved

 

RO
Rreturns0s

0x000 0000

3

reserved

To aid synthesis - reads as zero

RO

0

2

ref_select

When '1' the sb clock input is fed to the DLL reference

RW

0

1

cfm_select

Feeds the MBIST clock rather than DLL clock to the CFM block

RW

0

0

cfm_enable

When set enables the DLL output to the frequency meter inside the PF-Controller for test use

RW

0

 

pfsoc_mss_top_scb_regs : DLL3_CTRL0

Address offset

0x260

Physical address

0x2000 3260

Instance

SYSREGSCB

Description

DLL control register 0

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:28

lock_low

 

RW

0x8

27:24

lock_high

 

RW

0x8

23:22

Reserved

 

RO

0x0

21:20

lock_flt

 

RW

0x0

19

lock_frc

 

RW

0

18:16

Reserved

 

RO

0x0

15:14

alu_upd

 

RW

0x0

13:11

Reserved

 

RO

0x0

10

div_sel

 

RW

0

9

fb_sel

 

RW

0

8

ref_sel

 

RW

0

7:6

sel_s

 

RW

0x0

5:4

sel_p

 

RW

0x0

3:2

phase_s

 

RW

0x3

1:0

phase_p

All these registers follow the standard allocation for DLL blocks used in PF. Please refer to the DLL SAC specification for details of register functions.

RW

0x3

 

pfsoc_mss_top_scb_regs : DLL3_CTRL1

Address offset

0x264

Physical address

0x2000 3264

Instance

SYSREGSCB

Description

DLL control register 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

Reserved

 

RO

0

30

relock_fast

 

RW

0

29:24

init_code

 

RW

0x00

23

test_ring

 

RW

0

22:16

Reserved

 

RO

0x00

15

test_s

 

RW

0

14:8

adj_del4

 

RW

0x00

7:0

set_alu

 

RW

0x00

 

pfsoc_mss_top_scb_regs : DLL3_STAT0

Address offset

0x268

Physical address

0x2000 3268

Instance

SYSREGSCB

Description

DLL status register 0

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:24

Reserved

 

RO

0x00

23:16

Reserved

 

RO

0x00

15:14

Reserved

 

RO

0x0

13

Reserved

 

RO

0

12

phase_move_clk

 

RW

1

11

Reserved

 

RO

0

10

Reserved

 

RO

0

9

Reserved

 

RO

0

8

Reserved

 

RO

0

7:5

Reserved

 

RO

0x0

4

Reserved

 

RO

0

3

Reserved

 

RO

0

2

Reserved

 

RO

0

1

bypass

 

RW

1

0

reset

 

RW

1

 

pfsoc_mss_top_scb_regs : DLL3_STAT1

Address offset

0x26C

Physical address

0x2000 326C

Instance

SYSREGSCB

Description

DLL status register 1

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:30

Reserved

 

RO

0x0

29:28

Reserved

 

RO

0x0

27:26

Reserved

 

RO

0x0

25

Reserved

 

RO

0

24:16

sro_alu_cnt

 

RO

0x001

15:8

Reserved

 

RO

0x00

7

Reserved

 

RO

0

6:0

sro_del4

 

RO

0x00

 

pfsoc_mss_top_scb_regs : DLL3_STAT2

Address offset

0x270

Physical address

0x2000 3270

Instance

SYSREGSCB

Description

DLL status register 2

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:24

Reserved

 

RO

0x00

23:16

Reserved

 

RO

0x00

15:7

Reserved

 

RO

0x000

6

Reserved

 

RO

0

5

Reserved

 

RO

0

4

Reserved

 

RO

0

3

Reserved

 

RO

0

2

sro_lock

 

RO

0

1

Reserved

 

RO

0

0

Reserved

 

RO

0

 

pfsoc_mss_top_scb_regs : DLL3_TEST

Address offset

0x274

Physical address

0x2000 3274

Instance

SYSREGSCB

Description

Enables test modes on the DLL

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:4

Reserved

 

RO
Rreturns0s

0x000 0000

3

reserved

To aid synthesis - reads as zero

RO

0

2

ref_select

When '1' the sb clock input is fed to the DLL reference

RW

0

1

cfm_select

Feeds the MBIST clock rather than DLL clock to the CFM block

RW

0

0

cfm_enable

When set enables the DLL output to the frequency meter inside the PF-Controller for test use

RW

0

 

pfsoc_mss_top_scb_regs : MSSIO_VB2_CFG

Address offset

0x278

Physical address

0x2000 3278

Instance

SYSREGSCB

Description

dpc values for MSSIO bank 2

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:15

Reserved

 

RO
Rreturns0s

0x0 0000

14

dpc_io_cfg_lp_bypass_en

 

RW

0

13

dpc_io_cfg_lp_persist_en

 

RW

0

12

dpc_io_cfg_atp_en

 

RW

0

11

dpc_io_cfg_wpu

 

RW

1

10

dpc_io_cfg_wpd

 

RW

0

9

dpc_io_cfg_lockdn_en

 

RW

0

8

dpc_io_cfg_enhyst

 

RW

0

7

dpc_io_cfg_clamp

 

RW

0

6

dpc_io_cfg_drv_3

 

RW

0

5

dpc_io_cfg_drv_2

 

RW

1

4

dpc_io_cfg_drv_1

 

RW

0

3

dpc_io_cfg_drv_0

 

RW

1

2

dpc_io_cfg_ibufmd_2

 

RW

0

1

dpc_io_cfg_ibufmd_1

 

RW

0

0

dpc_io_cfg_ibufmd_0

 

RW

0

 

pfsoc_mss_top_scb_regs : MSSIO_VB4_CFG

Address offset

0x27C

Physical address

0x2000 327C

Instance

SYSREGSCB

Description

dpc values for MSSIO bank 4

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:15

Reserved

 

RO
Rreturns0s

0x0 0000

14

dpc_io_cfg_lp_bypass_en

 

RW

0

13

dpc_io_cfg_lp_persist_en

 

RW

0

12

dpc_io_cfg_atp_en

 

RW

0

11

dpc_io_cfg_wpu

 

RW

1

10

dpc_io_cfg_wpd

 

RW

0

9

dpc_io_cfg_lockdn_en

 

RW

0

8

dpc_io_cfg_enhyst

 

RW

0

7

dpc_io_cfg_clamp

 

RW

0

6

dpc_io_cfg_drv_3

 

RW

0

5

dpc_io_cfg_drv_2

 

RW

1

4

dpc_io_cfg_drv_1

 

RW

0

3

dpc_io_cfg_drv_0

 

RW

1

2

dpc_io_cfg_ibufmd_2

 

RW

0

1

dpc_io_cfg_ibufmd_1

 

RW

0

0

dpc_io_cfg_ibufmd_0

 

RW

0

 

pfsoc_mss_top_scb_regs has no common memories.