This section
provides information on the pfsoc_mss_top_sysreg Module Instance. Each of the
module registers is described below.
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x000A C7E1 |
0x000 |
0x2000 2000 |
|
RW |
32 |
0x0000 0000 |
0x004 |
0x2000 2004 |
|
RW |
32 |
0x0000 0010 |
0x008 |
0x2000 2008 |
|
RW |
32 |
0x0001 0064 |
0x00C |
0x2000 200C |
|
RW |
32 |
0x0000 0000 |
0x010 |
0x2000 2010 |
|
RW |
32 |
0x0000 0000 |
0x014 |
0x2000 2014 |
|
RW |
32 |
0x0000 0000 |
0x018 |
0x2000 2018 |
|
RW |
32 |
0x0000 0000 |
0x01C |
0x2000 201C |
|
RW |
32 |
0x0000 01FF |
0x020 |
0x2000 2020 |
|
RO |
32 |
0x0000 0000 |
0x024 |
0x2000 2024 |
|
RO |
32 |
0x0000 0000 |
0x028 |
0x2000 2028 |
|
RW |
32 |
0x0000 0000 |
0x040 |
0x2000 2040 |
|
RW |
32 |
0x0000 0000 |
0x044 |
0x2000 2044 |
|
RW |
32 |
0x0000 0000 |
0x048 |
0x2000 2048 |
|
RW |
32 |
0x0000 0000 |
0x04C |
0x2000 204C |
|
RW |
32 |
0x0000 0000 |
0x050 |
0x2000 2050 |
|
RW |
32 |
0x0000 0000 |
0x054 |
0x2000 2054 |
|
RW |
32 |
0x0000 0000 |
0x080 |
0x2000 2080 |
|
RW |
32 |
0x0000 0001 |
0x084 |
0x2000 2084 |
|
RW |
32 |
0x3FFF FFFE |
0x088 |
0x2000 2088 |
|
RW |
32 |
0x0000 FFFF |
0x08C |
0x2000 208C |
|
RW |
32 |
0x0000 0000 |
0x090 |
0x2000 2090 |
|
RW |
32 |
0x0000 0002 |
0x098 |
0x2000 2098 |
|
RW |
32 |
0x000F 0703 |
0x09C |
0x2000 209C |
|
RO |
32 |
0x0000 0000 |
0x0A4 |
0x2000 20A4 |
|
RO |
32 |
0x0000 0000 |
0x0A8 |
0x2000 20A8 |
|
RW |
32 |
0x0000 0004 |
0x0AC |
0x2000 20AC |
|
RW |
32 |
0x0000 004E |
0x0B0 |
0x2000 20B0 |
|
RW |
32 |
0xC700 5EED |
0x0B4 |
0x2000 20B4 |
|
RW |
32 |
0x4005 004F |
0x0B8 |
0x2000 20B8 |
|
RO |
32 |
0x0000 0000 |
0x0BC |
0x2000 20BC |
|
RW |
32 |
0x0000 0000 |
0x0C0 |
0x2000 20C0 |
|
RW |
32 |
0x0000 0000 |
0x0C4 |
0x2000 20C4 |
|
RW |
32 |
0x0000 0000 |
0x0C8 |
0x2000 20C8 |
|
RW |
32 |
0x0000 0000 |
0x0F0 |
0x2000 20F0 |
|
RW |
32 |
0x0000 0000 |
0x0F4 |
0x2000 20F4 |
|
RO |
32 |
0x0000 0000 |
0x0F8 |
0x2000 20F8 |
|
RW |
32 |
0x0000 0000 |
0x0FC |
0x2000 20FC |
|
RW |
32 |
0x0000 0000 |
0x100 |
0x2000 2100 |
|
RW |
32 |
0x0000 0000 |
0x104 |
0x2000 2104 |
|
RW |
32 |
0x0000 0000 |
0x108 |
0x2000 2108 |
|
RW |
32 |
0x0000 0000 |
0x10C |
0x2000 210C |
|
RW |
32 |
0x0000 0000 |
0x110 |
0x2000 2110 |
|
RW |
32 |
0x0000 0000 |
0x114 |
0x2000 2114 |
|
RW |
32 |
0x0000 0000 |
0x118 |
0x2000 2118 |
|
RW |
32 |
0x0000 0000 |
0x11C |
0x2000 211C |
|
RW |
32 |
0x0000 0000 |
0x120 |
0x2000 2120 |
|
RW |
32 |
0x0000 0000 |
0x124 |
0x2000 2124 |
|
RW |
32 |
0x0000 0000 |
0x140 |
0x2000 2140 |
|
RW |
32 |
0x0000 0000 |
0x144 |
0x2000 2144 |
|
RW |
32 |
0x0000 0000 |
0x148 |
0x2000 2148 |
|
RW |
32 |
0x0000 0000 |
0x14C |
0x2000 214C |
|
RW |
32 |
0x0000 0000 |
0x150 |
0x2000 2150 |
|
RO |
32 |
0x0000 0000 |
0x154 |
0x2000 2154 |
|
RW |
32 |
0x0000 0000 |
0x158 |
0x2000 2158 |
|
RW |
32 |
0x0000 0000 |
0x15C |
0x2000 215C |
|
RW |
32 |
0x0000 0000 |
0x168 |
0x2000 2168 |
|
RW |
32 |
0x0000 0000 |
0x16C |
0x2000 216C |
|
RW |
32 |
0x0000 0000 |
0x170 |
0x2000 2170 |
|
RW |
32 |
0x0000 0000 |
0x174 |
0x2000 2174 |
|
RW |
32 |
0x0000 3FFF |
0x200 |
0x2000 2200 |
|
RW |
32 |
0xFFFF FFFF |
0x204 |
0x2000 2204 |
|
RW |
32 |
0x00FF FFFF |
0x208 |
0x2000 2208 |
|
RW |
32 |
0xFFFF FFFF |
0x20C |
0x2000 220C |
|
RW |
32 |
0xFFFF FFFF |
0x210 |
0x2000 2210 |
|
RW |
32 |
0xFFFF FFFF |
0x214 |
0x2000 2214 |
|
RW |
32 |
0x0000 0000 |
0x218 |
0x2000 2218 |
|
RW |
32 |
0x0828 0828 |
0x234 |
0x2000 2234 |
|
RW |
32 |
0x0828 0828 |
0x238 |
0x2000 2238 |
|
RW |
32 |
0x0828 0828 |
0x23C |
0x2000 223C |
|
RW |
32 |
0x0828 0828 |
0x240 |
0x2000 2240 |
|
RW |
32 |
0x0828 0828 |
0x244 |
0x2000 2244 |
|
RW |
32 |
0x0828 0828 |
0x248 |
0x2000 2248 |
|
RW |
32 |
0x0828 0828 |
0x24C |
0x2000 224C |
|
RW |
32 |
0x0828 0828 |
0x254 |
0x2000 2254 |
|
RW |
32 |
0x0828 0828 |
0x258 |
0x2000 2258 |
|
RW |
32 |
0x0828 0828 |
0x25C |
0x2000 225C |
|
RW |
32 |
0x0828 0828 |
0x260 |
0x2000 2260 |
|
RW |
32 |
0x0828 0828 |
0x264 |
0x2000 2264 |
|
RW |
32 |
0x0828 0828 |
0x268 |
0x2000 2268 |
|
RW |
32 |
0x0828 0828 |
0x26C |
0x2000 226C |
|
RW |
32 |
0x0828 0828 |
0x270 |
0x2000 2270 |
|
RW |
32 |
0x0828 0828 |
0x274 |
0x2000 2274 |
|
RW |
32 |
0x0828 0828 |
0x278 |
0x2000 2278 |
|
RW |
32 |
0x0828 0828 |
0x27C |
0x2000 227C |
|
RW |
32 |
0x0828 0828 |
0x280 |
0x2000 2280 |
|
RW |
32 |
0x0000 0000 |
0x2A8 |
0x2000 22A8 |
|
RW |
32 |
0x0000 0000 |
0x2AC |
0x2000 22AC |
|
RO |
32 |
0x0000 0000 |
0x2B0 |
0x2000 22B0 |
|
RO |
32 |
0x0000 0000 |
0x2B4 |
0x2000 22B4 |
|
RO |
32 |
0x0000 0000 |
0x2B8 |
0x2000 22B8 |
|
RO |
32 |
0x0000 0000 |
0x2BC |
0x2000 22BC |
|
RO |
32 |
0x0000 0000 |
0x2C0 |
0x2000 22C0 |
|
RO |
32 |
0x0000 0000 |
0x2C4 |
0x2000 22C4 |
|
RW |
32 |
0x0000 0000 |
0x2D0 |
0x2000 22D0 |
|
RW |
32 |
0x0000 0000 |
0x2D4 |
0x2000 22D4 |
|
RO |
32 |
0x0000 0000 |
0x2D8 |
0x2000 22D8 |
|
RW |
32 |
0x0000 0000 |
0x2DC |
0x2000 22DC |
|
RO |
32 |
0x0000 0000 |
0x2E0 |
0x2000 22E0 |
Address offset |
0x000 |
||
Physical address |
0x2000 2000 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Register for software use |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
DATA |
Scratch register for CPUS |
RW |
0x000A C7E1 |
Address offset |
0x004 |
||
Physical address |
0x2000 2004 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Register for software use |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
DATA |
Scratch register for CPUS |
RW |
0x0000 0000 |
Address offset |
0x008 |
||
Physical address |
0x2000 2008 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Master clock configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:9 |
Reserved |
|
RO |
0x00 0000 |
8 |
enable_1mhz |
When '1' requests pfsoc_control to enable the 1mHz (2MHz)
on-chip oscillator |
RW |
0 |
7:6 |
Reserved |
|
RO |
0x0 |
5:0 |
divider |
Sets the master synchronous clock divider |
RW |
0x10 |
Address offset |
0x00C |
||
Physical address |
0x2000 200C |
Instance |
pfsoc_mss_top_sysreg |
Description |
RTC clock divider |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:17 |
Reserved |
|
RO |
0x0000 |
16 |
enable |
RTC Clock enable. When chaning the divider the enable
should be trurned off first, the divider changed and the enable turned back
on. |
RW |
1 |
15:12 |
Reserved |
|
RO |
0x0 |
11:0 |
period |
Sets the division ratio to create the internal RTC clock
from the reference clock. |
RW |
0x064 |
Address offset |
0x010 |
||
Physical address |
0x2000 2010 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Fabric Reset mask |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
Reserved |
|
RO |
0x0000 0000 |
0 |
ENABLE |
This bitfield has no affect if changed |
RW |
0 |
Address offset |
0x014 |
||
Physical address |
0x2000 2014 |
Instance |
pfsoc_mss_top_sysreg |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
Reserved |
|
RO |
0x0000 0000 |
0 |
boot |
Written by firmware to indicate that the boot process
failed, drives the fab_boot_fail signal to the fabric. Is cleared by the
fabric asserting fab_boot_fail_clear |
RW |
0 |
Address offset |
0x018 |
||
Physical address |
0x2000 2018 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Allows the CPU to fully reset the MSS |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:16 |
Reserved |
|
RO |
0x0000 |
15:0 |
RESET_VALUE |
When written to 16'hDEAD will cause a full MSS reset. The
Reset wil clear this register. The register may be writtent to any value but
only a value off 16'hDEAD will cause the reset to happen |
RW |
0x0000 |
Address offset |
0x01C |
||
Physical address |
0x2000 201C |
Instance |
pfsoc_mss_top_sysreg |
Description |
Configuration lock |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
Reserved |
|
RO |
0x0000 0000 |
0 |
lock |
When written to '1' will cause all RWC registers to lock
until a master reset occurs. |
RW |
0 |
Address offset |
0x020 |
||
Physical address |
0x2000 2020 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Indicates which reset caused the last reset. After a reset
occurs register should be read and then zero written to allow the next reset
event to be correctly captured. |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:9 |
Reserved |
|
RO |
0x00 0000 |
8 |
CPU_SOFT_RESET |
Indicates that the CPU reset ths MSS using the soft reset
register |
RW |
1 |
7 |
SCB_BUS_RESET |
Indicates that SCB bus reset occurred (which causes warm
reset of MSS) |
RW |
1 |
6 |
GPIO_RESET |
Indicates that fabric asserted the GPIO reset inputs |
RW |
1 |
5 |
WDOG_RESET |
Reset was caused by the watchdog |
RW |
1 |
4 |
FABRIC_RESET |
Reset was caused by the fabric |
RW |
1 |
3 |
DEBUGER_RESET |
Reset was caused by the Risc-V Debugger |
RW |
1 |
2 |
SCB_CPU_RESET |
Reset was caused by the SCB CPU reset register |
RW |
1 |
1 |
SCB_MSS_RESET |
Reset was caused by the SCB MSS reset register |
RW |
1 |
0 |
SCB_PERIPH_RESET |
Reset was caused by the SCB periphery reset signal |
RW |
1 |
Address offset |
0x024 |
||
Physical address |
0x2000 2024 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Indicates the device status, in particular the state of
the FPGA fabric and the MSS IO banks |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:13 |
Reserved |
|
RO |
0x0 0000 |
12 |
IO_EN |
Indicates the status of the io_en input from G5 Control. |
RO |
0 |
11 |
io_bank_b6_status |
Power status of IO bank 6 |
RO |
0 |
10 |
io_bank_b5_status |
Power status of IO bank 5 |
RO |
0 |
9 |
io_bank_b4_status |
Power status of IO bank 4 |
RO |
0 |
8 |
io_bank_b2_status |
Power status of IO bank 2 |
RO |
0 |
7:4 |
Reserved |
|
RO |
0x0 |
3 |
FLASH_VALID |
Indicates the status of the flash_valid input from G5
Control. |
RO |
0 |
2 |
FF_IN_PROGRESS |
Indicates the status of the ff_in_progress input from G5
Control. |
RO |
0 |
1 |
LP_STATE |
Indicates the status of the lp_state input from G5
Control. |
RO |
0 |
0 |
CORE_UP |
Indicates the status of the core_up input from G5 Control.
|
RO |
0 |
Address offset |
0x028 |
||
Physical address |
0x2000 2028 |
Instance |
pfsoc_mss_top_sysreg |
Description |
MSS Build Info |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
REVISION |
Set to the SVN revision of the pfsoc_mss_main.sv file |
RO |
0x0000 0000 |
Address offset |
0x040 |
||
Physical address |
0x2000 2040 |
Instance |
pfsoc_mss_top_sysreg |
Description |
U54-1 Fabric interrupt enable |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
ENABLE |
Enables the F2H_interrupts[31:0] to interrupt U54_1
directly |
RW |
0x0000 0000 |
Address offset |
0x044 |
||
Physical address |
0x2000 2044 |
Instance |
pfsoc_mss_top_sysreg |
Description |
U54-2 Fabric interrupt enable |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
ENABLE |
Enables the F2H_interrupts[31:0] to interrupt U54_1
directly |
RW |
0x0000 0000 |
Address offset |
0x048 |
||
Physical address |
0x2000 2048 |
Instance |
pfsoc_mss_top_sysreg |
Description |
U54-3 Fabric interrupt enable |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
ENABLE |
Enables the F2H_interrupts[31:0] to interrupt U54_1
directly |
RW |
0x0000 0000 |
Address offset |
0x04C |
||
Physical address |
0x2000 204C |
Instance |
pfsoc_mss_top_sysreg |
Description |
U54-4 Fabric interrupt enable |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
ENABLE |
Enables the F2H_interrupts[31:0] to interrupt U54_1
directly |
RW |
0x0000 0000 |
Address offset |
0x050 |
||
Physical address |
0x2000 2050 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Allows the Ethernat interrupts to be directly routed to
the U54 CPUS. |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
Reserved |
|
RO |
0x000 0000 |
3 |
MAC1_U54_4 |
Enables the Ethernet MAC1 to interrupt U54_1 directly |
RW |
0 |
2 |
MAC1_U54_3 |
Enables the Ethernet MAC1 to interrupt U54_1 directly |
RW |
0 |
1 |
MAC0_U54_2 |
Enables the Ethernet MAC0 to interrupt U54_1 directly |
RW |
0 |
0 |
MAC0_U54_1 |
Enables the Ethernet MAC0 to interrupt U54_1 directly |
RW |
0 |
Address offset |
0x054 |
||
Physical address |
0x2000 2054 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Switches GPIO interrupt from PAD to Fabric GPIO |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
select |
Setting these bits will disable the Pad interrupt, and
enable the fabric GPIO interrupt for bits 31:0. When the bit is set the Pad
interrupt will be ORED into the GPIO0 & GPIO1 non-direct interrupts. When
the bit is not set the Fabric interrupt is ORED into the GPIO2 non-direct
interrupt. To prevent ORING then the interrupt should not be enabled in the
GPIO block |
RW |
0x0000 0000 |
Address offset |
0x080 |
||
Physical address |
0x2000 2080 |
Instance |
pfsoc_mss_top_sysreg |
Description |
AMP Mode peripheral mapping register. |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
h2fint |
|
RW |
0 |
22 |
rtc |
|
RW |
0 |
21 |
gpio2 |
|
RW |
0 |
20 |
gpio1 |
|
RW |
0 |
19 |
gpio0 |
|
RW |
0 |
18 |
timer |
|
RW |
0 |
17 |
gem1 |
|
RW |
0 |
16 |
gem0 |
|
RW |
0 |
15 |
can1 |
|
RW |
0 |
14 |
can0 |
|
RW |
0 |
13 |
i2c1 |
|
RW |
0 |
12 |
i2c0 |
|
RW |
0 |
11 |
spi1 |
|
RW |
0 |
10 |
spi0 |
|
RW |
0 |
9 |
wdog4 |
|
RW |
0 |
8 |
wdog3 |
|
RW |
0 |
7 |
wdog2 |
|
RW |
0 |
6 |
wdog1 |
|
RW |
0 |
5 |
wdog0 |
|
RW |
0 |
4 |
mmuart4 |
|
RW |
0 |
3 |
mmuart3 |
|
RW |
0 |
2 |
mmuart2 |
|
RW |
0 |
1 |
mmuart1 |
|
RW |
0 |
0 |
mmuart0 |
|
RW |
0 |
Address offset |
0x084 |
||
Physical address |
0x2000 2084 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Enables the clock to the MSS peripheral. By turning clocks
off dynamic power can be saved. |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:30 |
Reserved |
|
RO |
0x0 |
29 |
CFM |
|
RW |
0 |
28 |
ATHENA |
|
RW |
0 |
27 |
FIC3 |
|
RW |
0 |
26 |
FIC2 |
|
RW |
0 |
25 |
FIC1 |
|
RW |
0 |
24 |
FIC0 |
|
RW |
0 |
23 |
DDRC |
|
RW |
0 |
22 |
GPIO2 |
|
RW |
0 |
21 |
GPIO1 |
|
RW |
0 |
20 |
GPIO0 |
|
RW |
0 |
19 |
QSPI |
|
RW |
0 |
18 |
RTC |
|
RW |
0 |
17 |
Reserved |
|
RO |
0 |
16 |
USB |
|
RW |
0 |
15 |
CAN1 |
|
RW |
0 |
14 |
CAN0 |
|
RW |
0 |
13 |
I2C1 |
|
RW |
0 |
12 |
I2C0 |
|
RW |
0 |
11 |
SPI1 |
|
RW |
0 |
10 |
SPI0 |
|
RW |
0 |
9 |
MMUART4 |
|
RW |
0 |
8 |
MMUART3 |
|
RW |
0 |
7 |
MMUART2 |
|
RW |
0 |
6 |
MMUART1 |
|
RW |
0 |
5 |
MMUART0 |
|
RW |
0 |
4 |
TIMER |
|
RW |
0 |
3 |
MMC |
|
RW |
0 |
2 |
MAC1 |
|
RW |
0 |
1 |
MAC0 |
|
RW |
0 |
0 |
ENVM |
|
RW |
1 |
Address offset |
0x088 |
||
Physical address |
0x2000 2088 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Holds the MSS peripherals in reset. |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:30 |
Reserved |
|
RO |
0x0 |
29 |
CFM |
|
RW |
1 |
28 |
ATHENA |
|
RW |
1 |
27 |
FIC3 |
|
RW |
1 |
26 |
FIC2 |
|
RW |
1 |
25 |
FIC1 |
|
RW |
1 |
24 |
FIC0 |
|
RW |
1 |
23 |
DDRC |
|
RW |
1 |
22 |
GPIO2 |
|
RW |
1 |
21 |
GPIO1 |
|
RW |
1 |
20 |
GPIO0 |
|
RW |
1 |
19 |
QSPI |
|
RW |
1 |
18 |
RTC |
|
RW |
1 |
17 |
FPGA |
|
RW |
1 |
16 |
USB |
|
RW |
1 |
15 |
CAN1 |
|
RW |
1 |
14 |
CAN0 |
|
RW |
1 |
13 |
I2C1 |
|
RW |
1 |
12 |
I2C0 |
|
RW |
1 |
11 |
SPI1 |
|
RW |
1 |
10 |
SPI0 |
|
RW |
1 |
9 |
MMUART4 |
|
RW |
1 |
8 |
MMUART3 |
|
RW |
1 |
7 |
MMUART2 |
|
RW |
1 |
6 |
MMUART1 |
|
RW |
1 |
5 |
MMUART0 |
|
RW |
1 |
4 |
TIMER |
|
RW |
1 |
3 |
MMC |
|
RW |
1 |
2 |
MAC1 |
|
RW |
1 |
1 |
MAC0 |
|
RW |
1 |
0 |
ENVM |
|
RW |
0 |
Address offset |
0x08C |
||
Physical address |
0x2000 208C |
Instance |
pfsoc_mss_top_sysreg |
Description |
Configures how many outstanding transfers the AXI-AHB
bridges in front off the USB and Crypto blocks should allow. (See Synopsys
AXI-AHB bridge documentation) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:16 |
Reserved |
|
RO |
0x0000 |
15:12 |
ATHENA_RBCNT |
Number of outstanding read transactions to Athena block |
RW |
0xF |
11:8 |
ATHENA_WBCNT |
Number of outstanding write transactions to Athena block |
RW |
0xF |
7:4 |
USB_RBCNT |
Number of outstanding read transactions to USB block |
RW |
0xF |
3:0 |
USB_WBCNT |
Number of outstanding write transactions to USB block |
RW |
0xF |
Address offset |
0x090 |
||
Physical address |
0x2000 2090 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Configures the two AHB-APB bridges on S5 and S6 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:2 |
Reserved |
|
RO |
0x0000 0000 |
1 |
APB1_POSTED |
Enables posted mode on the AHB-APB bridge, when set the
AHB write cycle will complete before the APB write cycle completes. |
RW |
0 |
0 |
APB0_POSTED |
Enables posted mode on the AHB-APB bridge, when set the
AHB write cycle will complete before the APB write cycle completes. |
RW |
0 |
Address offset |
0x098 |
||
Physical address |
0x2000 2098 |
Instance |
pfsoc_mss_top_sysreg |
Description |
MSS Corner APB interface controls |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:2 |
Reserved |
|
RO |
0x0000 0000 |
1 |
reset |
Asserts the APB reset to the MSS corner, is asserted at
MSS reset. |
RW |
1 |
0 |
clockon |
Turns on the APB clock to the MSS Corner, is off at reset.
Once corner blocks is configured the firmware may turn off the clock, but
periodically should turn back on to allow refresh of TMR registers inside the
corner block. |
RW |
0 |
Address offset |
0x09C |
||
Physical address |
0x2000 209C |
Instance |
pfsoc_mss_top_sysreg |
Description |
GPIO Blocks reset control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23:20 |
gpio2_default |
Sets the reset value off the GPIO0 per byte |
RW |
0x0 |
19:16 |
gpio2_soft_reset_select |
This signal selects whether the associated byte is reset
by soft reset or the the MSS_GPIO_RESET_N signal from the FPGA fabric. The
allowed values are: |
RW |
0xF |
15 |
Reserved |
|
RO |
0 |
14:12 |
gpio1_default |
Sets the reset value off the GPIO0 per byte |
RW |
0x0 |
11 |
Reserved |
|
RO |
0 |
10:8 |
gpio1_soft_reset_select |
This signal selects whether the associated byte is reset
by soft reset or the the MSS_GPIO_RESET_N signal from the FPGA fabric. The
allowed values are: |
RW |
0x7 |
7:6 |
Reserved |
|
RO |
0x0 |
5:4 |
gpio0_default |
Sets the reset value off the GPIO0 per byte |
RW |
0x0 |
3:2 |
Reserved |
|
RO |
0x0 |
1:0 |
gpio0_soft_reset_select |
This signal selects whether the associated byte is reset
by soft reset or the the MSS_GPIO_RESET_N signal from the FPGA fabric. The
allowed values are: |
RW |
0x3 |
Address offset |
0x0A4 |
||
Physical address |
0x2000 20A4 |
Instance |
pfsoc_mss_top_sysreg |
Description |
MAC0 configuration register |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
Reserved |
|
RO |
0x000 0000 |
3:0 |
speed_mode |
Current speed mode on the MAC |
RO |
0x0 |
Address offset |
0x0A8 |
||
Physical address |
0x2000 20A8 |
Instance |
pfsoc_mss_top_sysreg |
Description |
MAC1 configuration register |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
Reserved |
|
RO |
0x000 0000 |
3:0 |
speed_mode |
Current speed mode on the MAC |
RO |
0x0 |
Address offset |
0x0AC |
||
Physical address |
0x2000 20AC |
Instance |
pfsoc_mss_top_sysreg |
Description |
USB Configuration register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
Reserved |
|
RO |
0x000 0000 |
3 |
LPI_CARKIT_EN |
Set when entry is made into CarKit mode and cleared on
exit from CarKit mode. |
RO |
0 |
2 |
POWERDOWN |
Indicates that the USB CLK may be stopped to save power.
Derived from combination of signals from CLK & XCLK flip-flops, AVALID,
VBUSVALID and LINESTATE. When asserted the USB clock into the core is
stopped. |
RO |
1 |
1 |
powerdown_enable |
When '1' will stops the clock to the USB core when the
core asserts its POWERDOWN output. For G4 compatability this bit defaults to
0. |
RW |
0 |
0 |
DDR_SELECT |
Configures USB for Single-Data Rate(SDR) mode or
Double-Data Rate(DDR) mode. |
RO |
0 |
Address offset |
0x0B0 |
||
Physical address |
0x2000 20B0 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Crypto Mesh control and status register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:26 |
Reserved |
|
RO |
0x00 |
25 |
OKAY |
Indicates that the Mesh is functioning correctly. Will be set
approximately 520 clock cycles after mesh started and stay set as long as the
mesh is not detecting any errors. |
RO |
0 |
24 |
MESH_ERROR |
Indicates that Mesh detected an error. Cleared by writing
a '1' |
RW |
0 |
23:17 |
Reserved |
|
RO |
0x00 |
16 |
INJECT_ERROR |
When set will inject an error in the mesh |
RW |
0 |
15:13 |
Reserved |
|
RO |
0x0 |
12:1 |
HOLD |
Sets the amount of time that the mesh is held active for,
actual hold time includes up to 256 us of random variation. |
RW |
0x027 |
0 |
START |
Writing a 1 will start the Mesh System |
RW |
0 |
Address offset |
0x0B4 |
||
Physical address |
0x2000 20B4 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Crypto mesh seed and update rate |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
clkrate |
Sets the rate that the mesh value is changed. Rate =
AHBCLK/(clkrate+1). Rate must be less than 1MHz, setting slower will reduce
power consumption. |
RW |
0xC7 |
23 |
Reserved |
|
RO |
0 |
22:0 |
seed |
Sets the mesh seed value, any value may be used, zero
should be avoided |
RW |
0x00 5EED |
Address offset |
0x0B8 |
||
Physical address |
0x2000 20B8 |
Instance |
pfsoc_mss_top_sysreg |
Description |
ENVM AHB Controller setup |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
timer |
Sets the duration of the timer used to detect a non
response of slow response from the PNVM on C and R bus accesses. |
RW |
0x40 |
23:19 |
Reserved |
|
RO |
0x00 |
18 |
interrupt_enable |
Enable the ENVM interrupt |
RW |
1 |
17 |
slowread |
When '1' the controller will initate separate ENVM reads
for all reads. No buffering or speculative operations will be carried out.
When performing word reads incrementing through PNVM each location will be
read twice (intended for test use) |
RW |
0 |
16 |
readahead |
Enables "readahead" on the ENVM controller. The controller
will automatically read the next PNVM location as soon as possible ahead of
the AHB request. This will improve read performance when incrementing though
memory as the NVM reads and AHB cycles are pipelined. When set non
incrementing accesses will take longer as the controller may be in the
process of reading the next address and the PNVM cycle needs to complete
prior to starting the required read |
RW |
1 |
15:10 |
Reserved |
|
RO |
0x00 |
9 |
clock_suppress |
When set suppresses clock edge between C-Bus access cycles
so that they appear as consecutive access cycles. |
RW |
0 |
8 |
clock_continuous |
When '1' the PNVM clock will be always generated, and not
stopped between access cycles. Setting this will increase access latency but
mean that the PNVM clock operates at a stable rate. |
RW |
0 |
7 |
Reserved |
|
RO |
0 |
6 |
clock_okay |
Indicates the eNVM is running at the configured divider
rate. |
RO |
1 |
5:0 |
clock_period |
Sets the number of AHB cycles used to generate the PNVM
clock, |
RW |
0x0F |
Address offset |
0x0BC |
||
Physical address |
0x2000 20BC |
Instance |
pfsoc_mss_top_sysreg |
Description |
Reserved |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
Reserved |
|
RO |
0x0000 0000 |
0 |
Reserved |
Reserved register
address |
RO |
0 |
Address offset |
0x0C0 |
||
Physical address |
0x2000 20C0 |
Instance |
pfsoc_mss_top_sysreg |
Description |
QOS Athena, USB & MMC Configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:28 |
trace_write |
Sets the QOS value from the specified device into the
switch |
RW |
0x0 |
27:24 |
trace_read |
Sets the QOS value from the specified device into the
switch |
RW |
0x0 |
23:20 |
mmc_write |
Sets the QOS value from the specified device into the
switch |
RW |
0x0 |
19:16 |
mmc_read |
Sets the QOS value from the specified device into the
switch |
RW |
0x0 |
15:12 |
usb_write |
Sets the QOS value from the specified device into the
switch |
RW |
0x0 |
11:8 |
usb_read |
Sets the QOS value from the specified device into the
switch |
RW |
0x0 |
7:4 |
athena_write |
Sets the QOS value from the specified device into the
switch |
RW |
0x0 |
3:0 |
athena_read |
Sets the QOS value from the specified device into the
switch |
RW |
0x0 |
Address offset |
0x0C4 |
||
Physical address |
0x2000 20C4 |
Instance |
pfsoc_mss_top_sysreg |
Description |
QOS Configuration Coreplex |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:28 |
fabric1_write |
Sets the QOS value from the specified device into the
switch |
RW |
0x0 |
27:24 |
fabric1_read |
Sets the QOS value from the specified device into the
switch |
RW |
0x0 |
23:20 |
fabric0_write |
Sets the QOS value from the specified device into the
switch |
RW |
0x0 |
19:16 |
fabric0_read |
Sets the QOS value from the specified device into the
switch |
RW |
0x0 |
15:12 |
device1_write |
Sets the QOS value from the specified device into the
switch |
RW |
0x0 |
11:8 |
device1_read |
Sets the QOS value from the specified device into the
switch |
RW |
0x0 |
7:4 |
device0_write |
Sets the QOS value from the specified device into the
switch |
RW |
0x0 |
3:0 |
device0_read |
Sets the QOS value from the specified device into the
switch |
RW |
0x0 |
Address offset |
0x0C8 |
||
Physical address |
0x2000 20C8 |
Instance |
pfsoc_mss_top_sysreg |
Description |
QOS configuration DDRC |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:16 |
Reserved |
|
RO |
0x0000 |
15:12 |
ncache_write |
Sets the QOS value from the specified device into the
switch |
RW |
0x0 |
11:8 |
ncache_read |
Sets the QOS value from the specified device into the
switch |
RW |
0x0 |
7:4 |
cache_write |
Sets the QOS value from the specified device into the
switch |
RW |
0x0 |
3:0 |
cache_read |
Sets the QOS value from the specified device into the
switch |
RW |
0x0 |
Address offset |
0x0F0 |
||
Physical address |
0x2000 20F0 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Indicates that a master caused a MPU violation. Interrupts
via maintenance interrupt. |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:10 |
Reserved |
|
RO |
0x00 0000 |
9 |
trace |
Bit is set on violation. Cleared by writing '1' |
RW |
0 |
8 |
scb |
Bit is set on violation. Cleared by writing '1' |
RW |
0 |
7 |
mmc |
Bit is set on violation. Cleared by writing '1' |
RW |
0 |
6 |
usb |
Bit is set on violation. Cleared by writing '1' |
RW |
0 |
5 |
gem1 |
Bit is set on violation. Cleared by writing '1' |
RW |
0 |
4 |
gem0 |
Bit is set on violation. Cleared by writing '1' |
RW |
0 |
3 |
athena |
Bit is set on violation. Cleared by writing '1' |
RW |
0 |
2 |
fic2 |
Bit is set on violation. Cleared by writing '1' |
RW |
0 |
1 |
fic1 |
Bit is set on violation. Cleared by writing '1' |
RW |
0 |
0 |
fic0 |
Bit is set on violation. Cleared by writing '1' |
RW |
0 |
Address offset |
0x0F4 |
||
Physical address |
0x2000 20F4 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Enables interrupts on MPU violations |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:10 |
Reserved |
|
RO |
0x00 0000 |
9 |
trace |
Enables the interrupt |
RW |
0 |
8 |
scb |
Enables the interrupt |
RW |
0 |
7 |
mmc |
Enables the interrupt |
RW |
0 |
6 |
usb |
Enables the interrupt |
RW |
0 |
5 |
gem1 |
Enables the interrupt |
RW |
0 |
4 |
gem0 |
Enables the interrupt |
RW |
0 |
3 |
athena |
Enables the interrupt |
RW |
0 |
2 |
fic2 |
Enables the interrupt |
RW |
0 |
1 |
fic1 |
Enables the interrupt |
RW |
0 |
0 |
fic0 |
Enables the interrupt |
RW |
0 |
Address offset |
0x0F8 |
||
Physical address |
0x2000 20F8 |
Instance |
pfsoc_mss_top_sysreg |
Description |
AXI switch decode fail |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
addr |
The address (bits 31:0) that failed. Redaing this address
as 64-bits will return the 38-bit address in assingle read combined with
additional information in the next register |
RO |
0x0000 0000 |
Address offset |
0x0FC |
||
Physical address |
0x2000 20FC |
Instance |
pfsoc_mss_top_sysreg |
Description |
AXI switch decode fail |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:18 |
Reserved |
|
RO |
0x0000 |
17 |
failed |
|
RW |
0 |
16 |
write |
AXI write=1 or read=0 |
RO |
0 |
15:8 |
ID |
AXI ID off failure |
RO |
0x00 |
7:6 |
Reserved |
|
RO |
0x0 |
5:0 |
addr |
Upper 6 bits off address [37:32] |
RO |
0x00 |
Address offset |
0x100 |
||
Physical address |
0x2000 2100 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Set when an ECC event happens |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:14 |
Reserved |
|
RO |
0x0 0000 |
13 |
CAN1_2E |
|
RW |
0 |
12 |
CAN1_1E |
|
RW |
0 |
11 |
CAN0_2E |
|
RW |
0 |
10 |
CAN0_1E |
|
RW |
0 |
9 |
USB_2E |
|
RW |
0 |
8 |
USB_1E |
|
RW |
0 |
7 |
MAC1_2E |
|
RW |
0 |
6 |
MAC1_1E |
|
RW |
0 |
5 |
MAC0_2E |
|
RW |
0 |
4 |
MAC0_1E |
|
RW |
0 |
3 |
DDRC_2E |
|
RW |
0 |
2 |
DDRC_1E |
|
RW |
0 |
1 |
MMC_2E |
|
RW |
0 |
0 |
MMC_1E |
|
RW |
0 |
Address offset |
0x104 |
||
Physical address |
0x2000 2104 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Enables ECC interrupt on event |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:14 |
Reserved |
|
RO |
0x0 0000 |
13 |
CAN1_2E |
|
RW |
0 |
12 |
CAN1_1E |
|
RW |
0 |
11 |
CAN0_2E |
|
RW |
0 |
10 |
CAN0_1E |
|
RW |
0 |
9 |
USB_2E |
|
RW |
0 |
8 |
USB_1E |
|
RW |
0 |
7 |
MAC1_2E |
|
RW |
0 |
6 |
MAC1_1E |
|
RW |
0 |
5 |
MAC0_2E |
|
RW |
0 |
4 |
MAC0_1E |
|
RW |
0 |
3 |
DDRC_2E |
|
RW |
0 |
2 |
DDRC_1E |
|
RW |
0 |
1 |
MMC_2E |
|
RW |
0 |
0 |
MMC_1E |
|
RW |
0 |
Address offset |
0x108 |
||
Physical address |
0x2000 2108 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Count off single bit errors |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:10 |
Reserved |
|
RO |
0x00 0000 |
9:0 |
COUNT |
|
RW |
0x000 |
Address offset |
0x10C |
||
Physical address |
0x2000 210C |
Instance |
pfsoc_mss_top_sysreg |
Description |
Count off single bit errors |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:10 |
Reserved |
|
RO |
0x00 0000 |
9:0 |
COUNT |
|
RW |
0x000 |
Address offset |
0x110 |
||
Physical address |
0x2000 2110 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Count off single bit errors |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:10 |
Reserved |
|
RO |
0x00 0000 |
9:0 |
COUNT |
|
RW |
0x000 |
Address offset |
0x114 |
||
Physical address |
0x2000 2114 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Count off single bit errors |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:10 |
Reserved |
|
RO |
0x00 0000 |
9:0 |
COUNT |
|
RW |
0x000 |
Address offset |
0x118 |
||
Physical address |
0x2000 2118 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Count off single bit errors |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:10 |
Reserved |
|
RO |
0x00 0000 |
9:0 |
COUNT |
|
RW |
0x000 |
Address offset |
0x11C |
||
Physical address |
0x2000 211C |
Instance |
pfsoc_mss_top_sysreg |
Description |
Count off single bit errors |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:10 |
Reserved |
|
RO |
0x00 0000 |
9:0 |
COUNT |
|
RW |
0x000 |
Address offset |
0x120 |
||
Physical address |
0x2000 2120 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Count off single bit errors |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:10 |
Reserved |
|
RO |
0x00 0000 |
9:0 |
COUNT |
|
RW |
0x000 |
Address offset |
0x124 |
||
Physical address |
0x2000 2124 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Will Corrupt write data to rams, 1E corrupts bit 0, 2E
bits 1 and 2. |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:14 |
Reserved |
|
RO |
0x0 0000 |
13 |
CAN1_2E |
|
RW |
0 |
12 |
CAN1_1E |
|
RW |
0 |
11 |
CAN0_2E |
|
RW |
0 |
10 |
CAN0_1E |
|
RW |
0 |
9 |
USB_2E |
|
RW |
0 |
8 |
USB_1E |
|
RW |
0 |
7 |
MAC1_2E |
|
RW |
0 |
6 |
MAC1_1E |
|
RW |
0 |
5 |
MAC0_2E |
|
RW |
0 |
4 |
MAC0_1E |
|
RW |
0 |
3 |
DDRC_2E |
|
RW |
0 |
2 |
DDRC_1E |
|
RW |
0 |
1 |
MMC_2E |
|
RW |
0 |
0 |
MMC_1E |
|
RW |
0 |
Address offset |
0x140 |
||
Physical address |
0x2000 2140 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Maintenance Interrupt Enable. |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:21 |
Reserved |
|
RO |
0x000 |
20 |
dll |
Enables interrupt on a DLL event, DLL_STATUS_INTEN_CR
should also be set |
RW |
0 |
19 |
io_bank_b6_off |
Enables interrupt on bank6 powered off |
RW |
0 |
18 |
io_bank_b5_off |
Enables interrupt on bank5 powered off |
RW |
0 |
17 |
io_bank_b4_off |
Enables interrupt on bank4 powered off |
RW |
0 |
16 |
io_bank_b2_off |
Enables interrupt on bank2 powered off |
RW |
0 |
15 |
io_bank_b6_on |
Enables interrupt on bank6 powered on |
RW |
0 |
14 |
io_bank_b5_on |
Enables interrupt on bank5 powered on |
RW |
0 |
13 |
io_bank_b4_on |
Enables interrupt on bank4 powered on |
RW |
0 |
12 |
io_bank_b2_on |
Enables interrupt on bank2 powered on |
RW |
0 |
11 |
mesh_error |
Enables interrupt on Mesh violation detection |
RW |
0 |
10 |
scb_fault |
Enables interrupt on SCB failure |
RW |
0 |
9 |
scb_error |
Enables interrupt on SCB error |
RW |
0 |
8 |
fpga_off |
Enables interrupt when FPGA turned off |
RW |
0 |
7 |
fpga_on |
Enables interrupt when FPGA turned on |
RW |
0 |
6 |
ff_end |
Enables interrupt as flash_freeze goes low |
RW |
0 |
5 |
ff_start |
Enables interrupt as flash_freeze goes high |
RW |
0 |
4 |
lp_state_exit |
Enables interrupt as lp_state goes low |
RW |
0 |
3 |
lp_state_enter |
Enables interrupt as lp_state goes high |
RW |
0 |
2 |
decode |
Enables interrupt on a AXI switch decode error |
RW |
0 |
1 |
mpu |
Enables interrupt on a MPU access violation |
RW |
0 |
0 |
pll |
Enables interrupt on a PLL event, PLL_STATUS_INTEN_CR
should also be set |
RW |
0 |
Address offset |
0x144 |
||
Physical address |
0x2000 2144 |
Instance |
pfsoc_mss_top_sysreg |
Description |
PLL Status interrupt enables |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:7 |
Reserved |
|
RO |
0x000 0000 |
6 |
SGMII_UNLOCK |
Enables interrupt on SGMII PLL unlocking |
RW |
0 |
5 |
DFI_UNLOCK |
Enables interrupt on DFT PLL unlocking |
RW |
0 |
4 |
CPU_UNLOCK |
Enables interrupt on CPU PLL unlocking |
RW |
0 |
3 |
Reserved |
|
RO |
0 |
2 |
SGMII_LOCK |
Enables interrupt on SGMII PLL locking |
RW |
0 |
1 |
DFI_LOCK |
Enables interrupt on DFT PLL locking |
RW |
0 |
0 |
CPU_LOCK |
Enables interrupt on CPU PLL locking |
RW |
0 |
Address offset |
0x148 |
||
Physical address |
0x2000 2148 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Maintenace interrupt, indicates fault and status events. |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:21 |
Reserved |
|
RO |
0x000 |
20 |
dll |
Indicates that IO bank 6 has turned off, cleared by
writing a '1' |
RO |
0 |
19 |
io_bank_b6_off |
Indicates that one off the DLLs whent into the lock or
unlock state. Cleared via DLL status register |
RW |
0 |
18 |
io_bank_b5_off |
Indicates that IO bank 5 has turned off, cleared by
writing a '1' |
RW |
0 |
17 |
io_bank_b4_off |
Indicates that IO bank 4 has turned off, cleared by
writing a '1' |
RW |
0 |
16 |
io_bank_b2_off |
Indicates that IO bank 2 has turned off, cleared by
writing a '1' |
RW |
0 |
15 |
io_bank_b6_on |
Indicates that IO bank 6 has turned on, cleared by writing
a '1' |
RW |
0 |
14 |
io_bank_b5_on |
Indicates that IO bank 5 has turned on, cleared by writing
a '1' |
RW |
0 |
13 |
io_bank_b4_on |
Indicates that IO bank 4 has turned on, cleared by writing
a '1' |
RW |
0 |
12 |
io_bank_b2_on |
Indicates that IO bank 2 has turned on, cleared by writing
a '1' |
RW |
0 |
11 |
mesh_error |
Indicates that the mesh over the Crypto triggered, cleared
via Mesh system error |
RO |
0 |
10 |
scb_fault |
Indicates that the SCB bus fault occurred, cleared via SCB
controller |
RO |
0 |
9 |
scb_error |
Indicates that the SCB slave reported an error, cleared
via SCB controller |
RO |
0 |
8 |
fpga_off |
Indicates that the FPGA array has been turned off, cleared
by writing a '1' |
RW |
0 |
7 |
fpga_on |
Indicates that the FPGA array has been turned on, cleared
by writing a '1' |
RW |
0 |
6 |
ff_end |
Indicates the device has exited the flash freezer state,
cleared by writing '1' |
RW |
0 |
5 |
ff_start |
Indicates the device has entered the flash freezer state,
cleared by writing '1' |
RW |
0 |
4 |
lp_state_exit |
Indicates the device has exited the lower power state,
cleared by writing '1' |
RW |
0 |
3 |
lp_state_enter |
Indicates the device has entered the lower power state,
cleared by writing '1' |
RW |
0 |
2 |
decode |
Indicates that the AXI switch detected an illegal address.
Cleared when SREG.SW_FAIL.ADDR1_CR_FAILED is cleared. |
RO |
0 |
1 |
mpu |
Indicates that one off the MPUS signaled a MPU violation.
Cleared via MPU Violation Register |
RO |
0 |
0 |
pll |
Indicates that one off the PLLs whent into the lock or
unlock state. Cleared via PLL status register |
RO |
0 |
Address offset |
0x14C |
||
Physical address |
0x2000 214C |
Instance |
pfsoc_mss_top_sysreg |
Description |
PLL interrupt register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:11 |
Reserved |
|
RO |
0x00 0000 |
10 |
SGMII_LOCK_NOW |
Current state off SGMII PLL locked signal |
RO |
0 |
9 |
DFI_LOCK_NOW |
Current state off DFI PLL locked signal |
RO |
0 |
8 |
CPU_LOCK_NOW |
Current state off CPU PLL locked signal |
RO |
0 |
7 |
Reserved |
|
RO |
0 |
6 |
SGMII_UNLOCK |
Indicates that the SGMII PLL has unlocked, cleared by
writing a '1' |
RW |
0 |
5 |
DFI_UNLOCK |
Indicates that the DFI PLL has unlocked, cleared by
writing a '1' |
RW |
0 |
4 |
CPU_UNLOCK |
Indicates that the CPU PLL has unlocked, cleared by
writing a '1' |
RW |
0 |
3 |
Reserved |
|
RO |
0 |
2 |
SGMII_LOCK |
Indicates that the SGMII PLL has locked, cleared by
writing a '1' |
RW |
0 |
1 |
DFI_LOCK |
Indicates that the DFI PLL has locked, cleared by writing
a '1' |
RW |
0 |
0 |
CPU_LOCK |
Indicates that the CPU PLL has locked, cleared by writing
a '1' |
RW |
0 |
Address offset |
0x150 |
||
Physical address |
0x2000 2150 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Enable to CFM Timer |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:5 |
Reserved |
|
RO |
0x000 0000 |
4:0 |
Enable |
When set and the CFM channel is in timer mode and CFM
channel is set to 2 (Group C) this register allows the timet to count. Allows
software to start and stop the timers. |
RW |
0x00 |
Address offset |
0x154 |
||
Physical address |
0x2000 2154 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Miscellanous Register |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:2 |
Reserved |
|
RO |
0x0000 0000 |
1 |
VOLT_TEMP_ALARM |
Indicates that the user voltage or temperature detectors
are signalling an alarm condition. |
RO |
0 |
0 |
CONT_SPI_INTERRUPT |
Indicates that Interrupt from the PFC MSS SCB SPI
controller is active |
RO |
0 |
Address offset |
0x158 |
||
Physical address |
0x2000 2158 |
Instance |
pfsoc_mss_top_sysreg |
Description |
DLL Interrupt enables |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:13 |
Reserved |
|
RO |
0x0 0000 |
12 |
FIC4_UNLOCK |
Enables the DLL4 (crypto) unlock interrupt |
RW |
0 |
11 |
FIC3_UNLOCK |
Enables the DLL3 unlock interrupt |
RW |
0 |
10 |
FIC2_UNLOCK |
Enables the DLL2 unlock interrupt |
RW |
0 |
9 |
FIC1_UNLOCK |
Enables the DLL1 unlock interrupt |
RW |
0 |
8 |
FIC0_UNLOCK |
Enables the DLL0 unlock interrupt |
RW |
0 |
7:6 |
Reserved |
|
RO |
0x0 |
5 |
FIC4_LOCK |
Enables the DLL4 (Crypto) lock interrupt |
RW |
0 |
4 |
FIC3_LOCK |
Enables the DLL3 lock interrupt |
RW |
0 |
3 |
Reserved |
|
RO |
0 |
2 |
FIC2_LOCK |
Enables the DLL2 lock interrupt |
RW |
0 |
1 |
FIC1_LOCK |
Enables the DLL1 lock interrupt |
RW |
0 |
0 |
FIC0_LOCK |
Enables the DLL0 lock interrupt |
RW |
0 |
Address offset |
0x15C |
||
Physical address |
0x2000 215C |
Instance |
pfsoc_mss_top_sysreg |
Description |
DLL interrupt register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:21 |
Reserved |
|
RO |
0x000 |
20 |
FIC4_LOCK_NOW |
Current state off FIC4 DLL locked signal |
RO |
0 |
19 |
FIC3_LOCK_NOW |
Current state off FIC3 DLL locked signal |
RO |
0 |
18 |
FIC2_LOCK_NOW |
Current state off FIC2 DLL locked signal |
RO |
0 |
17 |
FIC1_LOCK_NOW |
Current state off FIC1 DLL locked signal |
RO |
0 |
16 |
FIC0_LOCK_NOW |
Current state off FIC0 DLL locked signal |
RO |
0 |
15:13 |
Reserved |
|
RO |
0x0 |
12 |
FIC4_UNLOCK |
Indicates that the FIC4 (Crypto) DLL has unlocked, cleared
by writing a '1' |
RW |
0 |
11 |
FIC3_UNLOCK |
Indicates that the FIC3 DLL has unlocked, cleared by
writing a '1' |
RW |
0 |
10 |
FIC2_UNLOCK |
Indicates that the FIC2 DLL has unlocked, cleared by
writing a '1' |
RW |
0 |
9 |
FIC1_UNLOCK |
Indicates that the FIC1 DLL has unlocked, cleared by
writing a '1' |
RW |
0 |
8 |
FIC0_UNLOCK |
Indicates that the FIC0 DLL has unlocked, cleared by
writing a '1' |
RW |
0 |
7:6 |
Reserved |
|
RO |
0x0 |
5 |
FIC4_LOCK |
Indicates that the FIC4 (Crypto) DLL has locked, cleared
by writing a '1' |
RW |
0 |
4 |
FIC3_LOCK |
Indicates that the FIC3 DLL has locked, cleared by writing
a '1' |
RW |
0 |
3 |
Reserved |
|
RO |
0 |
2 |
FIC2_LOCK |
Indicates that the FIC2 DLL has locked, cleared by writing
a '1' |
RW |
0 |
1 |
FIC1_LOCK |
Indicates that the FIC1 DLL has locked, cleared by writing
a '1' |
RW |
0 |
0 |
FIC0_LOCK |
Indicates that the FIC0 DLL has locked, cleared by writing
a '1' |
RW |
0 |
Address offset |
0x168 |
||
Physical address |
0x2000 2168 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Puts all the RAMS in that block into low leakage mode. RAM
contents and Q value preserved. |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:14 |
Reserved |
|
RO |
0x0 0000 |
13 |
l2 |
|
RW |
0 |
12 |
u54_4 |
|
RW |
0 |
11 |
u54_3 |
|
RW |
0 |
10 |
u54_2 |
|
RW |
0 |
9 |
u54_1 |
|
RW |
0 |
8 |
e51 |
|
RW |
0 |
7 |
ddrc |
|
RW |
0 |
6 |
athena |
|
RW |
0 |
5 |
mmc |
|
RW |
0 |
4 |
gem1 |
|
RW |
0 |
3 |
gem0 |
|
RW |
0 |
2 |
usb |
|
RW |
0 |
1 |
can1 |
|
RW |
0 |
0 |
can0 |
|
RW |
0 |
Address offset |
0x16C |
||
Physical address |
0x2000 216C |
Instance |
pfsoc_mss_top_sysreg |
Description |
Puts all the RAMS in that block into deep sleep mode. RAM
contents preserved. Powers down the periphery circuits. |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:14 |
Reserved |
|
RO |
0x0 0000 |
13 |
l2 |
|
RW |
0 |
12 |
u54_4 |
|
RW |
0 |
11 |
u54_3 |
|
RW |
0 |
10 |
u54_2 |
|
RW |
0 |
9 |
u54_1 |
|
RW |
0 |
8 |
e51 |
|
RW |
0 |
7 |
ddrc |
|
RW |
0 |
6 |
athena |
|
RW |
0 |
5 |
mmc |
|
RW |
0 |
4 |
gem1 |
|
RW |
0 |
3 |
gem0 |
|
RW |
0 |
2 |
usb |
|
RW |
0 |
1 |
can1 |
|
RW |
0 |
0 |
can0 |
|
RW |
0 |
Address offset |
0x170 |
||
Physical address |
0x2000 2170 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Puts all the RAMS in that block into shut down mode. RAM
contents not preserved. Powers down the RAM and periphery circuits. |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:14 |
Reserved |
|
RO |
0x0 0000 |
13 |
l2 |
|
RW |
0 |
12 |
u54_4 |
|
RW |
0 |
11 |
u54_3 |
|
RW |
0 |
10 |
u54_2 |
|
RW |
0 |
9 |
u54_1 |
|
RW |
0 |
8 |
e51 |
|
RW |
0 |
7 |
ddrc |
|
RW |
0 |
6 |
athena |
|
RW |
0 |
5 |
mmc |
|
RW |
0 |
4 |
gem1 |
|
RW |
0 |
3 |
gem0 |
|
RW |
0 |
2 |
usb |
|
RW |
0 |
1 |
can1 |
|
RW |
0 |
0 |
can0 |
|
RW |
0 |
Address offset |
0x174 |
||
Physical address |
0x2000 2174 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Allows each bank of the L2 Cache to be powered down, orded
with global shutdown |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
Reserved |
|
RO |
0x000 0000 |
3:0 |
L2_RAMS |
|
RW |
0x0 |
Address offset |
0x200 |
||
Physical address |
0x2000 2200 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Selects whether the peripheral is connected to the Fabric
or IOMUX structure. |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:14 |
Reserved |
|
RO |
0x0 0000 |
13 |
mdio1_fabric |
|
RW |
1 |
12 |
mdio0_fabric |
|
RW |
1 |
11 |
mmuart4_fabric |
|
RW |
1 |
10 |
mmuart3_fabric |
|
RW |
1 |
9 |
mmuart2_fabric |
|
RW |
1 |
8 |
mmuart1_fabric |
|
RW |
1 |
7 |
mmuart0_fabric |
|
RW |
1 |
6 |
qspi_fabric |
|
RW |
1 |
5 |
can1_fabric |
|
RW |
1 |
4 |
can0_fabric |
|
RW |
1 |
3 |
i2c1_fabric |
|
RW |
1 |
2 |
i2c0_fabric |
|
RW |
1 |
1 |
spi1_fabric |
|
RW |
1 |
0 |
spi0_fabric |
|
RW |
1 |
Address offset |
0x204 |
||
Physical address |
0x2000 2204 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Configures the IO Mux structure for each IO pad. See the
MSS MAS specification for for description. |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:28 |
pad7 |
|
RW |
0xF |
27:24 |
pad6 |
|
RW |
0xF |
23:20 |
pad5 |
|
RW |
0xF |
19:16 |
pad4 |
|
RW |
0xF |
15:12 |
pad3 |
|
RW |
0xF |
11:8 |
pad2 |
|
RW |
0xF |
7:4 |
pad1 |
|
RW |
0xF |
3:0 |
pad0 |
|
RW |
0xF |
Address offset |
0x208 |
||
Physical address |
0x2000 2208 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Configures the IO Mux structure for each IO pad. See the
MSS MAS specification for for description. |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23:20 |
pad13 |
|
RW |
0xF |
19:16 |
pad12 |
|
RW |
0xF |
15:12 |
pad11 |
|
RW |
0xF |
11:8 |
pad10 |
|
RW |
0xF |
7:4 |
pad9 |
|
RW |
0xF |
3:0 |
pad8 |
|
RW |
0xF |
Address offset |
0x20C |
||
Physical address |
0x2000 220C |
Instance |
pfsoc_mss_top_sysreg |
Description |
Configures the IO Mux structure for each IO pad. See the
MSS MAS specification for for description. |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:28 |
pad21 |
|
RW |
0xF |
27:24 |
pad20 |
|
RW |
0xF |
23:20 |
pad19 |
|
RW |
0xF |
19:16 |
pad18 |
|
RW |
0xF |
15:12 |
pad17 |
|
RW |
0xF |
11:8 |
pad16 |
|
RW |
0xF |
7:4 |
pad15 |
|
RW |
0xF |
3:0 |
pad14 |
|
RW |
0xF |
Address offset |
0x210 |
||
Physical address |
0x2000 2210 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Configures the IO Mux structure for each IO pad. See the
MSS MAS specification for for description. |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:28 |
pad29 |
|
RW |
0xF |
27:24 |
pad28 |
|
RW |
0xF |
23:20 |
pad27 |
|
RW |
0xF |
19:16 |
pad26 |
|
RW |
0xF |
15:12 |
pad25 |
|
RW |
0xF |
11:8 |
pad24 |
|
RW |
0xF |
7:4 |
pad23 |
|
RW |
0xF |
3:0 |
pad22 |
|
RW |
0xF |
Address offset |
0x214 |
||
Physical address |
0x2000 2214 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Configures the IO Mux structure for each IO pad. See the
MSS MAS specification for for description. |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:28 |
pad37 |
|
RW |
0xF |
27:24 |
pad36 |
|
RW |
0xF |
23:20 |
pad35 |
|
RW |
0xF |
19:16 |
pad34 |
|
RW |
0xF |
15:12 |
pad33 |
|
RW |
0xF |
11:8 |
pad32 |
|
RW |
0xF |
7:4 |
pad31 |
|
RW |
0xF |
3:0 |
pad30 |
|
RW |
0xF |
Address offset |
0x218 |
||
Physical address |
0x2000 2218 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Sets whether the MMC/SD Voltage select lines are inverted
on entry to the IOMUX structure |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:9 |
Reserved |
|
RO |
0x00 0000 |
8 |
SD_VOLT_2 |
|
RW |
0 |
7 |
SD_VOLT_1 |
|
RW |
0 |
6 |
SD_VOLT_0 |
|
RW |
0 |
5 |
SD_LED |
|
RW |
0 |
4 |
VLT_DIR_1_3 |
|
RW |
0 |
3 |
VLT_DIR_0 |
|
RW |
0 |
2 |
VLT_CMD_DIR |
|
RW |
0 |
1 |
VLT_EN |
|
RW |
0 |
0 |
VLT_SEL |
|
RW |
0 |
Address offset |
0x234 |
||
Physical address |
0x2000 2234 |
Instance |
pfsoc_mss_top_sysreg |
Description |
IO electrical configuration for MSSIO pad |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31 |
Reserved |
|
RO |
0 |
30 |
rpc_io_cfg_1_lp_bypass_en |
|
RW |
0 |
29 |
rpc_io_cfg_1_lp_persist_en |
|
RW |
0 |
28 |
rpc_io_cfg_1_atp_en |
|
RW |
0 |
27 |
rpc_io_cfg_1_wpu |
|
RW |
1 |
26 |
rpc_io_cfg_1_wpd |
|
RW |
0 |
25 |
rpc_io_cfg_1_lockdn_en |
|
RO |
0 |
24 |
rpc_io_cfg_1_enhyst |
|
RW |
0 |
23 |
rpc_io_cfg_1_clamp |
|
RW |
0 |
22 |
rpc_io_cfg_1_drv_3 |
|
RW |
0 |
21 |
rpc_io_cfg_1_drv_2 |
|
RW |
1 |
20 |
rpc_io_cfg_1_drv_1 |
|
RW |
0 |
19 |
rpc_io_cfg_1_drv_0 |
|
RW |
1 |
18 |
rpc_io_cfg_1_ibufmd_2 |
|
RW |
0 |
17 |
rpc_io_cfg_1_ibufmd_1 |
|
RW |
0 |
16 |
rpc_io_cfg_1_ibufmd_0 |
|
RW |
0 |
15 |
Reserved |
|
RO |
0 |
14 |
rpc_io_cfg_0_lp_bypass_en |
|
RW |
0 |
13 |
rpc_io_cfg_0_lp_persist_en |
|
RW |
0 |
12 |
rpc_io_cfg_0_atp_en |
|
RW |
0 |
11 |
rpc_io_cfg_0_wpu |
|
RW |
1 |
10 |
rpc_io_cfg_0_wpd |
|
RW |
0 |
9 |
rpc_io_cfg_0_lockdn_en |
|
RO |
0 |
8 |
rpc_io_cfg_0_enhyst |
|
RW |
0 |
7 |
rpc_io_cfg_0_clamp |
|
RW |
0 |
6 |
rpc_io_cfg_0_drv_3 |
|
RW |
0 |
5 |
rpc_io_cfg_0_drv_2 |
|
RW |
1 |
4 |
rpc_io_cfg_0_drv_1 |
|
RW |
0 |
3 |
rpc_io_cfg_0_drv_0 |
|
RW |
1 |
2 |
rpc_io_cfg_0_ibufmd_2 |
|
RW |
0 |
1 |
rpc_io_cfg_0_ibufmd_1 |
|
RW |
0 |
0 |
rpc_io_cfg_0_ibufmd_0 |
|
RW |
0 |
Address offset |
0x238 |
||
Physical address |
0x2000 2238 |
Instance |
pfsoc_mss_top_sysreg |
Description |
IO electrical configuration for MSSIO pad |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31 |
Reserved |
|
RO |
0 |
30 |
rpc_io_cfg_3_lp_bypass_en |
|
RW |
0 |
29 |
rpc_io_cfg_3_lp_persist_en |
|
RW |
0 |
28 |
rpc_io_cfg_3_atp_en |
|
RW |
0 |
27 |
rpc_io_cfg_3_wpu |
|
RW |
1 |
26 |
rpc_io_cfg_3_wpd |
|
RW |
0 |
25 |
rpc_io_cfg_3_lockdn_en |
|
RO |
0 |
24 |
rpc_io_cfg_3_enhyst |
|
RW |
0 |
23 |
rpc_io_cfg_3_clamp |
|
RW |
0 |
22 |
rpc_io_cfg_3_drv_3 |
|
RW |
0 |
21 |
rpc_io_cfg_3_drv_2 |
|
RW |
1 |
20 |
rpc_io_cfg_3_drv_1 |
|
RW |
0 |
19 |
rpc_io_cfg_3_drv_0 |
|
RW |
1 |
18 |
rpc_io_cfg_3_ibufmd_2 |
|
RW |
0 |
17 |
rpc_io_cfg_3_ibufmd_1 |
|
RW |
0 |
16 |
rpc_io_cfg_3_ibufmd_0 |
|
RW |
0 |
15 |
Reserved |
|
RO |
0 |
14 |
rpc_io_cfg_2_lp_bypass_en |
|
RW |
0 |
13 |
rpc_io_cfg_2_lp_persist_en |
|
RW |
0 |
12 |
rpc_io_cfg_2_atp_en |
|
RW |
0 |
11 |
rpc_io_cfg_2_wpu |
|
RW |
1 |
10 |
rpc_io_cfg_2_wpd |
|
RW |
0 |
9 |
rpc_io_cfg_2_lockdn_en |
|
RO |
0 |
8 |
rpc_io_cfg_2_enhyst |
|
RW |
0 |
7 |
rpc_io_cfg_2_clamp |
|
RW |
0 |
6 |
rpc_io_cfg_2_drv_3 |
|
RW |
0 |
5 |
rpc_io_cfg_2_drv_2 |
|
RW |
1 |
4 |
rpc_io_cfg_2_drv_1 |
|
RW |
0 |
3 |
rpc_io_cfg_2_drv_0 |
|
RW |
1 |
2 |
rpc_io_cfg_2_ibufmd_2 |
|
RW |
0 |
1 |
rpc_io_cfg_2_ibufmd_1 |
|
RW |
0 |
0 |
rpc_io_cfg_2_ibufmd_0 |
|
RW |
0 |
Address offset |
0x23C |
||
Physical address |
0x2000 223C |
Instance |
pfsoc_mss_top_sysreg |
Description |
IO electrical configuration for MSSIO pad |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31 |
Reserved |
|
RO |
0 |
30 |
rpc_io_cfg_5_lp_bypass_en |
|
RW |
0 |
29 |
rpc_io_cfg_5_lp_persist_en |
|
RW |
0 |
28 |
rpc_io_cfg_5_atp_en |
|
RW |
0 |
27 |
rpc_io_cfg_5_wpu |
|
RW |
1 |
26 |
rpc_io_cfg_5_wpd |
|
RW |
0 |
25 |
rpc_io_cfg_5_lockdn_en |
|
RO |
0 |
24 |
rpc_io_cfg_5_enhyst |
|
RW |
0 |
23 |
rpc_io_cfg_5_clamp |
|
RW |
0 |
22 |
rpc_io_cfg_5_drv_3 |
|
RW |
0 |
21 |
rpc_io_cfg_5_drv_2 |
|
RW |
1 |
20 |
rpc_io_cfg_5_drv_1 |
|
RW |
0 |
19 |
rpc_io_cfg_5_drv_0 |
|
RW |
1 |
18 |
rpc_io_cfg_5_ibufmd_2 |
|
RW |
0 |
17 |
rpc_io_cfg_5_ibufmd_1 |
|
RW |
0 |
16 |
rpc_io_cfg_5_ibufmd_0 |
|
RW |
0 |
15 |
Reserved |
|
RO |
0 |
14 |
rpc_io_cfg_4_lp_bypass_en |
|
RW |
0 |
13 |
rpc_io_cfg_4_lp_persist_en |
|
RW |
0 |
12 |
rpc_io_cfg_4_atp_en |
|
RW |
0 |
11 |
rpc_io_cfg_4_wpu |
|
RW |
1 |
10 |
rpc_io_cfg_4_wpd |
|
RW |
0 |
9 |
rpc_io_cfg_4_lockdn_en |
|
RO |
0 |
8 |
rpc_io_cfg_4_enhyst |
|
RW |
0 |
7 |
rpc_io_cfg_4_clamp |
|
RW |
0 |
6 |
rpc_io_cfg_4_drv_3 |
|
RW |
0 |
5 |
rpc_io_cfg_4_drv_2 |
|
RW |
1 |
4 |
rpc_io_cfg_4_drv_1 |
|
RW |
0 |
3 |
rpc_io_cfg_4_drv_0 |
|
RW |
1 |
2 |
rpc_io_cfg_4_ibufmd_2 |
|
RW |
0 |
1 |
rpc_io_cfg_4_ibufmd_1 |
|
RW |
0 |
0 |
rpc_io_cfg_4_ibufmd_0 |
|
RW |
0 |
Address offset |
0x240 |
||
Physical address |
0x2000 2240 |
Instance |
pfsoc_mss_top_sysreg |
Description |
IO electrical configuration for MSSIO pad |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31 |
Reserved |
|
RO |
0 |
30 |
rpc_io_cfg_7_lp_bypass_en |
|
RW |
0 |
29 |
rpc_io_cfg_7_lp_persist_en |
|
RW |
0 |
28 |
rpc_io_cfg_7_atp_en |
|
RW |
0 |
27 |
rpc_io_cfg_7_wpu |
|
RW |
1 |
26 |
rpc_io_cfg_7_wpd |
|
RW |
0 |
25 |
rpc_io_cfg_7_lockdn_en |
|
RO |
0 |
24 |
rpc_io_cfg_7_enhyst |
|
RW |
0 |
23 |
rpc_io_cfg_7_clamp |
|
RW |
0 |
22 |
rpc_io_cfg_7_drv_3 |
|
RW |
0 |
21 |
rpc_io_cfg_7_drv_2 |
|
RW |
1 |
20 |
rpc_io_cfg_7_drv_1 |
|
RW |
0 |
19 |
rpc_io_cfg_7_drv_0 |
|
RW |
1 |
18 |
rpc_io_cfg_7_ibufmd_2 |
|
RW |
0 |
17 |
rpc_io_cfg_7_ibufmd_1 |
|
RW |
0 |
16 |
rpc_io_cfg_7_ibufmd_0 |
|
RW |
0 |
15 |
Reserved |
|
RO |
0 |
14 |
rpc_io_cfg_6_lp_bypass_en |
|
RW |
0 |
13 |
rpc_io_cfg_6_lp_persist_en |
|
RW |
0 |
12 |
rpc_io_cfg_6_atp_en |
|
RW |
0 |
11 |
rpc_io_cfg_6_wpu |
|
RW |
1 |
10 |
rpc_io_cfg_6_wpd |
|
RW |
0 |
9 |
rpc_io_cfg_6_lockdn_en |
|
RO |
0 |
8 |
rpc_io_cfg_6_enhyst |
|
RW |
0 |
7 |
rpc_io_cfg_6_clamp |
|
RW |
0 |
6 |
rpc_io_cfg_6_drv_3 |
|
RW |
0 |
5 |
rpc_io_cfg_6_drv_2 |
|
RW |
1 |
4 |
rpc_io_cfg_6_drv_1 |
|
RW |
0 |
3 |
rpc_io_cfg_6_drv_0 |
|
RW |
1 |
2 |
rpc_io_cfg_6_ibufmd_2 |
|
RW |
0 |
1 |
rpc_io_cfg_6_ibufmd_1 |
|
RW |
0 |
0 |
rpc_io_cfg_6_ibufmd_0 |
|
RW |
0 |
Address offset |
0x244 |
||
Physical address |
0x2000 2244 |
Instance |
pfsoc_mss_top_sysreg |
Description |
IO electrical configuration for MSSIO pad |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31 |
Reserved |
|
RO |
0 |
30 |
rpc_io_cfg_9_lp_bypass_en |
|
RW |
0 |
29 |
rpc_io_cfg_9_lp_persist_en |
|
RW |
0 |
28 |
rpc_io_cfg_9_atp_en |
|
RW |
0 |
27 |
rpc_io_cfg_9_wpu |
|
RW |
1 |
26 |
rpc_io_cfg_9_wpd |
|
RW |
0 |
25 |
rpc_io_cfg_9_lockdn_en |
|
RO |
0 |
24 |
rpc_io_cfg_9_enhyst |
|
RW |
0 |
23 |
rpc_io_cfg_9_clamp |
|
RW |
0 |
22 |
rpc_io_cfg_9_drv_3 |
|
RW |
0 |
21 |
rpc_io_cfg_9_drv_2 |
|
RW |
1 |
20 |
rpc_io_cfg_9_drv_1 |
|
RW |
0 |
19 |
rpc_io_cfg_9_drv_0 |
|
RW |
1 |
18 |
rpc_io_cfg_9_ibufmd_2 |
|
RW |
0 |
17 |
rpc_io_cfg_9_ibufmd_1 |
|
RW |
0 |
16 |
rpc_io_cfg_9_ibufmd_0 |
|
RW |
0 |
15 |
Reserved |
|
RO |
0 |
14 |
rpc_io_cfg_8_lp_bypass_en |
|
RW |
0 |
13 |
rpc_io_cfg_8_lp_persist_en |
|
RW |
0 |
12 |
rpc_io_cfg_8_atp_en |
|
RW |
0 |
11 |
rpc_io_cfg_8_wpu |
|
RW |
1 |
10 |
rpc_io_cfg_8_wpd |
|
RW |
0 |
9 |
rpc_io_cfg_8_lockdn_en |
|
RO |
0 |
8 |
rpc_io_cfg_8_enhyst |
|
RW |
0 |
7 |
rpc_io_cfg_8_clamp |
|
RW |
0 |
6 |
rpc_io_cfg_8_drv_3 |
|
RW |
0 |
5 |
rpc_io_cfg_8_drv_2 |
|
RW |
1 |
4 |
rpc_io_cfg_8_drv_1 |
|
RW |
0 |
3 |
rpc_io_cfg_8_drv_0 |
|
RW |
1 |
2 |
rpc_io_cfg_8_ibufmd_2 |
|
RW |
0 |
1 |
rpc_io_cfg_8_ibufmd_1 |
|
RW |
0 |
0 |
rpc_io_cfg_8_ibufmd_0 |
|
RW |
0 |
Address offset |
0x248 |
||
Physical address |
0x2000 2248 |
Instance |
pfsoc_mss_top_sysreg |
Description |
IO electrical configuration for MSSIO pad |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31 |
Reserved |
|
RO |
0 |
30 |
rpc_io_cfg_11_lp_bypass_en |
|
RW |
0 |
29 |
rpc_io_cfg_11_lp_persist_en |
|
RW |
0 |
28 |
rpc_io_cfg_11_atp_en |
|
RW |
0 |
27 |
rpc_io_cfg_11_wpu |
|
RW |
1 |
26 |
rpc_io_cfg_11_wpd |
|
RW |
0 |
25 |
rpc_io_cfg_11_lockdn_en |
|
RO |
0 |
24 |
rpc_io_cfg_11_enhyst |
|
RW |
0 |
23 |
rpc_io_cfg_11_clamp |
|
RW |
0 |
22 |
rpc_io_cfg_11_drv_3 |
|
RW |
0 |
21 |
rpc_io_cfg_11_drv_2 |
|
RW |
1 |
20 |
rpc_io_cfg_11_drv_1 |
|
RW |
0 |
19 |
rpc_io_cfg_11_drv_0 |
|
RW |
1 |
18 |
rpc_io_cfg_11_ibufmd_2 |
|
RW |
0 |
17 |
rpc_io_cfg_11_ibufmd_1 |
|
RW |
0 |
16 |
rpc_io_cfg_11_ibufmd_0 |
|
RW |
0 |
15 |
Reserved |
|
RO |
0 |
14 |
rpc_io_cfg_10_lp_bypass_en |
|
RW |
0 |
13 |
rpc_io_cfg_10_lp_persist_en |
|
RW |
0 |
12 |
rpc_io_cfg_10_atp_en |
|
RW |
0 |
11 |
rpc_io_cfg_10_wpu |
|
RW |
1 |
10 |
rpc_io_cfg_10_wpd |
|
RW |
0 |
9 |
rpc_io_cfg_10_lockdn_en |
|
RO |
0 |
8 |
rpc_io_cfg_10_enhyst |
|
RW |
0 |
7 |
rpc_io_cfg_10_clamp |
|
RW |
0 |
6 |
rpc_io_cfg_10_drv_3 |
|
RW |
0 |
5 |
rpc_io_cfg_10_drv_2 |
|
RW |
1 |
4 |
rpc_io_cfg_10_drv_1 |
|
RW |
0 |
3 |
rpc_io_cfg_10_drv_0 |
|
RW |
1 |
2 |
rpc_io_cfg_10_ibufmd_2 |
|
RW |
0 |
1 |
rpc_io_cfg_10_ibufmd_1 |
|
RW |
0 |
0 |
rpc_io_cfg_10_ibufmd_0 |
|
RW |
0 |
Address offset |
0x24C |
||
Physical address |
0x2000 224C |
Instance |
pfsoc_mss_top_sysreg |
Description |
IO electrical configuration for MSSIO pad |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31 |
Reserved |
|
RO |
0 |
30 |
rpc_io_cfg_13_lp_bypass_en |
|
RW |
0 |
29 |
rpc_io_cfg_13_lp_persist_en |
|
RW |
0 |
28 |
rpc_io_cfg_13_atp_en |
|
RW |
0 |
27 |
rpc_io_cfg_13_wpu |
|
RW |
1 |
26 |
rpc_io_cfg_13_wpd |
|
RW |
0 |
25 |
rpc_io_cfg_13_lockdn_en |
|
RO |
0 |
24 |
rpc_io_cfg_13_enhyst |
|
RW |
0 |
23 |
rpc_io_cfg_13_clamp |
|
RW |
0 |
22 |
rpc_io_cfg_13_drv_3 |
|
RW |
0 |
21 |
rpc_io_cfg_13_drv_2 |
|
RW |
1 |
20 |
rpc_io_cfg_13_drv_1 |
|
RW |
0 |
19 |
rpc_io_cfg_13_drv_0 |
|
RW |
1 |
18 |
rpc_io_cfg_13_ibufmd_2 |
|
RW |
0 |
17 |
rpc_io_cfg_13_ibufmd_1 |
|
RW |
0 |
16 |
rpc_io_cfg_13_ibufmd_0 |
|
RW |
0 |
15 |
Reserved |
|
RO |
0 |
14 |
rpc_io_cfg_12_lp_bypass_en |
|
RW |
0 |
13 |
rpc_io_cfg_12_lp_persist_en |
|
RW |
0 |
12 |
rpc_io_cfg_12_atp_en |
|
RW |
0 |
11 |
rpc_io_cfg_12_wpu |
|
RW |
1 |
10 |
rpc_io_cfg_12_wpd |
|
RW |
0 |
9 |
rpc_io_cfg_12_lockdn_en |
|
RO |
0 |
8 |
rpc_io_cfg_12_enhyst |
|
RW |
0 |
7 |
rpc_io_cfg_12_clamp |
|
RW |
0 |
6 |
rpc_io_cfg_12_drv_3 |
|
RW |
0 |
5 |
rpc_io_cfg_12_drv_2 |
|
RW |
1 |
4 |
rpc_io_cfg_12_drv_1 |
|
RW |
0 |
3 |
rpc_io_cfg_12_drv_0 |
|
RW |
1 |
2 |
rpc_io_cfg_12_ibufmd_2 |
|
RW |
0 |
1 |
rpc_io_cfg_12_ibufmd_1 |
|
RW |
0 |
0 |
rpc_io_cfg_12_ibufmd_0 |
|
RW |
0 |
Address offset |
0x254 |
||
Physical address |
0x2000 2254 |
Instance |
pfsoc_mss_top_sysreg |
Description |
IO electrical configuration for MSSIO pad |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31 |
Reserved |
|
RO |
0 |
30 |
rpc_io_cfg_1_lp_bypass_en |
|
RW |
0 |
29 |
rpc_io_cfg_1_lp_persist_en |
|
RW |
0 |
28 |
rpc_io_cfg_1_atp_en |
|
RW |
0 |
27 |
rpc_io_cfg_1_wpu |
|
RW |
1 |
26 |
rpc_io_cfg_1_wpd |
|
RW |
0 |
25 |
rpc_io_cfg_1_lockdn_en |
|
RO |
0 |
24 |
rpc_io_cfg_1_enhyst |
|
RW |
0 |
23 |
rpc_io_cfg_1_clamp |
|
RW |
0 |
22 |
rpc_io_cfg_1_drv_3 |
|
RW |
0 |
21 |
rpc_io_cfg_1_drv_2 |
|
RW |
1 |
20 |
rpc_io_cfg_1_drv_1 |
|
RW |
0 |
19 |
rpc_io_cfg_1_drv_0 |
|
RW |
1 |
18 |
rpc_io_cfg_1_ibufmd_2 |
|
RW |
0 |
17 |
rpc_io_cfg_1_ibufmd_1 |
|
RW |
0 |
16 |
rpc_io_cfg_1_ibufmd_0 |
|
RW |
0 |
15 |
Reserved |
|
RO |
0 |
14 |
rpc_io_cfg_0_lp_bypass_en |
|
RW |
0 |
13 |
rpc_io_cfg_0_lp_persist_en |
|
RW |
0 |
12 |
rpc_io_cfg_0_atp_en |
|
RW |
0 |
11 |
rpc_io_cfg_0_wpu |
|
RW |
1 |
10 |
rpc_io_cfg_0_wpd |
|
RW |
0 |
9 |
rpc_io_cfg_0_lockdn_en |
|
RO |
0 |
8 |
rpc_io_cfg_0_enhyst |
|
RW |
0 |
7 |
rpc_io_cfg_0_clamp |
|
RW |
0 |
6 |
rpc_io_cfg_0_drv_3 |
|
RW |
0 |
5 |
rpc_io_cfg_0_drv_2 |
|
RW |
1 |
4 |
rpc_io_cfg_0_drv_1 |
|
RW |
0 |
3 |
rpc_io_cfg_0_drv_0 |
|
RW |
1 |
2 |
rpc_io_cfg_0_ibufmd_2 |
|
RW |
0 |
1 |
rpc_io_cfg_0_ibufmd_1 |
|
RW |
0 |
0 |
rpc_io_cfg_0_ibufmd_0 |
|
RW |
0 |
Address offset |
0x258 |
||
Physical address |
0x2000 2258 |
Instance |
pfsoc_mss_top_sysreg |
Description |
IO electrical configuration for MSSIO pad |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31 |
Reserved |
|
RO |
0 |
30 |
rpc_io_cfg_3_lp_bypass_en |
|
RW |
0 |
29 |
rpc_io_cfg_3_lp_persist_en |
|
RW |
0 |
28 |
rpc_io_cfg_3_atp_en |
|
RW |
0 |
27 |
rpc_io_cfg_3_wpu |
|
RW |
1 |
26 |
rpc_io_cfg_3_wpd |
|
RW |
0 |
25 |
rpc_io_cfg_3_lockdn_en |
|
RO |
0 |
24 |
rpc_io_cfg_3_enhyst |
|
RW |
0 |
23 |
rpc_io_cfg_3_clamp |
|
RW |
0 |
22 |
rpc_io_cfg_3_drv_3 |
|
RW |
0 |
21 |
rpc_io_cfg_3_drv_2 |
|
RW |
1 |
20 |
rpc_io_cfg_3_drv_1 |
|
RW |
0 |
19 |
rpc_io_cfg_3_drv_0 |
|
RW |
1 |
18 |
rpc_io_cfg_3_ibufmd_2 |
|
RW |
0 |
17 |
rpc_io_cfg_3_ibufmd_1 |
|
RW |
0 |
16 |
rpc_io_cfg_3_ibufmd_0 |
|
RW |
0 |
15 |
Reserved |
|
RO |
0 |
14 |
rpc_io_cfg_2_lp_bypass_en |
|
RW |
0 |
13 |
rpc_io_cfg_2_lp_persist_en |
|
RW |
0 |
12 |
rpc_io_cfg_2_atp_en |
|
RW |
0 |
11 |
rpc_io_cfg_2_wpu |
|
RW |
1 |
10 |
rpc_io_cfg_2_wpd |
|
RW |
0 |
9 |
rpc_io_cfg_2_lockdn_en |
|
RO |
0 |
8 |
rpc_io_cfg_2_enhyst |
|
RW |
0 |
7 |
rpc_io_cfg_2_clamp |
|
RW |
0 |
6 |
rpc_io_cfg_2_drv_3 |
|
RW |
0 |
5 |
rpc_io_cfg_2_drv_2 |
|
RW |
1 |
4 |
rpc_io_cfg_2_drv_1 |
|
RW |
0 |
3 |
rpc_io_cfg_2_drv_0 |
|
RW |
1 |
2 |
rpc_io_cfg_2_ibufmd_2 |
|
RW |
0 |
1 |
rpc_io_cfg_2_ibufmd_1 |
|
RW |
0 |
0 |
rpc_io_cfg_2_ibufmd_0 |
|
RW |
0 |
Address offset |
0x25C |
||
Physical address |
0x2000 225C |
Instance |
pfsoc_mss_top_sysreg |
Description |
IO electrical configuration for MSSIO pad |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31 |
Reserved |
|
RO |
0 |
30 |
rpc_io_cfg_5_lp_bypass_en |
|
RW |
0 |
29 |
rpc_io_cfg_5_lp_persist_en |
|
RW |
0 |
28 |
rpc_io_cfg_5_atp_en |
|
RW |
0 |
27 |
rpc_io_cfg_5_wpu |
|
RW |
1 |
26 |
rpc_io_cfg_5_wpd |
|
RW |
0 |
25 |
rpc_io_cfg_5_lockdn_en |
|
RO |
0 |
24 |
rpc_io_cfg_5_enhyst |
|
RW |
0 |
23 |
rpc_io_cfg_5_clamp |
|
RW |
0 |
22 |
rpc_io_cfg_5_drv_3 |
|
RW |
0 |
21 |
rpc_io_cfg_5_drv_2 |
|
RW |
1 |
20 |
rpc_io_cfg_5_drv_1 |
|
RW |
0 |
19 |
rpc_io_cfg_5_drv_0 |
|
RW |
1 |
18 |
rpc_io_cfg_5_ibufmd_2 |
|
RW |
0 |
17 |
rpc_io_cfg_5_ibufmd_1 |
|
RW |
0 |
16 |
rpc_io_cfg_5_ibufmd_0 |
|
RW |
0 |
15 |
Reserved |
|
RO |
0 |
14 |
rpc_io_cfg_4_lp_bypass_en |
|
RW |
0 |
13 |
rpc_io_cfg_4_lp_persist_en |
|
RW |
0 |
12 |
rpc_io_cfg_4_atp_en |
|
RW |
0 |
11 |
rpc_io_cfg_4_wpu |
|
RW |
1 |
10 |
rpc_io_cfg_4_wpd |
|
RW |
0 |
9 |
rpc_io_cfg_4_lockdn_en |
|
RO |
0 |
8 |
rpc_io_cfg_4_enhyst |
|
RW |
0 |
7 |
rpc_io_cfg_4_clamp |
|
RW |
0 |
6 |
rpc_io_cfg_4_drv_3 |
|
RW |
0 |
5 |
rpc_io_cfg_4_drv_2 |
|
RW |
1 |
4 |
rpc_io_cfg_4_drv_1 |
|
RW |
0 |
3 |
rpc_io_cfg_4_drv_0 |
|
RW |
1 |
2 |
rpc_io_cfg_4_ibufmd_2 |
|
RW |
0 |
1 |
rpc_io_cfg_4_ibufmd_1 |
|
RW |
0 |
0 |
rpc_io_cfg_4_ibufmd_0 |
|
RW |
0 |
Address offset |
0x260 |
||
Physical address |
0x2000 2260 |
Instance |
pfsoc_mss_top_sysreg |
Description |
IO electrical configuration for MSSIO pad |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31 |
Reserved |
|
RO |
0 |
30 |
rpc_io_cfg_7_lp_bypass_en |
|
RW |
0 |
29 |
rpc_io_cfg_7_lp_persist_en |
|
RW |
0 |
28 |
rpc_io_cfg_7_atp_en |
|
RW |
0 |
27 |
rpc_io_cfg_7_wpu |
|
RW |
1 |
26 |
rpc_io_cfg_7_wpd |
|
RW |
0 |
25 |
rpc_io_cfg_7_lockdn_en |
|
RO |
0 |
24 |
rpc_io_cfg_7_enhyst |
|
RW |
0 |
23 |
rpc_io_cfg_7_clamp |
|
RW |
0 |
22 |
rpc_io_cfg_7_drv_3 |
|
RW |
0 |
21 |
rpc_io_cfg_7_drv_2 |
|
RW |
1 |
20 |
rpc_io_cfg_7_drv_1 |
|
RW |
0 |
19 |
rpc_io_cfg_7_drv_0 |
|
RW |
1 |
18 |
rpc_io_cfg_7_ibufmd_2 |
|
RW |
0 |
17 |
rpc_io_cfg_7_ibufmd_1 |
|
RW |
0 |
16 |
rpc_io_cfg_7_ibufmd_0 |
|
RW |
0 |
15 |
Reserved |
|
RO |
0 |
14 |
rpc_io_cfg_6_lp_bypass_en |
|
RW |
0 |
13 |
rpc_io_cfg_6_lp_persist_en |
|
RW |
0 |
12 |
rpc_io_cfg_6_atp_en |
|
RW |
0 |
11 |
rpc_io_cfg_6_wpu |
|
RW |
1 |
10 |
rpc_io_cfg_6_wpd |
|
RW |
0 |
9 |
rpc_io_cfg_6_lockdn_en |
|
RO |
0 |
8 |
rpc_io_cfg_6_enhyst |
|
RW |
0 |
7 |
rpc_io_cfg_6_clamp |
|
RW |
0 |
6 |
rpc_io_cfg_6_drv_3 |
|
RW |
0 |
5 |
rpc_io_cfg_6_drv_2 |
|
RW |
1 |
4 |
rpc_io_cfg_6_drv_1 |
|
RW |
0 |
3 |
rpc_io_cfg_6_drv_0 |
|
RW |
1 |
2 |
rpc_io_cfg_6_ibufmd_2 |
|
RW |
0 |
1 |
rpc_io_cfg_6_ibufmd_1 |
|
RW |
0 |
0 |
rpc_io_cfg_6_ibufmd_0 |
|
RW |
0 |
Address offset |
0x264 |
||
Physical address |
0x2000 2264 |
Instance |
pfsoc_mss_top_sysreg |
Description |
IO electrical configuration for MSSIO pad |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31 |
Reserved |
|
RO |
0 |
30 |
rpc_io_cfg_9_lp_bypass_en |
|
RW |
0 |
29 |
rpc_io_cfg_9_lp_persist_en |
|
RW |
0 |
28 |
rpc_io_cfg_9_atp_en |
|
RW |
0 |
27 |
rpc_io_cfg_9_wpu |
|
RW |
1 |
26 |
rpc_io_cfg_9_wpd |
|
RW |
0 |
25 |
rpc_io_cfg_9_lockdn_en |
|
RO |
0 |
24 |
rpc_io_cfg_9_enhyst |
|
RW |
0 |
23 |
rpc_io_cfg_9_clamp |
|
RW |
0 |
22 |
rpc_io_cfg_9_drv_3 |
|
RW |
0 |
21 |
rpc_io_cfg_9_drv_2 |
|
RW |
1 |
20 |
rpc_io_cfg_9_drv_1 |
|
RW |
0 |
19 |
rpc_io_cfg_9_drv_0 |
|
RW |
1 |
18 |
rpc_io_cfg_9_ibufmd_2 |
|
RW |
0 |
17 |
rpc_io_cfg_9_ibufmd_1 |
|
RW |
0 |
16 |
rpc_io_cfg_9_ibufmd_0 |
|
RW |
0 |
15 |
Reserved |
|
RO |
0 |
14 |
rpc_io_cfg_8_lp_bypass_en |
|
RW |
0 |
13 |
rpc_io_cfg_8_lp_persist_en |
|
RW |
0 |
12 |
rpc_io_cfg_8_atp_en |
|
RW |
0 |
11 |
rpc_io_cfg_8_wpu |
|
RW |
1 |
10 |
rpc_io_cfg_8_wpd |
|
RW |
0 |
9 |
rpc_io_cfg_8_lockdn_en |
|
RO |
0 |
8 |
rpc_io_cfg_8_enhyst |
|
RW |
0 |
7 |
rpc_io_cfg_8_clamp |
|
RW |
0 |
6 |
rpc_io_cfg_8_drv_3 |
|
RW |
0 |
5 |
rpc_io_cfg_8_drv_2 |
|
RW |
1 |
4 |
rpc_io_cfg_8_drv_1 |
|
RW |
0 |
3 |
rpc_io_cfg_8_drv_0 |
|
RW |
1 |
2 |
rpc_io_cfg_8_ibufmd_2 |
|
RW |
0 |
1 |
rpc_io_cfg_8_ibufmd_1 |
|
RW |
0 |
0 |
rpc_io_cfg_8_ibufmd_0 |
|
RW |
0 |
Address offset |
0x268 |
||
Physical address |
0x2000 2268 |
Instance |
pfsoc_mss_top_sysreg |
Description |
IO electrical configuration for MSSIO pad |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31 |
Reserved |
|
RO |
0 |
30 |
rpc_io_cfg_11_lp_bypass_en |
|
RW |
0 |
29 |
rpc_io_cfg_11_lp_persist_en |
|
RW |
0 |
28 |
rpc_io_cfg_11_atp_en |
|
RW |
0 |
27 |
rpc_io_cfg_11_wpu |
|
RW |
1 |
26 |
rpc_io_cfg_11_wpd |
|
RW |
0 |
25 |
rpc_io_cfg_11_lockdn_en |
|
RO |
0 |
24 |
rpc_io_cfg_11_enhyst |
|
RW |
0 |
23 |
rpc_io_cfg_11_clamp |
|
RW |
0 |
22 |
rpc_io_cfg_11_drv_3 |
|
RW |
0 |
21 |
rpc_io_cfg_11_drv_2 |
|
RW |
1 |
20 |
rpc_io_cfg_11_drv_1 |
|
RW |
0 |
19 |
rpc_io_cfg_11_drv_0 |
|
RW |
1 |
18 |
rpc_io_cfg_11_ibufmd_2 |
|
RW |
0 |
17 |
rpc_io_cfg_11_ibufmd_1 |
|
RW |
0 |
16 |
rpc_io_cfg_11_ibufmd_0 |
|
RW |
0 |
15 |
Reserved |
|
RO |
0 |
14 |
rpc_io_cfg_10_lp_bypass_en |
|
RW |
0 |
13 |
rpc_io_cfg_10_lp_persist_en |
|
RW |
0 |
12 |
rpc_io_cfg_10_atp_en |
|
RW |
0 |
11 |
rpc_io_cfg_10_wpu |
|
RW |
1 |
10 |
rpc_io_cfg_10_wpd |
|
RW |
0 |
9 |
rpc_io_cfg_10_lockdn_en |
|
RO |
0 |
8 |
rpc_io_cfg_10_enhyst |
|
RW |
0 |
7 |
rpc_io_cfg_10_clamp |
|
RW |
0 |
6 |
rpc_io_cfg_10_drv_3 |
|
RW |
0 |
5 |
rpc_io_cfg_10_drv_2 |
|
RW |
1 |
4 |
rpc_io_cfg_10_drv_1 |
|
RW |
0 |
3 |
rpc_io_cfg_10_drv_0 |
|
RW |
1 |
2 |
rpc_io_cfg_10_ibufmd_2 |
|
RW |
0 |
1 |
rpc_io_cfg_10_ibufmd_1 |
|
RW |
0 |
0 |
rpc_io_cfg_10_ibufmd_0 |
|
RW |
0 |
Address offset |
0x26C |
||
Physical address |
0x2000 226C |
Instance |
pfsoc_mss_top_sysreg |
Description |
IO electrical configuration for MSSIO pad |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31 |
Reserved |
|
RO |
0 |
30 |
rpc_io_cfg_13_lp_bypass_en |
|
RW |
0 |
29 |
rpc_io_cfg_13_lp_persist_en |
|
RW |
0 |
28 |
rpc_io_cfg_13_atp_en |
|
RW |
0 |
27 |
rpc_io_cfg_13_wpu |
|
RW |
1 |
26 |
rpc_io_cfg_13_wpd |
|
RW |
0 |
25 |
rpc_io_cfg_13_lockdn_en |
|
RO |
0 |
24 |
rpc_io_cfg_13_enhyst |
|
RW |
0 |
23 |
rpc_io_cfg_13_clamp |
|
RW |
0 |
22 |
rpc_io_cfg_13_drv_3 |
|
RW |
0 |
21 |
rpc_io_cfg_13_drv_2 |
|
RW |
1 |
20 |
rpc_io_cfg_13_drv_1 |
|
RW |
0 |
19 |
rpc_io_cfg_13_drv_0 |
|
RW |
1 |
18 |
rpc_io_cfg_13_ibufmd_2 |
|
RW |
0 |
17 |
rpc_io_cfg_13_ibufmd_1 |
|
RW |
0 |
16 |
rpc_io_cfg_13_ibufmd_0 |
|
RW |
0 |
15 |
Reserved |
|
RO |
0 |
14 |
rpc_io_cfg_12_lp_bypass_en |
|
RW |
0 |
13 |
rpc_io_cfg_12_lp_persist_en |
|
RW |
0 |
12 |
rpc_io_cfg_12_atp_en |
|
RW |
0 |
11 |
rpc_io_cfg_12_wpu |
|
RW |
1 |
10 |
rpc_io_cfg_12_wpd |
|
RW |
0 |
9 |
rpc_io_cfg_12_lockdn_en |
|
RO |
0 |
8 |
rpc_io_cfg_12_enhyst |
|
RW |
0 |
7 |
rpc_io_cfg_12_clamp |
|
RW |
0 |
6 |
rpc_io_cfg_12_drv_3 |
|
RW |
0 |
5 |
rpc_io_cfg_12_drv_2 |
|
RW |
1 |
4 |
rpc_io_cfg_12_drv_1 |
|
RW |
0 |
3 |
rpc_io_cfg_12_drv_0 |
|
RW |
1 |
2 |
rpc_io_cfg_12_ibufmd_2 |
|
RW |
0 |
1 |
rpc_io_cfg_12_ibufmd_1 |
|
RW |
0 |
0 |
rpc_io_cfg_12_ibufmd_0 |
|
RW |
0 |
Address offset |
0x270 |
||
Physical address |
0x2000 2270 |
Instance |
pfsoc_mss_top_sysreg |
Description |
IO electrical configuration for MSSIO pad |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31 |
Reserved |
|
RO |
0 |
30 |
rpc_io_cfg_15_lp_bypass_en |
|
RW |
0 |
29 |
rpc_io_cfg_15_lp_persist_en |
|
RW |
0 |
28 |
rpc_io_cfg_15_atp_en |
|
RW |
0 |
27 |
rpc_io_cfg_15_wpu |
|
RW |
1 |
26 |
rpc_io_cfg_15_wpd |
|
RW |
0 |
25 |
rpc_io_cfg_15_lockdn_en |
|
RO |
0 |
24 |
rpc_io_cfg_15_enhyst |
|
RW |
0 |
23 |
rpc_io_cfg_15_clamp |
|
RW |
0 |
22 |
rpc_io_cfg_15_drv_3 |
|
RW |
0 |
21 |
rpc_io_cfg_15_drv_2 |
|
RW |
1 |
20 |
rpc_io_cfg_15_drv_1 |
|
RW |
0 |
19 |
rpc_io_cfg_15_drv_0 |
|
RW |
1 |
18 |
rpc_io_cfg_15_ibufmd_2 |
|
RW |
0 |
17 |
rpc_io_cfg_15_ibufmd_1 |
|
RW |
0 |
16 |
rpc_io_cfg_15_ibufmd_0 |
|
RW |
0 |
15 |
Reserved |
|
RO |
0 |
14 |
rpc_io_cfg_14_lp_bypass_en |
|
RW |
0 |
13 |
rpc_io_cfg_14_lp_persist_en |
|
RW |
0 |
12 |
rpc_io_cfg_14_atp_en |
|
RW |
0 |
11 |
rpc_io_cfg_14_wpu |
|
RW |
1 |
10 |
rpc_io_cfg_14_wpd |
|
RW |
0 |
9 |
rpc_io_cfg_14_lockdn_en |
|
RO |
0 |
8 |
rpc_io_cfg_14_enhyst |
|
RW |
0 |
7 |
rpc_io_cfg_14_clamp |
|
RW |
0 |
6 |
rpc_io_cfg_14_drv_3 |
|
RW |
0 |
5 |
rpc_io_cfg_14_drv_2 |
|
RW |
1 |
4 |
rpc_io_cfg_14_drv_1 |
|
RW |
0 |
3 |
rpc_io_cfg_14_drv_0 |
|
RW |
1 |
2 |
rpc_io_cfg_14_ibufmd_2 |
|
RW |
0 |
1 |
rpc_io_cfg_14_ibufmd_1 |
|
RW |
0 |
0 |
rpc_io_cfg_14_ibufmd_0 |
|
RW |
0 |
Address offset |
0x274 |
||
Physical address |
0x2000 2274 |
Instance |
pfsoc_mss_top_sysreg |
Description |
IO electrical configuration for MSSIO pad |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31 |
Reserved |
|
RO |
0 |
30 |
rpc_io_cfg_17_lp_bypass_en |
|
RW |
0 |
29 |
rpc_io_cfg_17_lp_persist_en |
|
RW |
0 |
28 |
rpc_io_cfg_17_atp_en |
|
RW |
0 |
27 |
rpc_io_cfg_17_wpu |
|
RW |
1 |
26 |
rpc_io_cfg_17_wpd |
|
RW |
0 |
25 |
rpc_io_cfg_17_lockdn_en |
|
RO |
0 |
24 |
rpc_io_cfg_17_enhyst |
|
RW |
0 |
23 |
rpc_io_cfg_17_clamp |
|
RW |
0 |
22 |
rpc_io_cfg_17_drv_3 |
|
RW |
0 |
21 |
rpc_io_cfg_17_drv_2 |
|
RW |
1 |
20 |
rpc_io_cfg_17_drv_1 |
|
RW |
0 |
19 |
rpc_io_cfg_17_drv_0 |
|
RW |
1 |
18 |
rpc_io_cfg_17_ibufmd_2 |
|
RW |
0 |
17 |
rpc_io_cfg_17_ibufmd_1 |
|
RW |
0 |
16 |
rpc_io_cfg_17_ibufmd_0 |
|
RW |
0 |
15 |
Reserved |
|
RO |
0 |
14 |
rpc_io_cfg_16_lp_bypass_en |
|
RW |
0 |
13 |
rpc_io_cfg_16_lp_persist_en |
|
RW |
0 |
12 |
rpc_io_cfg_16_atp_en |
|
RW |
0 |
11 |
rpc_io_cfg_16_wpu |
|
RW |
1 |
10 |
rpc_io_cfg_16_wpd |
|
RW |
0 |
9 |
rpc_io_cfg_16_lockdn_en |
|
RO |
0 |
8 |
rpc_io_cfg_16_enhyst |
|
RW |
0 |
7 |
rpc_io_cfg_16_clamp |
|
RW |
0 |
6 |
rpc_io_cfg_16_drv_3 |
|
RW |
0 |
5 |
rpc_io_cfg_16_drv_2 |
|
RW |
1 |
4 |
rpc_io_cfg_16_drv_1 |
|
RW |
0 |
3 |
rpc_io_cfg_16_drv_0 |
|
RW |
1 |
2 |
rpc_io_cfg_16_ibufmd_2 |
|
RW |
0 |
1 |
rpc_io_cfg_16_ibufmd_1 |
|
RW |
0 |
0 |
rpc_io_cfg_16_ibufmd_0 |
|
RW |
0 |
Address offset |
0x278 |
||
Physical address |
0x2000 2278 |
Instance |
pfsoc_mss_top_sysreg |
Description |
IO electrical configuration for MSSIO pad |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31 |
Reserved |
|
RO |
0 |
30 |
rpc_io_cfg_19_lp_bypass_en |
|
RW |
0 |
29 |
rpc_io_cfg_19_lp_persist_en |
|
RW |
0 |
28 |
rpc_io_cfg_19_atp_en |
|
RW |
0 |
27 |
rpc_io_cfg_19_wpu |
|
RW |
1 |
26 |
rpc_io_cfg_19_wpd |
|
RW |
0 |
25 |
rpc_io_cfg_19_lockdn_en |
|
RO |
0 |
24 |
rpc_io_cfg_19_enhyst |
|
RW |
0 |
23 |
rpc_io_cfg_19_clamp |
|
RW |
0 |
22 |
rpc_io_cfg_19_drv_3 |
|
RW |
0 |
21 |
rpc_io_cfg_19_drv_2 |
|
RW |
1 |
20 |
rpc_io_cfg_19_drv_1 |
|
RW |
0 |
19 |
rpc_io_cfg_19_drv_0 |
|
RW |
1 |
18 |
rpc_io_cfg_19_ibufmd_2 |
|
RW |
0 |
17 |
rpc_io_cfg_19_ibufmd_1 |
|
RW |
0 |
16 |
rpc_io_cfg_19_ibufmd_0 |
|
RW |
0 |
15 |
Reserved |
|
RO |
0 |
14 |
rpc_io_cfg_18_lp_bypass_en |
|
RW |
0 |
13 |
rpc_io_cfg_18_lp_persist_en |
|
RW |
0 |
12 |
rpc_io_cfg_18_atp_en |
|
RW |
0 |
11 |
rpc_io_cfg_18_wpu |
|
RW |
1 |
10 |
rpc_io_cfg_18_wpd |
|
RW |
0 |
9 |
rpc_io_cfg_18_lockdn_en |
|
RO |
0 |
8 |
rpc_io_cfg_18_enhyst |
|
RW |
0 |
7 |
rpc_io_cfg_18_clamp |
|
RW |
0 |
6 |
rpc_io_cfg_18_drv_3 |
|
RW |
0 |
5 |
rpc_io_cfg_18_drv_2 |
|
RW |
1 |
4 |
rpc_io_cfg_18_drv_1 |
|
RW |
0 |
3 |
rpc_io_cfg_18_drv_0 |
|
RW |
1 |
2 |
rpc_io_cfg_18_ibufmd_2 |
|
RW |
0 |
1 |
rpc_io_cfg_18_ibufmd_1 |
|
RW |
0 |
0 |
rpc_io_cfg_18_ibufmd_0 |
|
RW |
0 |
Address offset |
0x27C |
||
Physical address |
0x2000 227C |
Instance |
pfsoc_mss_top_sysreg |
Description |
IO electrical configuration for MSSIO pad |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31 |
Reserved |
|
RO |
0 |
30 |
rpc_io_cfg_21_lp_bypass_en |
|
RW |
0 |
29 |
rpc_io_cfg_21_lp_persist_en |
|
RW |
0 |
28 |
rpc_io_cfg_21_atp_en |
|
RW |
0 |
27 |
rpc_io_cfg_21_wpu |
|
RW |
1 |
26 |
rpc_io_cfg_21_wpd |
|
RW |
0 |
25 |
rpc_io_cfg_21_lockdn_en |
|
RO |
0 |
24 |
rpc_io_cfg_21_enhyst |
|
RW |
0 |
23 |
rpc_io_cfg_21_clamp |
|
RW |
0 |
22 |
rpc_io_cfg_21_drv_3 |
|
RW |
0 |
21 |
rpc_io_cfg_21_drv_2 |
|
RW |
1 |
20 |
rpc_io_cfg_21_drv_1 |
|
RW |
0 |
19 |
rpc_io_cfg_21_drv_0 |
|
RW |
1 |
18 |
rpc_io_cfg_21_ibufmd_2 |
|
RW |
0 |
17 |
rpc_io_cfg_21_ibufmd_1 |
|
RW |
0 |
16 |
rpc_io_cfg_21_ibufmd_0 |
|
RW |
0 |
15 |
Reserved |
|
RO |
0 |
14 |
rpc_io_cfg_20_lp_bypass_en |
|
RW |
0 |
13 |
rpc_io_cfg_20_lp_persist_en |
|
RW |
0 |
12 |
rpc_io_cfg_20_atp_en |
|
RW |
0 |
11 |
rpc_io_cfg_20_wpu |
|
RW |
1 |
10 |
rpc_io_cfg_20_wpd |
|
RW |
0 |
9 |
rpc_io_cfg_20_lockdn_en |
|
RO |
0 |
8 |
rpc_io_cfg_20_enhyst |
|
RW |
0 |
7 |
rpc_io_cfg_20_clamp |
|
RW |
0 |
6 |
rpc_io_cfg_20_drv_3 |
|
RW |
0 |
5 |
rpc_io_cfg_20_drv_2 |
|
RW |
1 |
4 |
rpc_io_cfg_20_drv_1 |
|
RW |
0 |
3 |
rpc_io_cfg_20_drv_0 |
|
RW |
1 |
2 |
rpc_io_cfg_20_ibufmd_2 |
|
RW |
0 |
1 |
rpc_io_cfg_20_ibufmd_1 |
|
RW |
0 |
0 |
rpc_io_cfg_20_ibufmd_0 |
|
RW |
0 |
Address offset |
0x280 |
||
Physical address |
0x2000 2280 |
Instance |
pfsoc_mss_top_sysreg |
Description |
IO electrical configuration for MSSIO pad |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31 |
Reserved |
|
RO |
0 |
30 |
rpc_io_cfg_23_lp_bypass_en |
|
RW |
0 |
29 |
rpc_io_cfg_23_lp_persist_en |
|
RW |
0 |
28 |
rpc_io_cfg_23_atp_en |
|
RW |
0 |
27 |
rpc_io_cfg_23_wpu |
|
RW |
1 |
26 |
rpc_io_cfg_23_wpd |
|
RW |
0 |
25 |
rpc_io_cfg_23_lockdn_en |
|
RO |
0 |
24 |
rpc_io_cfg_23_enhyst |
|
RW |
0 |
23 |
rpc_io_cfg_23_clamp |
|
RW |
0 |
22 |
rpc_io_cfg_23_drv_3 |
|
RW |
0 |
21 |
rpc_io_cfg_23_drv_2 |
|
RW |
1 |
20 |
rpc_io_cfg_23_drv_1 |
|
RW |
0 |
19 |
rpc_io_cfg_23_drv_0 |
|
RW |
1 |
18 |
rpc_io_cfg_23_ibufmd_2 |
|
RW |
0 |
17 |
rpc_io_cfg_23_ibufmd_1 |
|
RW |
0 |
16 |
rpc_io_cfg_23_ibufmd_0 |
|
RW |
0 |
15 |
Reserved |
|
RO |
0 |
14 |
rpc_io_cfg_22_lp_bypass_en |
|
RW |
0 |
13 |
rpc_io_cfg_22_lp_persist_en |
|
RW |
0 |
12 |
rpc_io_cfg_22_atp_en |
|
RW |
0 |
11 |
rpc_io_cfg_22_wpu |
|
RW |
1 |
10 |
rpc_io_cfg_22_wpd |
|
RW |
0 |
9 |
rpc_io_cfg_22_lockdn_en |
|
RO |
0 |
8 |
rpc_io_cfg_22_enhyst |
|
RW |
0 |
7 |
rpc_io_cfg_22_clamp |
|
RW |
0 |
6 |
rpc_io_cfg_22_drv_3 |
|
RW |
0 |
5 |
rpc_io_cfg_22_drv_2 |
|
RW |
1 |
4 |
rpc_io_cfg_22_drv_1 |
|
RW |
0 |
3 |
rpc_io_cfg_22_drv_0 |
|
RW |
1 |
2 |
rpc_io_cfg_22_ibufmd_2 |
|
RW |
0 |
1 |
rpc_io_cfg_22_ibufmd_1 |
|
RW |
0 |
0 |
rpc_io_cfg_22_ibufmd_0 |
|
RW |
0 |
Address offset |
0x2A8 |
||
Physical address |
0x2000 22A8 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Sets H2F [31:0] Spares out signals |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
data |
See MSS MAS specification for full description |
RW |
0x0000 0000 |
Address offset |
0x2AC |
||
Physical address |
0x2000 22AC |
Instance |
pfsoc_mss_top_sysreg |
Description |
Sets H2F [37:32] Spares out signals |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:6 |
Reserved |
|
RO |
0x000 0000 |
5:0 |
data |
See MSS MAS specification for full description |
RW |
0x00 |
Address offset |
0x2B0 |
||
Physical address |
0x2000 22B0 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Read H2F [31:0] Spares out signals |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
data |
See MSS MAS specification for full description |
RO |
0x0000 0000 |
Address offset |
0x2B4 |
||
Physical address |
0x2000 22B4 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Read H2F [37:32] Spares out signals |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:6 |
Reserved |
|
RO |
0x000 0000 |
5:0 |
data |
See MSS MAS specification for full description |
RO |
0x00 |
Address offset |
0x2B8 |
||
Physical address |
0x2000 22B8 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Read F2H [31:0] Spares in1 signals |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
data |
See MSS MAS specification for full description |
RO |
0x0000 0000 |
Address offset |
0x2BC |
||
Physical address |
0x2000 22BC |
Instance |
pfsoc_mss_top_sysreg |
Description |
Read F2H [37:32] Spares in1 signals |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:6 |
Reserved |
|
RO |
0x000 0000 |
5:0 |
data |
See MSS MAS specification for full description |
RO |
0x00 |
Address offset |
0x2C0 |
||
Physical address |
0x2000 22C0 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Read F2H [31:0] Spares in2 signals |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
data |
See MSS MAS specification for full description |
RO |
0x0000 0000 |
Address offset |
0x2C4 |
||
Physical address |
0x2000 22C4 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Read F2H [37:32] Spares in2 signals |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:6 |
Reserved |
|
RO |
0x000 0000 |
5:0 |
data |
See MSS MAS specification for full description |
RO |
0x00 |
Address offset |
0x2D0 |
||
Physical address |
0x2000 22D0 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Register for ECO usage |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
Reserved |
|
RO |
0x00 0000 |
7:0 |
DATA |
No function, provided for future ECO use |
RW |
0x00 |
Address offset |
0x2D4 |
||
Physical address |
0x2000 22D4 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Register for ECO usage |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
Reserved |
|
RO |
0x00 0000 |
7:0 |
DATA |
No function, provided for future ECO use |
RW |
0x00 |
Address offset |
0x2D8 |
||
Physical address |
0x2000 22D8 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Register for ECO usage |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:16 |
Reserved |
|
RO |
0x0000 |
15:0 |
DATA |
Provides readback of { W1P, RW } registers. No function, provided
for future ECO use. |
RO |
0x0000 |
Address offset |
0x2DC |
||
Physical address |
0x2000 22DC |
Instance |
pfsoc_mss_top_sysreg |
Description |
Spare signal back to PFC |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:10 |
Reserved |
|
RO |
0x00 0000 |
9 |
MMUART0_RXD |
When set MMUART0 RXD is received on perimeter 5 from PFC.
When enabled in PFC it the SPI SDI input is drives this connection. When
enabled the PFC QSPI interrupt is disabled. (This function intended for
manufacturing use only) |
RW |
0 |
8 |
MMUART0_TXD |
When set MMUART0 TXD is sent on Perimeter 2 to PFC, when
enabled in PFC it will be output on the SPI SDO pin. (This function intended
for manufacturing use only) |
RW |
0 |
7 |
Reserved |
|
RO |
0 |
6:4 |
DATA |
Controls perim_spare_out bits 5 7 & 9 when the ENABLE
bits set |
RW |
0x0 |
3 |
Reserved |
|
RO |
0 |
2:0 |
ENABLE |
Allows the MSS to control the perim_spare_out bits 5 7
& 9. No function, provided for future ECO use. |
RW |
0x0 |
Address offset |
0x2E0 |
||
Physical address |
0x2000 22E0 |
Instance |
pfsoc_mss_top_sysreg |
Description |
Unused FIC resets |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
Reserved |
|
RO |
0x000 0000 |
3:0 |
RESET |
Connected to spare FIC 0-3 Reset inputs to provide simple
RO bits. No defined use |
RO |
0x0 |
pfsoc_mss_top_sysreg
has no common memories.