TRACE

This section provides information on the TRACE Module Instance. Each of the module registers is described below.

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TRACE Register Mapping Summary

TRACE Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

US_CTL

RW

32

0x0000 0000

0x0 0000

0x2300 0000

US_INT_CTL

RW

32

0x0000 0000

0x0 0004

0x2300 0004

US_INT_STS

RW

32

0x0000 0000

0x0 0008

0x2300 0008

US_DATA

WO

32

0x0000 0000

0x0 000C

0x2300 000C

US_BUF_STS

RO

32

0x0000 0000

0x0 0010

0x2300 0010

US_WR_STS

RO

32

0x0000 0000

0x0 0014

0x2300 0014

US_GP

RW

32

0x0000 0000

0x0 0018

0x2300 0018

US_EVT

RW

32

0x0000 0000

0x0 001C

0x2300 001C

DS_CTL

RW

32

0x0000 0000

0x0 0080

0x2300 0080

DS_INT_CTL

RW

32

0x0000 0000

0x0 0084

0x2300 0084

DS_INT_STS

RW

32

0x0000 0000

0x0 0088

0x2300 0088

DS_DATA

RO

32

0x0000 0000

0x0 008C

0x2300 008C

DS_BUF_STS

RO

32

0x0000 0000

0x0 0090

0x2300 0090

DS_RD_STS

RO

32

0x0000 0000

0x0 0094

0x2300 0094

DS_EVT

RW

32

0x0000 0000

0x0 009C

0x2300 009C

DS_EVT_CTL

RW

32

0x0000 0000

0x0 00A0

0x2300 00A0

DS_EVT_STS

RO

32

0x0000 0000

0x0 00A4

0x2300 00A4

DS_EVT_FILTER_0

RW

32

0x0000 0000

0x0 00A8

0x2300 00A8

DS_EVT_FILTER_1

RW

32

0x0000 0000

0x0 00AC

0x2300 00AC

SMB_REG_GLOBAL_CFG

RW

32

0x0000 0000

0x1 0000

0x2301 0000

SMB_REG_GLOBAL_EN

RW

32

0x0000 0000

0x1 0004

0x2301 0004

SMB_REG_GLOBAL_INT

RW

32

0x0000 0000

0x1 0008

0x2301 0008

SMB_REG_GLOBAL_ID

RW

32

0x0000 0000

0x1 000C

0x2301 000C

SMB_REG_BUF_CFG_LO_0

RW

32

0x0000 0000

0x1 0040

0x2301 0040

SMB_REG_BUF_CFG_HI_0

RW

32

0x0000 0000

0x1 0044

0x2301 0044

SMB_REG_INT_CTRL_0

RW

32

0x0000 0000

0x1 0048

0x2301 0048

SMB_REG_INT_STS_0

RW

32

0x0000 0000

0x1 004C

0x2301 004C

SMB_REG_BASE_LO_0

RW

32

0x0000 0000

0x1 0050

0x2301 0050

SMB_REG_BASE_HI_0

RW

32

0x0000 0000

0x1 0054

0x2301 0054

SMB_REG_LIMIT_0

RW

32

0x0000 0000

0x1 0058

0x2301 0058

SMB_REG_RD_ADDR_0

RW

32

0x0000 0000

0x1 005C

0x2301 005C

SMB_REG_WR_ADDR_0

RO

32

0x0000 0000

0x1 0060

0x2301 0060

SMB_REG_PURGE_0

RW

32

0x0000 0000

0x1 0064

0x2301 0064

SMB_REG_BUFFER_ACTIVE_0

RO

32

0x0000 0000

0x1 0068

0x2301 0068

SMB_REG_BUF_CFG_LO_1

RW

32

0x0000 0000

0x1 0140

0x2301 0140

SMB_REG_BUF_CFG_HI_1

RW

32

0x0000 0000

0x1 0144

0x2301 0144

SMB_REG_INT_CTRL_1

RW

32

0x0000 0000

0x1 0148

0x2301 0148

SMB_REG_INT_STS_1

RW

32

0x0000 0000

0x1 014C

0x2301 014C

SMB_REG_BASE_LO_1

RW

32

0x0000 0000

0x1 0150

0x2301 0150

SMB_REG_BASE_HI_1

RW

32

0x0000 0000

0x1 0154

0x2301 0154

SMB_REG_LIMIT_1

RW

32

0x0000 0000

0x1 0158

0x2301 0158

SMB_REG_RD_ADDR_1

RW

32

0x0000 0000

0x1 015C

0x2301 015C

SMB_REG_WR_ADDR_1

RO

32

0x0000 0000

0x1 0160

0x2301 0160

SMB_REG_PURGE_1

RW

32

0x0000 0000

0x1 0164

0x2301 0164

SMB_REG_BUFFER_ACTIVE_1

RO

32

0x0000 0000

0x1 0168

0x2301 0168

VCON_ENABLES

RW

32

0x0000 0000

0x2 0000

0x2302 0000

VCON_ENABLES_OR

RW

32

0x0000 0000

0x2 0004

0x2302 0004

VCON_ENABLES_AND

RW

32

0x0000 0000

0x2 0008

0x2302 0008

VCON_INTERRUPT_CONFIG

RW

32

0x0000 0000

0x2 000C

0x2302 000C

VCON_GLOBAL_STATUS

RO

32

0x0000 0000

0x2 0010

0x2302 0010

VCON_GLOBAL_ALLOC

RW

32

0x0000 0000

0x2 0014

0x2302 0014

VCON_CHAN0_BURSTDATA

RW

32

0x0000 0000

0x2 007C

0x2302 007C

VCON_CHAN1_BURSTDATA

RW

32

0x0000 0000

0x2 00FC

0x2302 00FC

VCON_CHAN2_BURSTDATA

RW

32

0x0000 0000

0x2 01DC

0x2302 01DC

VCON_CHAN0_CONFIG

RW

32

0x0000 0000

0x2 0200

0x2302 0200

VCON_CHAN0_STATUS

RO

32

0x0000 0000

0x2 0204

0x2302 0204

VCON_CHAN0_INT_CONFIG

RW

32

0x0000 0000

0x2 0208

0x2302 0208

VCON_CHAN0_INT_STATUS

RO

32

0x0000 0000

0x2 020C

0x2302 020C

VCON_CHAN0_ALLOC

RW

32

0x0000 0000

0x2 0210

0x2302 0210

VCON_CHAN0_DATA

RW

32

0x0000 0000

0x2 0214

0x2302 0214

VCON_CHAN1_CONFIG

RW

32

0x0000 0000

0x2 0220

0x2302 0220

VCON_CHAN1_STATUS

RO

32

0x0000 0000

0x2 0224

0x2302 0224

VCON_CHAN1_INT_CONFIG

RW

32

0x0000 0000

0x2 0228

0x2302 0228

VCON_CHAN1_INT_STATUS

RO

32

0x0000 0000

0x2 022C

0x2302 022C

VCON_CHAN1_ALLOC

RW

32

0x0000 0000

0x2 0230

0x2302 0230

VCON_CHAN1_DATA

RW

32

0x0000 0000

0x2 0234

0x2302 0234

VCON_CHAN2_CONFIG

RW

32

0x0000 0000

0x2 0240

0x2302 0240

VCON_CHAN2_STATUS

RO

32

0x0000 0000

0x2 0244

0x2302 0244

VCON_CHAN2_INT_CONFIG

RW

32

0x0000 0000

0x2 0248

0x2302 0248

VCON_CHAN2_INT_STATUS

RO

32

0x0000 0000

0x2 024C

0x2302 024C

VCON_CHAN2_ALLOC

RW

32

0x0000 0000

0x2 0250

0x2302 0250

VCON_CHAN2_DATA

RW

32

0x0000 0000

0x2 0254

0x2302 0254

VCON_CHAN3_CONFIG

RW

32

0x0000 0000

0x2 0260

0x2302 0260

VCON_CHAN3_STATUS

RO

32

0x0000 0000

0x2 0264

0x2302 0264

VCON_CHAN3_INT_CONFIG

RW

32

0x0000 0000

0x2 0268

0x2302 0268

VCON_CHAN3_INT_STATUS

RO

32

0x0000 0000

0x2 026C

0x2302 026C

VCON_CHAN3_ALLOC

RW

32

0x0000 0000

0x2 0270

0x2302 0270

VCON_CHAN3_DATA

RW

32

0x0000 0000

0x2 0274

0x2302 0274

VCON_CHAN4_CONFIG

RW

32

0x0000 0000

0x2 0280

0x2302 0280

VCON_CHAN4_STATUS

RO

32

0x0000 0000

0x2 0284

0x2302 0284

VCON_CHAN4_INT_CONFIG

RW

32

0x0000 0000

0x2 0288

0x2302 0288

VCON_CHAN4_INT_STATUS

RO

32

0x0000 0000

0x2 028C

0x2302 028C

VCON_CHAN4_ALLOC

RW

32

0x0000 0000

0x2 0290

0x2302 0290

VCON_CHAN4_DATA

RW

32

0x0000 0000

0x2 0294

0x2302 0294

VCON_CHAN3_BURSTDATA

RW

32

0x0000 0000

0x2 02BC

0x2302 02BC

VCON_CHAN4_BURSTDATA

RW

32

0x0000 0000

0x2 039C

0x2302 039C

 

TRACE Register Descriptions

TRACE : US_CTL

Address offset

0x0 0000

Physical address

0x2300 0000

Instance

TRACE

Description

Upstream general control

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:7

Reserved

Read as zero

RO

0x000 0000

6

int_polarity

Upstream interrupt output is active high when this bit is 1. or active low when 0. Initial value at reset is set according to an instantiation parameter. so it should not be necessary to change the value of this bit.

RW

0

5

int_type

Upstream interrupt output is a pulse when this bit is 1. or a level when it is 0

RW

0

4

int_en

Upstream master interrupt enable

RW

0

3

Reserved

Read as zero

RO

0

2

flush

Flush the message currently being written from upstream message buffer. Must be applied before the last write of a message. Selfclearing. so always reads as zero

WO

0

1

clear

Clear upstream message buffer. Debug option; do not set without consulting UltraSoC

RW

0

0

enable

Upstream enable.

RW

0

 

TRACE : US_INT_CTL

Address offset

0x0 0004

Physical address

0x2300 0004

Instance

TRACE

Description

control of upstream interrupt behaviour

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

Read as zero

RO

0x0000 0000

2

empty

Enable buffer empty interrupt

RW

0

1

not_full

Enable buffer not full interrupt

RW

0

0

err

Enable upstream error interrupt

RW

0

 

TRACE : US_INT_STS

Address offset

0x0 0008

Physical address

0x2300 0008

Instance

TRACE

Description

upstream interrupt status

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

Read as zero

RO

0x0000 0000

2

empty

Enable buffer empty interrupt. The upstream message buffer is empty. and there is therefore sufficient space to write an entire message via us_data.

RW

0

1

not_full

Enable buffer not full interrupt. The upstream message buffer is no longer full. and further message data can be written via us_data

RW

0

0

err

Enable upstream error interrupt. This indicates us_data was written when there was no space available in the upstream message buffer (us_buf_sts full bit set).

RW

0

 

TRACE : US_DATA

Address offset

0x0 000C

Physical address

0x2300 000C

Instance

TRACE

Description

Upstream message data

Type

WO

 

Bits

Field Name

Description

Type

Reset

31:0

data

Upstream message data

WO

0x0000 0000

 

TRACE : US_BUF_STS

Address offset

0x0 0010

Physical address

0x2300 0010

Instance

TRACE

Description

upstream buffer status

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:27

Reserved

Read as zero

RO

0x00

26:16

messages

Number of whole messages contained in the upstream buffer.

RO

0x000

15:4

Reserved

Read as zero

RO

0x000

3

wr_ongoing

Write ongoing. Part of a message has been written in to the buffer via us_data.

RO

0

2

rd_ongoing

Read ongoing. Part of a message has been output from the message interface

RO

0

1

empty

Upstream buffer is empty

RO

0

0

full

Upstream buffer is full

RO

0

 

TRACE : US_WR_STS

Address offset

0x0 0014

Physical address

0x2300 0014

Instance

TRACE

Description

Upstream write status

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:16

Reserved

Read as zero

RO

0x0000

15:8

header

Header (byte 0) of the message being written into upstream message buffer (only valid if wr_ongoing is 1).

RO

0x00

7:4

entries

Number of 32-bit words of an incomplete message written into the upstream buffer (only valid if wr_ongoing is 1).

RO

0x0

3:2

Reserved

Read as zero

RO

0x0

1

wr_ongoing

Write ongoing. Part of a message has been written in to the buffer via us_data

RO

0

0

done

Upstream buffer contains a complete message

RO

0

 

TRACE : US_GP

Address offset

0x0 0018

Physical address

0x2300 0018

Instance

TRACE

Description

Upstream general purpose

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:8

Reserved

Read as zero

RO

0x00 0000

7:0

gp

General purpose location

RW

0x00

 

TRACE : US_EVT

Address offset

0x0 001C

Physical address

0x2300 001C

Instance

TRACE

Description

Upstream event

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:8

Reserved

Read as zero

RO

0x00 0000

7:0

Event

Event number to send

RW

0x00

 

TRACE : DS_CTL

Address offset

0x0 0080

Physical address

0x2300 0080

Instance

TRACE

Description

Downstream general control

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:7

Reserved

Read as zero

RO

0x000 0000

6

int_polarity

Downstream interrupt output is active high when this bit is 1. or active low when 0. Initial value at reset is set according to an instantiation parameter. so it should not be necessary to change the value of this bit

RW

0

5

int_type

Downstream interrupt output is a pulse when this bit is 1. or a level when it is 0.

RW

0

4

int_en

Downstream master interrupt enable.

RW

0

3

msg_stall

Stall the downstream message interface to prevent new downstream data accumulating in the downstream buffer. Debug option; do not set without consulting UltraSoC.

RW

0

2

Reserved

Read as zero

RO

0

1

clear

Clear downstream message buffer. Debug option; do not set without consulting UltraSoC

RW

0

0

enable

Downstream enable

RW

0

 

TRACE : DS_INT_CTL

Address offset

0x0 0084

Physical address

0x2300 0084

Instance

TRACE

Description

control of downstream interrupt behaviour

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:5

Reserved

Read as zero

RO

0x000 0000

4

evt_overflow

Enable event FIFO overflow interrupt

RW

0

3

evt_avail

Enable event available interrupt

RW

0

2

not_empty

Enable buffer not empty interrupt

RW

0

1

full

Enable buffer full interrupt.

RW

0

0

err

Enable downstream error interrupt

RW

0

 

TRACE : DS_INT_STS

Address offset

0x0 0088

Physical address

0x2300 0088

Instance

TRACE

Description

downstream interrupt status

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:5

Reserved

Read as zero

RO

0x000 0000

4

evt_overflow

Event FIFO overflow interrupt. A downstream event was lost because there was no room to store it in the downstream event FIFO

RW

0

3

evt_avail

Event available interrupt. The downstream event FIFO is no longer empty

RW

0

2

not_empty

Downstream buffer not empty interrupt. A new message is available and can be read from ds_data.

RW

0

1

full

Downstream buffer full interrupt. The downstream message buffer is full. indicating that no further messages can be accepted and backpressure is being applied to the downstream message interface

RW

0

0

err

Downstream error interrupt. This indicates ds_data was read when there was no message data available

RW

0

 

TRACE : DS_DATA

Address offset

0x0 008C

Physical address

0x2300 008C

Instance

TRACE

Description

Downstream message data

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

data

Downstream message data

RO

0x0000 0000

 

TRACE : DS_BUF_STS

Address offset

0x0 0090

Physical address

0x2300 0090

Instance

TRACE

Description

Downstream buffer status

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:27

Reserved

Read as zero

RO

0x00

26:16

messages

Number of whole messages contained in the downstream buffer

RO

0x000

15:4

total_entries

Number of buffer entries containing valid message data

RO

0x000

3

wr_ongoing

Write ongoing. Part of a message has been received from the message interface.

RO

0

2

rd_ongoing

Read ongoing. Part of a message has been read out of the buffer via ds_data

RO

0

1

empty

Downstream buffer is empty

RO

0

0

full

Downstream buffer is full

RO

0

 

TRACE : DS_RD_STS

Address offset

0x0 0094

Physical address

0x2300 0094

Instance

TRACE

Description

downstream read status

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:16

Reserved

Read as zero

RO

0x0000

15:8

header

Header (byte 0) of the message being read from the downstream message buffer (only valid if rd_ongoing is 1).

RO

0x00

7:4

entries

Number of 32-bit words of a message yet to be read out of the downstream buffer (only valid if rd_ongoing is 1).

RO

0x0

3:2

Reserved

Read as zero

RO

0x0

1

rd_ongoing

Read ongoing. Part of a message has been read out of the buffer via ds_data

RO

0

0

ready

Downstream buffer contains a complete message ready for reading.

RO

0

 

TRACE : DS_EVT

Address offset

0x0 009C

Physical address

0x2300 009C

Instance

TRACE

Description

Downstream event

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:9

Reserved

Read as zero

RO

0x00 0000

8

valid

Event valid

RW

0

7:0

Event

Event number received (when valid is 1).

RW

0x00

 

TRACE : DS_EVT_CTL

Address offset

0x0 00A0

Physical address

0x2300 00A0

Instance

TRACE

Description

control of downstream real-time events

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Read as zero

RO

0x0000 0000

1

flush

Flush the downstream event FIFO. Once set. all events will be discarded until a zero is written to this bit

RW

0

0

enable

Event FIFO enable. Must be set in order to receive events via ds_evt

RW

0

 

TRACE : DS_EVT_STS

Address offset

0x0 00A4

Physical address

0x2300 00A4

Instance

TRACE

Description

status of downstream real-time events

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:10

Reserved

Read as zero

RO

0x00 0000

9

full

Indicates that the downstream event FIFO is full

RO

0

8

empty

Indicates that the downstream event FIFO is empty

RO

0

7:0

events

Number of events in the downstream event FIFO

RO

0x00

 

TRACE : DS_EVT_FILTER_0

Address offset

0x0 00A8

Physical address

0x2300 00A8

Instance

TRACE

Description

Downstream event filter 0

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

Reserved

Read as zero

RO

0x0000

15:8

filter_match

Filter match. Capture all real-time events that meet the condition: event & filter_mask == filter_match & filter_mask

RW

0x00

7:0

filter_mask

Filter mask

RW

0x00

 

TRACE : DS_EVT_FILTER_1

Address offset

0x0 00AC

Physical address

0x2300 00AC

Instance

TRACE

Description

Downstream event filter 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

Reserved

Read as zero

RO

0x0000

15:8

filter_match

Filter match. Capture all real-time events that meet the condition: event & filter_mask == filter_match & filter_mask

RW

0x00

7:0

filter_mask

Filter mask

RW

0x00

 

TRACE : SMB_REG_GLOBAL_CFG

Address offset

0x1 0000

Physical address

0x2301 0000

Instance

TRACE

Description

Global configuration

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:28

Reserved

Read as zero

RO

0x0

27:24

mem_read_rate

Controls the rate at which the read access credit counter is replenished in powers of 2.

RW

0x0

23:22

mem_read_credit

Controls the access credit available to the bus master for read accesses to the system memory.

RW

0x0

21:18

mem_write_rate

Controls the rate at which the write access credit counter is replenished in powers of 2. 0x0 replenishes continuously

RW

0x0

17:16

mem_write_credit

Controls the access credit available to the bus master for write accesses to the system memory.

RW

0x0

15:12

idle_period

Controls the idle message injection timer period

RW

0x0

11:4

burst_length

Programmable burst length for system memory transfers. Defaults to the parameter sys_mem_blen_p

RW

0x00

3:2

msg_lc

The logical channel the network message adapter must output messages on.

RW

0x0

1

double_end_enable

Read enable for double-ended buffering mode.

RW

0

0

module_enable

Global enable for the System Memory Buffer. 0-Disable 1-Enable

RW

0

 

TRACE : SMB_REG_GLOBAL_EN

Address offset

0x1 0004

Physical address

0x2301 0004

Instance

TRACE

Description

Global enable

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:8

Reserved

Read as zero.

RO

0x00 0000

7:1

Reserved

Read as zero.

RO

0x00

0

module_enable

Global enable for the System Memory Buffer. 0-Disable 1-Enable

RW

0

 

TRACE : SMB_REG_GLOBAL_INT

Address offset

0x1 0008

Physical address

0x2301 0008

Instance

TRACE

Description

Global interrupt control

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

Read as zero

RO

0x0000 0000

2

int_polarity

Interrupt polarity: 1 - Active high. 0 - Active low.

RW

0

1

int_type

Interrupt type: 1 - Pulse, 0 Level.

RW

0

0

int_enable

Global interrupt enable control

RW

0

 

TRACE : SMB_REG_GLOBAL_ID

Address offset

0x1 000C

Physical address

0x2301 000C

Instance

TRACE

Description

Global master bus interface ID control

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

mst_id

Global master bus interface ID control

RW

0x0000 0000

 

TRACE : SMB_REG_BUF_CFG_LO_0

Address offset

0x1 0040

Physical address

0x2301 0040

Instance

TRACE

Description

Logical buffer configuration (lower 32b) i logical buffer index; i = 0 for 1st buffer

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:21

Reserved

Read as zero.

RO

0x000

20

buf_event_enable

Enable event generation for the logical buffer when set

RW

0

19:16

flow_mask

Mask to filter the messages accepted based on their flow

RW

0x0

15:13

Reserved

Read as zero

RO

0x0

12

timer_enable

Controls whether the purge timer is enabled for a logical buffer. 0-Purge timer disabled 1-Purge timer enabled

RW

0

11

buf_continuous

Set to make the buffer lossless by configuring it to block its message input when in a paused state.

RW

0

10

buf_armed

Set to arm the logical buffer in single shot mode

RW

0

9

buf_arm_mode

Set to enable single-shot mode. clear for automatic rearming

RW

0

8

buf_init

Initialises the buffer when set to 1, application of 0 has no effect. Read as zero

RW

0

7:4

cm_forward_id

The communicator ID to forward the message stream to upon reading of the logical buffer

RW

0x0

3:2

buf_mode

Buffering modes. 00 : Streaming mode (FIFO) 01 : Trace to mode 10 : Trace from mode 11 : Trace about mode

RW

0x0

1

buf_type

Buffer control type: 0 : Double-ended buffering mode (default) 1 : Single-ended buffering mode

RW

0

0

buf_enable

Logical buffer enable control: 0 : Disable the logical buffer 1 : Enable the logical buffer

RW

0

 

TRACE : SMB_REG_BUF_CFG_HI_0

Address offset

0x1 0044

Physical address

0x2301 0044

Instance

TRACE

Description

Logical buffer configuration (upper 32b) i logical buffer index; i = 0 for 1st buffer

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:24

buf_trigger

The real-time event to accept as a trigger when the buffer is configured in a triggered mode

RW

0x00

23:16

buf_event

The event to output when a buffer trigger occurs

RW

0x00

15:8

message_hi

Message filter range upper value

RW

0x00

7:0

message_lo

Message filter range lower value.

RW

0x00

 

TRACE : SMB_REG_INT_CTRL_0

Address offset

0x1 0048

Physical address

0x2301 0048

Instance

TRACE

Description

Interrupt control

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

Read as zero

RO

0x0 0000

11:8

buf_note

Selects the buffer status changes that a debugger is to be notified about using a real-time event or interrupt.

RW

0x0

7:1

Reserved

Read as zero

RO

0x00

0

buf_int_enable

Logical buffer interrupts enable.

RW

0

 

TRACE : SMB_REG_INT_STS_0

Address offset

0x1 004C

Physical address

0x2301 004C

Instance

TRACE

Description

Interrupt status

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:4

Reserved

Read as zero

RO

0x000 0000

3

buf_full

Logical buffer full interrupt

RW

0

2

buf_triggered

Logical buffer triggered interrupt

RW

0

1

buf_block_avail

Logical buffer memory block available to read interrupt.

RW

0

0

buf_not_empty

Logical buffer changed to not empty interrupt.

RW

0

 

TRACE : SMB_REG_BASE_LO_0

Address offset

0x1 0050

Physical address

0x2301 0050

Instance

TRACE

Description

Logical buffer base address (lower 32b)

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

base_addr_lo

Memory base address lower 32b for the message buffers

RW

0x0000 0000

 

TRACE : SMB_REG_BASE_HI_0

Address offset

0x1 0054

Physical address

0x2301 0054

Instance

TRACE

Description

Logical buffer base address (upper 32b)

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

base_addr_hi

Memory base address upper 32b for the message buffers

RW

0x0000 0000

 

TRACE : SMB_REG_LIMIT_0

Address offset

0x1 0058

Physical address

0x2301 0058

Instance

TRACE

Description

Logical buffer limit address

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

limit_addr

Memory limit address configuring the end of a logical buffer

RW

0x0000 0000

 

TRACE : SMB_REG_RD_ADDR_0

Address offset

0x1 005C

Physical address

0x2301 005C

Instance

TRACE

Description

Memory read address

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

read_ptr

Memory read address pointer. Read only if the buffer is enabled in double ended mode

RW

0x0000 0000

 

TRACE : SMB_REG_WR_ADDR_0

Address offset

0x1 0060

Physical address

0x2301 0060

Instance

TRACE

Description

Memory write address

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

write_ptr

Memory write address pointer

RO

0x0000 0000

 

TRACE : SMB_REG_PURGE_0

Address offset

0x1 0064

Physical address

0x2301 0064

Instance

TRACE

Description

Logical buffer purge

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Read as zero

RO

0x0000 0000

0

purge

Applying a 1 causes the packer and input FIFO of the logical buffer to be purged.

WO

0

 

TRACE : SMB_REG_BUFFER_ACTIVE_0

Address offset

0x1 0068

Physical address

0x2301 0068

Instance

TRACE

Description

Logical buffer buffer active

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Read as zero

RO

0x0000 0000

1

read_buffer_active

Read operations from the buffer are active when 1

RO

0

0

write_buffer_active

Write operations from the buffer are active when 1

RO

0

 

TRACE : SMB_REG_BUF_CFG_LO_1

Address offset

0x1 0140

Physical address

0x2301 0140

Instance

TRACE

Description

Logical buffer configuration (lower 32b) i logical buffer index; i = 0 for 1st buffer

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:21

Reserved

Read as zero.

RO

0x000

20

buf_event_enable

Enable event generation for the logical buffer when set

RW

0

19:16

flow_mask

Mask to filter the messages accepted based on their flow

RW

0x0

15:13

Reserved

Read as zero

RO

0x0

12

timer_enable

Controls whether the purge timer is enabled for a logical buffer. 0-Purge timer disabled 1-Purge timer enabled

RW

0

11

buf_continuous

Set to make the buffer lossless by configuring it to block its message input when in a paused state.

RW

0

10

buf_armed

Set to arm the logical buffer in single shot mode

RW

0

9

buf_arm_mode

Set to enable single-shot mode. clear for automatic rearming

RW

0

8

buf_init

Initialises the buffer when set to 1, application of 0 has no effect. Read as zero

RW

0

7:4

cm_forward_id

The communicator ID to forward the message stream to upon reading of the logical buffer

RW

0x0

3:2

buf_mode

Buffering modes. 00 : Streaming mode (FIFO) 01 : Trace to mode 10 : Trace from mode 11 : Trace about mode

RW

0x0

1

buf_type

Buffer control type: 0 : Double-ended buffering mode (default) 1 : Single-ended buffering mode

RW

0

0

buf_enable

Logical buffer enable control: 0 : Disable the logical buffer 1 : Enable the logical buffer

RW

0

 

TRACE : SMB_REG_BUF_CFG_HI_1

Address offset

0x1 0144

Physical address

0x2301 0144

Instance

TRACE

Description

Logical buffer configuration (upper 32b) i logical buffer index; i = 0 for 1st buffer

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:24

buf_trigger

The real-time event to accept as a trigger when the buffer is configured in a triggered mode

RW

0x00

23:16

buf_event

The event to output when a buffer trigger occurs

RW

0x00

15:8

message_hi

Message filter range upper value

RW

0x00

7:0

message_lo

Message filter range lower value.

RW

0x00

 

TRACE : SMB_REG_INT_CTRL_1

Address offset

0x1 0148

Physical address

0x2301 0148

Instance

TRACE

Description

Interrupt control

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

Read as zero

RO

0x0 0000

11:8

buf_note

Selects the buffer status changes that a debugger is to be notified about using a real-time event or interrupt.

RW

0x0

7:1

Reserved

Read as zero

RO

0x00

0

buf_int_enable

Logical buffer interrupts enable.

RW

0

 

TRACE : SMB_REG_INT_STS_1

Address offset

0x1 014C

Physical address

0x2301 014C

Instance

TRACE

Description

Interrupt status

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:4

Reserved

Read as zero

RO

0x000 0000

3

buf_full

Logical buffer full interrupt

RW

0

2

buf_triggered

Logical buffer triggered interrupt

RW

0

1

buf_block_avail

Logical buffer memory block available to read interrupt.

RW

0

0

buf_not_empty

Logical buffer changed to not empty interrupt.

RW

0

 

TRACE : SMB_REG_BASE_LO_1

Address offset

0x1 0150

Physical address

0x2301 0150

Instance

TRACE

Description

Logical buffer base address (lower 32b)

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

base_addr_lo

Memory base address lower 32b for the message buffers

RW

0x0000 0000

 

TRACE : SMB_REG_BASE_HI_1

Address offset

0x1 0154

Physical address

0x2301 0154

Instance

TRACE

Description

Logical buffer base address (upper 32b)

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

base_addr_hi

Memory base address upper 32b for the message buffers

RW

0x0000 0000

 

TRACE : SMB_REG_LIMIT_1

Address offset

0x1 0158

Physical address

0x2301 0158

Instance

TRACE

Description

Logical buffer limit address

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

limit_addr

Memory limit address configuring the end of a logical buffer

RW

0x0000 0000

 

TRACE : SMB_REG_RD_ADDR_1

Address offset

0x1 015C

Physical address

0x2301 015C

Instance

TRACE

Description

Memory read address

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

read_ptr

Memory read address pointer. Read only if the buffer is enabled in double ended mode

RW

0x0000 0000

 

TRACE : SMB_REG_WR_ADDR_1

Address offset

0x1 0160

Physical address

0x2301 0160

Instance

TRACE

Description

Memory write address

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

write_ptr

Memory write address pointer

RO

0x0000 0000

 

TRACE : SMB_REG_PURGE_1

Address offset

0x1 0164

Physical address

0x2301 0164

Instance

TRACE

Description

Logical buffer purge

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Read as zero

RO

0x0000 0000

0

purge

Applying a 1 causes the packer and input FIFO of the logical buffer to be purged.

WO

0

 

TRACE : SMB_REG_BUFFER_ACTIVE_1

Address offset

0x1 0168

Physical address

0x2301 0168

Instance

TRACE

Description

Logical buffer buffer active

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Read as zero

RO

0x0000 0000

1

read_buffer_active

Read operations from the buffer are active when 1

RO

0

0

write_buffer_active

Write operations from the buffer are active when 1

RO

0

 

TRACE : VCON_ENABLES

Address offset

0x2 0000

Physical address

0x2302 0000

Instance

TRACE

Description

Virtual Console global enables register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

channel_enables

Channel enable. The enable for channel i corresponds to bit 16 + i.

RW

0x0000

15:2

Reserved

Read as zero.

RO

0x0000

1

interrupt_enable

Global interrupt enable

RW

0

0

module_enable

Global module enable

RW

0

 

TRACE : VCON_ENABLES_OR

Address offset

0x2 0004

Physical address

0x2302 0004

Instance

TRACE

Description

Logical OR between the value written and the Virtual Console global enables register.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

vcon_enables_or

 

RW

0x0000 0000

 

TRACE : VCON_ENABLES_AND

Address offset

0x2 0008

Physical address

0x2302 0008

Instance

TRACE

Description

Logical AND between the value written and the Virtual Console group enables register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

vcon_enables_and

 

RW

0x0000 0000

 

TRACE : VCON_INTERRUPT_CONFIG

Address offset

0x2 000C

Physical address

0x2302 000C

Instance

TRACE

Description

Virtual Console interrupt configuration register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Read as Zero

RO

0x0000 0000

1

int_polarity

Interrupt polarity: 0: Active low. 1: Active high. Reset value defined at design time. It should not normally be necessary to change the value of this bit.

RW

0

0

int_type

Interrupt type: 0: Level. 1: Pulse. Reset to 0.

RW

0

 

TRACE : VCON_GLOBAL_STATUS

Address offset

0x2 0010

Physical address

0x2302 0010

Instance

TRACE

Description

Virtual Console global status register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Read as Zero

RO

0x0000 0000

1

rx_not_empty

Channel i upstream buffer not empty flag

RO

0

0

tx_has_space

Channel i downstream buffer has space flag

RO

0

 

TRACE : VCON_GLOBAL_ALLOC

Address offset

0x2 0014

Physical address

0x2302 0014

Instance

TRACE

Description

Virtual Console global allocation register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:6

Reserved

Read as Zero

RO

0x000 0000

5:4

manage_op

Allocation operation: 00 (get): Requests allocation status of global resource 01 (allocate): Allocate global resource to debugger_id if currently unallocated. 10 (release): Deallocate global resource. 11 (force): Allocate global resource to debugger_id even if this resource is already allocated.

RW

0x0

3:0

debugger_id

ID of debugger or other software API. Zero means unallocated.

RW

0x0

 

TRACE : VCON_CHAN0_BURSTDATA

Address offset

0x2 007C

Physical address

0x2302 007C

Instance

TRACE

Description

Virtual Console channel 0 burst data register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

burstdata

Write transactions transfer data to the channel i upstream buffer. Read transactions retrieve data from the channel I downstream buffer.

RW

0x0000 0000

 

TRACE : VCON_CHAN1_BURSTDATA

Address offset

0x2 00FC

Physical address

0x2302 00FC

Instance

TRACE

Description

Virtual Console channel 1 burst data register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

burstdata

Write transactions transfer data to the channel i upstream buffer. Read transactions retrieve data from the channel I downstream buffer.

RW

0x0000 0000

 

TRACE : VCON_CHAN2_BURSTDATA

Address offset

0x2 01DC

Physical address

0x2302 01DC

Instance

TRACE

Description

Virtual Console channel 2 burst data register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

burstdata

Write transactions transfer data to the channel i upstream buffer. Read transactions retrieve data from the channel I downstream buffer.

RW

0x0000 0000

 

TRACE : VCON_CHAN0_CONFIG

Address offset

0x2 0200

Physical address

0x2302 0200

Instance

TRACE

Description

Virtual Console channel 0 configuration register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

tx_timeout

Transmit timeout in cycles

RW

0x0000

15:8

space_threshold

Available space threshold for signalling an interrupt. An interrupt is issued when the available space is greater than this value

RW

0x00

7:4

data_size

The maximum length - in bytes - of the data field in vconsole_data messages. plus one.

RW

0x0

3

Reserved

Read as Zero.

RO

0

2

timestamp_enable

Enable timestamps on vconsole_data messages

RW

0

1:0

flow

The flow assigned to flow_control_report and vconsole_data messages

RW

0x0

 

TRACE : VCON_CHAN0_STATUS

Address offset

0x2 0204

Physical address

0x2302 0204

Instance

TRACE

Description

Virtual Console channel 0 status register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:20

rx_used

Channel i upstream buffer usage in bytes

RO

0x000

19:18

tx_space

Channel i downstream buffer space in bytes

RO

0x0

17:2

Reserved

Read as Zero

RO

0x0000

1

rx_not_empty

Channel i upstream buffer not empty flag

RO

0

0

tx_has_space

Channel i downstream buffer has space flag

RO

0

 

TRACE : VCON_CHAN0_INT_CONFIG

Address offset

0x2 0208

Physical address

0x2302 0208

Instance

TRACE

Description

Virtual Console channel 0 interrupt configuration register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:9

Reserved

Read as Zero

RO

0x00 0000

8

tx_purge

Purge channel i downstream buffer. Read as 1 until purge request is complete

RW

0

7:2

Reserved

Read as Zero

RW

0x00

1

rx_int_enable

Enable interrupt when the channel i upstream buffer state transitions from empty to not empty

RW

0

0

tx_int_enable

Enable interrupt when the channel i downstream buffer space available is greater than space_threshold.

RW

0

 

TRACE : VCON_CHAN0_INT_STATUS

Address offset

0x2 020C

Physical address

0x2302 020C

Instance

TRACE

Description

Virtual Console channel i interrupt status register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Read as Zero

RO

0x0000 0000

1

rx_int_status

Status of channel i RX interrupt (upstream buffer).

RO

0

0

tx_int_status

Status of channel i TX interrupt (downstream buffer).

RO

0

 

TRACE : VCON_CHAN0_ALLOC

Address offset

0x2 0210

Physical address

0x2302 0210

Instance

TRACE

Description

Virtual Console channel 0 allocation register.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:6

Reserved

Read as Zero

RO

0x000 0000

5:4

manage_op

Allocation operation: 00 (get): Requests allocation status of global resource 01 (allocate): Allocate global resource to debugger_id if currently unallocated. 10 (release): Deallocate global resource. 11 (force): Allocate global resource to debugger_id even if this resource is already allocated.

RW

0x0

3:0

debugger_id

ID of debugger or other software API. Zero means unallocated

RW

0x0

 

TRACE : VCON_CHAN0_DATA

Address offset

0x2 0214

Physical address

0x2302 0214

Instance

TRACE

Description

Virtual Console channel 0 data register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

data

Write transactions transfer a single byte to the channel i upstream buffer. Read transactions retrieve a single byte from the channel i downstream buffer.

RW

0x0000 0000

 

TRACE : VCON_CHAN1_CONFIG

Address offset

0x2 0220

Physical address

0x2302 0220

Instance

TRACE

Description

Virtual Console channel 1 configuration register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

tx_timeout

Transmit timeout in cycles

RW

0x0000

15:8

space_threshold

Available space threshold for signalling an interrupt. An interrupt is issued when the available space is greater than this value

RW

0x00

7:4

data_size

The maximum length - in bytes - of the data field in vconsole_data messages. plus one.

RW

0x0

3

Reserved

Read as Zero.

RO

0

2

timestamp_enable

Enable timestamps on vconsole_data messages

RW

0

1:0

flow

The flow assigned to flow_control_report and vconsole_data messages

RW

0x0

 

TRACE : VCON_CHAN1_STATUS

Address offset

0x2 0224

Physical address

0x2302 0224

Instance

TRACE

Description

Virtual Console channel 1 status register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:20

rx_used

Channel i upstream buffer usage in bytes

RO

0x000

19:18

tx_space

Channel i downstream buffer space in bytes

RO

0x0

17:2

Reserved

Read as Zero

RO

0x0000

1

rx_not_empty

Channel i upstream buffer not empty flag

RO

0

0

tx_has_space

Channel i downstream buffer has space flag

RO

0

 

TRACE : VCON_CHAN1_INT_CONFIG

Address offset

0x2 0228

Physical address

0x2302 0228

Instance

TRACE

Description

Virtual Console channel 1 interrupt configuration register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:9

Reserved

Read as Zero

RO

0x00 0000

8

tx_purge

Purge channel i downstream buffer. Read as 1 until purge request is complete

RW

0

7:2

Reserved

Read as Zero

RW

0x00

1

rx_int_enable

Enable interrupt when the channel i upstream buffer state transitions from empty to not empty

RW

0

0

tx_int_enable

Enable interrupt when the channel i downstream buffer space available is greater than space_threshold.

RW

0

 

TRACE : VCON_CHAN1_INT_STATUS

Address offset

0x2 022C

Physical address

0x2302 022C

Instance

TRACE

Description

Virtual Console channel 1 interrupt status register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Read as Zero

RO

0x0000 0000

1

rx_int_status

Status of channel i RX interrupt (upstream buffer).

RO

0

0

tx_int_status

Status of channel i TX interrupt (downstream buffer).

RO

0

 

TRACE : VCON_CHAN1_ALLOC

Address offset

0x2 0230

Physical address

0x2302 0230

Instance

TRACE

Description

Virtual Console channel 1 allocation register.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:6

Reserved

Read as Zero

RO

0x000 0000

5:4

manage_op

Allocation operation: 00 (get): Requests allocation status of global resource 01 (allocate): Allocate global resource to debugger_id if currently unallocated. 10 (release): Deallocate global resource. 11 (force): Allocate global resource to debugger_id even if this resource is already allocated.

RW

0x0

3:0

debugger_id

ID of debugger or other software API. Zero means unallocated

RW

0x0

 

TRACE : VCON_CHAN1_DATA

Address offset

0x2 0234

Physical address

0x2302 0234

Instance

TRACE

Description

Virtual Console channel 1 data register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

data

Write transactions transfer a single byte to the channel i upstream buffer. Read transactions retrieve a single byte from the channel i downstream buffer.

RW

0x0000 0000

 

TRACE : VCON_CHAN2_CONFIG

Address offset

0x2 0240

Physical address

0x2302 0240

Instance

TRACE

Description

Virtual Console channel 2 configuration register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

tx_timeout

Transmit timeout in cycles

RW

0x0000

15:8

space_threshold

Available space threshold for signalling an interrupt. An interrupt is issued when the available space is greater than this value

RW

0x00

7:4

data_size

The maximum length - in bytes - of the data field in vconsole_data messages. plus one.

RW

0x0

3

Reserved

Read as Zero.

RO

0

2

timestamp_enable

Enable timestamps on vconsole_data messages

RW

0

1:0

flow

The flow assigned to flow_control_report and vconsole_data messages

RW

0x0

 

TRACE : VCON_CHAN2_STATUS

Address offset

0x2 0244

Physical address

0x2302 0244

Instance

TRACE

Description

Virtual Console channel 2 status register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:20

rx_used

Channel i upstream buffer usage in bytes

RO

0x000

19:18

tx_space

Channel i downstream buffer space in bytes

RO

0x0

17:2

Reserved

Read as Zero

RO

0x0000

1

rx_not_empty

Channel i upstream buffer not empty flag

RO

0

0

tx_has_space

Channel i downstream buffer has space flag

RO

0

 

TRACE : VCON_CHAN2_INT_CONFIG

Address offset

0x2 0248

Physical address

0x2302 0248

Instance

TRACE

Description

Virtual Console channel 2 interrupt configuration register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:9

Reserved

Read as Zero

RO

0x00 0000

8

tx_purge

Purge channel i downstream buffer. Read as 1 until purge request is complete

RW

0

7:2

Reserved

Read as Zero

RW

0x00

1

rx_int_enable

Enable interrupt when the channel i upstream buffer state transitions from empty to not empty

RW

0

0

tx_int_enable

Enable interrupt when the channel i downstream buffer space available is greater than space_threshold.

RW

0

 

TRACE : VCON_CHAN2_INT_STATUS

Address offset

0x2 024C

Physical address

0x2302 024C

Instance

TRACE

Description

Virtual Console channel 2 interrupt status register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Read as Zero

RO

0x0000 0000

1

rx_int_status

Status of channel i RX interrupt (upstream buffer).

RO

0

0

tx_int_status

Status of channel i TX interrupt (downstream buffer).

RO

0

 

TRACE : VCON_CHAN2_ALLOC

Address offset

0x2 0250

Physical address

0x2302 0250

Instance

TRACE

Description

Virtual Console channel 2 allocation register.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:6

Reserved

Read as Zero

RO

0x000 0000

5:4

manage_op

Allocation operation: 00 (get): Requests allocation status of global resource 01 (allocate): Allocate global resource to debugger_id if currently unallocated. 10 (release): Deallocate global resource. 11 (force): Allocate global resource to debugger_id even if this resource is already allocated.

RW

0x0

3:0

debugger_id

ID of debugger or other software API. Zero means unallocated

RW

0x0

 

TRACE : VCON_CHAN2_DATA

Address offset

0x2 0254

Physical address

0x2302 0254

Instance

TRACE

Description

Virtual Console channel 2 data register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

data

Write transactions transfer a single byte to the channel i upstream buffer. Read transactions retrieve a single byte from the channel i downstream buffer.

RW

0x0000 0000

 

TRACE : VCON_CHAN3_CONFIG

Address offset

0x2 0260

Physical address

0x2302 0260

Instance

TRACE

Description

Virtual Console channel 3 configuration register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

tx_timeout

Transmit timeout in cycles

RW

0x0000

15:8

space_threshold

Available space threshold for signalling an interrupt. An interrupt is issued when the available space is greater than this value

RW

0x00

7:4

data_size

The maximum length - in bytes - of the data field in vconsole_data messages. plus one.

RW

0x0

3

Reserved

Read as Zero.

RO

0

2

timestamp_enable

Enable timestamps on vconsole_data messages

RW

0

1:0

flow

The flow assigned to flow_control_report and vconsole_data messages

RW

0x0

 

TRACE : VCON_CHAN3_STATUS

Address offset

0x2 0264

Physical address

0x2302 0264

Instance

TRACE

Description

Virtual Console channel 3 status register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:20

rx_used

Channel i upstream buffer usage in bytes

RO

0x000

19:18

tx_space

Channel i downstream buffer space in bytes

RO

0x0

17:2

Reserved

Read as Zero

RO

0x0000

1

rx_not_empty

Channel i upstream buffer not empty flag

RO

0

0

tx_has_space

Channel i downstream buffer has space flag

RO

0

 

TRACE : VCON_CHAN3_INT_CONFIG

Address offset

0x2 0268

Physical address

0x2302 0268

Instance

TRACE

Description

Virtual Console channel 3 interrupt configuration register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:9

Reserved

Read as Zero

RO

0x00 0000

8

tx_purge

Purge channel i downstream buffer. Read as 1 until purge request is complete

RW

0

7:2

Reserved

Read as Zero

RW

0x00

1

rx_int_enable

Enable interrupt when the channel i upstream buffer state transitions from empty to not empty

RW

0

0

tx_int_enable

Enable interrupt when the channel i downstream buffer space available is greater than space_threshold.

RW

0

 

TRACE : VCON_CHAN3_INT_STATUS

Address offset

0x2 026C

Physical address

0x2302 026C

Instance

TRACE

Description

Virtual Console channel 3 interrupt status register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Read as Zero

RO

0x0000 0000

1

rx_int_status

Status of channel i RX interrupt (upstream buffer).

RO

0

0

tx_int_status

Status of channel i TX interrupt (downstream buffer).

RO

0

 

TRACE : VCON_CHAN3_ALLOC

Address offset

0x2 0270

Physical address

0x2302 0270

Instance

TRACE

Description

Virtual Console channel 3 allocation register.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:6

Reserved

Read as Zero

RO

0x000 0000

5:4

manage_op

Allocation operation: 00 (get): Requests allocation status of global resource 01 (allocate): Allocate global resource to debugger_id if currently unallocated. 10 (release): Deallocate global resource. 11 (force): Allocate global resource to debugger_id even if this resource is already allocated.

RW

0x0

3:0

debugger_id

ID of debugger or other software API. Zero means unallocated

RW

0x0

 

TRACE : VCON_CHAN3_DATA

Address offset

0x2 0274

Physical address

0x2302 0274

Instance

TRACE

Description

Virtual Console channel 3 data register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

data

Write transactions transfer a single byte to the channel i upstream buffer. Read transactions retrieve a single byte from the channel i downstream buffer.

RW

0x0000 0000

 

TRACE : VCON_CHAN4_CONFIG

Address offset

0x2 0280

Physical address

0x2302 0280

Instance

TRACE

Description

Virtual Console channel 4 configuration register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

tx_timeout

Transmit timeout in cycles

RW

0x0000

15:8

space_threshold

Available space threshold for signalling an interrupt. An interrupt is issued when the available space is greater than this value

RW

0x00

7:4

data_size

The maximum length - in bytes - of the data field in vconsole_data messages. plus one.

RW

0x0

3

Reserved

Read as Zero.

RO

0

2

timestamp_enable

Enable timestamps on vconsole_data messages

RW

0

1:0

flow

The flow assigned to flow_control_report and vconsole_data messages

RW

0x0

 

TRACE : VCON_CHAN4_STATUS

Address offset

0x2 0284

Physical address

0x2302 0284

Instance

TRACE

Description

Virtual Console channel 4 status register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:20

rx_used

Channel i upstream buffer usage in bytes

RO

0x000

19:18

tx_space

Channel i downstream buffer space in bytes

RO

0x0

17:2

Reserved

Read as Zero

RO

0x0000

1

rx_not_empty

Channel i upstream buffer not empty flag

RO

0

0

tx_has_space

Channel i downstream buffer has space flag

RO

0

 

TRACE : VCON_CHAN4_INT_CONFIG

Address offset

0x2 0288

Physical address

0x2302 0288

Instance

TRACE

Description

Virtual Console channel 4 interrupt configuration register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:9

Reserved

Read as Zero

RO

0x00 0000

8

tx_purge

Purge channel i downstream buffer. Read as 1 until purge request is complete

RW

0

7:2

Reserved

Read as Zero

RW

0x00

1

rx_int_enable

Enable interrupt when the channel i upstream buffer state transitions from empty to not empty

RW

0

0

tx_int_enable

Enable interrupt when the channel i downstream buffer space available is greater than space_threshold.

RW

0

 

TRACE : VCON_CHAN4_INT_STATUS

Address offset

0x2 028C

Physical address

0x2302 028C

Instance

TRACE

Description

Virtual Console channel 4 interrupt status register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Read as Zero

RO

0x0000 0000

1

rx_int_status

Status of channel i RX interrupt (upstream buffer).

RO

0

0

tx_int_status

Status of channel i TX interrupt (downstream buffer).

RO

0

 

TRACE : VCON_CHAN4_ALLOC

Address offset

0x2 0290

Physical address

0x2302 0290

Instance

TRACE

Description

Virtual Console channel 4 allocation register.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:6

Reserved

Read as Zero

RO

0x000 0000

5:4

manage_op

Allocation operation: 00 (get): Requests allocation status of global resource 01 (allocate): Allocate global resource to debugger_id if currently unallocated. 10 (release): Deallocate global resource. 11 (force): Allocate global resource to debugger_id even if this resource is already allocated.

RW

0x0

3:0

debugger_id

ID of debugger or other software API. Zero means unallocated

RW

0x0

 

TRACE : VCON_CHAN4_DATA

Address offset

0x2 0294

Physical address

0x2302 0294

Instance

TRACE

Description

Virtual Console channel 4 data register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

data

Write transactions transfer a single byte to the channel i upstream buffer. Read transactions retrieve a single byte from the channel i downstream buffer.

RW

0x0000 0000

 

TRACE : VCON_CHAN3_BURSTDATA

Address offset

0x2 02BC

Physical address

0x2302 02BC

Instance

TRACE

Description

Virtual Console channel 3 burst data register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

burstdata

Write transactions transfer data to the channel i upstream buffer. Read transactions retrieve data from the channel I downstream buffer.

RW

0x0000 0000

 

TRACE : VCON_CHAN4_BURSTDATA

Address offset

0x2 039C

Physical address

0x2302 039C

Instance

TRACE

Description

Virtual Console channel 4 burst data register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

burstdata

Write transactions transfer data to the channel i upstream buffer. Read transactions retrieve data from the channel I downstream buffer.

RW

0x0000 0000

 

TRACE has no common memories.