PolarFire SoC SEV Kit Notes ----------------------------- Original Rev. 1-Aug-2023 Current Rev. 8-Spt-2023 This demo board uses a MPFS250-1FCG1152I part. Bank 1 and Bank 9 use separate power supplies. Page 5 is Bank 1 and may have a WIFI think with a number ATWIlC3000-MR110CA_NL and a 32.768 kHz oscillator Page 6 is Bank 9 which is I think the FMC connector on page 7 what is HPC ? page 8 The Clock input to the SGMII section is from some fancy dual frequency clock: U13, it has 2 power pins both given 3V3, it looks like it can make either 100 MHz or 125 MHz, this oscillator feeds just the MSS SGMII Ref Clk differential input pins V3 and W3, this oscillator is a DSC2033FI2-F0012. They have a separate 125 MHz oscillator DSC1001DL5-125.0000 feeding their VSC8662XIC. They have a DSC1103BI2-148.5000 oscillator feeding one of the Reference Clock inputs of the High-Speed Serial Transceivers. I think this is for HDMI video. The High-Speed Serial Transciver for their PCIE connection uses a DSC2033FI2-F0044 oscillator. Page 12 is Bank 7 and I think has a 50 MHz Oscillator DSC1001DL5-050.0000/DSC1001DI5-050.0000 Alternate = ECS-2520S25-500-FN-TR which feeds pin T3 GPIO143PB7/CLKIN_W_4/CCC_NW_CLKIN_W_4 It looks like the small CPU GPIO Bank 4 is used for some SD Memory stuff. It is 1V8 or 3V3 It looks like the small CPU Bank 2 is used for USB plus other stuff e.g. QSPI It is 3V3 The USB Phy is a USB3340-EZK-TR USB3340_QFN32 on page 22. There is CAN Bus and mikroBUS on page 23 what ever that is Bank 3 at 3V3 is on page 24 with JTAG and SPI Memory. SPI Memory is MT25QL01GBBB8ESF-0SIT Page 25 may start their fancy connection to the demo system involving U22 a M2S025-VFG256Q309 Page 32 is Ground and No-Connects to the main FPGA/CPU Page 33 shows separate MIC27600YJL-TR supplies for Bank 1 and Bank 9. Page 34 shows separate VDDIx and VDDAUXx capacitors for Bank 1 and Bank 9. Page 38 is common 1V8 power for Bank 0 and Bank 8 as would expect for their wide DDR Memory for the FPGA. Page 39 is the commpletely separate power supplies for Bank 1 and Bank 9 both set to default to 3V3 but there is completely separate output voltage controls. Power Supply Connections: ------------------------- This kit uses the MPFS250-1FCG1152I part. I want to understand the power supply connections to the noise sensitive buses on this part, e.g. do the VDD25 and VDDA25 loads share the same supply without isolation ? Connections to the FPGA/CPU from page 31: VDD25 is pins: AC16, AC24, M15, M25, U18 supplied from net 2P5V through a 10 mOhm resistor and these pins are net VDD25 VDD18 is pins: AA18, AA22, AB17, AB19, AB21, AB23, AC18 supplied directly by net 1P8V and these pins are that net VDDA25 is pins: P25, T25, V25, Y25 supplied from net 2P5V through a 10 mOhm resistor and these pins are net VDDA25 XCVR_VREF is pins: P26, M26 and is tied to Gnd through a 10k Ohm resistor and bypassed to Gnd with two 100 nFd 16 V caps. VDD_XCVR_CLK is pins: AB25, N25, U25, W25 supplied directly by net 2P5V and these pins are that net VDDA is 27 pins e.g.: AA29, AB27, AC29, ... W29, Y27, Y32 it is supplied directly by net VDDA and these pins are that net Power Supply Bus Nets from page 40: Net 1P8V is the 1.80 V output of a MIC27600YJL switching regulator U62 Net 2P5V is the 2.50 V output of a MIC69502 linear regulator U66 that is powered by 5P0V and provides: VDD25, VDDA25, and VDD_XCVR_CLK Net VDDA is the 1.05 V output of a MIC69502 linear regulator U65 on page 40 that is powered by 5P0V Net VDD25 is the FPGA PLL & PNVM 2V5 supply Net VDDA25 is the XCVR PLL 2V5 supply Bypass Capacitors Page 34: Net VDD25 1x 47 uFd, 3x 100 nFd, 1x 10 nFd, 1x 1 nFd not loaded: 1x 10 uFd, 1x 1 uFd Net VDD18 2x 47 uFd, 1x 100 nFd, 1x 10 nFd not loaded: 1x 22 uFd, 1x 10 uFd, 11x 100 nFd Net 2P5V 1x 10 uFd, 2x 100 nFd VDDSREF not loaded: 1x 47 uFd, 1x 10 uFd, 4x 100 nFd Net VDDA 2x 47 uFd, 6x 100 nFd, 1x 10 nFd, 3x 4.7 nFd not loaded: 1x 10 uFd, 1x 1 uFd, not loaded: 30x 100 nFd, 3x 10 nFd, 3x 4,7 nFd Net VDDA25 1x 47 uFd, 2x 100 nFd, 2x 1 nFd not loaded: 1x 22 uFd, 1x 10 uFd Summary: - The FPGA PLLs and PNVM, and the XCVR PLLs and Clock Buffers are all supplied by the same 2.50 Volt supply which comes from a MIC69502 linear regulator. There is no noise filter separation of these 3 loads on this single supply. - The FPGA VDD18 Program and HSIO Aux is supplied by a MIC27600YJL switching regulator. - The XCVR VDDA Tx & Rx supply comes from MIC69502 linear regulator. - The MIC69502 is a low drop out 5 Amp max output linear regulator. FPGA DDR4 Memory Connection 8-Sept-2023: ------------------------------------------ Looking at the xlsx pin table for the MPFS250T-FCG1152 it has just a Normal Migratable version of the DDR4 pin mapping that has either a NORTH_NE or NORTH_NW "anchor". From the schematic of this demo board it is clear that they use the NW anchor on this demo board. Their schematic nets like: CLK0 P and N, CKE0, CS0_N, and ODT0 go to the pins on the FPGA as indicated in the xlsx pin table - but the pin table uses different names for these pins: CK, CK_N, CKE, CS_N, ODT. Note that on this Demo Board that they do freely swap data lines within a byte of 8 lines. On the schematic for the Deom Brd in some auxiliary lables they do give some pins names such as: CLK1 P & N, CKE1, CS1_N, ODT1 but these are pins that are NOT used at all with the DDR4 on this board, they make connections to some HDMI stuff, and these pins with "1" auxiliary labels are not in the xlsx pin table for the NW anchor. They are pins that are used for DDR4 if you use the NE anchor.