Clock Consumers on the DK Board ----------------------------------- Initial Rev. 26-APR-2023 Current Rev. 28-Apr-2023 The intent of this file is to list all of the items on the DK board that require a clock and what the source of that clock is. The plan is to use the minimum number of crystal oscillator practical and use the Clock Conditioning Circuits (PLLs and such) in the FPGA to make the other required clock frequencies. The following crystal oscillators are used: 50 MHz, 52 MHz, 125 MHz ?, and a spare First list all of the clock consumers that are outside of the PHFS250T FPGA/CPU: 1. AD9546 Timing Generator: ----------------------------- This part requires a 52 MHz clock. See pages: 9, 39, 40, 49 for details about the required clock. Clock Inputs XOA pin 42 XOB pin 43. The differential clock inputs are DC self biased so the external clock source must be AC coupled to this part. The self bias common mode voltage is about 0.75 Volts. The minimum clock signal is 250 mVpp The recomended clock signal is 800 mVpp Single Ended HI is 0.9 V minimum Single Ended LOW is 0.5 V Maximum The instantanious value of the clock signal must must never be over: 1.2 V 2. TI CC2564C Bluetooth Transceiver: -------------------------------------- This Bluetooth Transceiver requires two clocks: a 32.768 kHz +- 250 ppm "Slow Clock" and a 26.000 MHz +- 20 ppm "Fast Clock". 50 MHz divided by 1526 is 32.765400 kHz this is 2.600 kHz low, i.e. 79 ppm low 52 MHz divided by 1587 is 32.766226 kHz this is 1.774 kHz low, i.e. 54 ppm low The Slow Clk input pin is A25 and this clock source should be a normal 1V8 logic signal that is DC coupled to pin A25. The Slow Clk voltage limits are: Low < 0.35 x VDD_IO High > 0.65 x VDD_IO The Fast Clk input pins are: FREFP pin B4 and FREFM pin A4. The Fast Clk can be supplied as a square wave but the high frequency components must be removed so that it is basically a sinusoidal waveform before it is passed to the FREF input pins. The 26 MHz square wave should be RC filtered until its is a sine wave with a PP amplitude between 400 mV and 1.6 V. Connect this signal to the FREFP pin B4 and connect VDD_IO to the FREFM pin A4. This DC coupled "sine" wave will be centered around the 0.9 Volt center of the DC coupled 1V8 logic clock signal. The input circuit needs the DC average of this cloks signal to be in the range: 0.2 Volts to 1.4 Volts. See pages: 14, 15, 21, 22, 23 of the CC256x datasheet. See pages: 16, 17, 24, 25, 26 of the CC2564C datasheet. 3. USB3340 USB Phy Chip: -------------------------- The USB3340 chip can be used with an external 26 MHz clock source by connecting the external clock to the REFCLK/X1 pin, and the XO pin should be left floating. XO is pin 25, REFCLK/X1 is pin 26. See pages: 6, 8, 22, 24, 25, and 73 of the USB3340 datasheet. 4. ADIN2111 Ethernet Phy and Switch: -------------------------------------- The ADIN2111 requires a 25 MHz clock +- 50 ppm which can be supplied by an external source. The clock pins on the ADIN2111 are: XTAL_1/CLK_IN pin 23 and XTAL_0 pin 24. The external 25 MHz clock signal can be a square wave with an amplitude between 800 mVpp and 2.5 Vpp. A 1V8 logic clock signal should be AC coupled with a 1 nFd capacitor to the XTAL_1/CLK_IN pin and the XTAL_0 pin should be left open. The datasheet says that the external clock can be a "sine or (filtered) square wave" and it shows a 1 nFd series coupling capacitor. The datasheet shows a square wave source but does not show any filtering. If the source is over 2.5 Vpp it shows the use of a capacitor voltage divider. See pages: 3, 8, and 34 of the ADIN2111 datasheet. 5. TDC7200 TDC Chip: ---------------------- The TDC7200 needs a 3V3 digital clock signal on its CLOCK pin - pin number 5. The frequency of this clock should be: 1 MHz min, 8 MHz typ, and 16 MHz max. A very low frequency clock results is a poor standard deviation is the measured time values. For any clock frequency in the range of 12 to 16 MHz the standard deviation is basically the same. TI says, "using a reference clock of 16 MHz is recommended for optimal performance". 50 MHz divided by 4 is 12.5 MHz. 52 MHz divided by 4 is 13 MHz. See pages: 4, 5, and 13 of the TDC7200 datasheet. 6. TLV320ADC6140 BB Audio ADC: -------------------------------- The clock signals and data from this ADC can be handled in a number of ways. The most rational setup for the DK application is probably to send a clock signal to it on its GPIO1 pin and get the serial data back from it with the BCLK signal, which tells the FPGA when to ingest each bit in the serial bit stream and the FSYNC signal, which tells the FPGA when each frame of ADC samples begins. Operation in this mode is described in the document, "Configuring and Operating TLV320ADCx140 as Audio Bus Master". Section 2 of this document shows the details. The clock sent to the TLV320ADC6140 is called the Master Clock (MCLK) and is sent to its GPIO1 pin (pin 20) as a 1V8 digital square wave signal. The required frequency is typically in the range of 12 to 16 MHz.