Clock Consumers  on the  DK Board
        -----------------------------------


                                      Initial Rev.  26-APR-2023
                                      Current Rev.   4-June-2025


The intent of this file is to list all of the items on the
DK board that require a clock and what the source of that
clock is.

The plan is to use the minimum number of individual crystal
oscillator components as practical and  use the Clock
Conditioning Circuits  (PLLs and such)  in the FPGA to
make most of the required external clock frequencies.

The following crystal oscillators are used:

   125 MHz  Y1501  to startup the CPU and FPGA
            shown in DK Drawing #24

     Spare  Y1502  with a good connection into
            the FPGA  shown in DK Drawing #24

    52 MHz  Y901  the "System Clock" for the AD9546
            Timing Generator  shown in DK Drawing #50


Now list all of the clock consumers that are  outside  of
the MPFS250T-1FCG1152I  FPGA/CPU:


 1.  AD9546  Timing Generator  U901:
 -----------------------------------

     This part requires a "System Clock" in the range
     of 52 MHz.  Using 52 MHz allows convenient M/N values
     in the PLL feedback networks inside of this timing
     generator.  We use a plain crystal, Y901, outside of
     the timing generator and use its internal oscillator
     circuit to make this 52 MHz clock.  The internal
     oscillator circuit is setup for:  frequency doubler
     and uses compensation method #3.



 2.  AD9083  PMT ADC  U601:
 --------------------------

     The AD9083 PMT ADC requires a very stable 125 MHz clock
     with a known latency for its  ADC_Clk  input  and a
     100 Hz clock that is locked to the above for its
     Sys_Ref input.  Both of these clocks are directly
     provided by the AD9546 Timing Generator

 

 3.  USB3340  USB Phy Chip  U1051:
 ---------------------------------

     The  USB3340  USB Phy chip can be used with an external
     24 MHz clock by connecting the external clock to its
     REFCLK/X1  pin  and  floating the its  XO  pin.

     See pages:  6, 8, 22, 24, 25, and 73  of the USB3340
     datasheet.  They want this external clock AC coupled
     and DC centered wrt the 1V8 bus for input to the
     REFCLK/X1 pin.

     This 24 MHz clock is generated from 125 MHz by a
     "clock conditioner circuit" inside the FPGA and
     comes from a  Bank #9  1V8 I/O pin  B17  GPIO35PB9.
     See DK Drawings  #77,  #18  and  #54.



 4.  USB2412  USB Hub Chip  U1052:
 ---------------------------------

     The  USB2412  USB Hub chip can be used with an external
     24 MHz clock by connecting the external clock to its
     Clock_In  pin  and  floating its  Xtal_Out  pin.

     See pages:  11 and 21  of the USB2412 datasheet.  They
     want this external clock attenuated to the 1.2 Volt level,
     AC coupled and DC centered wrt the 1V2 bus for input to
     the Clock_In pin.

     This 24 MHz clock is generated from 125 MHz by a
     "clock conditioner circuit" inside the FPGA and
     comes from a  Bank #9  1V8 I/O pin  B17  GPIO35PB9.
     See DK Drawings  #77,  #78  and  #54.



 5.  TLV320ADC6140  BB Audio ADC  U1101:
 ---------------------------------------

     The TLV320ADC6140  BB Audio ADC can receive its "Master
     Clock" signal on its GPIO1 pin.  In the P-ONE application
     of this ADC  a clock of 24 MHz is appropriate.

     Digitized data is sent to the FPGA as a serial stream with
     the  BCLK  signal telling the FPGA when to ingest each bit
     in the SDOUT serial bit stream  and  the  FSYNC  signal
     telling the FPGA when each frame of ADC samples begins.
     Operation in this mode is described in the document,
     "Configuring and Operating TLV320ADCx140 as Audio Bus
     Master".  Section 2 of this document shows the details.

     The clock sent to the TLV320ADC6140 is called the
     Master Clock  (MCLK)  and is sent to its  GPIO1  pin
     (pin 20)  as a 1V8 digital square wave signal.

     This 24 MHz clock is generated from 125 MHz by a
     "clock conditioner circuit" inside the FPGA and
     comes from a  Bank #9  1V8 I/O pin  B21  GPIO49NB9.
     See DK Drawings  #37  and  #54.