FPGA/CPU Clock Notes ----------------------- Initial Rev 25-July-2023 Current Rev 28-July-2023 A main concern is to make certain that we connect the external clocks to the FPGA/CPU on pins that allow optimum connection of the external clocks to the resources inside the chip. - Pg 4 Preferred Clock Inputs—have access to the global clock network and/or CCCs through low-latency paths. Preferred clock input pins are recommended for connecting external clocks to the clock inputs of Phase-Locked Loops (PLLs), Delay-Locked Loops (DLLs), and fabric logic. While it is possible to use regular I/Os as clock inputs, doing so introduces high latency on the path. Preferred Clock Outputs—are used to connect PLL clock outputs to external components. Preferred clockoutput pins have low-latency routing from the PLL clock outputs. Both the device families offer 24 full-chip or 48 half-chip global signals, up to 101 regional signals, and six high-speed I/O signals per I/O bank - Pg 5 The PolarFire SoC FPGA MSS has a dedicated clock controller for generating clocks to all the MSS sub-blocks for correct operation and synchronous communication with the user logic in the FPGA fabric. - Pg 6 Global Clocks The global clock network can be driven by any of the following: Preferred clock inputs (CLKIN_z_w) On-chip oscillators CCC (PLL/DLL) Fabric routed signals Clock dividers NGMUXs Transceiver interface clocks Only one global clock is supported per transceiver quad. CCC == Clock Conditioning Circuit NGMUX == No-Glitch Clock Multiplexer ICB == Interface Clock Block MSS == Microprocessor Sub-System i.e. the CPU GB == Global Buffer GCLK == Global Clock CLKINT == ICB == RGB == Row Global Buffer RGCLK == Tow Global Clock There are 48 GBs - 24 GBs distribute clocks to the left half of the fabric and the remaining 24 GBs distribute clocks to the right half through vertical clock stripes Each GB drives an independent half-chip global clock (GCLK). Two GBs, one from each half, are instantiated by the Libero SoC to distribute a clock to the entire FPGA fabric. A design can have a maximum of 24 full-chip global signals or 48 half-chip global signals. Up to 24 fabric routed signals can drive the half-chip globals. Clocks driven from regular I/Os, internally generated clocks, and high fan-out signals, such as resets can be routed to GBs using a CLKINT macro. ---> For PolarFire SoC FPGAs, there is no feeder line from CCC_NW going to west ICB. Instead the CCC_NW can generate reference clock to MSS - Pg 9 Regional Clock Networks - Pg 12 High-Speed I/O Clock Networks High-speed I/O clock networks are low-skew high-speed clocks distributed along the edge of the device to service the I/Os. High-speed I/O networks are used to clock data in and out of the I/O logic when implementing the high-speed I/O interfaces. There are no high-speed I/O clock networks located on the east side of the FPGA fabric. I assume that this is because the East side is the side with the High-Speed Serial Transceivers. Each I/O bank has six high-speed I/O clocks. High-speed I/O clocks from adjacent banks on the same edge can be bridged to build large I/O interfaces. High-speed I/O clock networks can be driven from I/Os or CCCs. I assume that they mean that a High-Speed I/O Clock Network can be driven from a Prefered Clock Input pin. The high-speed I/O clocks can feed reference clock inputs of adjacent CCCs through hardwired connections For PolarFire SoC FPGAs, there is no high-speed I/O clock input going to CCC_NW from west edge and no feeder line from CCC_NW to high-speed I/O clock network on west edge (as highlighted in figure 2-7). - Pg 13 Preferred Clock Inputs CLKIN_z_w and CCC_xy_CLKIN_z_w represents a preferred clock input that drives a global clock network directly, and an input to one of the CCCs respectively. xy represents the CCC location: NE, SE, SW, or NW z represents location of the Preferred clock input: N, W, or S w represents the preferred clock input number: 0 to 15 - Pg 15 Interface Clock Block Interface Clock Block (ICB) multiplexes clock inputs from various clock sources (CCCs, preferred clock inputs, High-Speed I/O network, Oscillators, and FPGA fabric) and provides an entry into the global clock network. The east and west edges of the device have one ICB each. The north and south edges of the core have two ICBs each. Each ICB contains four clock dividers, two no-glitch clock multiplexers (NGMUXs), 12 clock gating circuits, and clock routing multiplexers to route clocks. Each ICB has two ICB_INT cells and 12 ICB_CLKINT cells. The ICB_INT cell sare needed to route clocks from fabric to ICB. ICB_CLKINT cells are needed to route clocks from ICB to global buffers. - Pg 25 Clock Conditioning Circuits The reference inputs to a CCC are the following: Preferred Clock Inputs High-Speed I/O Clocks Fabric Routed Clocks Transceiver Reference Clocks <--- to CCC_SE only Transceiver Interface Clocks <--- to CCC_SE and CCC_NE only For PolarFire SoC FPGAs, there is no preferred clock input going to CCC_NW from west edge and there is no feeder line from CCC_NW going to west ICB. Instead the CCC_NW can generate reference clock to MSS. For PolarFire SoC FPGAs, there is no high-speed I/O clock input going to CCC_NW from west edge and no feeder line from CCC_NW to high-speed I/O clock network on west edge. My translation of all of this - To get a reference clock to the CCC_NW it needs to come from the Fabric (not interested in that) or from the North edge. - Pg 59 MSS Clock Controller aka CPU Clock Controller The PolarFire SoC MSS has a dedicated clock controller for generating clocks to all the MSS sub-blocks for correct operation and synchronous communication with the user logic in the FPGA fabric. The MSS clock controller includes dedicated PLLs (MPLLs, DDR PLL, and SGMII PLL) for MSS clocking. The base clock for these PLLs comes either from: a dedicated I/O (REFCLK) from Bank 5 or one of the NW PLL outputs OUT2 or OUT3. This dedicated I/O can be connected to a clock source, which can supply 100 MHz or 125 MHz clock. That is what MicroChip says about the CPU reference clock. To me this means that the only two possible reference source for the CPU Clock Controller are: The Bank 5 SGMII reference clock input in pins, i.e. pin R11 name MSS_REFCLK_IN_N pin P11 name MSS_REFCLK_IN_P or Output_2 or Output_3 from the NW PLL In the following note that only Banks 0 and 8 have a Prefered Clock Input that connects to CCC_NW. Pins on the MPFS250T FCVG784 that are Clock connections ------------------------------------------------------------- Pin Number Pin Name PLL Ref Clk 0 PLL Ref Clk 1 PLL FB Clk DLL Ref Clk DLL FB Clk ------ -------------------- ------------- ------------- ---------- ----------- ---------- Bank 3 is the system controller I/O and has no Clock pins. Bank 1 D9 GPIO0PB1/CLKIN_S_4 B7 GPIO1PB1/CLKIN_S_5 A8 GPIO3PB1/CLKIN_S_6 B10 GPIO5PB1/CLKIN_S_7 G12 GPIO9PB1/CLKIN_S_8/CCC_SE_CLKIN_S_8 PLL0_SE/PLL1_SE PLL0_SE/PLL1_SE --- --- --- J14 GPIO11PB1/CLKIN_S_9/CCC_SE_CLKIN_S_9 PLL0_SE/PLL1_SE PLL0_SE/PLL1_SE --- --- --- C14 GPIO15PB1/CCC_SE_CLKIN_S_10 --- --- PLL0_SE/PLL1_SE DLL0_SE/DLL1_SE DLL0_SE/DLL1_SE A12 GPIO17PB1/CCC_SE_CLKIN_S_11 --- --- PLL0_SE/PLL1_SE DLL0_SE/DLL1_SE DLL0_SE/DLL1_SE Bank 9 C27 GPIO56PB9/DQS/CCC_SE_PLL0_OUT0 A27 GPIO57PB9/CLKIN_S_12/CCC_SE_CLKIN_S_12/CCC_SE_PLL0_OUT0 PLL0_SE/PLL1_SE PLL0_SE/PLL1_SE -- -- -- D25 GPIO58PB9/CCC_SE_PLL0_OUT1 B28 GPIO59PB9/CLKIN_S_13/CCC_SE_CLKIN_S_13 PLL0_SE/PLL1_SE PLL0_SE/PLL1_SE -- -- -- F22 GPIO62PB9/DQS/CCC_SE_PLL1_OUT0 E21 GPIO63PB9/CCC_SE_CLKIN_S_14/CCC_SE_PLL1_OUT0 -- -- PLL0_SE/PLL1_SE DLL0_SE/DLL1_SE DLL0_SE/DLL1_SE H22 GPIO64PB9/CCC_SE_PLL1_OUT1 F23 GPIO65PB9/CCC_SE_CLKIN_S_15 -- -- PLL0_SE/PLL1_SE DLL0_SE/DLL1_SE DLL0_SE/DLL1_SE Bank 0 AC27 HSIO66PB0/CCC_NE_CLKIN_N_11 -- -- PLL0_NE/PLL1_NE DLL0_NE/DLL1_NE DLL0_NE/DLL1_NE AD28 HSIO67PB0/CCC_NE_PLL0_OUT1 AB25 HSIO68PB0/CCC_NE_CLKIN_N_10/CCC_NE_PLL0_OUT0 -- -- PLL0_NE/PLL1_NE DLL0_NE/DLL1_NE DLL0_NE/DLL1_NE AE27 HSIO69PB0/DQS/CCC_NE_PLL0_OUT0 AA23 HSIO72PB0/CLKIN_N_9/CCC_NE_CLKIN_N_9 PLL0_NE/PLL1_NE PLL0_NE/PLL1_NE -- -- -- W22 HSIO73PB0/CCC_NE_PLL1_OUT1 AD23 HSIO74PB0/CLKIN_N_8/CCC_NE_CLKIN_N_8/CCC_NE_PLL1_OUT0 PLL0_NE/PLL1_NE PLL0_NE/PLL1_NE -- -- -- AD21 HSIO75PB0/DQS/CCC_NE_PLL1_OUT0 AE26 HSIO78PB0/CLKIN_N_7 AF24 HSIO80PB0/CLKIN_N_6 AH24 HSIO84PB0/CLKIN_N_5 AH22 HSIO86PB0/CLKIN_N_4 AF20 HSIO90PB0/CLKIN_N_3/CCC_NW_CLKIN_N_3 -- -- PLL0_NW/PLL1_NW DLL0_NW/DLL1_NW DLL0_NW/DLL1_NW AF19 HSIO92PB0/CLKIN_N_2/CCC_NW_CLKIN_N_2 -- -- PLL0_NW/PLL1_NW DLL0_NW/DLL1_NW DLL0_NW/DLL1_NW AH18 HSIO94PB0/CCC_NW_CLKIN_N_1 PLL0_NW/PLL1_NW PLL0_NW/PLL1_NW -- -- -- AE18 HSIO95PB0/CCC_NW_CLKIN_N_0 PLL0_NW/PLL1_NW PLL0_NW/PLL1_NW -- -- -- Bank 8 AB12 HSIO127PB8/CCC_NW_PLL0_OUT1 AB14 HSIO128PB8/CCC_NW_PLL0_OUT0 Y13 HSIO129PB8/DQS/CCC_NW_PLL0_OUT0 AD9 HSIO132PB8/CCC_NW_CLKIN_N_15 -- -- PLL0_NW/PLL1_NW DLL0_NW/DLL1_NW DLL0_NW/DLL1_NW AH7 HSIO133PB8/CCC_NW_PLL1_OUT1 AF8 HSIO134PB8/CCC_NW_CLKIN_N_14/CCC_NW_PLL1_OUT0 -- -- PLL0_NW/PLL1_NW DLL0_NW/DLL1_NW DLL0_NW/DLL1_NW AG6 HSIO135PB8/DQS/CCC_NW_PLL1_OUT0 AF7 HSIO136PB8/CLKIN_N_13/CCC_NW_CLKIN_N_13 PLL0_NW/PLL1_NW PLL0_NW/PLL1_NW -- -- -- AE8 HSIO137PB8/CLKIN_N_12/CCC_NW_CLKIN_N_12 PLL0_NW/PLL1_NW PLL0_NW/PLL1_NW -- -- -- Bank 6 is the CPU DDR Memory Bank and does not appear to have any clock pins. Bank 5 is the SGMII Bank and has only its private SGMII Reference Clock input pins. R11 MSS_REFCLK_IN_N P11 MSS_REFCLK_IN_P Bank 4 is CPU GPIO pins and does not have any clock pins. Bank 2 is CPU GPIO pins and does not have any clock pins. Bank 7 J3 GPIO139PB7/CLKIN_W_7 J5 GPIO140PB7/CLKIN_W_6 K7 GPIO142PB7/CLKIN_W_5 H7 GPIO143PB7/CLKIN_W_4 K1 GPIO162PB7/CLKIN_W_3/CCC_SW_CLKIN_W_3 -- -- PLL0_SW/PLL1_SW DLL0_SW/DLL1_SW DLL0_SW/DLL1_SW H1 GPIO163PB7/CLKIN_W_2/CCC_SW_CLKIN_W_2/CCC_SW_PLL0_OUT0 - - PLL0_SW/PLL1_SW DLL0_SW/DLL1_SW DLL0_SW/DLL1_SW F4 GPIO164PB7/CLKIN_W_1/CCC_SW_CLKIN_W_1 PLL0_SW/PLL1_SW PLL0_SW/PLL1_SW -- -- -- G2 GPIO165PB7/DQS/CCC_SW_PLL0_OUT0 G5 GPIO167PB7/CLKIN_W_0/CCC_SW_CLKIN_W_0 PLL0_SW/PLL1_SW PLL0_SW/PLL1_SW -- -- -- Bank 1 more of them C2 GPIO168PB1/CCC_SW_CLKIN_S_0 PLL0_SW/PLL1_SW PLL0_SW/PLL1_SW -- -- -- E3 GPIO169PB1/CCC_SW_CLKIN_S_1 PLL0_SW/PLL1_SW PLL0_SW/PLL1_SW -- -- -- E1 GPIO170PB1/DQS/CCC_SW_PLL1_OUT0 D3 GPIO171PB1/CLKIN_S_2/CCC_SW_CLKIN_S_2/CCC_SW_PLL1_OUT0 - - PLL0_SW/PLL1_SW DLL0_SW/DLL1_SW DLL0_SW/DLL1_SW C1 GPIO172PB1/CCC_SW_PLL1_OUT1 A2 GPIO173PB1/CLKIN_S_3/CCC_SW_CLKIN_S_3 -- -- PLL0_SW/PLL1_SW DLL0_SW/DLL1_SW DLL0_SW/DLL1_SW D4 GPIO176PB1/DQS/CCC_SW_PLL0_OUT0 B4 GPIO177PB1/CCC_SW_PLL0_OUT0 D6 GPIO178PB1/CCC_SW_PLL0_OUT1