FPGA/CPU I/O Signals ----------------------- Initial Rev. 24-Apr-2023 Current Rev. 3-Aug-2023 The intent of this file is to list all of the I/O signals to the MPFS250T FPGA/CPU on the DK board. Except to mention them the DDR4 buses to the FPGA memory and to the CPU memory will be left out of this file for now. The main point of this file is just to collect an overall list of all of the I/O signals to the FPGA/CPU. Many of these signals will be to Peripherals that are part of the CPU but because of pin availability reasons these connections may be made to I/O Banks that are part of the FPGA. FPGA/CPU Reset plus 3 Control Signals Drw 12: ------------------------------------------------ FPGA/CPU RESET + 3 Control 4 Signals Bank 3 Fixed 3V3 System Controller SPI to FPGA Configuration Memory Drw 12, 48: ------------------------------------------------------------------- System Controller SPI Bus 4 Signals Bank 3 Fixed 3V3 System Controller JTAG through buffers to JTAG Header Drw 13: ---------------------------------------------------------------- JTAG bus plus TRST_B 5 Signals Bank 3 Fixed 3V3 USB Connection to USB Phy Chip Drw 17, 18: --------------------------------------------- ULPI bus to the USB Phy Chip 12 Signals Bank 2 Fixed 3V3 CPU QSPI Bus to CPU Configuration Memory Drw 48: ----------------------------------------------------- CPU QSPI Controller 6 Signals Bank ? Float 3V3 CPU SPI Controller 0 to PMT ADC Drw 16, 48: ------------------------------------------------ CPU SPI Controller #0 4/3 Signals Bank ? Float 3V3 3 pins CPU SPI Controller 1 to Interposers Drw 48, 51: ---------------------------------------------------- CPU SPI Controller #1 5 Signals Bank ? Float 3V3 CPU I2C Controller #0 to Timing Generator and SFPs Drw 23, 42, 49: ----------------------------------------------------------------------- CPU I2C Controller #0 2 Signals Bank ? Float 3V3 CPU I2C Controller #1 to Envir Sensors and Audio ADC Drw 36, 37, 49: ------------------------------------------------------------------------- CPU I2C Controller #1 2 Signals Bank ? Float 1V8 CPU MMUARTs 0:4 Drw 43, 44, 52, 60: --------------------------------------- CPU MMUART_0 to Header 2 Signals Bank ? Float 3V3 CPU MMUART_1 to Emergency Res 2 Signals Bank ? Float 3V3 CPU MMUART_2 to Barnacle 2 Signals Bank ? Float 3V3 CPU MMUART_3 to Interposer 1 2 Signals Bank ? Float 1V8 CPU MMUART_4 to Interposer 2 2 Signals Bank ? Float 1V8 CPU Sane and Power Control/Reset via CPU GPIO Drw 55, 56, 19: ---------------------------------------------------------------- CPU_IS_AWAKE 8 CPU GPIO Signals Bank ? Float 3V3 CPU_IS_AWAKE_B RUN_PMT_ADC RUN_CLOCK_GENERATOR RUN_USB RUN_BB_AUDIO_ADC RUN_BARNACLE STOP_TOMCAT Interposer Signals (not listed above) Drw 51, 52: ----------------------------------------------------- Interposer Chip Select GPIOs 3 Signals Bank ? Float 3V3 FLASH_NOW LVDS from FPGA 1 Signal Bank ? Float LVDS 2 pins MUON_Sx to GPIOs 4 Signals Bank ? Float 3V3 BB Audio ADC to FPGA Drw 37: --------------------------------- FSYNC Frame Sync \ BCLK Bit Clock | to FPGA 3 Signals Bank ? Float 1V8 SDOUT Serial Data / Clocks from FPGA to External Consumers Drw 18, 37, 43, 54: ------------------------------------------------------------- 1 Clk to BB Audio ADC GPIO1 1 Signal Bank ? Float 1V8 2 Clocks to the Barnacle 2 Signals Bank ? Float 1V8 1 Clock to the USB Phy Chip 1 Signal Bank ? Float 1V8 SFP Module GPIO type signals Drw 42: ---------------------------------------- 2 SFPs 3 signals each 6 Signals Bank ? Float 3V3 Control Timing to PMT ADC LVDS Drw 16: ------------------------------------------ 2 LVDS signals SYNC & TRIG 2 Signals Bank ? Float LVDS 4 pins Count of Bank 2 3V3 signals = 12 Count of Bank 3 3V3 signals = 13 In addition to Banks 2 and 3 there are: Count of 1V8 I/O pins on the FPGA/CPU = 13 Count of 3V3 I/O pins on the FPGA/CPU = 49 In addition to all of the above there are: Clock Input Signals = about 3 differential signals aka 6 pins High-Speed Serial Transceiver #0 Data 4 Signals 8 Pins Drw 53 Clk 1 Signal 2 Pins High-Speed Serial Transceiver #1 Data 4 Signals 8 Pins Drw 53 Clk 1 Signal 2 Pins DDR4 FPGA Memory Signals = 74 Drw 38 DDR4 CPU Memory Signals = 74 Drw 39 Total number of FPGA/CPU I/O pins in use - about 261