I2C, SPI, and UART Buses on the DK Board ------------------------------------------ Initial Rev. 21-Apr-2023 Current Rev. 4-June-2025 The intent of this file is to describe all of the I2C and SPI buses on the Disco Kraken board. At the end of this file there is a short description of the UARTs in both the DK's CPU/FPGA and in its Emergency Rescue uProcessor. References are given for the the DK Drawings that show the details of each of the buses. DK's I2C Buses 4 of them: -------------------------- The DK's 4 I2C Buses are shown in DK Drawing #49. Note that 2 of the I2C Controllers are actual hardware peripherals of the CPU while the bottom two controllers in Drawing #49 (#2S and #3S) are "soft" implementations of I2C Controllers in the FPGA fabric. - I2C Controller #0 uses Bank #9 1V8 I/O pins to communicate with the AD9546 Timing Generator. Once the Timing Generator has been configured and is running then this I2C Bus will be kept inactive during the bulk of the Physics running. The intent is to allow the Timing Generator to operate in a quiet as possible environment so that it can make the best timing signals possible. That is why this is a "private" I2C Bus. The I2C connection to the Timing Generator is shown in DK Drawing #23. - I2C Controller #1 also uses Bank #9 1V8 I/O pins to communicate with 3 targets: the 2 Environment Sensors and with the BB Audio ADC. This I2C Bus will be active at times during Physics running to readout these devices. DK Drawing #36 shows this I2C Bus connection to the Environment Sensors and DK Drawing #37 shows its connection to the BB Audio ADC. - I2C Controllers #2S and #3S are soft implementations of I2C Controllers in the FPGA Fabric. They are used to communicate with the 2 SFP Optical Transceiver modules. These SFP modules have a fixed I2C Address and thus 2 separate I2C Controllers was the most direct way to communicate with the 2 SFP modules. These I2C Controllers use 3V3 I/O pins in Bank #7 to communicate with their SFPs. The SFP I2C connections are shown in DK Drawings #42 & #66. DK's SPI Buses 5 of them: -------------------------- The DK's 5 SPI Buses are shown in DK Drawing #48. For these 5 SPI Buses we are using 4 different types of SPI Controllers. - SPI Controllers #0 and #1 are actual hardware peripherals of the CPU. They communicate with Interposers "A" and "B". These are 3.3 Volt normal 4 Wire SPI Buses that are routed out of the CPU/FPGA on pins in I/O Bank #1. The connection from DK to each Interposer includes a normal 4 Wire SPI Bus and has 3 additional address signals to select the target of the SPI Bus cycle and an additional Controller Reset signal that is used by the Interposer. These 4 signals that are in addition to the SPI Bus signals all come from a GPIO Port. The connection from DK to each Interposer is buffered by a 74LVC244 and each signal has a Pull-Up or Pull-Down resistor so that the overall bus to the Interposer is parked in a known quiescent state when the buffer outputs are tri-stated. At power up time, the buffers are kept tri-stated until the DK CPU is running and in control of its peripheral signals. See DK Drawing #51. - SPI Controller #2S is a "soft" implementation of an SPI Controller in the FPGA fabric that communicates with only the PMT ADC. This is a special 3 Wire SPI Bus that operates at the 1V8 level and uses Bank #9 I/O pins. This SPI Bus connection to the PMT ADC is shown in DK Drawing #16. This is a "private" SPI Bus connection because we want it to be quiet during Physics operation. - CPU/FPGA Bank #2 has a special dedicated "Quad Data Lane" SPI Controller that communicates with the CPU Boot Memory. This is a 6 Wire SPI Bus that operates at the 3V3 level. This CPU Boot Memory is shown in DK Drawing #59. Dedicated pins in I/O Bank #2 are used for the SPI connection to this flash memory. In our current plans for booting and managing the DK boards this flash memory is not used. - The I/O Bank #3 FPGA "System Controller" contains the dedicated SPI Controller that communicates with the FPGA Boot Memory. This is the Flash Memory that we will use to start the CPU and Configure the FPGA Fabric at power up time. The connection to the FPGA Boot Memory is a normal 4 Wire 3.3 Volt SPI Bus. In an emergency, e.g. if the contents of this boot flash memory are lost or corrupted we want to be able to re-write it. To facilitate such an emergency re-write, between the Bank #3 SPI Controller and this boot memory, we have a multiplexer that under specific conditions, allows the Emergency Rescue uProcessor to take control of this memory. The details of this arrangement are shown in DK Drawing #12. List of UARTs that are used on the DK Board: -------------------------------------------- UARTs in both the CPU/FPGA and in the Emergency Rescue uProcessor are used on the DK Board. A summary of these UARTs is given in DK Drawing #60. - CPU/FPGA MMUARTs 5 of them: For details about the MMUARTs in the MPFS250T-1FCG1152I see page 79 of the "MSS Technical Reference Manual". MMUART_0 - to the J12 Access Connector 3V3 MMUART_1 - to the Emergency Rescue UART_2 3V3 MMUART_2 - to the J7 Barnacle Connector 3V3 MMUART_3 - to the "A" Hemisphere Interposer 1V8 MMUART_4 - to the "B" Hemisphere Interposer 1V8 - Emergency Rescue uProcessor UARTs 5 of them: UART_0 - to the RS-485 Transceiver 3V3 UART_1 - to the J12 Access Connector 3V3 UART_2 - to CPU/FPGA MMUART_1 3V3 UART_3 - to TOMcat via 3V3 <--> LVDS 3V3 UART_4 - not used 3V3