Disco-Kratken Log Book #1 ------------------------------ Initial Rev. 4-Nov-2022 Current Rev. 17-Nov-2023 17-Nov-2023: ------------ Table of First Level LC Power Filters. These LC Power Filters are used to both clean up the power produced by the DCDC Converters and to isolate the noisy loads on a given DCDC Converter from the loads on that converter that need clean power. The direct output from a given DCDC Converter is labeled the BULK_xVy supply. For converters that have two First Level LC Output Filters, the output buses from these filters are typically labeled, Analog and Digit for the supplies to the noisy and the quiet loads on that converter. BULK_1V00 converter for the PMT ADC powers two loads: Analog_1V00 Load: 397 mA typ 471 mA max Inductor: 7443321000 10 uH 15.4 mOhm 9 Amp 1210 size V Drop: 6.1 mV typ 7.3 mV max Digital_1V00 Load: 797 mA typ 971 mA max Inductor: 7443320470 4.7 uH 7.9 mOhm 15 Amp 1210 size V Drop: 6.3 mV typ 7.7 mV max BULK_1V05 converter for the FPGA/CPU Core and Transceivers Analog_1V05 Load: 125 mA typ XCVR Inductor: 7443340470 4.7 uH 13 mOhm 7.5 Amp 8070 size V Drop: 2 mV typ Digital_1V05 Load: 2.2 A typ CORE Inductor: 7443320068 680 nH 1.35 mOhm 26 Amp 1210 size V Drop: 3 mV typ BULK_1V2 converter for the DDR4 Memory and the FPGA/CPU Memory Banks Estimated Load: 2.5 A to Memory Chips, 250 mA to Banks No LC Power Filters are used. BULK_1V8 converter for: FPGA/CPU, PMT ADC, BB ADC, Sensors, Timing Generator, Interposer Analog_1V8 Load: 95 mA typ 102 mA max --> 176 mOhm max PMT ADC Inductor: 7443341000 10 uH 38.5 mOhm 4.4 Amp 8070 size V Drop: 4 mV max Digital_1V8 Load: 41 mA typ 48 mA max --> 360 mOhm max PMT_ADC Inductor: 7443341000 10 uH 38.5 mOhm 4.4 Amp 8070 size V Drop: 2 mV max Interposer_1V8 Load: 500 mA max Inductor: 7443341000 10 uH 38.5 mOhm 4.4 Amp 8070 size V Drop: 19 mV max Timing_1V8 Load: 440 mA max AD9546 Inductor: 7443341000 10 uH 38.5 mOhm 4.4 Amp 8070 size Timing Gen V Drop: 17 mV max SENSOR_1V8 Load: 10 mA max Inductor: 742792116 60 mOhm 2.5 Amp 1206 size V Drop: 1 mV max BB_ADC_1V8 Load: 10 mA max Inductor: 742792116 60 mOhm 2.5 Amp 1206 size V Drop: 1 mV max BULK_2V5 converter for: DDR4 Memory, FPGA & its Trancever Analog 50 mA for DDR4 75 mA for FPGA & its Transceivers BULK_3V3 converter for: 14-Nov-2023: ------------ I gave up on a common TVS component for both the USB connection and for the PMT Signal Inputs. I also gave up on the rather specialized TVS from OnSemi for the PMT Signals. Now the PMT Signals will use a Littelfuse SP0115-01ETG in the SOD-882 package. The Demo Brd uses PGB1010603 MR for USB. 7-Nov-2023: ----------- 2nd Timing Meeting. - No copper links so no noise problems - Redundant signal paths so no single point failure - Independent timing delivery to each Module so one module does not depend on another - Power it is lower with all optical - Reliability is better with all optical because of fewer parts - All optical has no new parts - With the all optical the signal channel BW matches the timing requirements this is not so with copper I believe that there will be another timing meeting at the Philedalphia meeting that starts Nov 13. 31-Oct-2023: ------------ Shipped the Mechanical Only DK to Christian for the Assembly Test. This is on Air Waybill 7739 2219 6161. The FedEx place on Michigan Ave now sends out their last batch of stuff for air shipment that day at 17:00 (not at the old later time of 20:00). This shipment was stuck for a couple of days clearing customs. Customs needed to talk to the importer. It was delivered on Thursday Nov 9th. 27-Oct-2023: ----------- At noon MSU time there was a meeting titled, "Network & timing distribution", with Nathan, Felix, Christian, Michael, and Elisa Resconi. I'm so naive that I thought this was going to be a technical meeting where we would weigh the relitive advantages and disadvantages of the TOMCat and EPON like Timing Distribution schemes and make an informed technical decision based the the merits of the two options. It ended up being a 100% political meeting, all decisions had been made ahead of time. The only conversations were: mundane re-statements of adjusted history, statements that are factually incorrect, and attempts to bully me into doing things that I know are wrong. I was blocked from talking for most of the meeting. The result of the meeting is that Felix and Christian added a page about DK and its Timing Distribution reguirements. I believe that they now want an initial DK design with lots of options so that people can "play around" and then a final design that will be used in the real system. 17-Oct-2023: ----------- Before noon I sent out the data for the mechanical only DK board to Hughes. Waiting to hear back. 12-Oct-2023: ----------- Nathan brought me an EPON SFP module and it has the issue that the part that sticks out of the SFP Cage quite far and hangs down below the cage. It is bigger than a "normal" SFP module and the EPON module uses an SC type connector that is larger than an LC type connector. As far as I know all EPON SFP modules use an SC type connector. The EPON module sticks out of the SFP Cage by about 16.5 mm. It is about 13.8 mm Wide and about 11.3 mm High of which about 2.0 mm hangs down below the bottom of the SFP Cage. About 13.5 mm of hard plastic SC connector sticks out from the metal part of the EPON module. This hard plastic part is followed by about 30 mm of flexible cable support that is floating on the cable and not attached to it. This long flexible support could be trimmed to a length of about 10 to 12 mm to let the bend of the FO cable start sooner. Tentatively the cutout in the PCB will need to be about 29 mm in X by 24.5 mm in Y to allow for the part of the EPON SFP module that hangs down below the floor of the SFP Cage. There is the added question of will the PCB need a 9th mounting screw to support the small section of the PCB immediately East of the cutout. 11-Oct-2023: ----------- The scheme of running the long axis of the SFP Cages has the major problem that one can not insert or remove the SFP Module from the Cage unless you have no components on the PCB for about 40 mm in front of the Cage. If I rotate the Cages by 90 deg back to their original orientation then I need only about 20 mm of clear space in front of the Cage to give enough fiber optic cable length before it reaches the 340 mm Dia limit for the cable to bend. Measure things: From Back of Cage to Front of Cage 48.7 mm From Back of Cage to Front of SFP Module 57.8 mm From Back of Cage to Cable max Bend point 115 mm is OK 120 mm is Better From the SFP long center axis laterally to the maximum Bend point is about 28 mm There is also the variable of the length of cable support from the LC connector end. Looking at a number of cables I see this range from about 28 mm up to about 38 mm. The cable used for the above measurements had a support for about 33 mm. I assume that the actual FO cable will have a single LC connector but I need to verify that. The 3M 0.1" x 0.1" headers 14 & 26 pin are set with their geometries back from the pcb edge by 11.6 or 11.7 mm to put them close to the edge but not soo close as to cause trouble for the plug that goes into them. The Harwin M80 coax receptacles have the center of their geometry set back from the edge by 7.1 mm. This puts their connector edge at the PCB edge which should be OK because the coaxial plug that goes into them has locking screws. The Molex 2x20 2 mm headers have their geometry setup back from the edge by 7.4 mm. That makes the connector's edge hange over the PCB edge by about 0.4 mm the intent of this hang over being being to give the flex cable to the Interpoaser some open clearance to make use that the connector on the flex cable can go the whole way into these headers on the Disco board. The location of these headers and receptacles wrt PCB edge is to give maximum space on the PCB without putting any of the plugs at risk or getting any vias or traces or mounting screws too close to the PCB edge. 10-Oct-2023: ----------- The first Review of the DK Board was today. From the report I have a concern that they may think that actual detailed design work has started - which of course has not because I do not know which timing scheme is going to be used. 19-Sept-2023: ------------ Reader's Guide to some of the issues about DDR4 layout on the DK board: Polarfire IO User's Guide UG0686 or UG0916 "Shield" Pins: 7.1.12 pg 28 7.2.1.3 pg 29 7.2.13.3 pg 44 The pitch of the Gnd Rivets vs their maximum shielding frequency should be less than about 1/8 of a wavelength in the medium, i.e. < c / 8 x f x sqrt(Dk) c is 3.0 E+11 mm/sec Best to think of this as the maximum frequency at which the rivets keep the various Gnd planes clamped together. Xilinx PCB Guidelines for Memory Interfaces UG583 Pg 55 for the DDR4 layout they want a full extra row of Gnd Rivets between columns 2 & 3 and between columns 7 & 8. Recall that these 4 columns contain all of the fast signals and that columns 1 & 9 are power and Gnd pins. They stress the need for these return current paths for good high frequency layout. The clean way to handle this layout is to just put these vias in the Geom for the memory device which is THD in any case. Columns 1, 2 and 8, 9 then dog-bone to the outside edge of the device and columns 3, 7 dog-bone to the center to make a nice clean minimum stub setup for the high speed signals. The memory chip end of these DDR4 links will be a lot cleaner than the MicroChip FPGA end. 8-Sept-2023: ------------ I had a short meeting with Nathan starting at 5. Many small points but a major significant news is that Nathan says that the 16 Gbit 16 wide data SDRAM looks OK with the Microchip tools. The tools had looked OK with the Dual-Chip version of this size memory but until this news I did not know for certain that it worked OK with the contemporary single chip version of this size memory. The specific target part is: Micron MT40A1G16TB-062E:F 7-Spt-2023: ----------- Felix and I had a meeting so that I could start to understand the Signal from the Photo-Diode monitor of the Flasher's light output that a normal DK PMT ADC Channel will need to handle. Note that there are both SiPM and Photo-Diode monitors of the Flasher. The signal from the SiPM looks enough like a normal PMT signal that I do not need to worry about that. The Photo-Diode signal is much slower and positive going so it will require special processing on the DK before it goes into the PMT ADC. I need to remember that for many of the ADC control parameters that all 16 ADC channels are (must be) set up in the same way - so nothing special can be done in that sense for the Photo-Diode signals. The modules with a Flasher, a SiPM, and 2 Photo-Diode signals will have 4 of its normal PMTs removed in each hemisphere. These 4 missing PMTs in each hemisphere are the ADC channels that will handle the Photo- Diode and SiPM signals. The general scheme is that the Photo- Diode signals will be positive going, the rise in about 4 usec they are from an integrator that falls with a time constant of about 270 usec (270 pFd and 1 Meg Ohm) he will have a 50 Ohm back terminator resistor at the driving end and can have an AC coupling capacitor. He is sending me scope plots of typical signals that will come from his end. I need to propose how the DK will be modified to receive these signals, e.g. what the load will look like and what FS voltage is needed, Felix will then adjust the gain at his end to match these requirements. Reader's Guide for the Memory Controller User's Guide: Pages: 64, 82, 96, 163 29-Aug-2023: ------------ While working on the layout of the DK's power distribution network I need to review the complicated loads on two of the Bulk supplies: BULK_2V5 feeds: DDR4 Vpp Wordline Supply: 3 mA constant 48 mA peak FPGA VDD25 PLLs & PNVM: 12 mA from demo brd XCVR CLK Buffers: 2.2 mA from demo brd XCVR VDDA25 PLLs: 60 mA from demo brd BULK_1V8 feeds: FPGA VDD18 Prog&HSIO_Aux: 70 mA from demo brd PMT ADC Analog: 102 mA from DS PMT ADC Digital: 48 mA from DS BB Audio ADC IOVDD: 1 mA from DS BULK_1V05 feeds: FPGA VDD Core Supply: 2100 mA from demo brd XCVR VDDA Tx & Rx: 125 mA from demo brd To minimize power consumption and maximize reliability each of these buses use only a single power supply, i.e. there are not separate Analog and Digital supplies for these buses, so the LC noise filters and the bypass capacitors must be designed to be effective in controling the spread of noise on these buses. In addition the LC filters must attenuate the switching noise from the DCDC Converters before the power is supplied to the PLLs and analog components. In general there are separate LC filters at the output of these converters for their analog and digital loads plus a separate LC filter at each of the analog loads. 23-Aug-2023: ------------ This note list the components on the DK Board that require a custom geometry or that need to have a package type and geometry specified for their use on the DK Board. Function Full Part Number MG Geom. ----------------------- --------------------- ------------ DDR4 16 Gbit 16 wide MT40A1G16TB-062E:F DDR4_96_Pin FPGA Boot Flash 1 Gbit MT25QL01GBBB8ESF-0SIT so16w CPU Boot Flash 256 Mbit MT25QL256ABA8ESF-0SIT so16w FPGA/CPU MPFS250T-1FCVG784E FCVG_784_Geom High Side Switch MIC2544-1YM soic_8 Rescue uProcessor LPC845M301JHI33 HVQFN_32 Power Supply Supervisor TPS3808G01DBVR SOT_23_6 Always ON Regulator LT3060ETS8#TRMPBF TSOT_23_8 Converter 100V to 5V TEN20-7211WIR TEN20_Power DCDC Converter PTH04T230WAD ECL_PDSS PTH04T260WAD DDR4 Term Ref Supply TPS51200DRCT VSON_10 I2C Multiplexer 4 way PCA9546AD soic_16 Sensor Accel Magnet ISM303DAC ST_LGA_12 Sensor TPH BME280 Bosch_BME280 Clock Generator AD9546BCPZ qfn_48_56sq BB Audio ADC TLV320ADC6140IRTWT qfn_24_27sq SFP Cage 2227023-1 SFP_Optical 2227023-3 SFP Connector 1367073-2 SFP_Optical 1888247-1 USB Phy Chip USB3340-EZK qfn_32_33sq PMT ADC AD9083BBCZ ADC_100_BGA Transformer Input TC1-1TX+ Input_Transformer Transformer Split Sec. T-622-KK81+ Pulse_Transformer PMT Analog Input Conn M80-MH313M5-08 M80_MH313M5_08_Conn M80-MH314M5-08 USB "A" Connector 1-292303-2 USB_Conn 292303-4 Main Cable Connector 3429-5203 M3_2x13_Horz_Header Interposer Connector 87833-4020 Header_2mm_40pin_RA Barnacle Connector 87832-1420 Header_2x7_2mm JTAG Connector 87832-1020 Header_2x5_2mm ER uProc Debug Conn SBH31 Header_2x5_127mm Access & PS Mon Conn 87832-4020 Header_2x20_2mm Resistors 26 types all 1% comp or MF IPC 0402 0603 0805 Resistor 4 Wire 4 types FC4L or KRL Sense_Resistor Resistors Variable 4 types Bourns 3214 TRIM_POT_SM_43W Capacitors Ceramic 13 types all 10% X7R IPC 0402 0603 1206 IPC 1812 special 0201 Capacitors Tantalum 2 types T520V157M010ATE025 Tant_V_Case T520V337M006ATE025 Capacitor Film R75IW5100(1)40(2) Cap_Polyprop Inductors 7 types Wurth & Murata 7 custom geoms Clamp Diodes MMSZ46801G zener_sod123 15-Aug-2023: ------------ This note is to specify part numbers for the two Interposer connectors on the DK Board so that I can make geometries for them. The intent is to use generic 2 mm parts for these connections. To provide specific part numbers I will use the Molex Milli-Grid series. For each Interposer I will use a 40 pin connector as there is space for them on the perimeter of the board and 40 pins is enough to use signal-ground pairs for all high frequency signals, to use a differential pair for the Flash_Now signal, to use a differential pair for the low level hydrophone signal, and provide a comfortable number of power pins. On the DK Board I will use through hole connectors to remove the risk of pulling pads off of the card during final assembly. Right angle male header, through hole, shrouded, with center polarization slot and with side locking windows are part numbers: 87833-4020 for 15 u inch or 87833-4021 for 30 u inch gold. The housing for female wire mount crimp contacts is part number 51110-2050 without center polarization key and without side latches or 51110-2051 with center polarization key and side latches. This is for the 20 pin housing. The associated wire mount contact is part number 50394-8051 for 15 u inch or 50394-8052 for 30 u inch gold. Two housing with out side latches will end stack. The female 40 pin IDC connector is part number 87568-40x3 or 87568-40x4 for the 15 or 30 u inch gold where X is: 6 - without polarization and ramp, 7 - with single locking ramp, 9 - with polarization and locking ramp. A similar 40 pin IDC part is: 87985-3040 The female 40 pin straight through hole receptacle is: 79107-7019 or 79107-7069 for 15 or 30 u inch gold. The female 40 pin straight SMD top entry without pegs receptacle is part number: 79109-1019 or 79109-8419 or 79109-1069 or 79109-8469 for various options. The female 40 pin straight SMD top entry with locating pegs receptacle is part number: 79109-1219 or 79109-8619 or 79109-1269 or 79109-8669 for various options. An alternative 40 pin straight SMD top entry receptacle is part number: 87381-4064 or 87381-4063 The associated 2 mm parts, e.g. for the Barnacle connector or the Power Supply Monitor connector or the Access connector or the JTAG connectors are: Vertical 10 pin through hole: 87831-1020 or 87831-1021 Vertical 20 pin through hole: 87831-2020 or 87831-2021 Vertical 40 pin through hole: 87831-4020 or 87831-4021 Vertical 10 pin SMD: 87832-1020 or 87832-1021 Vertical 20 pin SMD: 87832-2020 or 87832-2021 Vertical 40 pin SMD: 87832-4020 or 87832-4021 Right Angle 20 pin through hole: 87833-2020 or 87833-2021 14-Aug-2023: ------------ The DK Board uses a significant number of ceramic and Tantalum capacitors. - Most of these capacitors are used in power supply filtering and bypassing applications. - A few of the ceramic capacitors are used in timing and AC coupling applications. The AC coupling includes 3 specialized applications: the 12 GHz links from the PMT ADC, the 1 GHz high-speed serial links to the SFPs, and the AC input coupling to the BB Audio ADC where piezoelectric noise is an issue. There are a few additional special purpose capacitors used on the DK Board, e.g. the 250 Volt polypropylene capacitors for the +100 Volt input power. The purpose of this note is to specify the types of ceramic and Tantalum capacitors that will be used on the DK Board. The goal is to control the number of different types of these capacitors that are used in order to simplity parts ordering, parts inventory, and assembly of the DK Boards. In all cases the ceramic capacitors need to have a wide margin in their operating voltage to avoid saturation of the dielectric. An operating voltage margin of at least 2 is required and a margin of 3 is better. This requirement leads to 3 ranges of ceramic capaciotor operating voltage on the DK Board: +100 Volt input power, 5 Volt power, and 3.3 Volt or less power buses. The Tantalum capacitors are all of the polymer type and require an operating voltage margin of at least a factor of 2. In general the ceramic material should be X7R dielectric with X5R used only where necessary. The following types of ceramic capacitors are used on the DK Board: Operating Dielec Chip Example Capacitance Voltage tric Size Part Number Notes ----------- --------- ------ ---- --------------- --------------------- 3.9 nFd 50 V X7R 0402 C0402C392K5RAC 0.50 mm Thick Time Gen. 10 nFd 50 V X7R 0402 C0402C103K5RAC 0.50 mm thick 33 nFd 25 V X7R 0402 C0402C333K3RAC 0.50 mm thick PMT ADC 47 nFd 25 V X7R 0402 C0402C473K3RAC 0.50 mm thick 100 nFd 6.3 V X5R 0201 C0201C104K9PAC 0.33 mm thick 100 nFd 16 V X7R 0402 C0402C104K4RAC 0.50 mm thick 100 nFd 25 V X7R 0603 C0603C104K3RAC 0.80 mm thick 220 nFd 25 V X7R 0603 C0603C224K3RAC 0.80 mm thick Time Gen. 0.47 uFd 250 V X7R 1812 QMK432B7474KM-T 2.50 mm thick +100 Volt C1812C474KARAC 1.85 mm thick filters 1 uFd 25 V X7R 0603 C0603C105K3RAC 0.80 mm thick BB ADC 2.2 uFd 10 V X7R 0603 C0603C225K8RAC 0.80 mm thick PMT ADC 10 uFd 25 V X7R 1206 C1206C106K3RAC 1.60 mm thick 22 uFd 10 V X7R 1206 C1206C226K8RAC 1.60 mm thick The following types of T520 Polymer Tantalum capacitors are used on the DK Board: Operating ESR Case Example Capacitance Voltage mOhm Size Part Number Notes ----------- --------- ---- ---- ------------------ --------------- 150 uFd 10 V 25 V T520V157M010ATE025 1.90 mm thick 330 uFd 6.3 V 25 V T520V337M006ATE025 1.90 mm thick The following is the list of resistor values and types that are used on the DK Board. We need to control the number of different resistor values and types used on DK to facilitate purchasing, inventory, and assembly of the DK Boards. Resistor Chip Value Ohm Size Tolerance Notes --------- ---- --------- ------------------------- zero 0603 --- Jumpers and Power Supply R4 27 0603 1% Generic Series Terminator 39 0402 1% DDR4 Terminators 110 0603 1% Generic Parallel Terminator 220 0603 1% Power Bus Monitor Series 240 0603 1% ZQ Calibration for DDR4 Memory 270 0603 1% Timing Generator Output Pull-Ups 136 0805 1% metal film PMT ADC Input 499 0805 1% metal film PMT ADC Input 11k 0805 1% metal film PMT ADC Input 4.7k 0603 1% Generic Pull-Ups 4.99k 0603 1% metal film PMT ADC RBias 10.0k 0603 1% 37.4k 0603 1% Power Supply UVLO 45.3k 0603 1% CNST 3V3 Supply RSet 62.8k 0603 1% All Power Good Supervisor 100K 0603 1% RS-485 Terminator 3 Resistor Values Trim resistors for the 100V to 5V Converter 0805 as needed DCDC Converter Vout Rset Fix Standard Values Resistors: 18.2k Ohm @1V0 0805 1% metal film 15.4k Ohm @1V05 11.0k Ohm @1V2 4.32k Ohm @1V8 2.15k Ohm @2V5 976 Ohm @3V3 DCDC Converter Variable Trim Resistors: 5.0k Ohm @1V0 2.0k Ohm @1V2 1.0k Ohm @1V8 500 Ohm @2V5 and @3V3 DCDC Converter current sense resistors: 5, 10, 15, 20, 25, or 30 mOhm to fit the load 4 terminal 2 Watt Ohmite Part No. FC4L64 4 terminal 2 Watt Susumu Part No. KRL64 11-Aug-2023: ------------ DK Board Inductors - The DK Board uses a significant number of inductors to filter noise on its various power supply buses. These noise filter inductors are used in two distinct ways: - In some cases the goal is to reduce the noise generated by the switching DCDC Converter before the power from that converter is sent to a load that is sensitive to power supply noise. - In other cases the goal is to prevent the noise that is generated by a particular load on a given power supply bus from getting onto that bus and thus potentially causing problems with other loads that operate from that bus. The typical value of these power supply filter inductors is 10 uH. This inductor value come from wanting the cut off frequency of the LC noise filters to be a couple of orders of magnitude below the switching frequency of the DCDC Converters when making these filters with a practical value of capacitance. The switching frequency of the DCDC Converters is 300 kHz or higher. Practical values of capacitance are about 22 uFd for X7R ceramic capacitors and about 330 uFd when Tantalum capacitors are used. The resulting cut off frequencies are about: 10.7 kHz with 22 uFd and about 2.77 kHz with 330 uFd capacitors. One must also be careful to verify that these power filters have a very low Q in the frequency range where the filters go series resonant. The DC voltage drop across these inductors must be kept low (order of 1% or 2% of the voltage of the associated power bus) so that loads that are down stream of these noise filter inductors receive the full voltage of the power bus. Controlling the DC voltage drop across the noise filter inductors requires inductors with low or very low DC resistance. Use of noise filter inductors is practical on most DK Board power buses only because most of the current loads on the DK Board are less than about 1 Amp. We also need to limit the number of different types of noise filter power inductors that are used on the DK Board in order to simplify purchasing, stocking, and pcb assembly operations. The following inductor part types are used on the DK Board: Self DC Rated Part Number Inductance Resonance Resistance Current Size ----------- ---------- --------- ---------- ------- ------ 74435561100 10 uH 14 MHz 6.9 mOhm 15 Amps 1890 7443321000 10 uH 29 MHz 15.4 mOhm 9 Amps 1210 7443341000 10 uH 29 MHz 38.5 mOhm 4.4 Amps 8070 742792116 500 Ohms at 100 Mhz 60 mOhm 2500 mA 1206 > 100 Ohms above 10 MHz BLM15AX300SN1D 30 Ohms at 100 MHz 110 mOhm 1100 mA see note 74477125 560 uH 2.5 MHz 740 mOhm 650 mA 1260 7446630027 27 mH --- 1.2 Ohms 600 mA SH Common Mode 253 uH leakage All of the part numbers beginning with "74" are manufactured by Wurth and the size designation is from Wurth. The Murata BLM15AX300SN1D part is used only in the differential output circuits of the AD9546 timing generator. The last two items in this list are used only for filtering the +100 Volt DC input power to the module. Size of the BLM15AX300SN1D is: The required foot print for the BLM15AX300SN1D is: 1.0 mm long, 0.5 mm by 0.5 mm cross section, metalized for 0.25 mm from each end, the center 0.50 mm is not metalized. PCB Pad size: 0.4 mm in X by 0.5 mm in Y C to C Pad spacing 0.8 mm in X Make pads wider in Y to help reduce the operating temperature. The inductor type selected for use with a given load on the DK Board is constrained by the DC Resistance requirement of: 1% or 2 % of the Amps Drawn DC Resistance Voltage of the by the Load x of the Inductor < Associated Power Bus 9-Aug-2023: ----------- Late Tuesday afternoon I had a short meeting with Nathan about the result of the Bank 9 Bank 1 discussion with Microchip. He gives me a sealed package with one engineering sample of the MPFS250T in the FCVG784 package. This chip is so I can probe it to confirm Bank 9 Bank 1 isolation and it can be used as a thermal profile chip at the assembly house. We also talked about the type of splice between the two 50 m cables that come into each Module. That is will these be only 2 wire splices or will there also be 3 wire splices. For example, will there just be one RS-485 pair coming out of the Splice Box and one RS-485 pin pair on the DK or will there be two RS-485 pairs coming out of the Splice Box (an Up pair and a Down pair), 2 pin pair for RS-485 on the DK board and the actual "splice" being made on the DK board. In the meeting Nathan says that he now wants the Copper Enet back in the design. He must have fallen off of the wagon. 8-Aug-2023: ----------- Nathan sends me an email note with some information about the current draw of the firmware and software that he is currently running on the Microchip SoC SEV Kit video demo board. I do not know exactly what all is in this firmware plus software. I think this is the readout of the hardware current monitor on the demo board - not the output of some power estimator tool. Nathan's note says, This came out of the software tools for the demo board. The CPU and the DDR controller together use about 80% of the power. VDD (1.05 V): 2078 mA VDD18 (1.8): 67.4 mA VDDI 1.1V: 204 mA VDDI 1.2V: 248 mA VDDA (1.05 V): 123 mA VDDA25 (2.5V): 59 mA VDAUX (2.5V): 10 mA VDDI 3.3 V: 0 VDDI 1.8V: 0 XCVR_VDD_CLK 2.5: 2.2 mA VDD25 (2.5 V): 12 mA The Microchip Tool labels "VDDI" are meaningless without a Bank Number after the VDDI. Apparently the voltages shown in parenthesis are the buses of fixed voltage and the voltages listed without parenthesis are buses with user selectable voltages. It appears that a current value of zero does not earn a unit label. 7-Aug-2023: ----------- The following is the major email notes with Microchip about the Bank 9 Bank 1 connection that they describe in their documentation: Date: Wed, 2 Aug 2023 19:29: Hello, For the MPFS250T in the FCVG784 package do the Bank 9 and Bank 1 voltages need to be the same ? Specifically must: VDDI9 = VDDI1 and VDDAUX9 = VDDAUX1 ? Your document, "PolarFire SoC FPGA Packaging and Pin Descriptions" Revision C from 09/2022 says, "12 I/Os from Bank 9 are connected to Bank 1 power in the package substrate to maintain pin-migration among devices and to maximize pin count in this package" this note is at the end of table 1-1. Which 12 I/Os from Bank 9 is this talking about ? In the same document by the drawings of the MPFS250T-FCVG784 and the MPFS250T-FCG1152 it says, "Bank 9 VDDI and VDDAUX power pins are connected to Bank 1 VDDI and VDDAUX power pins, respectively within the package substrate for pin migration compatibility." I doubt that this it true for the MPFS250T-FCG1152 because your SoC SEV Kit video demo board that uses a MPFS250T-FCG1152 has completely separate power supplies for Bank 9 and Bank 1. What are the actual requirements on the Bank 9 and Bank 1 power supplies for the MPFS250T-FCVG784 ? Thank you for your help, Dan Date: Mon, 7 Aug 2023 10:54 Hi Dan, Yes, you are right. VDDI1 and VDD9 are completely independent. Error is in note of user guide. Thank you so much for bringing this to our attention. The VDDI1 and VDDI9 are separate inside the package. The Bank 1 and Bank 9 are not connected internally. We will update the user guide as soon as possible. Regards, Rafik Date: Mon, 7 Aug 2023 15:04: Hello Rafik, Thank you for the quick answer. From your answer I understand that for the MPFS250T in the FCVG784 package that the Bank 9 and Bank 1 power supplies are independent of each other. That is: VDDI9 is independent of VDDI1 and VDDAUX9 is independent of VDDAUX1 Thank you again for your help, Dan Date: Mon, 7 Aug 2023 15:11 Hi Dan, Thank you for the confirmation. Please accept the resolution to close this case. Please respond to the survey for this case. Your additional feedback helps us to continuously improve the quality of our products and support. Regards, Rafik 4-Aug-2023: ----------- In preparation to making the MG geometry for the Harwin ganged coaxial connector this is a quick review of the parts: 8x cable mount connector M80-FC305F1-08 $84 each in qty 50 without any coax cable 8x cable mount connector M80-FC305F1-08-0450L $117 each in qty 50 with 450 mm of RG178 8x PCB mount M80-MH313M5-08 $96 each in qty 100 without mounting screws 8x PCB mount M80-5000000M5-08-313-00-000 $155 each in qty of 1 I think this is the same connector with mounting screws Note that this cable mount is for RG178 (not RG174). I think that connectors are available for RG174 and also there may be a 90 degree version of the cable mount connectors. In the pcb mount side, 313 is 3.0 mm termination for 1.6 mm pcb and 314 is 4.5 mm termination for 3.2 mm thich pcb. 1-Aug-2023: ----------- A big recent problem is the discovery (or re-discovery) that Banks 1 and 9 must operate from the same VDDIO and VDDAUX supply voltages. I don't think that this is a restriction of the silicon but is rather imposed by the packaging header to make these parts compatable with some other part or package. This is a big deal as it really screws up the layout under the FPGA/CPU. I can only find this restriction mentioned as a note in the Package and Pin Definition Guide and it appears to have only been added to the 5 revision of that document. Working to update "fpga_cpu_io_signals.txt" to the EPON version to see how bad of a problem this Bank 1 Bank 9 restriction will be. Currently assume that Bank 7 will need to become 1V8 I/O. 28-July-2023: ------------- Friday late afternoon meeting with Nathan about the Timing Distribution. Topics included: - The basic topology of the Timing Distribution is fanout by 7, then fanout by 10, then in the string fanout by 20. - There are 3 levels of the electronics: Hub, Intermediate, and Base Junction Box. For design efficiency, reliability and practicle reasons all 3 should be the same electronics. We want one common card with common technology between the Timing Distribution Card and the DK. - Couplers / splitters do fail - both the planar type and the blob of glass type. - For reliability we want 2 sets of electronics at each level. - Electronics with 1 Input SFP and 1 Output SFP - not very attractive - any failure kills the whole path. - Electronics with 2 Input SFPs and 1 Output SFP - not very attractive - cross coupling requires the fanout by 7 to be a 1:14 and the fanout by 10 to be a 1:20. - Electronics with 1 Input SFP and 2 Output SFPs - looks better: fanout by 7 can be two 2:7 and the fanout by 10 can be two 2:10. This cross couples at each tier and there is no single point fiber optic failure problem. - Not also that the String fanout can be two 2:10 instead of one 2:20. This give twice the optic power and improves the string reliability. All FO splitters could be a common 2:10 with only a little loss at the first stage. - Electronics with 2 Input SFPs and 2 Output SFPs is probably only useful in a tripple redundant system, perhaps at the Hub end, has many possible arrangements, and could use 2:x or 3:x or 4:x splitters. -Discussed operation without the full chain, e.g. with just one group of 10 Strings and in test setups. - We did not have time to discuss: . jabber control i.e. power Off control 100 V power input . eeprom control of startup . on board 10 MHz rock for test setups. 27-July-2023: ------------- Nathan and I had a quick meeting to review the Emergency Rescue and the Timing Distribution: - Yes, the normal power up script can just start the normal ER program once it has connected with the ISP and this normal ER program can take care of setting up the ER_IS_SANE and RST control of the RS-485 transmitter enable. - Thus we will keep ER_IS_SANE protection of the enable to the RS-485 transmitter. - There is no longer any need for it so we are dropping the ability of the DK's FPGA/CPU to Reset the ER LPC845 micro processor. - Yes, we will consider connecting "Module Status" signal to the 4 or 5 unused input GPIO pins on the ER LPC845. These signals could be things like: all power is good, CPU_IS_SANE, FPGA/CPU Boot Status, Clocks are Good, Receiving PMT_ADC Data. The intent is that when the Host asks a given ER node for its Status, that the ER LPC845 would reply with its unique ID number and the value of these various Status signals. - The RS-485 bus running up a string could be broken into a number of sections, e.g. 2 or 4 so that failure of one, e.g. from a flooded module do not kill the ER for the whole string. The base end of this bus (buses) will need to have the same control of the Enable to its transmitter and the same unbalanced terminator. - Nathan ran out of time before we could talk about the Clock Distribution. Not sure if I have fallen off the rails or not. 25-July-2023: ------------- A quick review of the connectors on the DK Board and their J numbers: J1 Main Cable Connector J2 & J3 PMT Analog Signal Connectors (may be only J2) J4 & J5 Interposer Connectors J6 TOMCat Connector J7 Barnacle Connector J8 Emergency Rescue LPC845 Debug Connector In addition there are connectors for: Access Connector JTAG Connector for DK's FPGA/CPU JTAG Connector for the TOMCat Power Supply Monitor Connector Clock Monitor Connector. The arrangement of the strings is: 7 groups of 10 strings each. So the rational setup for the Timing Signal Fanout is: Hub, 7x, 10x, 20x, Module. Just for reference from our previous designs, how much power does a 12 channel 10 Gbps MiniPOD take: Transmitter: 280 typ 365 max mA at 2.5 Volts 105 typ 185 max mA at 3.3 Volts 0.700 typ 0.913 max Watts at 2.5 Volts 0.347 typ 0.611 max Watts at 3.3 Volts 1.047 typ 1.524 max Watts total for 12 channels 0.087 typ 0.127 max Watts total per channel Receiver: 350 typ 425 max mA at 2.5 Volts 48 typ 90 max mA at 3.3 Volts 0.875 typ 1.063 max Watts at 2.5 Volts 0.158 typ 0.297 max Watts at 3.3 Volts 1.033 typ 1.360 max Watts total for 12 channels 0.086 typ 0.113 max Watts total per channel 24-July-2023: ------------- Had a meeting with Nathan late Friday afternoon on 21-July-23 to mostly talk about the Emergency Rescue setup and the EPON type of Timing Distribution. Points: - Yes, being able to Dead-Start via the RS-485 ER system sounds useful - thus we will need to power up wake up the LPC845 in its ISP Mode. This has some consequences: - For the first few ascii exchanges between the Host and the ISP - the Host will not be able to receive what the ISP is sending out. This is because the RTS pin for the LPC845's UART_0 is not setup by default so that it can be used to Enable the RS-485 transmitter. Only after the Host is connected to and using the IPS can it then setup the RTS pin on UART_0. - There is still the additional related question of do we need to protect against a given module being hung with its RS-485 driver enabled. - There is still the additional related question of do we want the DK's FPGA/CPU to be able to RESET the Emergency Rescue system's LPC845 ? - Yes, Powering Up a String will take on the order of 20 to 30 minutes. Part of this sequence needs to be getting the Host connected to the ISP of the LPC845 in each Module. The IPS uses the first Start-Bit that it receives to setup its Baud Rate and we need to get this setup at power up time and not just wait for days or years for the auto baud rate mechanism to trigger on a noise spike. - This makes about 3 commands that our program in the ER LPC845 will need to implement: . A "Ping" type command that maybe just returns the unique ID number from the LPC845 in each module. . A "Connect UARTs" type command that connects together two UARTs (e.g. so that the RS-485 port can talk with the DK's port or the TOMCat's port). This will need a special ascii sequence to break the UART to UART connection that is setup by this command. . A "Take Over the DK's FPGA/CPU Boot SPI Memory" commany. This would then be followed by a long sequence os stuff to reload the FPGA/CPU BOOT Memory and then I assume a power cycle of the Module to give the DK's FPGA/CPU in that Module another chance to wake up. - Yes, the LPC845 does inclue a unique ID number - a long one. - The Emergency Rescue system is only needed for unplanned emergency reload of the DK's FPGA/CPU Boot Memory. There is another mechanism to do a normal planned reload of the DK's FPGA/CPU Memory. - Yes, we will use LVDS to translate from the ER's LPC845 3.3 Volt UART to the TOMCat. - Yes, the 1% accurate Free Running Oscillator is good enough for the RS-845 communication with the ER system. - Yes, we understand that a flooded module will take out the ER system for the whole string. - Yes, the ER system needs to be designed so that it does not have some kind of single point failure mode that can then take out the normal Physics functions of a Module. - Testing of the ER system needs to be a serious part of the Final Production Testing of each module. - Yes, made a design fork of classic DK to EPON DK and I'm only maintaining the EPON version since about 12-July. - The AD9546 in each Module will be used in the following basic way: . The Reference from the Base Junction Box will be something like 100 MHz that is phase modulated at about 200 kHz indicating cycles that have been Time Stamped by the AD9546 in the BJB. . Note that that our Reference clock from the BJB is what AD would call the Common Clock. AD typically thinks in terms of a Common Clock and a separate Reference clock that the user want to replicate in each node with a AD9546. . Note that we are NOT going to setup a Common Time Scale (aka a common To) in the Modules. The way we use the AD9546 in the Modules it does not need a common time scale with the BJB. . One channel of Output section 0 in the Module's AD9546 will just re-generate the input Reference signal including the same cycles being phase modulated all of this with Zero Delay. This is what is returned to the BJB so that the Round Trip Delay can be measured by the AD9546 in the BJB. . The FPGA/CPU in the DK will need to Enable the optical transmitter in the Timing SFP of the Module when the BJB wants to measure the Round Trip Delay to that Module. . Two channels of Output section 0 in the Module's AD9546 will be used to generate the ADC Clock and the ADC SysRef signals. . Talked about possibly using the Reference Clock from the BJB (or possibly this signal divided by 2) as the input to the XOA and XOB System Clock of the AD9546 in the Module. The intent of doing this is that things have to work OK with zero drift between the input Reference Clock and the AD9546's output signals (just by definition) even with none of the Clock Compensation Methodes in use. . We did not get to talk about using the Reference Clock from the BJB directly as a clock input to the DK's FPGA/CPU. This needs to be looked at carefully, i.e. risk vs power saving. - The Reference signal from the BJB is very important (always has been very important). How redundant do we need to make the Timing Distribution system ? Fanout is probably 7x then 10x. 17-July-2023: ------------- The 1 km long electrical cable in a string will have a one way electrical length of about 5 usec assuming velocity factor of about 2/3 c. It could be that the velocity factor of the main cable is less than 2/3 c beccause it must have a rather dense solid dielectric. If one runs the RS-485 Emergency Rescue link at 9,600 Baud, i.e. 960 characters or octets per second, the link will have a bit time, aka Unit Interval, of about 104 usec i.e. about 10 times the electrical 2 way cable time. That is 9,600 Baud is a low frequency signal even for a 1 km long cable. The 1 km long single mode optical cable that runs the length of the string has a refractive index of about 1.45 so it too will conduct information with a velocity of about 2/3 c i.e. it has a group velocity of about 2/3 c. So both the optical and electrical signals in the main cable probably travel at about the same velocity. 1 km at a velocity of c is about 3.336 usec. Recall that c is about 299,792,458 m/sec. The velocity of light in sea water is about ? 11-July-2023: ------------- Review some of the details about the LPC845 uProcessor for the Emergency Rescue: - When operating from 3.3 Volts: the Min High voltage input is 0.7 VDD = 2.31 Volts the Max Low voltage input is 0.3 VDD = 0.99 Volts - The Pull-Up current is 50 uAmp Typ 85 uAmp Max Pull-Down current is 50 uAmp Typ 150 uAmp Max - So the absolute maximum value of a Pull-Up resistor that can over come the Pull-Down current is 6.6k Ohm. and the absolute maximum value of a Pull-Down resistor that can over come the Pull-Up current is 11.6k Ohm. - Pin assignments as used for the DK's ER Circuit: Pin Function As Used on DK ER Circuit --- ------------------------- -------------------------- 1 PIO0_13/ADC_10 -OK 2 PIO0_12 Fixed ISP Mode on page 2 3 PIO0_5/RESET_B Fixed RESET on page 2 4 PIO0_4/ADC_11/TRST/WAKEUP Fixed TRST on page 2 5 PIO0_28/WKTCLKIN -OK 6 SWCLK/PIO0_3/TCK Fixed SWCLK TCK on page 2 7 SWDIO/PIO0_2/TMS Fixed SWDIO TMS on page 2 8 PIO0_11/I2C0_SDA -High Current - Open Drain 9 PIO0_10/I2C0_SCL -High Current - Open Drain 10 PIO0_16 -High Current 11 PIO0_27 -OK 12 PIO0_26 -OK 13 PIO0_25 Default UART_0 Tx 14 PIO0_24 Default UART_0 Rx 15 PIO0_15 -OK 16 PIO0_1/ACMP_I2/CLKINTDI Fixed TDI on page 2 17 PIO0_9/XTALOUT -OK 18 PIO0_8/XTALIN -OK 19 VDD Fixed 3V3 on page 2 20 VREFN Fixed GND on page 2 21 VREFP Fixed 3V3 on page 2 22 PIO0_7/ADC_0 -OK 23 PIO0_6/ADC_1/ACMPVREF -OK 24 PIO0_0/ACMP_I1/TDO Fixed TDI on page 2 25 PIO0_14/ACMP_I3/ADC_2 -OK 26 PIO0_23/ADC_3/ACMP_I4 -OK 27 PIO0_22/ADC_4 -OK 28 PIO0_21/ADC_5 -OK 29 PIO0_20/ADC_6 -OK 30 PIO0_19/ADC_7 -OK 31 PIO0_18/ADC_8 -OK 32 PIO0_17/ADC_9/DACOUT_0 -OK 33 VSS Fixed GND on page 2 The 17 pins above labeled with "OK" are the first choice pins to assign to the 14 pin functions needed on page 1 of the DK's ER design. At RESET all 17 of these pins are setup as Inputs with their Internal Pull-Up current source enabled. 7-July-2023: ------------ Quick Friday afternoon meeting with Nathan. Reviewed: - The ER itself must control the RS-485 Transmit Enable because only it knows when it needs to talk. - At power up, to confirm that the ER is working, one could "ping" each ER as its Module is being turned ON and then either tell it not to transmit for the next N minutes, or assign it an ID number so that it from then on it only responds to messages sent to it. - Yes, the only connection from ER to the TOMCat is its UART. - We will dump the I2C connection between the DK's FPGA/CPU and the ER uProcessor. This connection was to provide a second data path to re-program the ER uProcessor but that does not make a lot of sense, i.e. if the RS-485 path is not reliable enough to re-program the ER uProcessor then it will never work in an emergency to re-program the Flash Boot/Config memory for the DK's FPGA/CPU. - Dumping the I2C path between DK's FPGA/CPU and the ER's uProcessor forces us at initial power up to program the ER uProcessor via RS-485 but that is GOOD becaue it forces us to test something that will only really be needed in an emergency. - Yes, it is the In System Programming method that will be used to program and if needed re-program the ER uProcessor. Entering the ISP mode requires, assert Reset, assert the I want to wake up in ISP Mode pin, release Reset, i.e. it requires 2 GPIO signals from the DK's FPGA/CPU (along with CPU_IS_SANE). - Yes, we will use the fixed Tx and Rx pins for the UART0 for the connection to the RS-485 transceiver. --- - Yes, just as long as the first string can get epon AD9546 timing in the base junction box then DK can be a single design - independent of whether the Enet data connection is 1000Base-T or EPON. - Blocks removed: Switch Yard, GPIO Expander for the Switch Yard, Copper Enet, concern about the Terminators for the Copper Enet and the Copper Timing, TDC7200s, and the SPI Mux connection for the TDC7200s. - New Current understanding of the I/O pins needed on the ER uprocessor: All are 3V3 CMOS level ER_UPROC_SANE 1 GPIO ER_UPROC_SANE_B 1 GPIO ER_TAKE_OVER_SHORE_COMMAND 1 GPIO ER_SPI_BUS 4 SPI ER_UART_to_TOMCat 2 UART3 ER_UART_to_DK_CPU 2 UART2 ER_UART_to_HEADER 2 UART1 ER_UART_to_RS_485 2 UART0 Tx pin 13 Rx pin 14 ER_ENABLE_RS_485_TX 1 GPIO ER_ENABLE_ISP_MODE 1 pin 2 ER_RESET 1 pin 3 ---- Total 18 signals - Nathan has a new cleaner way to setup the connections on the AD9546: Timing SFP Rx signal to Ref_A TOMCat 125 MHz Ref to Ref_B TOMCat 1 pps Marker to M Copy of the Flash Now to M Interposer_1 TDC Stop to M Interposer_2 TDC Stop to M ADC Clk comes from Out_0A ADC SysRef comes from Out_0B Timing SFP Tx signal from Out_0C FPGA HS Serial Ref Clk from Out_1A Extra Clock to FPGA from Out_1B The Interposer TDC Stop signal will be buffered and made available in either polarity. 5-July-2023: ------------ In the scrum meeting this afternoon Nathan described using an epon type technology to distribute the clock information from the base junction box to the 20 modules in a string. A question about this setup is needing to make a "central office" board to go in the base junction box. Another point is that using epon timing distribution: allows us to dump the following from the DK board: the Copper Timing Cable Switch Yard, the I2C GPIO Expander to control the Switch Yard, the TDC7200 TDSs, the SPI buffer connection to the TDC7200s which gives up a clean SPI Controller that connects to just the Interposers. Had a short meeting with Nathan and looked over some of the current drawings - including the first draft of the Emergency Rescue system. We discussed the Emergency Rescue: - Yes, we can operate the LPC845 on 3V3 so that its SPI bus can connect directly to the FPGA Boot/Config Memory. - The logic for the ER to take over the FPGA Boot/Config Memory will be: CPU is Not Sane AND ER is Sane AND Receive the Command from Shore to Take Over AND the ER has been running for at least long enough so that we are not in the initial thrashing at power up. - Yes, the RS-485 link will be operated Half-Duplex. - The logic to turn ON the RS-485 Transmitter will be: ER is Sane AND ER wants the Transmitter turned ON. Need to discuss with Nathan because he wanted the DK's FPGA/CPU to be in charge of RS-485 Tx Enable. - Yes, the 1 mA Receiver will be ON all of the time. - Yes, the THVD1410 transceiver tentatively looks OK and it is understood that this like will be slow, e.g. 9600 baud link 1 km long. - The ER will NOT have an ID Number, it will not have something like a DIP Switch on the board. Rather if we need the ER to recover a Module (or just want to talk to a given ER) we will just turn OFF the other 19 Modules. - The DK's FPGA/CPU has a unique ID number inside the device itself (like the Xilinx Ultra Scale). Need to verify that this Microchip FPGA/CPU has an internal ID number that is visible to: JTAG, to the FPGA, and to the CPU. - Nathan wants the HVQFN32 package, i.e. no expansion into voltage monitoring or stuff like that, and he understands that this could become an out of control sand box. - Yes, the 1% accurate internal clock is OK - nothing else needed. - Power up is not controlled, i.e. as soon as the BULK_3V3 bus is up then the ER will come up. Note specifically that the ER will be up before the DK's FPGA/CPU has come up or has declared that it is Sane. ER must NOT take over at this point. ER must wait and give the DK's FPGA/CPU a chance to come up. - Need to focus the design on not allowing the ER to become a single point of failure that can kill the whole module. - The ER uprocessor will not run an operating system, it will just run its 100 lines of c or assembler. - Discussed the need at power up for ER to negate its Take Over signal and negate its Enable Transmitter signal before asserting its Sane signal. - Nathan wants the DK's FPGA/CPU to be able to re-program the ER via an I2C link between the DK FPGA/CPU and the ER. This setup also requires the FPGA/CPU to assert a signal to a pin on the ER uprocessor to tell it to re-program itself. This signal will need to be well protected, e.g. DK CPU must be asserting that it is Sane. - This connection between DK FPGA/CPU and ER uprocessor looks risky to me but Nathan is worried about the RS-485 link being too slow or noisy to reprogram the ER uprocessor. Are there any chicken-egg or dead lock type issues ? What about at power up ? Is there a master slave issue on the I2C link between DK's FPGA/CPU and the ER uprocessor or an I2C address issue ? - On DK's FPGA/CPU he would like to instance another I2C controller in the FPGA fabric and have it use 3V3 I/O and have it talk with the ER uprocessor and with the DK's SFP cages, i.e. move the DK's SFP cages off of the I2C bus that runs the Timing Generator. - Current understanding of the I/O pins needed on the ER uprocessor: All are 3V3 CMOS level ER_UPROC_SANE 1 ER_UPROC_SANE_B 1 ER_TAKE_OVER_SHORE_COMMAND 1 ER_SPI_BUS 4 ER_UART_to_TOMCat 2 ER_UART_to_DK_CPU 2 ER_UART_to_HEADER 2 ER_UART_to_RS_485 2 ER_ENABLE_RS_485_TX 1 ER_ENABLE_RE_PROGRAM 1 ER_RE_PROGRAM_I2C_BUS 2 ---- Total 19 signals Must check check the fit of these 19 signals in the HVQFN32 package. 26-June-2023: ------------- Nathan has a very clean way to eliminate the copper links, use epon for both the Enet communications between each module and the base and use epon for the timing link between the base and the AD9546 Timing generator in each module. This scheme cleans up lots of things: no copper, independent (logically) optical link from base to each module, less parts --> more reliable, realization that the base + modules is that exact use case for pon, exact same timing signal to each module - better and easier to understand timing, less power, 22-June-2023: ------------- My list of decisions and action items from the 30 questions- points meeting with Nathan on 21-June-2023. 1. Required crystal clock oscillators: this is still a topic of discussion, 125 MHz *may* be enough for all of FPGA/CPU, coming in through a High-Speed Transceiver Reference Clock Input may work. 2. Barnacle: official decision - DK will only have a connector, no bluetooth or induction power supply, the connector needs: Gnd, Power, Reset (Power Down) MMUART2 Tx and Rx, Clocks for Bluetooth 26 MHz and 32.768 kHz. The Barnacle bluetooth and inductive power stuff if it ever exist will be on a separte board. 3. DK connection to RS-485 Emergency Rescue: MMUART1 on the DK's FPGA/CPU will connect to a UART on the RS-485 Emergency Rescue and the Emergency Rescue will be able to take control of the DK FPGA/CPU Bank 3 SPI Bus, i.e. the Emergency Rescue can reprogram the DK's FPGA Config Boot Memory. TBD how to control the "gate" from the Emergency Rescue to the Bank 3 SPI Bus. 4. TOMCat JTAG Pins: don't know, Nathan will ask, to a header ? 5. TOMCat to Emergency Rescue: I think just a UART connection ? 6. TOMCat LVDS Pair for 125 MHz and 1 pps marker: Nathan will ask 7. Separate FPGA and CPU config-Boot PROMs: Yes keep both of them. 8. Numbering of Main Cable Quads, Pairs, and Modules: Module numbering starts at 1, Module #1 is at the Bottom, Some one else is worrying about Quad/Pair labels and the assignment of signals/power/ground to them, don't know who is working on this, Nathan thinks that they are doing an OK job. 9. CPU Peripherals to package pins: Yes, I will lay this out based on my understanding of Microchip rules and then Nathan and Rob will check. 10. MMUART layout: It looks OK, keep MMUART0 to a header, it should be 3V3 not RS-232. 11. Environmental Sensors: Yes use the Bosch and STM parts, that is a final decision, get engineering sample parts now to verify their layout. 12. Express concern about the switching noise on the long cables causing trouble for the copper timing and Enet signals: Nathan is not worried. 13. All Power Good Supervisor: Yes dump it for a 1 second delay, intent is it is more reliable and that we gain no functionality from actually checking the voltages, there is a middle ground of doing both. 14. Resets to sub-sections is also the Power Down: Yes, Nathan understands. 15. Need to delay action after removing the Reset to a sub-section: Yes, Nathan now understands. At startup, need to set the Resets before asserting that the CPU is SANE: Yes, Nathan now understands. 16. PMT Analog signals will get: Clamp Diodes, Balum Trans, and Shield Gnd Pads: Yes, Nathan now understands and agrees. 17. Correct generation of Clocks by the FPGA for External Consumers: Yes, Nathan now understands. 18. TDC Clock is now 10 MHz: Yes, Nathan now understands. 19. Requirements in the DK design and layout to enable it to recover clock and marker from optical link: Need to verify this with Michael, Need to include jumpers on the DK pcb. 20. Rational speed UART, SPI, I2C: Yes, Nathan agrees and said that the software is 100 kHz I2C which matches the BB Audio ADC. 21. Same basic I/O Expander is Switch Yard as on Interposer: Yes, Nathan now knows - agrees. 22. No CPU controlled Reset to I/O Expanders: Yes, Nathan now knows and agrees. 23. All Interposer to FPGA/CPU connections are buffered or clamped: Yes, Nathan now knows and agrees. 24. Terminations on the Copper Links: Nathan now knows of this design issue, no decision made. 25. 2x Unused BB Audio ADC inputs: Yes, run these to the Interposer connectors, include jumpers. How much to fluf up the DK Interposer connections vs the 20 pin minimalist design on the Interposer: Yes, Nathan agrees, let's do this only once so: full differential connection to the BB Audio ADC Inputs, Single Ended of Differential "Flash Now" signal, 2nd BB Audio ADC Input, jumpers included for selection where needed. In an associated note about the BB Audio ADC Inputs: Nathan wants the full size low frequency AC coupling caps, not 10 kHz cut off caps. 26. 16 Gbit DDR Memory, 16 bits wide: Nathan now knows the issue and agrees to push forward with this size part. The associated pcb routing issue was discussed and a follow up note sent to Nathan, current understanding is that you can swap DQs within a byte lane but maybe not DQ0. 27. DK Block Diagram: OK but its missing the DK's SFP. 28. Review: OK understand that the description must be unique and no significant changes from a review before the detailied design work can start, yes - the best plan at this stage is to be careful and get Rev A correct. 29. Detailed Layout Start Requirements: OK, Nathan understands 30. Dump the copper timing and Enet links: No Other Points that I learned about: 1. The AD9546 Timing Generator outputs to the PMT-ADC and to the Transceiver Reference Clock Input are currently 156 MHz. 2. One may be able to use the Transceiver Reference Clk Input to ingest clocks for the FPGA/CPU or to ingest reference clocks for the CCC blocks in the FPGA/CPU. 3. Add Pull-Up, Pull-Down to the CPU_IS_AWAKE and _B GPIO signals. Drw 8. 4. Add Balun and Clamps to PMT-ADC Input Drw 10. 5. Add SPI Bus Selector Switch to the Bank #3 SPI connection to the FPGA Config/Boot Memory. Still not clear what controls this switch. Drw 12. 6. Timing Gen AD9546 will have its own rock. Drw 15. 7. USB needs a normal Type A connector. Drw 18. 8. A question that I forgot to ask is does the 1 V p2p version of the 10Base-T1L make it throug 50 meters of the actual main cable. Some 10Base-T1L length performance measurements have been made with pretty fancy foam cable ? Do we need a setup to control which end of the 10Base-T1L is Master and Slave at the link startup ? 9. Add max inductor currents to: Drw 2, 3, 17, 19, 20, 22, 23, 30?, 34, 36, 37, 42, 43 10. I need to make a view of the power feed to the FPGA/CPU and its Banks in graphical form. 11. Add SFP to block drawing Drw 40. 12. The SFP TX_Fault, TX_Disable, RX_Los all got to 3V3 FPGA GPIO - not to CPU GPIO. It's not clear what to do with the MOD_DEF0. Drw 42. 13. Need to add the 2 Clocks to the Barnacle connector in Drw 43. 14. This is an approximate description (obtained verbally from Nathan) of the RS-485 Emergency Rescue circuit: - It is an NXP LCP845 Arm uprocessor. Of the 8 versions of this part number available I will for now choose: Full Part Number: LPC845M301JHI33 Package: HVQFN33HVQFN Description: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 5 x 5 x 0.85 mm Flash KB: 64 SRAM KB: 16 USART: 5 I2C: 4 SPI: 2 DAC: 1 GPIO: 29 - The USARTs are used for: RS-485, TOMCat, DK FPGA/CPU, Header, and one spare - One SPI is gated to the DK's Bank #3 SPI bus so that the RS-485 Emergency Rescue can reprogram the DK's FPGA/CPU's Config-Boot Memory. - Big issue, under what conditions should the Emergency Rescue be allowed to take control of the DK's Config-Boot memory and how will it accomplish this, and how to prevent this from happening. - There was a hint that the Emergency Rescue should be allowed to "Reset" the DK's FPGA/CPU and I assume the other DK components, but you can do this via a power cycle if necessary. How to prevent the Emercency Rescue circuit from getting stuck with its Reset to the DK FPGA/CPU stuck asserted. - There was a hint that the DK should be able to reprogram the Emergency Rescue uprocessor - but no details about how this should work or keep from getting stuck. - There is the issue / question of how to control the power to the RS-485 transceiver, this transceiver will probably use significant power and we do not want to run it all of the time. - There is the issue / question of how / when the Emergency Rescue system should take control of the FPGA/CPU Config -Boot PROM. For examle of possible conditions before the Emergency-Rescue system break in: the FPGA/CPU has NOT asserted that it is Sane AND the Emergency-Rescue has asserted that it is SANE AND human initiated commands from shore have told the Emergency-Rescue system that it should take over. 6-June-2023: ------------ From the review of the PMT Base I now understand that the base's serial port with the 3 stage RC filter is the serial Output from the base and is pin 6 on the base's connector. The serial Input to the base is its connector pin 8 and runs through a 10k Ohm to the serial input pin of the uprocessor. Previously they have used PRTR5V0U2AX protection doises on the two serial lines, BAV99W diodes, 2x in series, in both directions, on the analog signal, and FPF2124 load switches. 2-June-2023: ------------ As the detailed design moves forward we will postpone some decisions, e.g.: - What clock sources will feed the FPGA/CPU and what clock inputs will be used - Will we use separate Configuration PROMs for the FPGA and for the CPU (which is now possible with the newest boot setup for the MPFS250T The designs are in for the two sections of the DK that use copper connections: copper Enet and the Cable Timing signals. But, there is the big issue of how fancy of the termination schemes should be for these two sections is still an issue. - The Enet could be as simple as capacitor coupling, or capacitor coupling with high resistance to ground on the floating cable, or full featured - balun, transformer coupling, common mode load, high frequency filter, and transit voltage protection. E.G. starting from the input, the Enet termination could include: on each side 47 pFd to Gnd, 4.7 Meg Ohm to Gnd, two series CDSOD323-T24SC TVS diodes, 470 uH common mode Balun 744242471, on each side a paralled 100k Ohm 0.47 uFd to the isolation transformer 74930000, series 100 Ohm 1 nFd from primary center tap to ground, 100 nFd from the secondary center tap to ground, 150 pFd from each side of the secondary to ground. - The copper Timing Cable is M-LVDS level and the termination scheme could be as simple as DC coupled with 100 Ohm shunt termination for the normal mode, or it could be very complicated: capacitor coupled, normal mode termination, common mode termination, supply common mode input voltage, pull the floating cable to ground with Hi value resistors, and transit voltage protection. I must double check that the signal on the copper Timing Cables is DC balanced. There are associated open questions: - What is the actual Zo of the cable, I understand that this Quad cable. - Can we have enough wires in the cable to lock the Signal Ground to a common potential in all modules, i.e. zero common mode voltage between modules. - How do we discharge the cable during final assembly. - Is the any ESD risk during operation, e.g. an lightning strike during use or during shipment - How can we organize the Quads and the pairs within a Quad to help control the: noise, Zo, cross-talk, 30-May-2023: ------------ Interposer "Preliminary Final" design review. Some questions: - If there are critical timing signals, e.g. Flash_Now, should they be Differential, e.g. LVDS, instead of single ended ? - Are there missing pull-up or pull-down resistors on the UART lines to the individual PMT Bases ? - The PMT base looks like it is running from 3.3V for both it uproc and HV section. Would it be better to run from 1.8V for the uproc and 5.0V for the HV ? - What is the common DC resistance from the DK to the PMT Bases ? Is that enough to start an oscillation ? - Is the Flasher Control Reset for U3 MCP23S13 coming from an I/O on U1 (another MCP23S17) OK, i.e. at power up the state of U3 can not hang up communications to U1 ? 26-May-2023: ------------ Look at the output characteristics of the AD9546 Timing Generator vs the input requirements of the various loads on the timing generator outputs, e.g. Clk and SysRef inputs of the AD9083 ADC. The AD9083 has a permanent internal 100 Ohm terminator (not center taped), has an internal 0.5 V common mode supply connected to its inputs through 172k Ohm resistors, wants a typical Vpp input of 700 mVpp, wants capacitor coupled inputs for the Clk signal (implying that 0.5 V common mode must be good or optimal), and claims that it is compatible with generic LVDS. So a question is what is the best value of the Pull-Up resistors to use at the outputs of the AD9546 timing generator to drive the "clk" inputs of the AD9083 ? The following table is for a 7.5 mA current Sink with the pull-up resistor to a 1.8 V rail. Pull-Up Differentail Common Mode Ohms Input mV Input V ------- ------------ ----------- 50 188 1.613 100 250 1.425 200 300 1.050 270 316 0.788 300 321 0.675 330 326 0.563 360 329 0.450 390 332 0.338 So for a working design let's pick 300 Ohm pull-up resistors (which can drift +- 10% with little change) and can be used with either AC or DC coupling and will provide a 642 mVpp input to the "clk" receiver. 24-May-2023: ------------ Reasons to question the use of Copper Timing and Enet between adjacent modules: - Cost - Reliability - Sole Source parts - Manufacture over a long time period - Distracts the focus of the DK design from the things that matter (PMT signal quality) to a bizarre and unnecissarily complicated timing scheme - Complicated un-clean software for now and for all future versions - Bizarre timing schemes can distract from the Quality of the Physics Data - Power consumption - prove that this complicated setup lowers it by a meaningful amount - This complicated setup makes testing each module much more complicated - Future collaborators will not understand how this thing works - It's not a modern rational system - No timing tests with real noise have been done. 3-May-2023: ----------- Summary of the meeting with Nathan yesterday and the subsequent emails and a summary of my understanding of the current Interposer design: 1. The ADIN2111 Ethernet Switch & Phys will be setup for 1 Volt signaling and use the lower voltage supply rails with its internal regulators which also means that holding this part in Reset will actually power it down. 2. We will study using a eMMC memory for the CPU Boot Memory. If eMMC and SPI memories have the same reliability then moving the CPU Boot Memory to eMMC will help clean up the SPI Controller connections. Using either eMMC or SPI (SPI must be on the QSPI Controller) are equally easy with the vanilla Linux for the MPFS250T. 3. The tentative arrangement of SPI Controllers and SPI Targets is the following: CPU QSPI Controller <---> ADIN2111 Ethernet Swch & Phys this is a private connection CPU SPI Controller 0 <---> via buffers to both Interposers CPU SPI Controller 1 <---> AD9083 PMT ADC with a 4-Wire to this is a private connection 3-Wire converter in the FPGA fabric FPGA SPI Controller <---> TDC7200 Time to Digital Converter IP in the fabric and any other SPI targets on-board the DK that may materialize 4. The currently known need for CPU GPIO lines is at least 29. CPU GPIO Blocks 0 and 1 can only connect to CPU I/O pins, i.e. pins in Banks 2 and 4, and thus are harder to route on the pcb. We will try to stay away from using CPU GPIO Blocks 0 and 1. CPU GPIO Block 3 has 32 signals and can connect to FPGA I/O pins. These Block 3 CPU GPIOs can be used as SPI CS_B signals when connected to FPGA I/O pins without extra software work. We will heavily use the Block 3 CPU GPIO. 5. Because we will likely need more than 32 CPU GPIO signals, we are taking the decision to move the 12 control signals for the "Cable Timing Signal Switch Yard" from being directly sourced by CPU GPIO Block 3 to being sourced from a 16 bit I2C GPIO "Expander". This I2C GPIO Expander will be on the same I2C bus as the AD9546 Clock Generator. A candidate part for this expander is the MCP23017, i.e. the I2C twin of the MCP23S17 SPI expander that Adam uses on the Interposer. 6. The BB TLV320ADC6140 Audio ADC will be operated on an I2C bus. Besides this Audio ADC, the other I2C bus targets on the DK board are the: AD9546 Clock Generator and its associated GPIO Expander Accelerometer Magnetometer DK's SFP Cage monitoring connection The MPFS250T has two I2C Controllers. The 6 I2C targets will be assigned to the two I2C Controllers based on: Core Physics Operation Components, i.e. Clock Generator and its GPIO Expander vs Peripheral Components, i.e. Audio ADC, Accelerometer, Magnetometer, SFP Cage and based on FPGA/CPU Bank Voltage vs Device I/O Voltage and based on Non-overlap of I2C Addresses 7. Connection to Interposer: The PMT analog signals are not carried by the Interposer or DK's connector to the Interposer cable / flex circuit. We want a separate connector for each Interposer and to have these 2 connectors symmetrically located along the "top" edge of the DK. One of these connectors will be wired backwards compared to the other. We will use a connector that can be plugged in "normally" or rotated by 180 degrees. We want a rational size connector that is physically strong enough for this application, can be easily plugged in during final assembly, latches in place, and can be unplugged if necessary without risk of damage to the DK or to the cable that runs to the Interposer. A 2 row 2mm pitch 90 degree 50 pin shrouded header with latches fits these requirements for the DK. A matching receptacle without a polarizing key fits these requirements for the cable to the Interposer. Such a connector is electrically appropriate for all of the power, ground, and signal types that flow between the Interposer and the DK board. On the DK we will talk with the Interposers in a uniform way using 4 Address lines, 1 SPI Controller, and 1 UART. Between the source of the Address, SPI, and UART signals in the DK's FPGA/CPU and the two Interposers there is a tri-state buffer for each Interposer. These two tri-state buffers are controlled by the high order Address line. 8. My understanding of the current Interposer design: On the Interposer the 3 lower order Address Lines are used to control which of the Interposer's 7 SPI Targets will actually receive the single CS_B signal from the DK board's SPI Controller. I believe that the 7 SPI Targets on each Interposer are: 3x MCP23S17 SPI to GPIO Expanders 16 bit 2x DAC53204RTER 4-Channel 10-Bit DAC 1x DS1023-25 8-bit programmable delay line 1x SFML-105-01-L-D-LC A Connector taking the SPI bus to the Piezo module or board Because of the large capacitive load from these 7 chips at the end of the DK to Interposer cable it is wise for DK to use a separate buffer to drive each Interposer. On the Interposer I believe that the 3 lower order Address Lines are NOT used to select the target of the UART connection. Rather I believe that one needs to use the Address Lines to select the correct SPI to GPIO Expander and then do an SPI write cycle to set this Expander's output signals that control a TMUX1208RSVR multiplexer which connects the DK's UART to the desired target (i.e. to the desired PMT base). The UART multiplexer is a TMUX1208RSVR which is just and analog switch type of mux, i.e. not a buffered digital mux. I do not know if there is some reason why the 3 lower order Address Lines are not used to directly control the UART mux, i.e. to select which PMT Base the UART is talking to. 12-Apr-2023: ------------ Meeting with Nathan - a few points: - DK needs an SPI memory on one of the normal CPU SPI buses to hold code for the CPU startup. The first level boot for the CPU comes from the 128 KByte eNVM that is part of the FPGA/CPU chip itself. The second part of the boot for the CPU will come from this SPI memory that is attached to one of the CPU's SPI buses. There are 2 normal SPI bus controllers and one QSPI bus controller. I *think* that the QSPI can also back off and do normal standard SPI with the Chip Enable coming from a normal CPU GPIO. - Yes, DK still needs to have the TDC chip on it. - Still not clear whether or not we need a 125 MHz clock to the MSS Reference Clock Inputs of Band 5. Note that this is a reference clock input that can be used for both the SGMII Enet MAC and as a reference for the whole set of PLL clock generators for the CPU section of this chip. - Should we think that TOMCat is by default turned On and that DK can turn it Off - or that it is by default Off and DK can turn it On. - The fixed location of the CPU's USB in Bank 2 is not real USB rather it is the ULPI (universal low pin count interface) version of USB. I will work on a design with the USB3340 external USB physical layer "PHY" chip. I think that the Bank 2 to Phy could use with 1V8 or 3V3 I/O. - Fuses although there is not a fire hazard once in place there are still at least 2 reasons to fuse the power to various sections of the DK board: avoid damage (or undetected damage) to a part of a DK board during Final Assembly and Testing and once in service to allow as much as possible of the DK to keep running when there is a power supply fault in some section. Possible locations for fuses: JTAG Connector, USB Connector, any section off of the Interposer that we could run without, at the power feed to each Interposer (so that with a power supply short on a given Interposer we could continue to run with 8 PMTs on the other Interposer). 15-Mar-2023: ------------ More work on what will connect to which Bank, which Banks will basically not be used, power fill plan under FPGA/CPU, and pcb stackup. I need more input from my betters. My current plan is: Bank Bank Type & Pins Function on Disco-Kraken ---- ---------------- ------------------------------------------ 0 FPGA HSIO 84 FPGA DDR4 Memory 1V2 1 FPGA GPIO 72 OK to use 1V2, 1V5, 1V8, 2V5, 3V3 2 CPU IO 24 best/only CPU I/O 1V2, 1V5, 1V8, 2V5, 3V3 3 JTAG Fixed 13 1V8, 2V5, 3V3 4 CPU IO 14 best not to use 1V2, 1V5, 1V8, 2V5, 3V3 5 CPU SGMII 10 2x RX, 2x TX, 1x Ref Clk 2V5, 3V3 6 CPU DDR4 88 CPU DDR4 Memory 1V2 7 FPGA GPIO 24 best not to use 1V2, 1V5, 1V8, 2V5, 3V3 8 FPGA HSIO 60 mostly blocked 1V2, 1V5, 1V8 9 FPGA GPIO 84 OK to use 1V2, 1V5, 1V8, 2V5, 3V3 FPGA DDR4 completely uses Bank 0. CPU DDR4 completely uses Bank 6. Access to Bank 8, the only FPGA HSIO Bank, is mostly blocked by routing between Bank 0 and Bank 6 and their DDR4 chips. Banks 1, 7, and 9 are all FPGA GPIO with Banks 1 and 9 being completely in the clear. It would be best to stay out of Bank 7 unless it is needed. Banks 2, 4, and 5 are all CPU I/O with Bank 5 being dedicated to two channels of SGMII. All other CPU I/O, e.g. SPI, I2C, must run through CPU I/O Banks 2 and 4. Minimizing the use of Bank 4 will make for a cleaner layout. Bank 3 is the JTAG and other Fixed locations and we must have access to it. 14-Mar-2023: ------------ The DDR4 Terminator and Reference supplies for both the FPGA and CPU are now in and their drawing (#6) was brought up to date. Reader's guide to the Polarfire Packaging and Pin Description User Guide vb.pdf pg 3 List of the Banks in each package pg 6 View of the Banks it must be from the bottom pg 14 Description of the In Package Capacitors pg 20 Drawing of the MPFS250T FCVG784 Package pg 31 Thermal Data pg 35 Thermal aspects of the Package and design pg 38 PCB Design of the BGA Pad (not via pad) Made a pin layout drawing to help understand the layer count. The Transceiver area will need at least 3 power planes. The Bank 0, the PLL / PNVM, and the Prog / HSIO Aux are all basically on top of each other. It's not good to bring the various power rails to the FPGA from its East because of the ADC and its high-speed serial I/O. The Transceiver Power Rails (Filtered) will need to come in from the East. It's not good to bring the various power rails to the FPGA from its South (except for DDR4_1V2 and maybe VDD_2V5 raw) because of the high use by the DDR4 layers and the Bank 8 escape. That leaves North and East which contain everything else. 13-Mar-2023: ------------ Current list of the Reference Designator map for the DK board: FPGA/CPU & Immediate Comps. 1 : 99 FPGA DDR4 Memory 301 : 399 CPU DDR4 Memory 401 : 499 PMT ADC Itself 601 : 679 PMT ADC Input Circuit 681 : 839 Power Input & 100 V to 5 V 1651 : 1669 PS Startup, PS Good, Resets 1671 : 1699 DCDC1 VDD_ADC_1V0 1701 : 1729 DCDC2 VDD_CORE_1V00 1731 : 1759 DCDC3 VDDA_XCVR_1V05 1761 : 1789 DCDC4 VDD_DDR4_1V2 1791 : 1819 DCDC5 VDD_BULK_1V8 1821 : 1849 DCDC6 VDD_BULK_2V5 1851 : 1879 DCDC7 VDD_BULK_3V3 1881 : 1909 FPGA_DDR4_REF_TERM_Supply 1921 : 1939 CPU_DDR4_REF_TERM_Supply 1941 : 1959 Constant 3V3 Supply 1971 : 1999 10-Mar-2023: ------------ Put in full set of comps and nets for the FPGA memory. Now at: Comps 538 Nets 439 Conn 1447. 9-Mar-2023: ----------- All of the CPU aka MSS 4 GByte memory components are in including all terminaors and bypass caps. Moved the FCVG784 geometry to pick up its BGA Pad Only pins from the single point nets in the sorted net list file. First look at the BOM for DK and I have a couple of part numbers to clean up. The BOM generator order is (I think): Both, 1 Item, 2 Company, 3 Geom (optinal), 4 Count, 5 Reference Desig. and 1 Ref Desig, 2 Company Part Numb, 3 Geom (optinal). Must verify. 8-Mar-2023: ----------- Had a quick mid morning visit with Nathan and a first visit to his lab - a pre stem building teaching lab. The big scope on the PDP LSI 11-03 cart is there. He is going to get his AD test setup working, with the ADC Demo board that I got from Robert. We will verify that it works and then I will modify 3 or 4 channels on it. Modifications will be by small steps to the input circuit with DC offset. E.G. start with just two equal resistors to give 0.7 V DC common mode and zero normal mode. Must verify noise level. Talked about items that must work at Rev A and need for FW and pcb to match and need of FW info for pcb design vs their documentation. 7-Mar-2023: ----------- I got new versions of the MSS Technical Reference Manual and of the MPFS250T FCVG784 Package Pin Table. I now have finally found the DDR4 PAR signal on the MSS (aka CPU) DDR Controller. It is listed in the overall pin list as MSS DDR PARITY pin U6 but is completely missing from the DDR4 pin list. The ALERT_B pin is pin V6. Their documentation is not good. Still need to verify that their DDR4 Controller will work with the proposed MT40A1G16 memory parts 16 Gbit parts 1 G Addresses by 16 bits wide one chip devices. 3,6-Mar-2023: ------------- More email notes with Nathan about the PMT signals. All of this data was moved to the web in the nathan info section or the PMT analog input circuit section. It looks like a very tight fit to get both the biggest signals and the smallest one photo-electron signals into the 12 bit dynamic range. Saturation of the biggest signals will likely be needed as the smallest one photo-electron signals are imporatant to the Physics. Exchange another set of notes with Felix about the fast PMT on the DK Brd and its input range. 2-Mar-2023: ----------- Move the FPGA, ADC, and 96 pin Memory geometries to all use the same set of Pin-Pad Stacks. These are the 3 geometries BGA 0.8 mm pitch in the DK design. For all members of this set of Pin-Pad Stacks move the BGA Pad Solder Mask opening from 0.52 mm to 0.48 mm and move the Via Drill from 0.20 mm to 0.23 mm. This puts us in the middle of what looks rational. The Via Drill diameter will be fully controlled by the board house anyway. I've also rotated the geometry for the 96 pin Memory devices so its long axis is now horizontal with pin #1 in the North East corner. 28-Feb-2023: ------------ I want to make the geometries for the FPGA/CPU and the memory chips a bit closer to their final version. Review some examples of NSMD 0.8 mm BGA layouts: Xilinx: BGA Pad dia 0.40 mm Solder Mask Opening 0.40 mm Via Pad dia 0.48 mm Finished Hole dia 0.25 mm BGA Pad to Via Pad distance 0.56 mm For the Power Fills inside the board they use a Drill Edge to Copper distance of 0.20 mm and for 1 oz copper plane they allow 0.075 Amps per mil of narrowest fill width (0.050 Amps for 1/2 oz copper). NXP: BGA Pad dia 0.35 mm Solder Mask Opening 0.50 mm Via Pad dia 0.485 mm Finished Hole dia 0.25 mm Anti-Pad 0.695 mm Lattice: BGA Pad dia 0.35 to 0.40 mm Solder Mask Opening 0.50 mm Via Pad dia 0.40 mm Via Drill dia 0.125 to 1.150 mm and lots of pictures of complicated power fills. So what I've been using for the design studies for the 0.8 mm pitch BGA parts (FPGA/CPU, Memory, ADC) looks right in the middle of things for now, i.e. until we talk with a specific board house for this build. Move the FPGA/CPU and Memory to quadrant escapes to continue the DDR4 study. 27-Feb-2023: ------------ Return to more detailed work on the DDR4 memory systems. 24-Feb-2023: ------------ All of the components and nets are in for the fast PMT ADC. It all more or less looks rational but will take a significant portion of the 235 x 235 mm board. Some 0402 bypass comps can fit on the back side of the board under the ADC. I need to learn about whether or not the TRIG pins are actually needed (e.g. for some emergency use connection to the FPGA/ CPU) or can I make these pad only pins in the geometry. Currently have 338 components and 426 nets. 23-Feb-2023: ------------ I had an email from Felix Henningsen about the photo-diode and SiPM signals. I passed to him the current design for the fast ADC and a note about what it would be easy to handle on the DK board. 22-Feb-2023: ------------ Had a Jitsi meeting with Michael Boehmer to talk about the emergency recovery facilities that he would like to have in the system. - TOMcat itself has two memory devices to hold its bitstream. It uses one of them if the power has been Off for a long time (>10 sec) and it uses a different memory device if the power has only been Off for a short time (order of one second). I believe that the Lattice FPGA on the TOMcat is one that needs its bitstream to be loaded from an external device. - He would like a full criss-cross between the FPGAs on the TOMcat and DK boards. That is: GPIO signals from the TOMcat FPGA would go to the JTAG pins on the DK FPGA and GPIO signals from the DK FPGA would go to the JTAG pins on the TOMcat FPGA. One would need to consider the issue of the state of the GPIOs on an un-configured device (or a device with bad firmware) putting the JTAG lines going to the second device in such a state that the second device could not load its firmware and start up. If I remember correctly the default state of the JTAG lines is HI. - He would like an Emergency RS-485 line that runs from the base junction box up through all 20 modules. Each module just taps onto this RS-485 path with some kind of mico- controller. Each micro-controller would have an address so it would know when it was being talked to. This micro-controller would have the ability to reprogram the SPI Memory (or whatever) the FPGA uses to load its bitstream. For an emergency with the loading of the DK's CPU this micro-controller would have UART access to the "boot console" for the CPU's boot loader LILO or GRUB or whatever. There was discussion about whether or not this micro- controller should be another mezzanine on the main DK board. This is part of the general issue of folks having designed a bunch of sole source parts into the P-ONE designs and expecting to spread the build over perhaps 5 years - which just does not sound realistic. One would need to consider the issue of the micro-controller itself having some issue and hanging up the bus to the memory device and thus preventing the FPGA from loading its firmware and starting up. Wednesday Feb 22nd was also normal "Secret Club" P-One electronics meeting. I learned that there are two other signals that they want processed by the fast PMT ADC: photo-diode and SiPM. These two devices make some type of calibration signals and would only be installed in certain modules. All normal modules have 16 normal PMTs. I brought up using clamp diodes on thier worry about PMT HV getting into other parts of the system (vs the idea of using a special isolated power supply and optical isolators on all of the control signals to the PMT bases). I also brought up using a separate PMT Signal Coax Cable system and using the flex pcb for the "everything else" connections to the Interposer. Michael showed a small linux cpu board that he would like to use in the base junction box. 6:10-Feb-2023: -------------- Friday morning meeting with Nathan. Look at the TOPcat topics, talk about the need for more detailed understanding of the analog part of the PMT ADC and now plan to hack a channel or two of his ADC Demo board to implement the Offset scheme and to verify things like what AD means by Vpp Diff. Started a specific write up about the analog input to ADC. Emails with Michael. I now understand more about TOMcat and have access to the information on Confluence. There are still questions but I have made a silk only geom for TOMcat and for the required Samtec ERF8-025 connector. All in the design now. Questions about: power up of TOMcat when the module receives its 100 Volt power, all of the full mesh re-programming stuff. Topics for meeting mext Thursday. Michael's note says, 15 mm between boards, TOMcat uses ERM8-025-08.0-L-DV-TR and for DK ERF8-025-05.0-S-DV-TR but I think that for 15 mm stack height DK may need to use ERF8-025-07.0-S-DV-TR. Maded a first pass placement and net list for the Power Input Filter and the 100 V to 5 V converter. It looks OK for a first pass but could be compacted some more. Using 34 pin Horizontal header for the Main Cable. That may be a good idea as it prevents pressing down and thus flexing the card and it gives free unused space to bend the cable and it keeps the DK within the 30 mm height. Added or made the rest of the geometries to instance a full example of the DCDC converter as a Relatively Placed Component Set. It looks OK but can be compacted a little more. Right in the geom for the TI 3 and 6 Amp converters I was able to add "auxiliary pins" so that the converters Ground pin has multiple vias down into the Ground Planes. Verified that DK must fit within a 340.0 mm diameter circle and that its current square shape 235.0 mm on an edge gives an radial air gap of 3.83 mm at each corner of the DK board. At the center of an edge of DK, the radial distance to the perimeter of the 340 mm diameter circle is 52.5 mm i.e. about 2.067" of open free space to route cable or escape bend a fiber optic cable. 1-Feb-2023: ----------- I had about a one hour long meeting with Nathan to talk specifically about the Timing Generator and the PMT ADC. AD9083 PMT ADC: We will put the transformers on the DK and we will use DC offset of the signal into the ADC to recover dynamic range. Will need a "Split Secondary" transformer - probably a trifilar transformer and two new voltage references. Will use AC Coupled terminator e.g. 200 Ohm and 100 nFd good down to 20 usec aka 8 kHz. Will need the same 100 nFd and a good RF cap from the transformer center taps to ground. Nathan says that the longest pulses that they care about are 1 usec long. They do need lots of dynamic range so we will use only 10% of the ADC's overall dynamic range to go negative for the transformer core reset. He wants the ADC in its 1 Volt mode and I'm still confused about what that actually means. For now the PMT signals will use a dual inline 32 pin header 2mm or 2.54 ? For now the coax shields will not be grounded. The ADC's Clock comes from Timing Gen Out 0 A The ADC's SysRef comes from Timing Gen Out 0 B The ADC's Syncinb comes from FPGA Fabric I/O JESD204B section The ADC's Trigger is not used and pins should float. Timing Generator: Out 0 A to ADC Clock Out 0 B to ADC SysRef Out 0 C to FPGA for the High-Speed Serial Link Receiver Clock Out 1 A to the DS91M125 1 In - 4 Out Fanout and then to ??? Nathan wants power down of the DS91M125 Out 1 B Operated as two Single-Ended signals each signal goes to a Buffer, Buffer output is SE or Diff ??? Buffer outputs go to ??? Both the Ref A input and the Ref B input come from the Tom-Cat as a differential signal LVDS ??? Ref A input is a Clock Ref B input is a Marker M0 These 4 M signal are conncted to a M1 set of Up and Down drivers that I M2 do not yet understand. M3 (but I'm close) M4 to FPGA Fabric I/O pin M4 to FPGA Fabric I/O pin M4 to FPGA Fabric I/O pin can be Chip Select for SPI control Main Cable Connector: The splice is hidden from DK. DK gets a clean pig-tail coming to it with only the wires/signals that that module needs. We get to define the connector. The wires are about AWG 20. For now pick dual inline 0.1" 0.1" header. Yes, the signal ground runs through all modules and to the Bottom Juntion Box. Yes, we will use air gap pins around the +100V power. 1 pair to carry Power and Power Return Down Only 1 pair Signal Ground on both wires Up and Down 2 pairs Timing Up LVDS 2 pairs Timing Down LVDS 1 pair Enet Up 1 pair Enet Down 1 pair Emergency ReProgram RS-485 Up 1 pair Emergency ReProgram RS-485 Down Do we want to signal ground the unused pairs or let them float ? 30,31-Jan-2023: --------------- All work was in the basement. 26,27-Jan-2023: --------------- Worked on the power supply description. Except for typos and such it is finished for now. Now need to push PMT ADC and the copper timing circuit. 25-Jan-2023: ------------ 50% basement and work on the power supply description and clean up 3 of the power supply circuit drawings. Recall the maximum component height above the top surface of the DK PCB is 22.5 mm see 14-Nov-2022. Note that this component height restriction rules out a number of the polypropylene 10 uFd 250 V capacitors. 24-Jan-2023: ------------ Worked on clean up of the power supply description. Note that besides the lifetime question the other issue with the long life 18 uFd 250V Al electrolytics is the lack of a specified ESR. The tangent of the loss angle for these capacitors is pretty high 0.24 Their ESR is probably above 1 Ohm or even well above that. Their specification lets this ESR loss grow with the aging of the capacitors. The ERS of the 10 uFd polypropylene capacitors is about 13 mOhms. 23-Jan-2023: ------------ Worked on finding an appropriate larger inductance common mode choke for the input power with a voltage rating well above 100 VDC. Found same physical size as on HTM card. Made a geometry for it custom for DK board. 22-Jan-2023: ------------ Work more on the design of the power input filter. I still have many questions: - Is power input over voltage protection needed ? - Is protection needed agains over voltage between power input and signal ground ? - Is protection needed on the connections to the copper signals between modules ? YES <---- - Are there any "Long Ground Pins" on either the module to module connectors or the module to Bottom Junction Box connector ? I.E. Does Ground make up first ? - Is there enough space to use a Film Capacitor for the "big" high voltage capacitor in the power input filter ? Examples of 10 uFd 250 Volt Polypropylene capacitors: KEMET: PHE426 radial C4G axial R75 radial C4AT radial Cornell Dubilier: PHC axial Illinois Capacitor 730P axial 930C axial PHB radial Nichicon: QAP axial PHB radial PHC axial PPB radial Vishay: MKP385 radial Beyschlad/Draloric WIMA: MKP4 ? MKP 10 ? Is 10 uFd the scale of the "big" capacitor that is needed in the power input filter for the 100V to 5V converter ? The switching frequency of this converter is 330 kHz and its DC input current is about 100 mA and its input ripple current is about 30 mA pk-pk. 100 mA across a 10 uFd cap for 10 usec gives 100 mV. Note that 10 usec is about 3x longer than the actual period of the 330 kHz switching frrequency. So 10 uFd is the right scale for the "big" capacitor in the power input filter. 10 uFd at 100 kHz has a reactance of 0.159 Ohms. The proposed 560 uH normal mode inductor has a reactance of 352 Ohms at 100 kHz. This LC is resonant at 2127 Hz with Xc = Xl = 7.48 Ohms 19,20-Jan-2023: --------------- Finished the last of the geometries for the power supply components. Worked on clean up of the power supply write up. From Nathan I received the 2004 schematics for the Ice Cube DOM and the parts list for that DOM is on the web at: http://glacier.lbl.gov/gtp/DOM/dataSheets/ The actual root of the DOM documentation at LBL is at: http://glacier.lbl.gov/gtp/DOM/ High resolution pictures are available in the Rev 5 sub-directory. The Rev 5.1 sub-directory looks to be missing. Their power input filtering is much like what we have designed, i.e. common mode input followed by normal mode and then the first power supply. Their common mode is 104 mH 200 mA Panasonic ELF-15N002A. Their normal mode is 330 uH 300 mA 2.62 Ohm Deleven SPD73-334. Their bigest cap is 10 uFd 160 Volt Polypropylene Dearborn 730P106X9160 and it's just between the common and normal chokes. The rest of the caps is just 470 nFd 250V ceramic. They do use many OSCON aluminum electrolytic caps. Originally they had aluminum electrolytic 250V in the power filter but dumped it in the move from Rev 2 to Rev 3. Note that I believe they carry communications and DC power on the same pair - thus all of this is part of a split filter. I believe that the split filter is on page 10 and then the power input filter (and power supplies) are on page 4. 18-Jan-2023: ------------ Worked on the geometries for the power supply components. 17-Jan-2023: ------------ Have about 18 Geometries to write to get in all of the components for the DK power supplies. I got started with all of the straight forward stuff. The 100 Volt line voltage Al Cap will use IPC-2221 standard for its clearances with a generous added allowance. For 101 to 150 Volts the IPC-2221 standard requires: Internal 0.20 mm B1 External Traces un-coated 0.60 mm B2 External coated 0.40 mm B4, B5 External un-coated component terminal 0.80 mm B6 I'm holding to a much wider minimum gap, e.g. 3.0 mm for anything external. All 3 of the 20k hour, 250 V Al caps that I have found are: 10 mm Dia 16 mm Long 0.60 mm Lead Dia 5.0 mm Lead Spacing For now I will make this a stand up Geom but may want to glue down this comp with 90 deg lead bend - this is to minimize lead pull. 16-Jan-2023: ------------ Finish for now the last of the power supply drawings. 9:13-Jan-2023: -------------- All week was about 60% working on DK Brd - 40% on other. Completed 8 drawings of the power supplies and reset circuits. Made selections for a number of components used in these circuits. Have questions about what power rails will be used by the Clock Generator and the ENet. 6-Jan-2023: ----------- Work on power supply design. It's taking lots of time to identify the best and the available passive components. Clean up the .dgn file for the DK Circuit Diagrams. Had a quick meeting in Rm 2150 with Nathan. Discussed: power supply design, need for quality and numerous bench supplies, general layout of the CPU and Fabric DDR4 memory and need to verify that the available DDR4 controllers can actually handle it, the need for long term DDR IP so lets not do stupid stuff like un-aligned transfers or clipped transfers, talked very briefly about Clocks and he will pass to me the details of his current ideas and the actual M/N s and frequencies. It sounds like the normal Physicist stuff: run from a jittery octive pull VCO, run the links at maximum possible rate, run the temperature at the specified limit, assume that the fates will give you a 20 year lifetime. We have had no time to talk about PMT ADC Analog section yet. He has a hardware meeting on Thursday of this coming week. 5-Jan-2023: ----------- Work on power supply design. Finally get the circuit diagram drawings started with a first pass at the common DCDC Converter schematic. So far I have forgotten to include: output zeners, output upside down clamps, and rail to rail upside down clamps. 4-Jan-2023: ----------- Working on power supply components. I want to keep all potential bottom-side components to a height under 2 mm. Recall the total vertical height available is only 30 mm. The T520 are still the commercial standard series of polymer-tantalum and appear to be reasonably available. The Kemet high reliability series are: T540, T541, T543, T550, T551, T555, T556 and the AEC-Q200 automotive series are: T597, T598, T599. For the DK Brd it is probably DK to look at the X5R series of ceramic capacitors because the DK board will only ever operate well below 85 C. For most of the caps I want to stay with X7R because of their general higher quality. Recall the temperature stability code: 1st character is lowest temperature with X --> -55 C, the middle character is the highest temperature with 5 --> 85 C and 7 --> 125 C, the last character indicates the percent change in capacitance over this temperature range with R --> +- 15%. The maximum capacitive "load" on the 100 V to 5 V converter is 5000 uFd and at startup this converter will run without a significant "real" load. For now I will split up this 5000 ufd as: 7 loads of 640 uFd each plus 520 uFd directly on the VDD_Bulk_5V0 bus itself. The 640 uFd in front of each of the 7 converters is made from: 4x 150 uFd Tant plus 4x 10 uFd ceramic. 3-Jan-2023: ----------- Work on details of the power supply design and on trying to understand which theoretical components are actually available. 2-Jan-2023: ----------- Work on the DK power supply design. Now have estimated / guessed loads for all rails except 3V3 and 1V8. I have given up and will use 3 separate converters for: VDD_CORE_1V00, VDD_ADC_1V00, and VDDA_XCVR_1V05. From the reliability point of view this seems stupid but from the noise point of view it seem to be required. 30-Dec-2022: ------------ Work on the DDR4 memory net lists for both the FPGA Fabric and for the CPU. Still lots of questions. Want to get back to power supply work - current estimates and module selection. 29-Dec-2022: ------------ Work on the FPGA Fabric and CPU DDR4 memory - 4 GBytes each. The schematics of the SPLASH Demo Brd DDR4 Fabric memory are on pages 3, 4, 5 of its schematics. The schematics of the ICICLE Demo Brd LPDDR4 CPU memory are on page 3 of its schematics. If the DK Brd Fabric DDR4 is tied to its Bank 0 only then the memory chips should probably be at about U202 124, 88 rotated 90 deg and U201 124, 69 rotated 90 deg. The Bank 0 only setup requires getting in 10 physical rings and up to 9 signal rings. This is spread over 13 horizontally. If the DK Brd Fabric DDR4 is tied mostly to Bank 8 then the memory chips should probably be at about U201 115, 88 rotate 270 deg and U202 115, 69 rotate 270 deg. This setup, mostly Bank 8 with DQ 16:31 to Bank 0, requires getting in 10 physical rings and up to 8 signal rings. This is spread over 15 or 16 horizontally. Get in the nets for the PMT ADC High-Speed Serial Links to the FPGA Transcerivers. 28-Dec-2022: ------------ Work on the Fabric DDR4 Net List. 27-Dec-2022: ------------ Put 4 of the DDR4_96_Pin geometries into the layout and work on the DDR4 net lists for both the CPU and FPGA Fabric. 22-Dec-2022: ------------ Delays this week from a megatron power supply that died in the basement and a failed disk drive in desmo and its thumb ISO drive had failed. Working on 4 GByte memory layout and a revised description of the layout for Nathan. 20-Dec-2022: ------------ Nathan will not be in the building this week. Try "design via email". 19-Dec-2022: ------------ Quick meeting with Nathan at about 16:30 : want to minimize cable count from Interposer Brds to the DK Brd (issue of closing the sphere), yes - we can have separate Signal Gnd wire between all modules and between lowest module and the Base Junction Box, quick review of part of the PS design, no time to review DDR Memory or anything about Analog input to PMT ADCs. White linux box with atom on cover dies --> no rational email. 8,9-Dec-2022: ------------- Work on power supply design and note to Nathan about: ADC high-speed link physical line rate, PMT Transformer location, Power Supply fancy vs simple, reliable, efficient. 7-Dec-2022: ----------- Sent note about documents ready for initial review and 3 things to explore with the FPGA design tools. 6-Dec-2022: ----------- Work on the required information list, and the what we need to learn form the tools list, advertise the connector and FPGA-CPU I/O list. I assume that the actual Bluetooth part that we are using is: CC2564CRVMR tape&reel 2,500 or CC2564CRVMT tape&reel 250, i.e. the "C" revision of the basic CC2564 part, i.e. Bluetooth v4.2 or did people want Bluetooth v 4.1 the "B" version of the basic part, CC2564BRVMR tape&reel 2,500 or CC2564BRVMT tape&reel 250. 5-Dec-2022: ----------- 100 % on other projects in the basement. 1,2-Dec-2022: ------------- Make the geometries for the CC2564C Bluetooth and for the TEN20-7211WIR Power Converter. On the qfn_mr_76_pin_geom.txt for the Bluetooth I still need to confirm that the Thermal Pad should be shifted from center by 0.17 mm. Some work on the what we need to know note. 29-Nov-2022: ------------ Work on the list of need to know barnacle specifications and on the geometries for the: BB ADC, TDC, and Bluetooth. 28-Nov-2022: ------------ Hallway meeting with Nathan: pcb stackup, power supplies, fabric DDR, specifications of the barnacles. Work on the fabric memory notes. 27-Nov-2022: ------------ Work on the overall connector and FPGA-CPU I/O documents and finally find some useful information about DDR connection to the Fabric part of the FPGA-CPU in the Fabric DDR user guide. Work on the Fabric DDR Memory document. 25-Nov-2022: ------------ Work on the FPGA Fabric DDR memory design - find the Splash Kit example. Also work on the BB audio adc specification example. 23-Nov-2022: ------------ Work on the overall FPGA-CPU I/O List and the overall DK board Connector List. Get initial datasheets for audio adc, tdc, and bluetooth transceiver. 22-Nov-2022: ------------ Start an overall list of FPGA-CPU I/Os and add more ideas about the FPGA DDR memory. 21-Nov-2022: ------------ Work all day in the basement. 20-Nov-2022: ------------ Work on the FPGA DDR memory and clean up the polarfire documents. 18-Nov-2022: ------------ Working on components to make a 4 GByte DDR Mentor for the FPGA that can run at 40 Gbps for 0.8 seconds. The Bank Layout of the 784 pin FPGA/CPU is approximately: Bank 1 Bank 9 FPGA GPIO FPGA GPIO x-------------------x | | Bank 7 FPGA GPIO | A1 | Bank 3 JTAG SPI | | XCVR 1 Banks 2,4 CPU IO | | Rx & Tx Bank 5 CPU SGMII | | | | | XCVR 0 Bank 6 | | | Rx & Tx CPU DDR | | | | | | x-------------------x Bank 8 Bank 0 FPGA HSIO FPGA HSIO 17-Nov-2022: ------------ Finished all of the U1 FPGA pin net list fines and can now account for all 784 pins in the FPGA/CPU package. Working on which Banks to use for what. 16-Nov-2022: ------------ The MSU Network or Force is still down - it has now been down for 2 full days. Working on understanding where the pins are on the 784 pin FPGA/CPU. Microchip Tech's idea of what a bank is is quite different than Xilinx's. Bank 6 the CPU DDR ban, Bank 1 a FPGA GPIO bank, and both of the quad High-Speed Transceivers are now in the design and visible. Working on the DRR memory for the CPU and for the FPGA. 15-Nov-2022: ------------ Started a pcb design on real Moto named Disco. Its seed is HTM-0. All of its scripts have been moved over to this new design except for the ones in Tools and Trace_Analysis and Trace_Work. Versions of Comps, Nets, and Traces were reset to 1. Meeting with Nathan: - There are 20 modules on a string and a total of 70 strings. The distance between modules is 50 m, a string is 1 km long. - From the copper cable the DK must land: +100 Volt Power and its Power Return Ethernet pair up and Ethernet pair down Timing pair up and Timing pair down RS485 pair up and RS485 pair down Spare pair up and Spare pair down Each of the 20 modules on a string has its own Power pair that runs the whole way down to the Base Junction Box on the ocean floor. Only there 20 Power pairs make a connection inside the Base Junction Box. Recall that the Copper part of the cable is 24 pairs. These 24 pairs are really 12 quads with no shielding. The cable also has 2 x 28 = 56 single mode fibers. The voltage drop on the Power pair is only expected to be 10 Volts to the module at the top of the string. I think that means a 5 Volt drop on the supply line and a 5 Volt drop on the return line. For 8 Watts of Power at 100 Volts the standing current in the Power Supply line or in the Power Return line is only 80 mA. A 5 Volt drop with 80 mA ---> 62.5 Ohms. 62.5 Ohms in 1 km ---> about 19.95 Ohms in 1000 ft ---> about a AWG #23 conductor. Yes, it is OK to include common and normal mode filtering on the input to the 100V to 12V converter and no fuse is needed - there is a circuit breaker for each module in the Base Junction Box. The 100V to 12V converter that they like is: Traco model Ten40-7212WIR. This is a 40 Watt power supply. They also make a model Ten20-xyz WIR i.e. a 20 Watt version in the same family. Yes, these are isolated converter rated at either 1000 V or 3000 V input to output isolation. Yes, it is the Power return line that they will use to connect together the "Signal Ground" from each module down in the Base Junction Box. Yes this "ground connection" will have 5 Volts standing on it plus noise coming from the input of the 100V --> 12V converter. Nathan does want RS485 transceivers on the RS485 pair even though there is no planned use for them at this time. These need to be isolated RS485 transceivers and I should probably include a way to turn them Off to save power. The FPGA memory needs to be able to sink 40 Gbps and hold about 1 second of data ---> a 40 Gbit long memory or a 5 GByte long memory. The read rate from this memory is a very small fraction of the write rate and may be ignored compared to 40 Gbps. This memory is a circular buffer that holds raw ADC data from the 16 PMTs not time stamped hit data or over threshold data. The CPU memory needs to be at least 2 GByte and a 4 GByte CPU memory would be OK if power and space is available. Note that the LPDDR3 memory on the CPU on the Demo Brd is only 512 MByte so a different solution is needed. Yes, Nathan is also concerned about electrical noise between the Signal Ground inside the module and the Sea Water Ground potential outside of the module. The photo-Cathodes are only an inch from this sea water ground and one can imagine that noise between the photo-cathodes and the sea water could cause trouble for the PMTs. 14-Nov-2022: ------------ Work on understanding what they need in the DDR memory, how the DDR is setup on the Demo Brd, and future cost and availability of DDR modules, and what DDR module fit in the space (height) available. On the Demo Brd the CPU DDR Memory is LPDDR4 and is Micron part number: MT53D512M32D2DS-053 WT:D TR This is connected to Bank 6. This is on page 3 of their print set. The MPFS250T-FCVG484 FPGA/CPU is U1 and this memory module is U2. On the Demo Brd there is a second DDR Memory that is connected to Bank 0 of chip U26, i.e. NOT to the MPFS250T. This is on pages 17 and 18 of the print set. This is a DDR3 type of memory. The memory module U23 which is a MT41K256M16TW-107 XIT:P. Parts that I do not understand yet: U26 is a M2S025-VFG256 which is a FPGA/CPU U4 is a VSC8662XIC which is a Dual Enet Phy The space (volume) currently reserved for the DK card is 340 mm diameter by 30 mm tall. - For now I will start the DK design as a square board 235 mm on a side. This fits within the 340 mm diameter circle with a 3.83 mm air gap at each corner. - The 30 mm total available height will be divided up as follows: 4.0 mm between the bottom of the pcb and the support plate 2.5 mm for the pcb thickness 22.5 mm maximum component height on top side of pcb 1.0 mm air gap from top of max height comp to 30 mm limit 11-Nov-2022: ------------ Work on understanding the power requirements and getting that written down. Meeting with Nathan and Philippe with 29 questions. 10-Nov-2022: ------------ Start some work on understanding the overall power supply requirements. I need to push on this as the power distribution layout under the FPGA/CPU could drive the PCB layer count. 9-Nov-2022: ----------- Finished what I believe to be clean versions of the QFN-48 geometry in versions for both a 4.1 mm sq and a 5.6 mm sq Exposed Pad and a geometry for a standard SOIC-16. MPFS250T-1FCVG784E FPGA/CPU BGA 784 pin 0.80 mm pitch AD9083BBCZ ADC BGA 100 pin 0.80 mm pitch AD9546BCPZ Clock Generator QFN-48 5.6 mm sq EP ADIN2111BCPZ Ethernet QFN-48 5.6 mm sq EP ADN4680EBCPZ M-LVDS Rec/Rep QFN-48 4.1 mm sq EP DS91M125 M-LVDS Fanout SOIC-16 So that gives usable Rev 1 geometries for all known ICs at this time. 8-Nov-2022: ----------- Pushing to understand an optimum default layout for the 0.8 mm pitch BGA packages - might as well dig into this now. Mostly working for NXP and Lattice documentation. - The AD9083 package is called BC-100-8 by AD and it has 0.48 mm solder balls. This solder ball diameter implies that we should use a 0.35 to 0.40 mm pad to receive the solder ball. - Typically want NSMD pads with an air gap between the pad and the SM of 0.60 to 0.075 mm. - There is general agreement that the Paste Mask opening should match the BGA Pad diameter. - For now I want to keep the dog-bone rather wide and I need this trace width to be different from any "key" widths, e.g. the high speed differential trace widths. - Drill holes for the vias in theory could be as small as 0.10 mm diameter. This matches data from board houses and you can get the same number by using a 16:1 aspect ratio on a 62 mill thick board. Lets use double the minimum and 0.20 mm diameter drill will give 0.63 mm trace "width" in the vias. Final but very revocable Decisions: ------------------------------------- For all of the BGA Ball SMD Pads: BGA Pad Land 0.38 mm in diameter BGA Pad Solder Mask Opening 0.52 mm in diameter BGA Pad Solder Paste Mask 0.38 mm in diameter For all Power, Ground, and normal I/O pin Vias: Via Drill Hole 0.20 mm in diameter Via Pad Land 0.45 mm in diameter Via Solder Mask Opening 0.35 mm in diameter Via Plane Relief 0.65 mm in diameter Dog-Bone Width 0.20 mm smaller for High-Speed signals --> edge of BGA pad to solder mask 0.070 mm --> clearance between adjacent pads 0.151 mm --> narrowest point of Solder Mask 0.131 mm --> Via donut width around drill hole 0.125 mm --> Via drill edge to plane clearance 0.225 mm --> Via drill hole edge to solder mask 0.070 mm --> edge of Via pad to solder mask 0.075 mm --> width of Gnd/Pow Web between pins 0.150 mm --> allowed width of inner escape traces 0.150 mm 7-Nov-2022: ----------- Continue work on the Rev 1 of the geometries for the FPGA and for the ADC. Working on the real Moto for now just in the Try_One directory. This is working OK for just Restoring ASCII geometries. Looking for information about 0.80 mm pitch BGA layout. Analog Devices has nothing useful. Xilinx says: 0.40 mm BGA pad with a 0.43 SM opening around it, a 0.25 mm finished Via Drill with a 0.48 mm Via Pad and no Via SM opening specified, dog-bone width of 0.13 mm - and they give a 100% non-realistic drawing of this. Also looking at recommendations from NXP and Lattice. 4-Nov-2022: ----------- On page 30 of the microchip_polarfire_soc_fpga_packaging_and_pin_descriptions_user_guide_vb.pdf it says that the FCVG784 package has a 1 mm pitch. I think that is wrong - it has a 0.8 mm pitch. Start work on the FCVG784 geometry Rev 1 which is just a surface pad array 28 x 28.