DK Log Book Started February 2024 ------------------------------------- The most recent entries appear first in this log book. ----------------------------------------------------------------- DATE: -Sept-2024 Topic(s): ----------------------------------------------------------------- DATE: 6-Sept-2024 Topic(s): FPGA DDR4 Except for the DDR4 all of the remaining work on DK layout is normal conventional stuff - so push on the DDR4 starting with the FPGA side. Working on a 4 layer route under the DDR4 chips, for a conservative weave through the chips it requires 4 layers. Do this on L3, L4, L9, L10 in their natural order. Among other things that keeps Top and Bot free for: the Vref supply, the 2V5 word line supply, the ZQ Reference Resistor, and maybe some other slow stuff, e.g. Reset, TEN, Alert_B. The routing of the DDR4 itself looks OK - the problems are in the FPGA escape where it would be nice to stay with our current easy 1 mm BGA design rules. Made an extra save copy of traces and then start the escape work. The assumption is that it may take 2 runs at this part of the routing, i.e. do a temp first job, based on that move FPGA and memory chips to final position, then do final routing. ----------------------------------------------------------------- DATE: 5-Sept-2024 Topic(s): Bids data to Purchasing One final change - Black Solder Mask then Nathan gave the go ahead to MSU Purchasing for the DK bid release. Trying to work on DDR4 starting with the FPGA side but too many other people want things. ----------------------------------------------------------------- DATE: 4-Sept-2024 Topic(s): Released the Bids Only Data, after a month get back to layout work, work on DDR4 routing Still fighting with drill sizes. As is common in many places a single drill size is surving multiple functions. With the THD components must verify that all constraints are meet: hole size reduction from plating, THD component lead tolerance, IPC recommendation of for fluxing/solder gap. Must also verify the requirements of the press-in SFP Cage. From this drill size work I need to change some geometries: - the Harwin connector drill needs to go from 0.65 to 0.70 and its pads must go up by 0.10 mm - the Rivet_1mm2 needs to become Rivet_1mm3 and god from a 0.65 drill to a 0.70 drill and increase its pad 1mm2 to 1mm3. In random order steps to get back into layout work: - Verify that the 6 DCDC Converters are in final positions route one and copy. - Finalize the location of the L101 and L102 chokes for the FPGA Core and Transceivers. - Dump the Address/Comman Bus to the further SDRAM chips so that the trace length is just from the FPGA to the closest SDRAM chip - that way Address/Comman Bus trace length match can be made. - Setup the final position of the FPGA and SDRAMs - can they go further North or East ? How much space will bee needed for the Surpentines. - Setup the final positions of chokes: L103, L104, L105 so that more shape work for the power fills can be done. - If necessary move: Crystal Oscillators, FPGA Boot PROM and its Mux, and the CPU Boot PROM to their final positions and then route. - Finalize the location and arrangement of the Timing Generator parts and route. - Write the Default Artwork Order geom for the full set of plots. Work on the DDR4 routing starting with the FPGA side. Need to verify the best orientation of the DDR4 chips but things are too confusing as is. Split the Command & Address Bus in the Close and Far and split the Data Bus into D0:D15 and D16:D31 sections. Now I can turn things on and off as needed to see what is going on. Split ddr4_fpga_bank_0_address_and_command_nets_fcg1152.txt into ddr4_fpga_bank_0_address_and_command_close_fcg1152.txt and ddr4_fpga_bank_0_address_and_command_far_fcg1152.txt Split ddr4_fpga_bank_0_data_path_nets_fcg1152.txt into ddr4_fpga_bank_0_data_path_d0_d15_fcg1152.txt and ddr4_fpga_bank_0_data_path_d16_d31_fcg1152.txt With the original 2 "nets" files turned on in the build script I see: 1406 Comps 1406 Nets 70 Float Pins 3960 Conn 1896 Finished 136 Un-Finished 1928 Guides With the new 4 "split" FPGA DDR4 files turned on in the build script I see: 1406 Comps 1406 Nets 70 Float Pins 3960 Conn 1896 Finished 136 Un-Finished 1928 Guides With only the new address_and_command_close "split" FPGA DDR4 file turned on in the build script I see: 1406 Comps 1362 Nets 266 Float Pins 3808 Conn 1896 Finished 136 Un-Finished 1776 Guides The net list build script said: FPGA Fabric DDR4 U301 has 74 pins with assigned nets out of 96 FPGA Fabric DDR4 U302 has 44 pins with assigned nets out of 96 And I can clear see just the Address and Command bus connection to U301 FPGA DDR4 chip. ----------------------------------------------------------------- DATE: 2,3-Sept-2024 Topic(s): Work on Bids Only Release Data ----------------------------------------------------------------- DATE: 1-Sept-2024 Topic(s): Working on the SMD XY placement script Fixed the stupid 3 consecutive zeros problem in the script that generates the Top/Bot SMD XY coordinate data. All release data for the bid now looks in good shape except for the 3 txt files. ----------------------------------------------------------------- DATE: 30-Aug-2024 Topic(s): Working on the BOM generation and SMD XY placement scripts Work to get all of the "not installed" parts out of the BOM and out of the SMD XY Placement data. Most of this is straight forward and had already been coded - but there are things that are specific to Disco-Kraken, e.g. which real actual components are not to be installed by the assembly house. Recall for the Jumpers that you must correctly write the comps file so that the not installed jumpers have the _1sb sufix on their geometry in order for the generate SMD XY Placement Data script to work properly. That is, it is up to you to make the DK comps file match what you want the default setup of the jumper to be. If the DK comps file is correct then everything else will follow automatically. The current official understanding of the default jumper settings is in .../Text/dk_jumper.txt Recall also that most not realy physical comps will automatically be pulled out of the BOM because their associated geometry will have the Not In BOM attribute. The equivalent removal of most not real physical comps from the XY Placement Data is taken care of via sed calls in the scripts that generate the XY data but it is up to you to get the geometries that you want pulled out of the XY Data into these sed delete calls. Everything appears to be working and correct except for some of the comps with a negative Y placement in the bump out area. This is the first card with negative Y values and the scripts have never been used before with negative Y values. 1406 Comps 1406 Nets 70 Float Pins Comps ver 820 Nets ver 544 3960 Conn 1896 Finished 136 Un-Finished 1928 Guides 18 Shapes Trc Ver 87 ----------------------------------------------------------------- DATE: -Aug-2024 Topic(s): Working on the scripts that generate the release data. The scripts to generate the BOM are now working. In the DK design there are only a couple of actual physical components that the Assembly House will not be installing. I have taken care of these with just the "NOT_In_BOM" attribute in their Geometry files. Specifically the SFP 1x2 Cage and the PEM Brackets have been pulled out of the BOM in this way - but they are real parts and I really need to purchase them. The script to make the Drill Table and Drill Files are working fine and are OK for both the RFQ release and the good for production release. The script for making the RFQ Gerbers are OK ? The gerbers made by this script do exactly match gerbers made today by hand using the exact same hand procedure as yesterday - but they do not match yesterdays hand made gerbers. What has changed ? The oly thing that I can think of is the edited Geoms for SFP Cage and PEM Bracket - but why would that change the Gerbers ? Still checking. Recall that this script does NOT generate an Aperture Table. ----------------------------------------------------------------- DATE: 28-Aug-2024 Topic(s): Working on the release data for getting the bid. Gerbers and Drills now look OK. Edited the Connectors part of the comps description file. Finished the THD file. Working on the SMD placement files. ----------------------------------------------------------------- DATE: 27-Aug-2024 Topic(s): Problem with the ER DeBug Header Yesterday a problem was discovered with geometry for the current Sullins SBH31 10 pin header for the DeBug connector on the Emergency Rescue uProcessor. This part actually takes two different size of drill holes for its alignment pins and the geom has both alignment pins as the same size. So using the Sullins part requaires two special drill just for it and each of these drills has only one hit, i.e. not effective for manufacturing these cards. Replace this Sullins component with Samtec: TFM-105-02-S-D-A Doing that requires: Editing the geometry for the 10 pin Header comp in the DK design, chaning the part number in the Comps file, and changing this entry in the Component Description file to reflect the new connector choice. After that re-run the Gerbers and Drills yet again. Plated Drills: -------------- Position Size Count Function -------- ---- ----- ------------------------------------ 1 0.23 476 0.8 mm BGA dog-bone vias 2 0.30 1036 1.0 mm BGA dog-bone vias, via_0mm65 3 0.40 606 via_0mm79, and ? 4 0.46 103 Power_Via_Arrays 5 0.60 53 via_1mm1 6 0.65 86 Rivet_Via_1mm2 Harwin M80 connector pins 7 0.80 42 DC-DC Converter Module Aux pins 8 0.90 118 Thru Hole Connector Pins 10 1.10 25 via_2mm2, SFP_1x2_Cage 11 1.20 17 10 uFd Poly Caps, SFP_1x2_Cage 12 1.30 8 USB Connector large pins 13 1.40 68 PEM Bracket Pins & DCDC Converter Module Main pins 16 1.60 6 TRACO DCDC Converter Pins 17 2.30 6 Harwin Mounting and Shield Mounting M2 Screws 18 2.70 8 PEM Bracket Screws & 3M Conn Screws M2.5 19 3.20 3 M3 Mounting Screws TOMcat (add 4th ?) Un-Plated Drills: ----------------- Position Size Count Function -------- ---- ----- --------------------------- 9 1.00 4 SMD Connector Locating Pins Access and PS Mon 14 1.45 4 SMD Connector Locating Pins ER DeBug and TOMcat 15 1.55 4 SMD Connector Locating Pins SFP+ Conn 20 3.20 8 Board Mounting M3 Screws ----------------------------------------------------------------- DATE: 26-Aug-2024 Topic(s): Edits to the 3 BGA Geoms on DK FPGA BGA Geom: Except for the Special XCVR Gnd Vias in Rev_3 of the FPGA Geom, all of the Pin/Pad Stacks are in Rev_2: bga_1152_stack_definitions_basic_5.txt and bga_1152_stack_definitions_all_other.txt. Currently only Pin/Pad Stacks from the basic_5 are in use. I will edit the pin/pad stacks in the basic_5 to bring them to the current standards - but for now I'm NOT going to edit any of the stacks in the all_other file because none of them are in use at this time. At some point I will probably want to use special pin/pad stacks on the 1 Gbps pins and at that time will need to edit and correctly implement some of the "small" pin/pad stacks in the all_other file. Also at some time the border between the dog-bone quadrants in the FPGA is going to move to optimize the power fills under the FPGA. ADC BGA Geom: I've edited the pin/pad stacks in the 5_standard to bring them up to the current standards - but for now I'm NOT going to edit any of the stacks in the n_special file because none of them are in use at this time. Currently I have 0.20 mm wide dog-bones. When I can find 2 hours - I must go back and implement 4 special "Wide" dogs for the ADC for its power and ground pins. DDR4 BGA Geom: The bga_0mm8_stack_definitions.txt for the DDR4 component has both the "5 normal" staks and 4 special Wide stacks in it. These special Wide stacks are in use in the over all design of the DDR4 BGA geom. Edit all 9 stacks to bring them up to the DK standard. Use 0.2 mm bones on the normal stackss and 0.30 mm bones on the special Wide stacks. That's the nice part about having separate normal and wide bones - you do not have to make a compromize with only one width. Generate new Gerbers and Drill Files: Now work on re-making the gerbers and drill files using the same method as described in the 22-Aug-2024 entry from last week. Plated Drills: -------------- Position Size Count Function -------- ---- ----- ------------------------------------ 1 0.23 476 0.8 mm BGA dog-bone vias 2 0.30 1036 1.0 mm BGA dog-bone vias, via_0mm65 3 0.40 606 via_0mm79, and ? 4 0.46 103 Power_Via_Arrays 5 0.60 53 via_1mm1 6 0.65 86 Rivet_Via_1mm2 Harwin M80 connector pins 7 0.80 42 DC-DC Converter Module Aux pins 8 0.90 118 Thru Hole Connector Pins 11 1.10 25 via_2mm2, SFP_1x2_Cage 12 1.20 17 10 uFd Poly Caps, SFP_1x2_Cage 13 1.30 8 USB Connector large pins 14 1.40 68 PEM Bracket Pins & DCDC Converter Module Main pins 17 1.60 6 TRACO DCDC Converter Pins 18 2.30 6 Harwin Mounting and Shield Mounting M2 Screws 19 2.70 8 PEM Bracket Screws & 3M Conn Screws M2.5 20 3.20 3 M3 Mounting Screws TOMcat (add 4th ?) Un-Plated Drills: ----------------- Position Size Count Function -------- ---- ----- --------------------------- 9 0.90 2 SMD Connector Locating Pins J8 Sullins SBH31 10 1.00 4 SMD Connector Locating Pins Access and PS Mon 15 1.45 2 SMD Connector Locating Pins TOMcat 16 1.55 4 SMD Connector Locating Pins SFP+ Conn 21 3.20 8 Board Mounting M3 Screws ----------------------------------------------------------------- DATE: 25-Aug-2024 Topic(s): Final immutable decisions on 0.8 mm BGAs and the special FPGA HS XCVR GNDs Recall the various BGA layouts on the DK board: Package Package Package Recommended IPC PCB Item Pitch Bal Dia. Pad Dia. PCB Pad Dia. Pad Dia. ---- ------- -------- -------- ------------ -------- ADC 0.8 mm 0.48 mm 0.?? mm 0.48 mm 0.38 mm DDR4 0.8 0.47 0.?? 0.42 0.37 FPGA 1.0 0.64 0.?? 0.50 0.49 For now I beleive that the AD recommended 0.48 mm PCB Pad diameter for the ADC is just plan wrong or a typo. Real data points: - The ADC Demo Brd uses via-in-pad 0.33 mm PCB Pads. - Xilinx appears to use 0.40 mm PCB Pads with their 0.8 mm pitch MT40A DDR4 parts - I can not yet tell what MicroChip uses on their Demo Brd for the MPFS250T-1FCG1152I because I can not yet read their .brd file. - MicroChip recommends 0.40 mm PCB Pads for their 0.8 mm pitch BGA packages which have 0.50 mm balls. Decision - Make the 0.8 mm pitch parts with 0.40 mm BGA Pads Make the 1.0 mm pitch parts with 0.50 mm BGA Pads Via Pad and Drill Diameters: 1.0 mm Pitch Normal Signals Ground & Power 0.58 mm dia 0.30 mm drill 1.0 mm Pitch Fast Signals 0.50 mm dia 0.23 mm drill 1.0 mm Pitch Special HS XCVR Gnd Vias 0.50 mm dia 0.23 mm drill 0.8 mm Pitch All 0.44 mm dia 0.23 mm Drill I need to keep thick dog-bones on the 0.8 mm pitch layout because the annular ring on these vias is only 0.105 mm wide. So lets keep these standard dog-bones 0.25 mm wide, i.e. just slightly wider than the drill. The tightest fit in this setup is the 0.105 mm annular ring on the 0.44 mm Via Pads for the 0.8 mm pitch parts. The pcb house could drop the drill size from 0.23 mm (9 mils) down to 0.20 mm (8 mils) and this would give a comfortable 0.12 mm annular ring. The nice thing about a 0.23 mm drill is that it holds a 10:1 or less aspect ratio with the expected 2.3 mm thick DK pcb board. Escapes: 1.0 mm Pitch driven by the 0.58 mm Via Pads 0.14 mm Trace 0.14 mm Space 0.8 mm Pitch driven by the 0.44 mm Via Pads 0.12 mm Trace 0.12 mm Space It would be a good idea to put all nets that actually need to escape between vias in the 0.8 mm pitch BGAs into their own net type so that I can assign them their own design rules. Recall also that all of the BGA Vias need to be plugged from the TOP. In the design I remove the Solder Mask from the Bottom only of the vias in the BGA arrays. The vias in the BGA arrays are both Plugged from the Top and covered with solder mask on the Top. All other normal (i.e. non BGA) vias in the DK design have the solder mask removed from the Top and Bottom. Get the work started to implement all of this. ----------------------------------------------------------------- DATE: 24-Aug-2024 Topic(s): Rivet Comp re-do to 0.65 drill Make a Rivet_via_1mm2 comp that uses a 0.65 mm plated drill and 1.2 mm pad land and move all large rivets in the ground_rivet_comps.txt DK design file to using it. This should eliminate the 0.60 mm plated drill. Rebuild comps and things look good. Would like to see the gerbers for the polarfire soc sev kit but all they provide is a .brd file from eagle. Looking for a viewer that works. ----------------------------------------------------------------- DATE: 23-Aug-2024 Topic(s): Still working on cleaning up the Drill Files Working to clean up the chaos in the plated Drill File. Move PEM Bracket Alignment Pins from 1.36 mm to 1.40 mm done also at some point may want to change the PEM Mounting Screw from M2.5 to M2. Move Harwin M2 Mounting Screws from 2.25 mm to 2.30 mm done to match the other M2 screw holes in the design. Move the Rivet_via_1mm1 (larger rivet) from 0.60 mm working to 0.65 mm. This means that I also need to change on it the Pad Land from 1.1 mm to 1.2 mm. That means that I must re-name this component. That means that I must edit the ground_rivet_comps.txt comps file to change all of the Geometry names that are called by that file. The big issue is the 0.23 mm drills for the vias in thinking the 0.8 mm BGAs and the 0.25 mm drill for the special on it Ground Vias by the FPGA High-Speed Transceiver connections. There needs to be a common approach to these similar problems. This means that I must finalize the 0.8 mm BGA DogBone sstructure for now and forever. Study the AD9083 demo board gerber files. They are using Via In Pad technology with 0.33 mm Pads from apature D61 Traces for the differential Analog, Clocks, and HS Data are 0.165 mm (6.5 mil) width and spaced 0.458 mm (18 mil) center to center. The 50 Ohm single ended traces are 0.2286 mm (9.0 mil) width. The L1 to L2 laminate is FR-408HR 5 mil thick. I can read their Drill File and clearly see 6 mil drills right at the same coordinates as the BGA pads for the AD9083. At the top of the L1 gerber file the D61 apature is defined as 13 mils 0.3302 mm. It appears that the make the Solder Mask and the Paste Stincil both exactly the same. In both cases the flashes for the ADC BGA Pads are exactly the same diameter as the Pads themselves - a rather strainge arrangement. So this is not either a SMD or NSMD type of BGA Pad. Trying to look in under the AD9083 to see its pads and their solder mask relief is useless. AD says that the AD9083 has 0.48 mm balls. Currently the AD9083 setup on DK is: BGA Pad Land 0.38 mm BGA Solder Mask 0.48 mm Via Pad Land 0.45 mm Via Drill 0.23 mm Via Donut Width 0.11 mm Via Plane Relief 0.65 mm The other 0.8 mm BGA parts are the Micron MT40A1G16 memory chips. The Micron data sheets do not give a recommended layout. They just say - the balls are 0.47 mm Dia and the BGA Pads should be 0.42 mm SMD. The Xilinx layout that I can find for these DDR4 parts shows about a 0.40 mm BGA Pad and a 0.40 mm Via Pad with a 0.19 mm Drill giving about a 10.5 mm donut width. Currently the DDR4 Geom for DK is setup: BGA Pad Land 0.38 mm BGA Solder Mask 0.48 mm Via Pad Land 0.45 mm Via Drill 0.23 mm Via Donut Width 0.11 mm Via Plane Relief 0.65 mm Besides the 5 standard Pin/Pad stacks for each of these 0.8 mm BGA Component Geometries - I have also written 4 "Wide-Dog" stacks for each component. I do not think that the Wide-Dogs have been assigned to any pins in the ADC yet - but they are in use for the DDR4 power and ground pins. ----------------------------------------------------------------- DATE: 22-Aug-2024 Topic(s): Gerbers and Drill Files for Release 2 Restored the default_artwork_order_rfq so that I can make the 3 plots for Release 2. It has only: dimensioned fabrication drawing, top side comps and copper, bottom side comps and copper. Fablink: (Arwork Format & Drill Format have already been setup) Artwork --> Change Aperture Table --> Delete All Apertures Artwork --> Change Aperture Table --> Fill Aperture Table: All Sizes, ReSize No, ReScale No, Flash Complex Stacks, Replace Artwork --> Create Artwork: Gerber 274X, Stroke Area Fill, Flash Polygon, ASCII, Board, All, Tear Drops Not, Output All Pins, Output All Vias, Output Unplated Holes, ReSize No, ReScale No No Missing Apertures, 1928 UnRouted 136 UnFinished Drill --> Change Drill Table --> Delete All Drills Drill --> Change Drill Table --> Fill Drill Table (Replace) Drill --> Create Dill Data: Excellon, Board, ASCII, Mirror No, Plated, All No Missing, Found: 1736 terminal pads and 925 vias Drill --> Create Dill Data: Excellon, Board, ASCII, Mirror No, UN-Plated No Missing Plated Drills: -------------- Position Size Count Function -------- ---- ----- ------------------------------------ 1 0.23 468 0.8 mm BGA dog-bone vias 2 0.25 8 FPGA Transceiver Special Ground Vias 3 0.30 1036 1.0 mm BGA dog-bone vias, via_0mm65 4 0.40 606 via_0mm79, and ? 5 0.46 103 Power_Via_Arrays 6 0.60 91 rivet_via_1mm1 (larger rivet) 7 0.65 48 Harwin M80 connector pins 8 0.80 42 DC-DC Converter Module Aux pins 9 0.90 118 Thru Hole Connector Pins 12 1.10 25 via_2mm2, SFP_1x2_Cage 13 1.20 17 10 uFd Poly Caps, SFP_1x2_Cage 14 1.30 8 USB Connector large pins 15 1.36 8 PEM Bracket Pins 16 1.40 60 DC-DC Converter Module Main pins 19 1.60 6 TRACO DCDC Converter Pins 20 2.25 4 Harwin M80 Mounting Screws 21 2.30 2 Shield Mounting Screws 22 2.70 8 PEM Bracket Screws & 3M Conn Screws M2.5 23 3.20 3 M3 Mounting Screws TOMcat (add 4th ?) Clearly a lot of clean up is needed - Positions: 1-2, 4-5, 6-7, 14-15-16, 20-21 Then need to re-make the Plated Drills. Actions: Move 0.8 mm BGA & special XCVR Gnd vias same size dump 1 or 2 Move PEM Bracket Pins from 1.36 to 1.40 i.e. dump 15 Move Harwin M80 Screws from 2.25 mm to 2.30 mm dump 20 Un-Plated Drills: ----------------- Position Size Count Function -------- ---- ----- --------------------------- 10 0.90 2 SMD Connector Locating Pins 11 1.00 4 SMD Connector Locating Pins 17 1.45 2 SMD Connector Locating Pins 18 1.55 4 SMD Connector Locating Pins 24 3.20 8 Board Mounting M3 Screws Typical current manufacturing: Minimum mechanical drill is 0.15 mm so we are OK. Minimum donut width is 0.10 so we are OK Minimum drill edge to other copper is 0.20 mm so we are OK Typical 12 Layer stackup is: P C P C P C P C P C P with the PrePreg being 6.4 mils and the Core 5 or 8 mils ----------------------------------------------------------------- DATE: 21-Aug-2024 Topic(s): FPGA Boot PROM Mux, PMT Input Term, Quartz Crystal, Note to MSU Purchasing A bunch of the time in the past 2 weeks has been on other work but I'm finally getting back to the DK Board. I'm late on getting the release data ready for the bid which is now at MSU Purchasing. Give up on patching the FPGA Boot PROM Mux with a 74xyz241. Move the Mux U1252 to a 74LVC257 (which is fully available). Note that the DQ1 MISO signal from the PROM going back to both the FPGA and the ER uProcessor is buffered by the 4th section of the Mux U1252 and has series terminators R1263 R1264. Move the PMT Input Terminators: R683/4, R693/4, ... R823/4, R833/4 from 140 Ohm 1% to 210 Ohm 0.1%. The 2x 210 Ohm in parallel with the expected 381 Ohm input to the ADC gives the required 200 Ohm termination across the transformer secondary. Finally finish the Components Description file with rational parts now selected for the 125 MHz oscillation and for the 53 MHz crystal. Added the dimensions to the real board layout for the bump out that was required by others. Note to MSU Purchasing asking Kaathy Perron to hold up releasing the RFP until Fri or Mon to give me time to finish the technical data for the release. Meeting with Felix about the trigger signal for the sonic pinger. 1406 Comps 1406 Nets 70 Float Pins Comps ver 810 Nets ver 544 3960 Conn 1896 Finished 136 Un-Finished 1928 Guides 18 Shapes Trc Ver 87 ----------------------------------------------------------------- DATE: 14-Aug-2024 Topic(s): Working on full Component Descriptions It appears that the 74xyz241 is not as common as it once was. It is available in LVC from Diodes and a few other places but it is most common in the TSSOP-20 and not in the SOIC-20. So an official final decision - move U1252 to a TSSOP-20 package. The 74xyz244 is still available from 5 or more manufacturers in the SOIC-20 package - so keep U1451 and U1452 as SOIC-20. ----------------------------------------------------------------- DATE: 12,13-Aug-2024 Topic(s): Working on Release Data for Bid After some days mainly working on Advanced Lab for next semester I'm back to DK design - working on the Release Data for the Bid which I must get ready this week. Currently still working on the DK Components description file and the assembly house version there of. Recall the current arrangement of Fuses and PTC Fuses: F1001 PTC 350 mA Drw 47 Emergency Rescue uProc JTAG Reference F1051 Fuse 2 Amp Drw 79 USB Power both Ports (expect 340 mA per Camera) F1401 PTC 350 mA Drw 13 JTAG Reference for the FPGA/CPU F1551 Fuse 2 Amp Drw 43 Barnacle Interface F1981 Fuse 2 Amp Drw 19 TOMcat Interface ----------------------------------------------------------------- DATE: 1-Aug-2024 Topic(s): FPGA Fills, start Bid Release Data, Krizma geometries checking I now have moto_too running in the student cubical for Krizma to use as part of checking the Geometries. It appears to have woken up from a couple year long sleep OK. Krizma could not come in today because of an mDOM data base problem. The 7 plausible fills are now in under the FPGA. This can be cleaned up a bunch but there is no point in doing that until I know that the FPGA is in its final position. Also some dog bones for the CORE supply and for the 3V3 supply need to be rotated in order to have the cleanest connections into their Fills. So sketchs of 18 Fills are now in but that leaves many to do: 1V2 and 2V5 under the DDR4, 5V0 at the Perimeter, general Bulk_3V3 and general Bulk_1V8. So at least 5 more Fills to need to be sketched in and all will need a lot of clean up. Now officially stop working on the layout and start working on the release data for the bid. 1404 Comps 1405 Nets 70 Float Pins Comps ver 797 Nets ver 540 3961 Conn 1896 Finished 136 Un-Finished 1929 Guides 18 Shapes Trc Ver 86 ----------------------------------------------------------------- DATE: 31-July-2024 Topic(s): FPGA Power Fills, PO meeting with Nathan Yesterdays attempt to directly enter the FPGA Power Fills crashed and burned. The layout of the 1152 package is just too different than the 784 package. So I worked up a full set of minimum required fill shape drawings (which are now on the web) : XCVR_1V05 Drw 107 BULK_1V2 Drw 108 BULK_3V3 Drw 109 CORE_1V05 Drw 110 Digital_1V8 Drw 111 Digital_2V5 Drw 112 Analog_2V5 Drw 113 Note: This is a 7 Fill design - not the expected 8 Fill design. FPGA PLLs & PNVM, XCVR PLL & Clk Buf are all 4 being powered by the same Analog_2V5 Fill. Fill Conflicts Include: Digital_1V8 vs Digital_2V5 vs Analog_2V5 all escape to the North CORE_1V05 vs Digital_1V8 vs Analog_2V5 all overlap core area Which Fills Can Coexist: XCVR_1V05 & BULK_3V3 & CORE_1V05 & Digital_2V5 Notes: this is a tight fit, Rotate all Core dogbones in the same direction, highest current ---> Signal_11 BULK_1V2 & Digital_1V8 Notes: Wide clean access for Bulk_1V2, place on Signal_12 Analog_2V5 Notes: place on Signal_3, this is a 1/2 oz layer, FPGA PLLs & PNVM, XCVR PLL & Clk Buf all 4 will be powered from the same thin plane ? Quick meeting with Nathan: He is going to trim some of the boiler plate from the RFP, and move so of the important stuff forward in the document. Starting Aug 1st I will push first of the minimum set of "for bid" documents and then, at this time, push for a full release of the 50% complete design. I need to get back to purchasing kit parts. ----------------------------------------------------------------- DATE: 30-July-2024 Topic(s): Power Fills under the FPGA, Meeting with MSU Purchasing, Scrum meeting Interfaces Review, Talk with Nathan about Noise Shield Meeting with Lara Druelle from MSU Purchasing about setting up the purchase of the DK boards - now pictured as one PO to cover a prototype build of perhaps about 20 and a production build of perhaps about 50. Scrum Interfaces meeting - I still need to write a "Reader's Guide to DK Interfaces" note. Talked with Nathan about Noise Shield over PMT Analog Input Section, and is this also a Heat-Sink for the PMT ADC. I need to work up the thermal resistance and expected Si temperature for: PMT ADC, Timing Generator, FPGA, DDR4s. Working on the Power Fills under the FPGA - Recall the 8 required fills: Disco-Kraken Power Net This Fill Must Connect To: ------------ ------------------------------------------ BULK_1V2 Bank I/O supply for Banks: 0 and 6 (BULK_1V2 also supplies the DDR4 memories themselves) BULK_3V3 Bank I/O supply for Banks: 1, 2, 3, 5, 7 and Bank Aux supply for Banks: 1, 2, 7 CORE_1V05 FPGA Core 2.2 Amps DIGITAL_1V8 Bank I/O supply for Bank 9 and FPGA VDD18 i.e. FPGA Program and HSIO Banks Aux Supply DIGITAL_2V5 Bank Aux supply for Bank: 9 (DK's 1V8 GPIO Bank) (DIGITAL_2V5 also supplies the DDR4 memories themselves) ANALOG_2V5 FPGA VDD25 for the FPGA's PLLs and PNVM ANALOG_2V5 Transceiver PLLs and Transceiver Clock Buffers XCVR_1V05 Transceiver Lane main power supply Questions about the FPGA Power Fills: 1. Can the FPGA VDD25 and the XCVR PLL + Clk Buf fills be the same or at least adjacent on the same physical lay with slits between them ? 2. Which are the lowest current fills and thus can go on a 1/2 oz layer, perhaps the Analog_2V5 fills ? 3. How to make the CORE_1V05 fill wide enough to carry the 2.2 Amps with minimal voltage drop. 4. How to keep whatever fill is on a 1/2 oz Signal Layer 100% out of Banks 0 and 6 so that the DDR4 has free use of: L3, L4 and L9 , L10. 5. Must also have enough access on a Signal Layer to connect the 10k Ohm pull-downs to: Bank #4 I/O and Aux supplies, and to Bank #8 I/O supply. When not using a Banks and just pulling its supply low does one need to connect to all of its supply pins ? ----------------------------------------------------------------- DATE: 29-July-2024 Topic(s): Clean up routing in the SFPs & TOMcat corrner, Move FPGA and start on its power fills, Krizma's first day Move some side 2 comps and clean up the SFPs + TOMcat corrner routing. An issue is no top surface routing in the SFP keep out area. This now looks OK and still has its long lines to do. This tentatively ends the routing work for now. Move FPGA East 5.5 mm and North 5 mm so that it is in approximate final position so that I can start working on the Power Fills that go under it. The issues are: enough space for I/O routing on the FPGA's East, West, and North, enough space for DDR4 routing with their required surpentines, East West space for DDR4 and the 1V05 filter inductors. Krizma started her first day working on checking the DK design. I need to get her a machine running the library and office space. 1404 Comps 1405 Nets 70 Float Pins Comps ver 797 Nets ver 540 3961 Conn 1896 Finished 136 Un-Finished 1929 Guides 11 Shapes ----------------------------------------------------------------- DATE: 28-July-2024 Topic(s): move and route in SFPs & TOMcat area, flux is signals to/from SFPs & TOMcat, edit dual SFP cage to mark bottom opening The placements of some component areas must take into consideration the flux of traces to/from the SFPs & TOMcat bump out - so start by just listing the signals to/from the SFPs & TOMcat corner: Timing SFP J13 3V3 Power Drw 42: ---------- 8 Single-Ended: 5 have pull-ups, 1x to the South side of the Startup-Reset logic, 7x to Bank #7 on West side of FPGA, assume that all 8 will route South of DCDC-2 & DCDC-3 and then up just West of DDR4. 2 Diff-Pairs: both to the Timing Generator area, escape due North and in the current TG layout they must cross-over. Ethernet SFP J14 3V3 Power Drw 66: ------------ 8 Single-Ended: 5 have pull-ups, 1x to the South side of the Startup-Reset logic, 7x to Bank #7 on West side of FPGA, assume that all 8 will route South of DCDC-2 & DCDC-3 and then up just West of DDR4. 2 Diff-Pairs: both to the Transceiver area on East side of the FPGA, XCVR 1 Tx/Rx 3, assume escape due North then jog West under the Timing Generator and then North between DDR4 and the Tming Generator. TOMcat J10 and U1621, U1622, TOMcat Power Switch 5V0 ------ Drws 19, 80, 89, 90 8 Single-Ended: 1x TOMcat_Power_Enable from Startup-Reset Logic 4x TOMcat JTAG 3V3 to/from Emergency-Rescue uProcessor 2x TOMcat Configuration 1V8 to Bank #9 FPGA's NE corner 1x TOMcat 100 Hz output 1V8 to Timing Gen M0 Input 2 Diff - 2 Singal 2x short local Diff-Pairs to/from LVDS-3V3_CMOS Translators then 2x long Single-Ended to/from Emergency Rescue uProcessor UART. 5 Diff-Pairs: 2x Diff-Pairs SGMII to/from Bank #5 FPGA West side 1x Diff-Pair TOMCat 125 MHz to Timing Generator 2x Diff-Pairs TOMcat 125 MHz and 100 Hz to Bank #9 FPGA's NE corner. This is about 44 traces total to/from the SFP & TOMcat corner. Some of them need to be well isolated high quality Diff-Pairs. The space limitation seems to be in the East-West direction. The Timing Generator needs to be reduced in the East-West layout and not increase in its North-South layout. There is still no natural place to locate L101 & L102 and their locations may be somewhat forced by the locations of the associated Power Fills. DDR4 layout must be controlled in the East-West direction and there will be other signals running North-South just beside the two DDR4 areas. 1404 Comps 1405 Nets 70 Float Pins Comps ver 792 Nets ver 540 3955 Conn 1875 Finished 136 Un-Finished 1944 Guides 11 Shapes ----------------------------------------------------------------- DATE: 26-July-2024 Topic(s): Finish Interposer I/Fs, start along South Edge TOM and SFPs, update Drawing 69 1404 Comps 1405 Nets 70 Float Pins Comps ver 792 Nets ver 540 3955 Conn 1870 Finished 133 Un-Finished 1952 Guides 11 Shapes ----------------------------------------------------------------- DATE: 25-July-2024 Topic(s): Routing Interposer SPI I/Fs 1404 Comps 1405 Nets 70 Float Pins Comps ver 784 Nets ver 540 3945 Conn 1784 Finished 117 Un-Finished 2044 Guides 11 Shapes ----------------------------------------------------------------- DATE: 24-July-2024 Topic(s): Routing along the North edge 1404 Comps 1405 Nets 70 Float Pins Comps ver 777 Nets ver 536 3935 Conn 1717 Finished 111 Un-Finished 2107 Guides 11 Shapes ----------------------------------------------------------------- DATE: 23-July-2024 Topic(s): Work routing USB I/F and Access J12 1404 Comps 1405 Nets 70 Float Pins Comps ver 764 Nets ver 530 3923 Conn 1533 Finished 96 Un-Finished 2294 Guides 11 Shapes ----------------------------------------------------------------- DATE: 22-July-2024 Topic(s): Fills, Moving comps and Routing traces 1404 Comps 1405 Nets 70 Float Pins Comps ver 755 Nets ver 529 3912 Conn 1400 Finished 75 Un-Finished 2437 Guides 11 Shapes ----------------------------------------------------------------- DATE: 21-July-2024 Topic(s): Routing work on West side, Move TOMcat power switch Move the TOMcat power switch from the SW corner to the SE corner where there is now more space (because DCDC-1 rotated by 180) and where it is closer to its load and there is Bulk_5V0 available. 1404 Comps 1405 Nets 70 Float Pins Comps ver 747 Nets ver 528 3894 Conn 1313 Finished 63 Un-Finished 2518 Guides 8 Shapes ----------------------------------------------------------------- DATE: 20-July-2024 Topic(s): Routing work on West side 1404 Comps 1405 Nets 70 Float Pins Comps ver 746 Nets ver 528 3887 Conn 1232 Finished 42 Un-Finished 2613 Guides 8 Shapes ----------------------------------------------------------------- DATE: 19-July-2024 Topic(s): Routing work in Isolated RS-485 Meeting with Nathan Late Friday meeting with Nathan: 20 / 200 version of build idea 1404 Comps 1405 Nets 70 Float Pins Comps ver 742 Nets ver 526 3879 Conn 1176 Finished 39 Un-Finished 2664 Guides 8 Shapes ----------------------------------------------------------------- DATE: 18-July-2024 Topic(s): Routing on the West side, Drawings All of the Power Input Filter and 100V to 5V converter is routed and to try to finish up J1 I'm working on the Isolated RS-485 bus. Updated drawing 91 so that it reflects the current arrangement of filter inductors and bypass capacitors. I believe that we could drop a few of the Dig_1V8 capacitors in favor of some additional caps for the Analog or Dig_1V0 rails. U1054 is powered by Bulk_3V3 - is that correct ? It looks like we need a Const_3V3 fill under most/all of the reset/startup area. 1404 Comps 1405 Nets 70 Float Pins Comps ver 736 Nets ver 522 3840 Conn 1068 Finished 39 Un-Finished 2733 Guides 8 Shapes ----------------------------------------------------------------- DATE: 17-July-2024 Topic(s): Slight clean up of Environment Sensors, Shield Mount Points, Start HV Route, DK Mounting and SCRUM meeting Made a little clean up of the Environment Sensors mostly for a cleaner power feed. In the SCRUM meeting today I verified with Christian that the orientation of the Sensors axis (magnetic and accelerometer) does not matter wrt some overall P-ONE coordinate system. I added 2 mounting points for a Shield over the PMT analog signal area. This is component shield_mounting_hole_m2 and is for a M2 screw size. It grounds these mounting screws. These 2 points are in a good location to also provide clamping force down onto the PMT ADC so that the Shield could also be a Heat Sink if that is needed. Started West side routing with the "HV" traces. I want to use design rules of: 1.2 mm clearance from HV to and other copper and 1.5 mm if that copper is the bore of a screw hole for a threaded screw. Modified the M3-2x8 connector and the ten20_7211wir power supply geoms for these rules and made a special via_2mm2_hv via with 1.2 mm of plane relief for this routing. Still the issue of Top Side routing under the edge of the 100V to 5V converter. The cleanest way to route the Power_Return out of the Main Cable M3 connector was to also include that connectors pin #17, aka screw hole, in that net. Just started this "HV" routing but need need to formalize the layer usage in this area. Made a new drawing, DRW 91 and included it in the DK print set. This is for Laszlo who is working on the mechanical mounting. Drw 91 shows the location of the 22 mm tall power filter capacitors. Currently this clashes with the uBase of a PMT. 1404 Comps 1405 Nets 3782 Conn Comps ver 736 Nets ver 522 955 Finished 38 Un-Finished 2789 Guides 70 Float Pins 8 Shapes ----------------------------------------------------------------- DATE: 16-July-2024 Topic(s): Power Supply monitor filter caps moved, route J11 PS Monitor and the Environment Sensors, Expected PMT ADC Voltage Drops Edited the comps (and where necessary the nets) to move the filter capacitors for the Power Supply Monitoring to be next to the J11 PS Monitor Connector. Do not want RF from the DK leaking into the DVM and making inaccurate PS voltage and current readings. This is 22 caps adjacent to J11. Edited: dcdc_1_converter_comps.txt dcdc_2_converter_comps.txt dcdc_3_converter_comps.txt dcdc_4_converter_comps.txt dcdc_5_converter_comps.txt dcdc_6_converter_comps.txt ddr4_fpga_ref_term_comps.txt ddr4_cpu_ref_term_comps.txt always_on_3v3_comps.txt power_input_comps.txt ps_monitor_caps_comps.txt A final draft of the Power Fills, Gnd Slit and lots of Gnd Rivets is now in the design for the PMT ADC. Still need to add Gnd Rivets by the AC Coupling caps for the Serial Links. The calculated voltage drops for feeding the PMT ADC are: Double Expected Expctd Fltr L Power Fill Layer Total Voltage PMT ADC Bus Load mOhms Length Width for mOhm Drop mV ----------- ------ ------ ------------- ------ ----- ------- Analog 1V0 471 mA 15.4 39 mm x 13 mm 20 mm 16.56 7.80 Analog 1V8 102 mA 38.5 45 mm x 12 mm 26 mm 39.89 4.07 Digital 1V0 971 mA 7.3 39 mm x 12 mm 20 mm 8.56 8.31 Digital 1V8 48 mA 38.5 45 mm x 13 mm none 40.30 1.93 The resistance of 1 oz copper is about 0.52 mOhm per square. Recall the AD9083 power supply voltage requirements: pg 4 1V00 buses: 0.95 V min 1.00 V norm 1.05 V max 1V80 buses 1.70 V min 1.80 V norm 1.90 V max Recall the AD9083 absolute maximum power supply voltages: pg 1V00 buses: 1.05 V Absolute Max 1V80 buses 2.00 V Absolute Max 1402 Comps 1405 Nets 3779 Conn Comps ver 732 Nets ver 518 947 Finished 38 Un-Finished 2794 Guides 70 Float Pins 8 Shapes ----------------------------------------------------------------- DATE: 15-July-2024 Topic(s): Work in PMT ADC Power Clean up the existing PMT ADC power fills and ground slits. Add 2nd side fills for half of the length of Analog 1V0 & 1V8 and for Digital 1V0, i.e. for all of the "high" current feeds. Add PVAs for the 2nd side fills and for the inputs to the filter inductors. Add these PVAs to the net lists. Add a sketch for the DCDC-1 to L601 & L603 BULK_1V00 power fill. Start moving the power converter voltage and current monitor final filter caps out of there private comps files and into a common comps file that locates them near the Power Supply Monitor Connector. Need to decide on final placement for DCDC-1 and DCDC-6. 1371 Comps 1405 Nets 3774 Conn Comps ver 722 Nets ver 512 857 Finished 38 Un-Finished 2879 Guides 70 Float Pins 8 Shapes ----------------------------------------------------------------- DATE: 14-July-2024 Topic(s): Work on PMT ADC power feeds and on the 6 step down DCDC converters Got in more of the net lists for the PMT ADC power via arrays. Edited the DCDC converter geometry to have 1 more Aux Gnd pin and added 4 Aux Output pins. Edited the net lists for the 6 converters to pickup these pins. Need to remove the final filtering caps on the voltage and current monitoring from the comps files for these converters and move them adjacent to the PS Monitor Connector. 1355 Comps 1405 Nets 3725 Conn Comps ver 716 Nets ver 509 819 Finished 36 Un-Finished 2870 Guides 70 Float Pins 4 Shapes ----------------------------------------------------------------- DATE: 13-July-2024 Topic(s): Work on adding a Power Via Array to the input of the 6 DCDC converters and on adding 3 or 4 more pin vias to their output pins. PVA added to all 6 DCDC comps files and just to DCDC-1 nets file. 1355 Comps 1405 Nets 3671 Conn Comps ver 716 Nets ver 507 819 Finished 36 Un-Finished 2816 Guides 100 Float Pins 2 Shapes ----------------------------------------------------------------- DATE: 12-July-2024 Topic(s): Work on PMT ADC power feeds, Improve the voltage drop in the ADC feed, email notes about Barnacle and DK mounting Have now added: Ground Slits and Ground Rivets to the layout around the PMT ADC. This is just an initial start but the machinery for this feature in now in the DK design. Also need Ground Return Rivets around the DC Blocking capacitors for the PMT ADC Serail Data Out. Have added some Power Via Arrays to the PMT ADC power distribution. This looks OK but is just getting started. The voltage drops on the 1 Amp runs to the PMT ADC are not trivial. This run is 1 oz copper and is about 15 mm wide and about 40 mm long to the center of the ADC. The resistance of 1 oz copper is about 0.52 mOhm per square. So the 1V0 runs to the ADC are about 1.4 mOhm. I can cut half of this resistance in half just by using the fill layer that is currently unused for half of the length between the filter inductor and the ADC. It's lots of work to add all of this but it's worth it. Also need PVAs at the inputs to the power filter inductors. Also need to add PVAs to the input of the current measuring resistor for each of the 6 low voltage DCDC converters and add 3 or 4 more vias to the DCDC converter Geom I took 3 or 4 hours and wrote the notes about Barnacle Master Reset B and why it's important at Module power up time and a note about DK mounting to the steel plate. Still have the PMT cable note to Vincent to get done. 1349 Comps 1405 Nets 3665 Conn Comps ver 712 Nets ver 505 819 Finished 36 Un-Finished 2810 Guides 70 Float Pins 2 Shapes ----------------------------------------------------------------- DATE: 11-July-2024 Topic(s): Work on PMT ADC power feeds and rotate the DCDC-1 converter 90 deg Testing meeting with Nathan, Jeanne & Dan All PMT ADC bypass are now connected and look more or less reasonable. Rotate the DCDC-1 converter by 90 deg CCW and it now fits better and has a shorter output run to the L601 & L603 power filters. Look up in Terman the selfinductance of round wire to estimate the inductance of the connection to PMT ADC Reg VCO. 5 mil wire is about 30 nH per inch. 1341 Comps 1405 Nets 3637 Conn Comps Ver 708 Nets Ver 502 819 Finished 36 Un-Finished 2782 Guides 70 Float Pins 2 Shapes ----------------------------------------------------------------- DATE: 10-July-2024 Topic(s): Work on power feed to the PMT ADC, Edit drawings: 16, 53, 80, 90 All bypass caps and power filter components for the PMT ADC are now in place. Still some work to do to optimize which side of which cap is Gnd and which is Bus. Power fills to do. It's now fairly clear where to put the Gnd Slices. Looking at rotating the DCDC-1 converter by 90 deg CCW. Edit drawings: 16, 53, 80, 90 to make them current with TOMcat using pin #29 for the 100 Hz signal and with PMT ADC data lanes 0 & 1 being inverted. 1341 Comps 1405 Nets 3619 Conn Comps Ver 692 Nets Ver 498 792 Finished 18 Un-Finished 2827 Guides 70 Float Pins 2 Shapes ----------------------------------------------------------------- DATE: 9-July-2024 Topic(s): Optimize the PMT ADC to FPGA links, Notes from: Michael and Adam At the FPGA end the two traces for a given high-speed serial Receiver can only escape in one way - with the Complement signal above the Direct Signal. At the ADC end the 2 traces in a lane can escape in either order. I can get the cleanest routes by escaping the ADC's Lane 0 & 1 with Dir above Cmp and Lanes 2 & 3 with Cmp above Dir. Thus for Lanes 0 & 1 I'm going to connect Dir to Cmp and Cmp to Dir. This means that we will need to include and Inversion in the data for Lanes 0 & 1 either at the ADC end or at the FPGA Receiver end. From their data sheets it appears that both the AD9083 and the FPGA can do data inversion in their high speed serial Tx or Rx. Lanes 2 & 3 should not inclue inversion. In email from Michael - he wants me to use TOMcat pin #29 as the source of the 100 Hz signal going to the Timing Gen Aux M0 input (not pin 27 - that was an error in the Confluence documentation). In email from Adam - he expects the power draw from the Interposer to be about 0.8 Watts with most of that being on the 3.3V bus. That would imply about 242 mA draw on the 3.3 V bus by each of the 2 Interposers or about 0.5 Amps total on the 3.3 V bus from the interposers. Today was also the Interposer design review. Adam is also concerned about noise on the 5.0 V bus, i.e. does he need to step up and the LDO back down to 5V0 in order to have a clean 5V0 bus on the Interposer. ----------------------------------------------------------------- DATE: 8-July-2024 Topic(s): Work on the PMT ADC bypass and other caps, meeting with Nathan For the first ring of 0402 caps using 0.3 mm trc to the BPA vias where possible and using 0.4 mm trc to 0mm65 via to Gnd where possible. Short meeting with Nathan: will have a testing meeting with group and start looking at the business side and how to start checking the design now side of things. 1348 Comps 1405 Nets 3619 Conn Comps Ver 666 Nets Ver 488 728 Finished 12 Un-Finished 2879 Guides 2 Shapes ----------------------------------------------------------------- DATE: 7-July-2024 Topic(s): Make a smaller version of the 0402 cap Geom, work on tight in PMT ADC bypass and other caps, add more spacing to the PMT ADC input feeds. ----------------------------------------------------------------- DATE: 6-July-2024 Topic(s): Work on PMT ADC placement and Routing Tentative full routes for the PMT ADC Inputs, tentative escapes for the various Clock, SPI, and Control signals so that I can find placements for the close in bypass caps. The 0402 cap is available up to 470 nFd with reasonable dielectric and voltage. I need to make a tighter 0402 cap geom for use under the 0.8 mm BGA, i.e. tighter silk and comp outline - same pad sizes. Things look hopeful that by reaching in a ring or two that I can have quite a few close in bypass caps under the PMT ADC. Need to add Ground Slits and Rivets and then better place the Inductors and Tants. 1348 Comps 1405 Nets 3608 Conn Comps Ver 660 Nets Ver 486 683 Finished 12 Un-Finished 2913 Guides 2 Shapes ----------------------------------------------------------------- DATE: 5-July-2024 Topic(s): Work on PMT ADC placement and Routing Get the Signal_12 Fills file going, Edit PMT ADC Geom for BGA Pads Only pins, Get PMT ADC power filters, Tants, and big ceramics into approximate place, Move J11, DCDC_1, and DCDC_4 for better placement, Move every other PMT ADC input pair up to L3 and clean up all of their routes. ----------------------------------------------------------------- DATE: 4-July-2024 Topic(s): Working on Analog routing and the PMT ADC Working on the PMT ADC input analog routing and on starting the Power Fills under the PMT ADC. The pinout of the PMT ADC AD9083 is rather rational and provides for good pcb routing. Need to move most/all of the PMT ADC comps. The PMT ADC itself is now 13 mm East of its original position. In the center aisles under the PMT ADC one can place 0402 by pass caps. The clearance from Cap SMD Pad to BGA Via Land is OK at about 0.24 or 0.25 mm. The spacing of the Cap SMD Pads is good for connecting to adjacent BGA Vias or to vias skipping one in the middle. In the Horz Center Aisle there is space to get at least one cap on 1V0 Digital and on 1V0 Analog. In the Vert Center Aisle there is space for at least two more on 1V0 Analog. Horz Center Aisle give indirect access to 1V8 Analog for 1 Cap. Work on placing bypass caps under PMT ADC and get: C605 & C606 under for 1V0 Analog, C622 & C623 under for 1V8 Analog, and C638 & C639 under for 1V0 Digital. Edit the PMT ADC Geom to move pins J4 & K4 to use SE vias. There is now a clear path for either a surface escape or an under bypass for pin H4 the Reg_VCO pin that says that it wants a < 1 nH connection to its Bypass to Analog Ground. Why are they more woried about Reg_VCO than about VCourse_VCO ? Work on Power Fills for PMT ADC. Get the machinery setup for DK. L6 is Signal_11 and has the nets: ADC_Digital_1V0 and ADC_Analog_1V8. ADC_Digital_1V0 is on L6 because it is the highest current PMT ADC bus. L7 is Signal_12 and has the nets: ADC_Digital_1V8 and ADC_Analog_1V0. Recall that the Power Fills are on layers Shape_Edit and on Dielectric_1 just for easier viewing. 1347 Comps 1405 Nets 3606 Conn Comps Ver 655 Nets Ver 485 648 Finished 32 Un-Finished 2926 Guides 2 Shapes ----------------------------------------------------------------- DATE: 3-July-2024 Topic(s): Orders, Connector Tail Length, Working on Analog into the PMT ADC The production parts orders are finally started using the GE bla account number. There is still some clean up of the BOM needed, e.g. the two interposer connectors currently have separate company part numbers. The bare DK PCB is expected to be 80 to 90 mils thick. This is a hard to match thickness vis-a-vis some connector tail lengths. The nice 3M 0.1 x 0.1 90 deg headers have either 0.112" or 0.155" solder tails. Assume that the PCB ends up 85 mils thick this results in either: 27 mil tails (a little too short) or in 70 mil tails (a little too long). The longer tails are OK because in the vertical layout we have 4 mm under the card (157 mils). Short Tail Long Tail ------------ ------------ 14 pin N3314-5302RB N3314-5303RB 16 pin N3408-5302RB N3408-5303RB 3M says that Short Tail is for 62 mil PCB and that Long Tail is for 94 to 125 mil PCB. In either case we need the LongLatch/Ejector option. Working on the Analog Diff Pairs from the PMT Input section to the PMT ADC inputs. Run as 0.18 mm width on 0.40 mm pitch. For now this is all on L10 Signal 9 and is a nominal 5 mil distance from L11 Gnd and a nominal 15 mil distance from L8 Gnd. For now there is nothing on L9 in the area of these analog pairs but using L9 does not really help with isolation. For now the analog pairs are spaced 2.0 mm C_to_C. If L3 and L4 remain open in the area of these analog pairs then every other pair will be moved to L3 in the future. Edited the PMT ADC Geom to swing all of its Analog Inputs to the East via escape. ----------------------------------------------------------------- DATE: 2-July-2024 Topic(s): PMT Analog Input Routing, Note from Adam - swap PMT uBase UART Tx & Rx Finished the PMT Conntector to Transformer routing. It looks OK and is all on L9 & L10 with L9 being a 0.4 mm Gnd Return and L10 being a 0.2 mm PMT Signal. Working on the analog routes to the PMT ADC and how much if any can I move the PMT ADC East. Finalize the design of the PMT ADC BGA Geom. Received a note from Adam that he would like the PMT uBase UART Tx & Rx lines swapped on the DK board, i.e. pins 31 and 32 swapped. I did that and explicitly renamed these UART Tx & Rx signals as uBase_UART_Tx/Rx. These names are wrt the uBase_, i.e. uBASE_UART_Tx DK J4/J5 pin 31 is data FROM the uBase going TO DK uBase_UART_Rx DK J4/J5 pin 32 is data FROM DK going TO the uBase This change required edits to Drawings 69 and 72. Now finally have special "Net_Types" assigned to the PMT Analog nets and to the 13 Ghz serial data nets: (NET_TYPE, 'DIFF_ANALOG') and (NET_TYPE, 'DIFF_PAIR_HS'). 1347 Comps 1405 Nets 3606 Conn Comps Ver 650 Nets Ver 483 652 Finished 28 Un-Finished 2926 Guides ----------------------------------------------------------------- DATE: 1-July-2024 Topic(s): RF connectors, Stackup, Besides the Harwin Datamate connectors the some of the other ones that were looked at include: Rosenberger 23C11D-40 (more money same size) and Amphenol FAKRA FM4-NZRP (too big). To route the PMT analog signals I need to stabalize the default stackup and thus the controlled Zo trace widths. This had been rather well studied but I can not find it written down right now. DK needs somewhat more strength than a 62 mil board has so target the thickness in the 80 to 90 mil range. 80 to 90 mil is 2.03 to 2.30 mm range so this mechanically fits 2.5 mm allowed space. This is a 12 layer stack. The 1/2 oz copper is about 0.6 mil and the 1 oz about 1.2 mil. The Isola FR408HR laminate will have a Dk of about 3.6 The overall copper thickness will be about: 2x 1.2 mil (1 oz) + 8x 0.6 mil (internal 1/2 oz) + 2x 2.0 mil (external 1/2 oz) about 11.4 mil total. Plating and Masks will add about 3.5 mils. This leaves about 70 mils for the 11 dielectric layers or about a nominal 6 mils per dielectric layer with 10 mil central core. Using the normal 100 Ohm differential design of: 0.14 mm width 0.4mm spacing center/center with an alternative of 0.5mm spacing cent/cent we know that the outer dielectric will need to be about 3.8 mil thick. The traces will embed in the for an effective thickness of about 3.3 mil. In general I need the dielectric to be thicker between the L3-L4 layers (L9-L10) so that I can have reasonable trace widths for the 100 Ohm differential and especially for the 50 Ohm broadside coupled PMT signal input traces. So for the current width calculations assume that nominal dielectric thicknesses will be: L1-L2 (L12-L11) 3.8 mil L2-L3 (L11-L10) 5.0 mil L3-L4 (L10-L9) 10.0 mil L4-L5 (L9-L8) 5.0 mil L5-L6 + L6-L7 + L7-L8 22.4 mil This lets us use a nominal 0.14 width 0.40 mm pitch differentail pair and a nominal 0.15 mm 50 Ohm on L3, L4, L9, L10. Continue work in the PMT Analog Input section. 1347 Comps 1405 Nets 3608 Conn Comps Ver 650 Nets Ver 481 646 Finished 36 Un-Finished 2926 Guides ----------------------------------------------------------------- DATE: 30-June-2024 Topic(s): Working in the PMT Analog Input I can save a little EW space in the PMT Analog Input section so pull things apart and move the Even column 2.2 mm East and move the Odd column 2.7 mm East and swap the Odd Terminators E for W and move them up 1.8 mm. Now start the routing over again in this area. 1347 Comps 1405 Nets 3636 Conn Comps Ver 650 Nets Ver 481 618 Finished 92 Un-Finished 2926 Guides ----------------------------------------------------------------- DATE: 29-June-2024 Topic(s): More work in the PMT Input section. Make a dual size AKA for between the TVS and the Input Connector. Move both to the bottom side and tight to the connector. Working on recovering EW space in the PMT Analog Input section or in its differential runs to the PMT ADC ? I want a different size routing via for the 50 Ohm analog signals in the PMT Analog Input section. Recall the standard size routing vias that have been frequently use: Pad Drill Ring Name Land Dia Width --------- ---- ----- ----- via_0mm65 0.65 0.30 0.175 Array 0.92 0.46 0.23 via_1mm1 1.10 0.60 0.25 via_2mm2 2.20 1.10 0.55 For clearance I want to keep the Pad Land slightly under 0.80 so make it 0.79. I want the ring to be at least slightly larger than 0.175 so make it 0.195. This gives us a 0.40 mm Drill. So compared to the via_0mm65 the via_0mm79 has: 21.5% larger Pad Land 33.3% larger Drill Dia 11.4 % Wider Ring Make the solder mask relief 0.60 mm so there should be a 0.10 mm thick ring of exposed metal around the drill hole. Make the Plane Relief 1.18 mm to give a Plane to Pad air gap of 0.195 mm and a Plane to Edge of Drill Hole air gap of 0.39 mm. I saved Traces for the escape from the PMT Input Connector and it forces a save of Tech_931 which I think is mostly a change of format not of content. Now by hand add via_0mm79 to the Tech file. In the DC Bias networks move the Resistor to the middle so that the two Capacitors have the direct connections to Ground vias. 1347 Comps 1405 Nets 3390 Conn Comps Ver 648 Nets Ver 481 3 Finished 2 Un-Finished 3385 Guides ----------------------------------------------------------------- DATE: 28-June-2024 Topic(s): Working in the PMT Input section Want to run the signals to the input transformers differentially. Work on some AKA comps to isolate the Input_CMP side of the signals from ground. Which is best - side coupled or overlap coupled ? This is driven by the space available between Input Conn and the transformers. ----------------------------------------------------------------- DATE: 27-June-2024 Topic(s): Verify the Stackup in the CAD Start routing work in PMT Input The board geom is setup with: $$attribute( "BOARD_ROUTING_LAYERS", "", , , , [12, 0]); $$attribute( "POWER_NET_NAMES", "GROUND"); The default_artwork_order_production geom in Disco matches HTM. Disco tech.tech_930 matches HTM. For now I will keep the tech file as is and use it as follows: L1 Top Trace & Pads Signal 1 Physical 1 Yellow L2 Ground Upper with ? Power 1 Physical 7 L3 Trace Signal 2 Physical 2 Green L4 Trace or Fill Signal 3 Physical 3 L5 Ground Mid with ? Power 1 Physical 7 L6 Power Fill 1 oz Signal 11 Physical 6 L7 Power Fill 1 oz Signal 12 Physical 8 L8 Ground Mid with ? Power 1 Physical 7 L9 Trace or Fill Signal 8 Physical 11 L10 Trace Signal 9 Physical 12 Red L11 Ground Lower with ? Power 1 Physical 7 L12 Bot Trace & Pads Signal 10 Physical 13 Light Blue All Power is done as positive Fills. All Ground is Negative. Study how to tighten up the routing in the PMT Analog Input section. There are a lot of points that need to be cleaned up. ----------------------------------------------------------------- DATE: 26-June-2024 Topic(s): Work on BOM clean up & PMT routing BOM some general clean up and decide to make Y1501 installed at build and Not Install Y1502 - so a new Geom was required. Working on getting ready to route the PMT input signals. Move the ESD diode from a SOD-882 package to a DFN-1610 package as that fits better and move them to the bottom side. For now 0.5 mm trace with 0m65 via for the signals and 0.4 mm to escape the connectors and 0.6 mm for the grounds with vias as tight as 0.5mm center to pad edge. Looking at moving and flipping the terminator RCs but its a bit confusing because this had been all well studied. Recall that the: ODD_template file holds the Transformers and DC Bias comps for the Odd channels, EVEN_template file holds the transformers, DC Bias, and Terminator comps for the Even channels, DN_4 template holds the terminators for Lower 4 Odd channels, and UP_4 template holds the terminators for Upper 4 Odd channels. The Odd channel column is to the West and the Even to the East. The DC Bias stuff looks OK - the Terminator stuff needs clean up before routing. ----------------------------------------------------------------- DATE: 25-June-2024 Topic(s): JTAG TRST_B, Timing Gen Connections Finally from the web and TI I think that I understand the requirement for the default not-in-use state of the JTAG TRST_B signal. It should be held Low, i.e. hold the JTAG TAP Controller in a Reset state when it is not in use. So I need to update the Jumpers file. Recall the short meeting with Nathan about connections to the Timing Generator late last Friday afternoon. All is OK and makes sense except connecting Aux M4 to a CLKIN 2:9 (a pure CLKIN does not need to be a CCC CLKIN). CLKIN 2:9 are all in Bank #1 and Aux M4 is a 1V8 single ended signal. I will put it in Bank #9. So the new set of Timing Generator connections will be: TOMcat 125 MHz pins 48,46 Ref_A input U1-F27 GPIO62PB9/DQS/ Ref_A alternative CCC_SE_PLL1_OUT0 U1-G27 GPIO62NB9/DQS TOMcat 100 Hz pin 27 Aux M0 input Aux M0 is a high quality input U1-A29 GPIO57PB9/CLKIN_S_12/ Aux M0 alternative CCC_SE_CLKIN_S_12/ CCC_SE_PLL0_OUT0 TOMcat 125 MHz pins 36,34 A25,B25 GPIO 53 P/N B9 TOMcat 100 Hz pins 30,28 B26,C26 GPIO 54 P/N B9 U1-A30 GPIO59PB9/CLKIN_S_13/ Aux M4 output Aux M4 is a CCC_SE_CLKIN_S_13 high quality output PMT Signal Input final decisions: - As previously decided, I'm connecting the shells of the PMT signal input connectors directly to Ground. Thus I'm forever dumping the Jumper that would allow one to operate these inputs in a pseudo-differential mode. - The Grounded center tap on the 2x 422 Ohm AC terminator on the secondary of the transformer is implemented in PCB layout by using either a single capacitor in the center or two capacitors running to Ground pads. There is no jumper. - I do not like the physical size of the TVS on the PMT inputs. It is fine electrically but I need to find it in a package that is an easier to work with size. Edit drawings: 64 and 90. 1331 Comps 1389 Nets 3374 Conn Comps Ver 633 Nets Ver 477 ----------------------------------------------------------------- DATE: 24-June-2024 Topic(s): Work on the document to describe the Jumpers and Defaults to match Design Work on the document to describe the 40 Jumpers on the DK board and their Default state at Build time. Work on making the Design fit these Defaults and verify the correct use of components and geoms in the design to generate and accurate BOM file. One of the many issues is the required default state of the JTAG TRST_B pin on the FPGA/CPU. The MicroChip documentation is not consistent: - their Board Design Guidelines User Guide on page 15 says: must be connected to VDDI3 through a 1k Ohm resistor must be low for device operation (normal or JTAG operation ?) their schematic shows a 1k Ohm to Ground - their Packaging and Pin Description document days: Weak Pull-Up/Unused Condition YES If TRSTB is unused and in Avionics mode, either a 1k Ohm resistor must be connected to it to override the internal weak pull-up or it must be driven low by an external source. Must be held Low during device operation. - their demo board schematic is not clear but hints that they are counting on the internal weak pull-up to hold the TRST_B line HI. Fix drawing 18 - the VBus pull-up must go to Bulk_5V0. ----------------------------------------------------------------- DATE: 21-June-2024 Topic(s): FPGA Clocks, Scrub BOM, Drawings Working with Nathan to optimize the clock connections to the FPGA for both internal and external routing. Work on scrubing the BOM file. Some significant rot to clean up. Now down to 127 component types. Drawings edited in the past 7 days: 6, 13, 14, 16, 23, 36, 50, 54, 64, 66, 70, 73, 89, 90 So things are not quite stable yet. 1347 Comps 1405 Nets 3422 Conn Comps Ver 629 Nets Ver 474 ----------------------------------------------------------------- DATE: 20-June-2024 Topic(s): Continue search for un-connected pins, Still editing the drawings, Recall how to handle the "special" components The 3 mounting screw holes for the TOMcat are electrical component pins and needed to be connected/grounded. This leaves 10 unknown un-connected pins. Edited Drawings 13 & 14 to fix the FPGA/CPU package type. The 2 DDR4 Terminator/Reference supply chips (U1921, U1941) each have 4 pads that are electrical pins, and are connected to Ground by default of their physical copper connection to the Thermal Pad but were not yet included in the Net List. That leaves 2 un-connected pins to look for. Pin #2 on each of the Crystal Oscillators (Y1501 and Y1502) has no function, is not connected to anything but had not yet been declared as NO_CONN_ pins. Finally zero unknown un-accounted for pins in the design. Edit Drawing #6 to add pins 15...18 to the Ground list. Recall how to handle the "Special" Components: - To keep all instances of a given Geometry out of the BOM, in that geometry use the "COMPONENT_NOT_IN_BOM" attribute. - To indicate a component that is not an actual component that is soldered onto the PCB but is rather a feature of the PCB itself, e.g. Rivets or Pad_Arrays or Diff_Via_Pairs then in the Comps file in the Part_Number column use the part number, "Not_A_Part". - To indicate a component that you do not want the assembly house to install, e.g. a jumper, then in the Comps file in the Symbol column use the symbol, Not_Installed. Recall that the above 3 are often used in combinations, e.g. a Not_Installed jumper is typically assigned a Geometry that has a Component_Not_In_BOM attribute, e.g. a one solder blob version of a res0603. For examples see this Log Book entry from 17-May-2024. This review is preparation for cleaning up the DK design and setting up the Default arrangement of its many Jumpers and its Not_Installed components, e.g. Power Input Converter Trim Resistors R1652 R1653. Review the drawings that include Jumpers: Drw #2 Input Power Converter DK Signal Gnd to Sea Water JMP1651 Will this GND be via a mounting screw or pigtail ? Drw #84 also shown in Drw #42 & #66 SFP Module Tx Laser Disable Control: JMP1171 ... JMP1175 Drw #85 TOMcat Power Control JMP1176, JMP1177 Drw #86 also shown in Drw #14 Crystal Oscillator Disable Control JMP1501 and JMP1502 Drw #12 Default Pull Direction on SCK to the FPGA Boot Memory Install either R1261 Pull-Up or R1262 Pull-Down. Drw #13 Default Pull Direction on TRST_B to the FPGA/CPU Bank #3 Install either R1409 Pull-Up or R1404 Pull-Down. Drw #18 USB Phy Reference Frequency Select Jumpers: JMP1051 ... JMP1056 - for 24 MHz Install 1,3,5 Open 2,4,6 USB Phy VBUS and ID Select Jumpers: R1065 / R1066 and JMP1057 / JMP1058 Drw #78 USB Hub Non-Removable Jumpers: R1073, R1074 Drw #36 TPH Environmental Sensor SDO JMP851 selects I2C Address see datasheet page 32 Drw #44 Emergency Rescue Take Over Control Install JMP1005 to require DK_CPU_NOT_SANE to allow ER Take Over Drw #47 Emergency Rescue uProcessor Boot Mode Install JMP1006 to get In System Programming command line at boot. Drw #68 Emergency Rescue continue RS-485 cable or Terminate jumpers Install JMP1001 & JMP1002 to continue the bus up the RS-485 cable. Install JMP1003 & JMP1004 to Terminate at the top of the String. Drw #83 Emergency Rescue Isolated RS-485 Power Supply Ramp Up Slew Rate Control R1020 Default Open for now Drw #89 Isolate TOMcat Configuration Signals JMP1621 and JMP1622 Default Install. Drw #90 REF_A Input Select C955 & C956 OR C955B & C956B Default Install C955 & C956 M0 Input Select Default Install Jumper for TOMcat This list may not be complete. See also this Log Book entry from 18-April-2024 for the Jumper List as it existed then. Fix Drw 54 and the design for a 3V3 vs 1V8 mistake in the USB I/F. 1347 Comps 1404 Nets 3419 Conn Comps Ver 627 Nets Ver 472 ----------------------------------------------------------------- DATE: 19-June-2024 Topic(s): Clean up the Clocks to Consumers Clean up the FPGA based clocks that are supplied to the USB and BB_ADC peripherals. These clocks now fully fit with the data sheet recommendations. This work involves changes to drawings 18, 37, 54, and 78. Also updated drawings 12 and 59 so that they now indicate the correct FCG1152 FPGA package. 70 of the lost non-connected pins are on not yet connected FPGA byapss caps: C107:C129, C205:C210 for Bank #0, C225:C230 Bank #6. Still looking for 36 pins. Start work on spliting the BOM into normal assembly house comps, not installed comps, and not a part comps. Dig out more unconnected pins: 12 for the M3 Screw Boses for the Interposer Connector Retainer Screws K1, K2, K3, K4. and a bunch of unused gate outputs: U1155 3x, U1402 2x, U1453 2x, U1454 2x, and U1551 2x. I had Tied-Down the inputs to these unused gates but had not declared their outputs as "not connected". This leaves 13 unknown un-connected component pins. ----------------------------------------------------------------- DATE: 18-June-2024 Topic(s): Bring the actual design up to date Edit the actual design to: implement the Erlangen TOMcat changes, swap the T.G. REF_A and REF_B inputs, move the Ethernet SFP to XCVR 1 TxRx 3, move Flash_Now from M0 to M3, move CCC_SE_PLL from M3 to M4, add TOMcat 100 Hz to M0, and BB ADC Clk is 24 Mhz same as USB clock. Remove now unused R602 and R901. Start the search for unconnected pins = 106. Make a current BOM. Drw 90 edits. Change the net list build script so it generates a fully cleaned up output for the following tools. Digging for unconnected. 1336 Comps 1393 Nets 3397 Conn Comps Ver 621 Nets Ver 458 ----------------------------------------------------------------- DATE: 17-June-2024 Topic(s): Work on Drawings and implementing the changes in the actual design Edit Drawings: 50, 70, 90, 73, 89, 64. Working now on bring the actual design up to date. From a quick meeting with Nathan: the connection of M4 to an FPGA clock net is the path for 100 Hz from the Timing generator that can be enabled or durned off via firmware, both the USB and the BB ADC will be given a 24 MHz clock from the FPGA and the CCC_NW PLL can make 24 MHz from the 125 MHz reference.. ----------------------------------------------------------------- DATE: 16-June-2024 Topic(s): Work on Drawings: Edit drawings: 16, 23, 64, 66, 90. ----------------------------------------------------------------- DATE: 14-June-2024 Topic(s): Work on the TOMcat and other changes Worked on both the drawings and the actual design to implement the Erlangen changes to TOMcat and other recent design changes. Had a quick meeting with Nathan. List of TOMcat implementation and other recent changes and effected drawings: 1. Swap XCVR 0 TxRx 0 with XCVR 1 TxRx 3. This is required for clock routing within the FPGA. Drawins 53 and 66. 2. Connect the Timing Generator Aux Pin M4 to an FPGA Clock Input. For the current design we only need M4 to be High at Reset but it is a quality clock path from the Timing Generator so it is stupid to leave it unconnected to the FPGA. Drawing 23. 3. Swap Timing Generator Aux Pins M0 and M3. With TOMcat now directly supplying the 100 Hz clock to the Timing Generator we can no longer use M3 as the 100 Hz input because the M3 pin must be Low at Timing Generator Power Up and Reset. Drawings: 64, 50, 70, 73, and 90. 4. Swap Timing Generator Ref A and B inputs. Required for best routing and use of the Timing Generator. Drawings: 42, 64, 50, 70, and 90. 5. Remove the R602 terminator from the SyncIn_B input to the PMT ADC because we can use an On Chip Terminator. Choose to continue driving PMT ACD SyncIn_B in the differential mode from a differential LVDS pair in the 1V8 Bank #9 - a single ended backup connection is avialable with this pcb trace routing. Drawing 16. Implementation of the Erlangen TOMcat changes require edits to Drawings: 42, 44, 64, 50, 70, 67, 80, 89, and 90. ----------------------------------------------------------------- DATE: 13-June-2024 Topic(s): Work on implementing Erlangen TOMcat changes, quick meeting with Nathan Work on implementing the Erlangen TOMcat changes: UART, JTAG, and the Config signal changes are now in the design and drawings. Nathan found a problem in using Transceiver Bank #0 for the SFP Ethernet. This has been moved to Transceiver Bank #1 Tx3 and Rx3. This location can get the required clocks and still has good routing lanes. Drawings: 2, 43, 44, 53, 60, 67 were edited. More to work on. ----------------------------------------------------------------- DATE: 12-June-2024 Topic(s): Bank #9 Floating Pin work, Start the rework for Erlangen TOMcat Rearrange about 25 pins in Bank #9 to give a more even distribution of the Floating Pin connections. Now has some slack at each end and only goes in 4 or 5 rings. Before pulling things apart for the Erlangen TOMcat - review the current setup of Timing Generator connections to the FPGA: Floating: I2C Bus 2 pins Bank #9 1V8 M5 & M6 2 pins Bank #9 1V8 Fixed: Ref_B F27/G27 CCC_SE_PLL1_OUT0 Bank #9 LVDS M3 J26 CCC_SE_PLL1_OUT1 Bank #9 LVDS OUT_1A F29/F30 XCVR 3A Ref Clk JESD Ref LVDS OUT_1B N13/N12 CLKIN_W_1 CCC_SW_CLKIN_W_1 Bank #7 LVDS From the Timing Generator point of view I believe that the work for the Erlangen TOMcat will change Ref_B and M3 connections. Start work to implement the Erlangen TOMcat: - The pins available on the Rescue uProcessor to implement the JTAG Master for TOMcat are 5, 17, 18, 32. Pins 8 & 9 are free but can not be used as they are "true" Open Drain pins designed for I2C. Using pins 17 & 18 will block the possible use of a Xtal with this ER uProc. This is all 3V3 so that part is easy. Whatever default Pull-Up or Pull-Down can be implemented in the uProc I/O Blocks. Use series term resistors, - The UART connection on the TOMcat is setup for LVDS or 2V5 CMOS levels. DK has no 2V5 I/O so LVDS it is. Will translate 3V3 <--> LVDS with 65LVDS1 Trans and 65LVDS2 Rec with external 100 Ohm at the receiver. - Michael's two Config pins #22 and #23 are 1V8, require Pull-Up resistors and I will add them to the East end of Bank #9. I'm a bit confused about #23 being both a 1 pps in or out signal to the DK FPGA and a Config pin. Does he mean pin 24 for the 2nd Config pin ? Still working on the rest of the Erlangen requirements. ----------------------------------------------------------------- DATE: 11-June-2024 Topic(s): Floating Pin net list work Finished the Bank #1 & #7 Floating Pin net lists and NO_CONN_ pins. Current Status - 89 Floating Pins total Bank #1 Floating Pins: 42 pins Interposer 1 "A" SPI Bus & Address Interface SPI Ctrl #0 8 Pins Interposer 2 "B" SPI Bus & Address Interface SPI Ctrl #1 8 Pins RUN and other Control Signals to the Reset-Startup Circuits 13 Pins Access Differential Signals 2x Diff Pairs 4 Pins Access Single Ended Signals 5x Signals 5 Pins CPU UART #0 Rx & Tx to the Access Header 2 Pins Power "A" & "B" Cameras to the USB Hub Power Control 2 Pins Bank #7 Floating Pins: 20 pins CPU UART #1 Tx & Rx to/from the Rescue uProcessor 2 Pins Timing SFP J13 Control Signals and I2C Bus Ctrl #2S 8 Pins Ethernet SFP J14 Control Signals and I2C Bus Ctrl #3S 8 Pins CPU UART #2 Tx & Rx to/from the Barnacle 2 Pins Bank #9 Floating Pins: 27 pins Timing Generator M5, M6 and I2C Ctrl #0 4 Pins PMT ADC Floating Connections Sync & SPI Ctrl #2S 5 Pins Environmental Sensor & BB ADC I2C Bus Ctrl #1 2 Pins BB Audio ADC Clock and Readout Data 4 Pins Interposer "A" Connections Flash_Now & UART 3 Pins Interposer "B" Connections Muon_Sx & UART 6 Pins USB Phy Reference Clock 1 Pin Configuration Signals from TOMcat to DK FPGA 2 Pins 1325 Comps 1388 Nets 3363 Conn ----------------------------------------------------------------- DATE: 10-June-2024 Topic(s): Floating Pin net list work Worked on the Bank #1 & #7 Floating Pin net lists and NO_CONN_ pins. ----------------------------------------------------------------- DATE: 7-June-2024 Topic(s): Floating Pin net lists, Drawings The Floating Pin net list for Bank #9 is mostly complete. The outlines for the Floating Pin net lists for Banks #1 and #7 are finished and work is started on filling in the Floating Pin net list for Bank #7. Coordination with the NO_CONN_ net lists for Banks #1, #7, and #9 is working OK with just human editing. I made the drawing updates so that the official drawing set now represents the FCG1152 design. Edits were made to drawings: 12, 13, 14, 16, 17, 50, 53, 55, 59, 64, 66, and 72. I still need to make the drawing edits to represent the TOMcat requested changes from Erlangen - about 5 drawings of the print set. ----------------------------------------------------------------- DATE: 6-June-2024 Topic(s): Floating Pin net list for FCG1152 The current task is to generate a net list for all of the "Floating" connections to the FPGA/CPU, i.e. connections to Banks: 1, 7, and 9 that are things like: GPIO, SPI, I2C and discrete control signals. These are specifically signals that do not need to be routed to a specific pin on the FPGA/CPU package. Note that there are a few "Fixed" pin signals also routed to Banks 1, 7, and 9 - these are typically Clock type signals. For the FCG1152 I'm writing separate Floating signal net lists for Bank 1 & 7 i.e. 3V3 and for Bank 9 i.e. 1V8. Also unlike the fcvg784 version of the Floating net list I'm not going to include tons of comments that explain each signal. I will put that explaination material in a separate file. These new Floating pin net lists will focus just on making clear the pin connections. There is the issue of the matching NO_CONN_ lists. I could make the generation of the NO_CONN_ net lists for Banks 1,7, and 9 all automatic but I do not think that is necessary because I do not expect that used and no_conn_ pins will swap around that much during routing. I will keep master pin order NO_CONN_ net lists for each of these 3 Banks that include all signal pins in each Bank, i.e. Bank 1 has 72, Bank 7 has 60, Bank 9 has 96 signal pins. In any case, after a new version of the overall net list is generated then a new version of the FCG1152 needs to be make by executing the build_rev_3_tailored_fcg1152_geom.sh script. You only need to do this if you want a matching geometry with just BGA Pads on all of the unused NO_CONN_ pins. ----------------------------------------------------------------- DATE: 5-June-2024 Topic(s): FCG1152 tailored geom Get all of the scripts and such to automatically build the fully tailored FCG1152 geometry working. So now it automatically picks up pins without a connection or with a top layer connection and uses just an BGA Pad in the Geometry. The rotation of dog-bones and vias and the special East Ground vias for use between the ADC serial link differential pairs are automatically included. ----------------------------------------------------------------- DATE: 4-June-2024 Topic(s): Continue work on FGC1152 net lists. Finished the following FCG1152 net lists: ddr4_cpu_bank_6_data_path_nets_fcg1152.txt ddr4_cpu_bank_6_no_connection_nets_fcg1152.txt fpga_cpu_bank_1_no_conn_pins_fcg1152.txt fpga_cpu_bank_2_no_conn_pins_fcg1152.txt fpga_cpu_bank_4_no_conn_pins_fcg1152.txt fpga_cpu_bank_5_no_conn_pins_fcg1152.txt fpga_cpu_bank_7_no_conn_pins_fcg1152.txt fpga_cpu_bank_9_no_conn_pins_fcg1152.txt The design now builds with the FPGA having 1152 nets. I think that the last 2 may be a Ref Clk pair to the HS Transceiver #0. Work on the automatically tailored geometry for the FCG1152. ----------------------------------------------------------------- DATE: 3-June-2024 Topic(s): Continue work on FGC1152 net lists. Make FCG1152 versions for net lists: boot_memory_fpga_nets_fcg1152.txt, boot_memory__cpu_nets_fcg1152.txt, ddr4_fpga_bank_0_data_path_nets_fcg1152.txt ddr4_fpga_bank_0_address_and_command_nets_fcg1152.txt, ddr4_fpga_bank_0_no_connection_nets_fcg1152.txt Include the Grounded Shield pins in the ddr4_fpga_bank_0_data_path net list file. Start the work on the files: ddr4_cpu_bank_6_address_and_command_nets_fcg1152.txt, ddr4_cpu_bank_6_no_connection_nets_fcg1152.txt, and ddr4_cpu_bank_6_data_path_nets_fcg1152.txt Note the non-consistent way that they count pins in Bank #6, i.e. 87 mss + 1 Vref. The total is 88. ----------------------------------------------------------------- DATE: 2-June-2024 Topic(s): Continue work on FCG1152 net lists Make FCG1152 versions for net lists: crystal_oscillator_nets_fcg1152.txt and tomcat_nets_fcg1152.txt. The TOMcat net list file is now up to date wrt the FCG1152 package but not wrt the Erlangen TOMcat changes. ----------------------------------------------------------------- DATE: 1-June-2024 Topic(s): Continue work on FCG1152 net lists Today completed moving the following net list files over to the new FCG1152 package: pmt_adc_serial_link_to_fpga_nets_fcg1152.txt, sfp_cage_conn_pin_nets_fcg1152.txt, pmt_adc_serial_link_to_fpga_nets_fcg1152.txt Still need to move: boot_memory_fpga_nets.txt, crystal_oscillator_nets.txt, some pins on the TOMcat connector, both the CPU & FPGA DDR Memory connections, and all "floating" FPGA/CPU pins to the new FCG1152 package. I believe that from the Erlangen meeting that I'm supposed to give TOMcat a direct connection to the Timing Gen Mx pins. I need to learn which Mx pin. Recall the Mx pin constraintes to power up time for the Timing Generator. ----------------------------------------------------------------- DATE: 31-May-2024 Topic(s): Netlist for FCG1152 DK design, Meeting with Nathan Work on making net list files for the FCG1162 version of the DK design. I'm forking all netlists that make a connection to the FPGA/CPU into an old FCVG784 version and a new FCG1152 version and keeping both versions. Making a separate file to hold the "fixed" single point nets, e.g. the No Assignment pins in the FCG1152 and the Bank #8 I/O pins. So far have: build_all_disco_nets_fcg1152.sh fpga_cpu_fixed_single_point_nets_fcg1152.txt fpga_cpu_floating_connection_nets_fcg1152.txt fpga_power_and_ground_pins_fcg1152.txt fpga_unused_hs_transceiver_pins_fcg1152.txt jtag_for_fpga_cpu_nets_fcg1152.txt startup_and_reset_nets_fcg1152.txt usb_phy_nets_fcg1152.txt Friday afternoon meeting with Nathan: official decision - push the FCG1152 version of the layout, TOMcat ENet will run to Bank #5 SGMII Rx0 Tx0 pins, Darren is here next week. ----------------------------------------------------------------- DATE: 30-May-2024 Topic(s): Make a 4 quadrant version of the FCG1152 geom. Write a 4 quadrant version of the FCG1152 version, work on a BGA pads only version, and on the full custom version with automatic selection of dog-bones or BGA pads based on current net list. Get far enought that so that layout can run again. Keep the FCVG784 version in a separate sub-directory. ----------------------------------------------------------------- DATE: 28,29-May-2024 Topic(s): Work on a FCG1152 based layout So far it continues to look like the FCG1152 package has a number of advantages including the escape of the 13 GHz lines on the top layer. Expect to use XCVR #3 for the JESD204B ADC data input: Used: Not Used: XCVR_3_RX0_P C32 XCVR_3_TX0_P B34 XCVR_3_RX0_N C31 XCVR_3_TX0_N B33 XCVR_3_RX1_P E32 XCVR_3_TX1_P D34 XCVR_3_RX1_N E31 XCVR_3_TX1_N D33 XCVR_3_RX2_P G32 XCVR_3_TX2_P F34 XCVR_3_RX2_N G31 XCVR_3_TX2_N F33 XCVR_3_RX3_P J32 XCVR_3_TX3_P H34 XCVR_3_RX3_N J31 XCVR_3_TX3_N H33 XCVR_3A_REFCLK_P F29 XCVR_3C_REFCLK_P D29 XCVR_3A_REFCLK_N F30 XCVR_3C_REFCLK_N D30 Expect to use XCVR #0 for the Ethernet connections to SFP and TOMcat: Used: Not Used: XCVR_0_RX0_P R32 XCVR_0_RX1_P T30 XCVR_0_RX0_N R31 XCVR_0_RX1_N T29 XCVR_0_TX0_P T34 XCVR_0_TX1_P U32 XCVR_0_TX0_N T33 XCVR_0_TX1_N U31 XCVR_0_RX3_P W32 XCVR_0_RX2_P V30 XCVR_0_RX3_N W31 XCVR_0_RX2_N V29 XCVR_0_TX3_P Y34 XCVR_0_TX2_P V34 XCVR_0_TX3_N Y33 XCVR_0_TX2_N V33 XCVR_0A_REFCLK_P U27 XCVR_0B_REFCLK_P W27 XCVR_0A_REFCLK_N U28 XCVR_0B_REFCLK_N W28 XCVR_0C_REFCLK_P R27 XCVR_0C_REFCLK_N R28 XCVRs #1 and #2 are not used at all. ----------------------------------------------------------------- DATE: 27-May-2024 Topic(s): Work on understanding the FCG1152 pinout Specifically can the 4 Rec lanes in the XCVR #3 all route out on the top layer ? ----------------------------------------------------------------- DATE: 24-May-2024 Topic(s): Work on DCDC Converters, move Interposer I/F, Next steps All DCDC Converters now have current comps and nets and placement. Things look good except for the DCDC_1 in the SE corner. Moved the Interposer I/F comps south and it now looks routable. Moved JTAG Buffer and BB Audio ADC south to try to make a uniform 5 mm relief between any comp and closest edge. That now looks better. No drawing edits this week but the latest changes for Michael are not yet in the design. The intent is to use Jumpers to avoid stubs in the situation where he wants to change between TOMcat and FLATcat which can not be done once a module is assembled anyway. I need to sketch out how to get his latest requests into the design and then make proper drawings. This effects the Clocks, Emergency Rescue, FPGA Bank #9, and ? I need to study the advantages of using the larger FCG1152 1 mm package. FCG1152 is 34 x 34 1.0 mm pitch 33.0 mm/side FCVG784 is 28 x 28 0.8 mm pitch 21.6 mm/side The FCG1152 has its 4 corner pins removed & is 11.4 mm larger per side. The FCG1152 bonds out 4 groups of 4 HS Transceivers instead of the 2 groups of 4 HS Transceivers in the FCVG784. 1324 comps 1038 nets 3292 conn Comps Rev 611 Nets Rev 395 ----------------------------------------------------------------- DATE: 23-May-2024 Topic(s): By compressing DCDC2 & DCDC3 was able to move FPGA south by 20 mm, Copy new DCDC comps to DCDC3, make each DCDC nets a separate file All 6 DCDC converters now have their new comps files and all but DCDC_5 and DCDC_6 have their new nets files. Start the work to find the best locations for DCDC_4 ... DCDC_6. A quick visit from Nathan and he wonders how much work it would be to connect the TOMcat ENet to its normal Bank #5 SGMII pins instead of to Transceiver pins. ----------------------------------------------------------------- DATE: 21-May-2024 Topic(s): Note to Michael, work on DCDC Converter vertical size under FPGA, quick meeting with Nathan Got a technical note written to answer Michael's questions about the +5 Volt feed to the TOMcat. Compressing the vertical height of DCDC2 and DCDC3 under the FPGA looks good enough that I should carry it over to the other 4 DCDC converters. Part of the squish has been moving from Wurth size 1210 to Wurth size 8070 input filter inductors. 74433 Induc- Rated DC Self Part Geometry tance Current Resistance Resonance ----- -------- ------ ------- ---------- --------- 21000 W1210 10 uH 9.0 A 15.4 mOhm 29 MHz 41000 W8070 10 uH 4.4 A 38.5 mOhm 29 MHz 20470 W1210 4.7 uH 15.5 A 7.3 mOhm 43 MHz 40470 W8070 4.7 uH 7.5 A 12.7 mOhm 45 MHz W1210 geom is 12.1 x 11.4 mm W8070 geom is 8.4 x 7.9 mm The converters require a minimum of 2.2V input or Vout + 0.5V as the minimum so 3.8V can run any of the 6 converters. The converter with the heaviest input current is DCDC3 1V2 with a 1091 mA input current. Next heaviest is DCDC2 1V05 with a 724 mA input current. The other 4 converters all have under 500 mA input current. So a choke with 38.5 mOhm resistance is OK. Move all converter input filters to 10 uH 4.4 A rated. Converter details are in 17-Nov-2023 update of the DK Power Supply Description document. ----------------------------------------------------------------- DATE: 20-May-2024 Topic(s): Work on clean up of the Timing Gen layout and on getting the Floating FPGA pins up to date, and DCDC-2 Work on compressing the vertical height of the two DCDC converters that are directly South of the FPGA. So far the squish is 10.5 mm with more possible if I move from the 15.4 mOhm input choke to the 38.5 mOhm version - which has to be fine for the 1.05V and 1.20V converters. Trying to not change too much of the schematic. 1324 Comps 1039 Nets 3291 Conn 579 Comps_Ver 385 Nets_Ver ----------------------------------------------------------------- DATE: 17-May-2024 Topic(s): I need to sweep back through the comps files to get straight all of the "not installed" parts, work on layout clean up of: USB Phy, BB ADC and sensors Recall the syntax for the not installed resistors, jumpers,...: JMP1543 Res_Zero_Ohm_0603 Not_Installed res_0603_1sb x y s r R2204 Res_4.99k_Ohm_0603 Not_Installed res_0603_1sb x y s r or for a cosmetic part e.g.: DPV518 NOT_A_PART SY_JUNK DIFF_PAIR_THRU x y s r AKA1 Not_a_Part SY_JUNK AKA_1MM20 x y s r In all cases the associated geometry must include the attribute "COMPONENT_NOT_IN_BOM". The Sensors, BB ADC, and USB Phy are cleaned up and basically ready to route. I should rotate FPGA Boot Memory by 90 deg CCW. Today edit drawings: 13, 17, 18. This week edit drawings: 12, 13, 17, 18, 51, 52, 59, 72, 73, 86, 88. DDR4 Notes: 2.5 Volt Vpp supply powers the Internal Word Line and averages about 2 to 4 mA in standby or active modes increasing to 10 to 20 mA in Refresh mode. These are average current draws. It draws power in narrow pulses of 20 to 60 mA. VRefDQ is internally generated in the DRAM. The Controller must set its VRefDQ to the proper matching value. Routing details of the Command Address Bus see Micron TN41-13 "DDR3 Point to Point". Micron DDR4 has on die capacitors for its core and I/O, i.e. Vdd-Dss and Vddq-Vssq. External decoupling is still needed. Core tends to have low frequency decoupling requirements. I/O tents to have high frequency decoupling requirements. 4 caps around the device, 1 in each corner. May want/need caps on both sides. Sor the smaller value I/O support caps want their physical size t match the I/O frequency, i.e. data frrequency/rate. From Page 17 of the Micron: Vdd 25 uFd per device - prefer multiple small value caps Vpp 3 uFd per device - 3x 1 uFd near the Vpp pins Vtt 1x 1 uFd per 2 Terminators on the CA Bus VRefCA 1x 100 nFd per device between VRefCA and Gnd or Vdd From MicroChip: 3.9.1.1 pg 64 DDR4 use the 2400 Mbps speed bin for 800 MHz controller speed 7.- pg 140 DQ bit swap within a Byte on pcb between Controller and Memory is supported. 7.3 Pg 145 Shows "Shield" between DQ groups. 7.3.1 Pg 145-147 DDR4 layout guidelines. Appendix Pg 163 Supported DDR4 devices 3.4.3 Pg 18 Integrated Phy 3.4.3.1 Pg 19 I/O Lane Each Data Lane uses one I/O Lane. Table 3-14 Pg 26 Shield is only on the Fabric DDR (not CPU) 7.1.12 Pg 28 I/O In the Command Address Bus Clock vs DQ Bus DQS the timing is such that the Clock can have a longer route that the DQS. Clock be upto 85 psec shorter or up to 935 psec longer than DQS. Typical layout requires longer Clock routing than DQS routing. ----------------------------------------------------------------- DATE: 16-May-2024 Topic(s): Finish getting in all of the current Interposer I/F circuits, drawing work, Clean up and move JTAG and CPU Boot Mem. All of the current Interposer interface is now in the design. Edit drawings: 52, 72, 73, 88. Start the work to get all of the current FPGA/CPU Floating pins back into the design in Banks #1, #7, and #9. Added a 2nd pull resistor to TRSTB in the JTAG circuits because it is not clear which way you need to default pull on it. Need to edit drawing 13. ----------------------------------------------------------------- DATE: 15-May-2024 Topic(s): 1V8 to/from 3V3 Conversion for some of the Interposer signals, Notes from Michael about new TOMcat pinout, Problem with Pin Count Script The Interposer I/F needs 1V8/3V3 conversion no matter what because the Flash_TDC signals from the Interposer are 3V3 and on DK they connect to the 1V8 Mx inputs of the Timing Generator. There are many possibilities for conversion. I do not want Open-Drian because it is the Positive edge that we need to time. I dot want the non-buffered single FET type of translators because the signals come from a long cable run. I want multi vendor. I want fast because we are timing the arrival of these signals. So what is left is the normal xTy45 type of translators. Because the things that need translations are kind of spread around I'm going with the 2T version, e.g. 74AVCH2T45 or 74AXCH2T45 from TI, NXP, and others. Use the 8 pin, 0.5 mm pitch, 3.1 mm lead tip to tip package width, i.e. VFSOP-8. Use one 2T45 package to receive the two FLASH_TDC signals and convert them to 1V8 and send them to the Timing Generator. The DK could generate the Flash_Now signal as 1V8, send this directly to the Timing Generator M0 input, and send it to both channels of another 2T45 package for conversion to 3V3 and from there to the two Inputerposer connectors. The 4 Muon S1:S4 signals could use two more 2T45 packages so that DK would receive them as 3V3 from the Interposer connectors, convert to 1V8, and send them to Bank #9 on the DK FPGA where I believe there are more free pins than in the 3V3 banks. I will lay it out so that all uses of the 2T45s are with their DIR pin grounded, i.e. B side is the Input and A side is Output. Received 3 or 4 notes from Michael about a new pinout for the TOMcat. His last note has a short overall list that I need to study. The Pin Count part of the overall net list build script has an error that it will counts pins described in comments. MG ignores the comments but the easiest fix is to make it the same as the comps build, i.e. pull out all comments before the Pin Count and before handing it to MG. ----------------------------------------------------------------- DATE: 14-May-2024 Topic(s): Layout work, Edit Drawings Finished the Interposer SPI & Adrs parts, it's everything else needs level translation for the Time Gen. M0. M1. M2 inputs. We could just 3.3V drive a 1.8V operated LVC244 to save on a part type but it looks like that would be pretty slow. Also finished the Interposer UART circuits - now cleaner. Still no Top Layer solution for the PMT ADC data. Edit Drawings: 12, 51, 59, 86 to catch up on changes. ----------------------------------------------------------------- DATE: 13-May-2024 Topic(s): Talk for Erlangen, Interposer work, PMT ADC to FPGA routing issue, note from Michael about TOMcat Conn pinout DK board talk for the Erlangen meeting was today. Screw up with my version of Zoom that would not let me un-mute. No error or warning message from zoom about it being an old version or that causing the block of un-mute. Moving the mentor design to the new much cleaner Interposer I/F. There is a major problem with the proposed routing of the PMT ADC signals. I can not escape all of the FPGA Receiver Lanes on the top layer. Yet another pinout mess with this part. Received a note from Michael about changes or additions to the TOMcat connector pinout. I still need to understand what he wants for JTAG and UART - is it really DK CPU or Emergency Rescue. ----------------------------------------------------------------- DATE: 12-May-2024 Topic(s): Work on the slides for the Erlangen meeting all day ----------------------------------------------------------------- DATE: 10-May-2024 Topic(s): Finish the comps and nets for the USB Hub circuit section. Still need some clean up of USB Phy, JTAG Buf, and Interposer I/F. Plots for talk. Still need to work on moving the FPGA South. Make a couple of plots for a talk on Monday. No change to any drawings this week. Edit the connection counting in the netlist build script to add the USB Hub chip and to put the counted items in rational order. 1346 Comps, 1055 Nets, 3322 Connections ----------------------------------------------------------------- DATE: 9-May-2024 Topic(s): Working on putting the USB PHY comps and nets back into the dessign and on entering the 2 Port USB Hub. Moved the: FPGA Boot PROM and Mux, Crystal Osc, and JTAG Buffers to new semi permanent locations. Fix the Invalid Net Warning: Invalid NET statement on line 5195 of /home2/designs/boards/Disco/Disco_pcb/pcb/nets.nets_341 was just a missing comment flag in the Barnacle nets file. ----------------------------------------------------------------- DATE: 8-May-2024 Topic(s): Isolated Power Supply work, what moves next All of the Isolated power supply and RS485 transceiver are now in the design. Most of it looks OK and should be routable as is. There is going to be a large flux of signals in this area mostly a vertical group at about the center of the polypropylene capacitors. In this same area need planes for: Bulk_3V3, CNST_3V3, Rescue_3V3?, filtered power for the Iso_5V0 converter, and the main BULK_5V0 needs to run under at least the output parts of this area, and it would be nice to route the far leads to the polypropylene caps on a 1 oz planes layer. FPGA BOOT Prom stuff could move to about 69.5 166.0 Y1501 could move to about 63.0 179.5 Y1502 to 75.0 179.5 J12 could stay vertical and be centered over GDT1001 then the USB Phy could be to the East of J12 and USB 2 Port to the West of it. CPU Boot PROPM may be able to come down to the area of around 87.5 185.5, then only the U1401 U1402 JTAG buffer is left up above the converters in the NW corner. The Boot PROMs are close enough so that I can drop the series terminators from both of them. DCDC5 Bulk_2V5 can move East a little to make more space for the CPU Boot PROM and escapes from the North edge of the FPGA. Started more MSU Training at 9:45 and about 1 Hr into it the site quit responding and my PW appears to be dead. ----------------------------------------------------------------- DATE: 7-May-2024 Topic(s): Work on the RS-485 Transceiver and it Isolated Power Supply Work on compacting the placement of the Isolated RS-485 Transceiver and its Power Supply and the RS-485 Terminator. Get side tracked into compacting the DCDC2 and DCDC3 Converters because I need to move the FPGA/CPU South by 20 mm or so. Also needed to compact the BOOT PROM and its Mux for the FPGA. That now looks tight. The plan for the DDR4 data lane escapes does not work mostly because of the pinout on the FPGA. I will next try 2 adjacent physical layers per lane, i.e. more complicated and more risk for timing but much more flexable. Stuck with a nets file error, "Warning: Invalid NET statement on line 5195 of /home2/designs/boards/Disco/Disco_pcb/pcb/nets.nets_318". I'm not certain when in the last day or two this came into the design. ----------------------------------------------------------------- DATE: 6-May-2024 Topic(s): Work on CNST_3V3 and Rescue uProc Worked on compacting the Always_ON 3V3 supply and the RS-485 Emergency Rescue components and making these layouts routable. Their QFPs were moved to the top side for easier assembly. In the scrum Christian confirms that Barnacle UART is 3V3. ----------------------------------------------------------------- DATE: 5-May-2024 Topic(s): Bring the design net lists up to date with the 125 MHz input change, start work on DDR4 CAC routing, Did NSF Demographics and MSU DEI > 2.5 Hr. Edit: Timing Gen, Floating, Crystal Osc net lists for the 125 MHz connections. The data path part of the DDR4 routing looks doable on 4 layers but part of it (bits 23:16) is not clean at all and needs to be fixed. To to the CAC part in a "fly by" way will require 4 layers or will require dual tracking in the 0.8 mm BGA which is a more expensive pcb. ----------------------------------------------------------------- DATE: 3-May-2024 Topic(s): Final decision to move 125 MHz inputs, Work on DDR4 layout, Drawing edits Work on the DDR4 data path layout that keeps each byte on its own physical pcb layer. It is possible to escape the FPGA BGA in with this scheme byt the order of the signal is not very good in some cases and there is still the issue of no ground plane between L3/L4 and L9/L10. Next look at a more complicated scheme to use two physical layers in each byte. In order to pick up direct PLL Reference type inputs to the CCC_SW clock conditioner (and keep the direct inputs to the Fabric Global Clock nets) I will move the two 125 MHz clock inputs to the FPGA. The Timing Generator 125 MHz output OUT_1B will move from CLKIN_S_3 to CLKIN_W_1 The 125 MHz Crystal Oscillator output will move from CLKIN_S_2 to CLKIN_W_0 The old S_2 & S_3 inputs are PLL Feedback type inputs to the CCC_SW clock conditioner circuit. For reference to the details of this change the full pin names are: Old input pins are in 3V3 Bank #1: pin D3 GPIO171PB1/CLKIN_S_2/CCC_SW_CLKIN_S_2/CCC_SW_PLL1_OUT0 pin C3 GPIO171NB1 pin A2 GPIO173PB1/CLKIN_S_3/CCC_SW_CLKIN_S_3 pin A3 GPIO173NB1 New input pins are in 3V3 Bank #7: pin G5 GPIO167PB7/CLKIN_W_0/CCC_SW_CLKIN_W_0 pin G4 GPIO167NB7 pin F4 GPIO164PB7/CLKIN_W_1/CCC_SW_CLKIN_W_1 pin F3 GPIO164NB7 Drawing edits this week: 14, 19, 23, 43, 50, 64, 70, 79 ----------------------------------------------------------------- DATE: 2-May-2024 Topic(s): Continue work on the Clock Generator DDR4 Data Path work Work on the Timing Generator includes: add zero Ohm jumpers in the output OUT0B DC coupled feed to PMT ADC System Reference, Special pull-up voltage source for the output OUT0B so that we can meet the 0.5 Volt common mode for the System Reference, and the question should we swap the Timing Gen and Xtal Osc 125 MHz feeds to the FPGA, which are currently CLKIN_S 2 & 3 for CLKIN_W 0 & 1 to pick up pins that are also PLL Reference type inputs to CCC_SW ? Working on a data path layout for the Fabric DDR4 that puts each of the 4 bytes on its own layer with all signals for a given byte (8x DQ, 1x Mask/Invert, 2x DQ Strobe) held to just that layer. The DDR4 chips are rotated so that their A row end faces the FPGA. Still have Gnd Plane issue in the BGA escape area. ----------------------------------------------------------------- DATE: 1-May-2024 Topic(s): DDR4 orientation and routing, Remaining steps in getting the design ready to route, what can move where, work to get Timing Generator up to date, FPGA Clock Pin Questions/Issues The following areas in the design are still not up to date: Emergency Rescue, USB Phy & Hub, Interposer Interfaces, Timing Gen. The following areas in the design still need to be moved: Boot PROMs & their Mux, Xtal Osc, JTAG Bufd, BB ASDC & Sensors, Always On 3V3 supply. Need to understand the height available under the TOMcat's SFP Cage in order to understand how far South the 1V05 and 1V20 Converters can move. Need to push on the Fabric DDR4: it looks like the memory chips need to rotate to put the CAC bus to the East or South. The intent is still to put all of the DQ bus (either 0:15 or 16:31) on a single adjacent routing pair, i.e. L3,L4 or L9, L10. The issue remains that at 12 layers there is no Ground Plane between these pairs and they route on top of each other while under the FPGA/CPU BGA. Is there a problem using CLKIN_S_2 and CLKIN_S_3 ?? These pins are Feedback type CCC Clock Inputs. There are two pins with the lable CCC_SE_CLL1_OUT0 F22 & E21 can either one have a direct "in-Bank" connection to CLKIN_S_12 ----------------------------------------------------------------- DATE: 30-Apr-2024 Topic(s): More work bringing the design up to date, Josh Spitz Seminar, TOMcat final design review The TOMcat Power Switch comps and nets were added back into the design and made to match the drawings. Barnacle IF comps were moved around so that everything fits on the bottom side under the big caps. Comps are arranged so that it should be one side routable. The AC Cooupling Caps for the SFP Receiver signals are now in the design. They are tight wrt the TOMcat connector. All of TOMcat Connector signals are now in except for the JTAG and the UART. This is still very confusing - Michael said that he wanted these connected to the DK FPGA/CPU but that is useless if the TOMcat is down and thus the DK FPGA/CPU has no connection to shore. Shouldn't TOMcat JTAG and UART be connected to the RS-485 Emergency Rescue system ? ----------------------------------------------------------------- DATE: 29-Apr-2024 Topic(s): Barnacle and USB Power Control, Working in understanding DDR4 Shield Bring the design up to date to match the drawings in the Barnacle and Dual USB Power Control sections. Move the parnacle J7 connector slightly further West so that it now centerlines on the big caps. This allows the possibility to move the 1V05 and 1V2 Bulk supplies about 9 mm South if they can be rearranged to keep their height under that required by TOMcat. For now I will fuse the Barnacle, USB, and TOMcat with actual "nano" fuses from Littelfuse rather than PTC "fuses". ----------------------------------------------------------------- DATE: 26-Apr-2024 Topic(s): Work on the Xtal Oscillator and SFP Module components and nets, Checking clock connections yet again Component placement and netlist work in the Xtal Osc and SFP Modules. Much of the SFP file related work involves removing all of the I2C and SPI fanout / multiplexer junk that used to be in the design. Things are much clean because we now use soft controlers to have extra I2C and SPI ports. Rechecking the drawings and netlist files to verify that all of the Clock signals are up to date. See the 8-Mar-24 entry for the most recent TOMcat notes. Error in drawing 50 that has the wrong pin number for the CLKIN_S_3 input of the 125 MHz from the Clock Gen OUT_1B port. 10-Apr-24 entry has the most recent information about the 4 "clocks" to the PMT ADC. Drawing edits this week: 5, 11, 14, 50, 56, 84, 85, 86 With lots of stuff pulled out: 1198 Comps, 862 Nets, 2956 Conn. ----------------------------------------------------------------- DATE: 25-Apr-2024 Topic(s): More work on the Startup/Reset/Enable circuits Finish the SFP Tx Disable and the Xtal Osc parts of the Startup/Reset/Enable circuits. Lots of rearrangement of parts under the polypropylene capacitors. The intent is to fit the USB and TOMcat power switches under the lower polypropylene capacitor. ----------------------------------------------------------------- DATE: 24-Apr-2024 Topic(s): Startup/Reset/Enable Nets The comps are in for the Startup/Reset/Enable and look more or less rational. They are mostly under the upper polypropylene cap. Still an issue of how to organize the placement of the associated jumpers. Work on the Nets file for these circuits and on placing the USB and TOMcat power switches under the lower polypropylene cap. Need to add a Property to the 100V input power nets so that they can have their own set of design rules. I got to spend some time talking with Sim who is here for a week. ----------------------------------------------------------------- DATE: 23-Apr-2024 Topic(s): Startup/Reset/Enable Comps and Nets Work on bring the Startup/Reset/Enable components and net list up to date with the drawings. Start at 1275 Comps, 927 Nets, 3142 Conn, then drop the Startup/Reset nets file so I can freely work on the associated Comps. I want to try placing a lot of this under the upper polypropylene capacitor so for now also drop the RS-485 ER comps and nets. This puts things at: 1235/878/2938. Now edit startup_and_reset_comps.txt to make it the same as current drawings. Use a 5.0 mm minimum between normal signal pads / traces / vias and anything to do with the 100V power pads / traces / vias. To picture how far the routing is likely to stick out past the component geometries in this Startup/Reset/Enable section - recall some typical routing of this type on other cards: Edge of component pad to center of Via for typical situations: logic signal nominal min 0.6 mm 0.18-0.20 mm Trc 0mm65 via 100 nFd 0603 0.6 mm 0.60 mm Trc 0mm65 via 10 uFd 1206 0.9 mm 1.20 mm Trc 1mm1 via V case Tant e.g. 330 uFd 1.6 mm 1.2-2.0 mm Trc 1mm1 via V case 2x Gnd vias 0.5 & 1.0 mm 2x 1.20 mm Trc 2x 1mm1 via ----------------------------------------------------------------- DATE: 22-Apr-2024 Topic(s): Power Input Filter and Converter Routing, IC comps on the bottom Ended up with 3 mm minimum clearance around the 100 Volt traces and pads. Recall the IPC-2221B specifications: 150 V requires 0.20 mm internal and 0.6 mm external uncoated 500 V requires 0.25 mm internal and 2.5 mm external uncoated The input current to the 100V converter should be no more than 0.25 Amps and even a 1 mm trace can handle that. I will run at least 2x this and need to connect to the via tunel copper on multiple levels. With 1 mm trace I can still route between the Brd mounting screw and the J1 mounting screw and maintain at least a 3 mm clearance. The output current from the 100V to 5V converter will not be more than 4 Amps. With 1 oz copper and 10 deg C rise a 2.1 mm wide trace can handle that. I will route DK with at least 2x this width and need multiple vias to reach the Ground and 5V planes. List of IC components that I will try to put on the bottom side where there is a total of 4mm between the bottom surface of the pcb and the metal mounting plate: all of the 14 and 16 pin discrete logic packages, TPS3808 startup supervisors, LT3060 always on regulator, 1.6 uH 60 mOhm chokes, the 0.47 uFd 250V ceramic caps (2.5mm thick), Diodes Zener, Reverse Protection and Schottky, Tants V case and maybe even D case, Isolated RS-485 Transceiver, single LVDS translator, both Boot PROMs (2.5 mm thick), MIC2544 TOMcat Power Switch, MIC2026 dual USB Power Switch, others ? ----------------------------------------------------------------- DATE: 21-Apr-2024 Topic(s): Work on compacting the placement of the Input Power Filter and 100V Converter Compact the placement of the Input Power Filter and the 100V Converter while keeping a 4mm clearance around all 100V Feed and Return pads and vias. ----------------------------------------------------------------- DATE: 19-Apr-2024 Topic(s): Finished clean up of DK Drawings, Start update of the actual CAD design In about the last 10 days I edited DK Drawings: 2, 14, 16, 19, 36, 42, 44, 47, 50, 55, 56, 66, 68, 70, 78, 81, 82, 83, 84, 85, 86, 87 These edits are mostly small changes and effect only the internal DK design - not the interface to external world. I believe that the drawings are now in good shape. Start the work to bringing the actual DK design up to date so that it matches the DK drawings. Most of the work is in the areas of: Power Input and +100V converter, Interface to the Interposers, Power Up Supervisor and Reset/Enable circuits, and RS-485 Rescue. In the 100V power input, filter, and converter section I will hold all pad and via clearances to 4 mm or more. This may require un-grounding the mounting screws on J1 but that is not a problem. Doing a tight placement squeeze in this area because I must save space for the unknown technical areas. Final decision - try pushing all of the QFN parts and all other parts with a thermal type pads type on to the top side of the board so that we only need Via Plugs from the top side. ----------------------------------------------------------------- DATE: 18-Apr-2024 Topic(s): Work on the clean up of the Emergency Rescue System, TOMcat questions, Start the overall list of Jumpers Remaining TOMcat Questions / Work: - Does TOMcat really want a JTAG bus from the DK's FPGA/CPU ? How can that work - if TOMcat is dead then the DK FPGA/CPU can not communicate with anything so a JTAG controller based in the DK FPGA/CPU can not rescue the TOMcat. Does Michael actually want a JTAG controller based in the RS-485 Emergency Rescue uProcessor ? - Does TOMcat really want a UART connection with the DK's FPGA/CPU or should it be with the RS-485 Emergency Rescue uProcessor ? - Michael wants some "spare lines" between the DK's FPGA/CPU and the TOMcat. These will be LVDS but I still need to get them into the design. Overall Jumper List - current count = 21: J1 Connect the DK Ground Planes to the Sea Water Reference J851 Temperature/Pressure/Humidity Sensor - Install, i.e Gnd pin 5, for I2C operation with default address. J1001, J1002 Connect the RS-485 Bus in the Module to the Up going Main Cable. J1003, J1004 Connect the RS-485 Bus in the Module to the Terminator (for the top module only). J1005 When installed requires the DK CPU to be NOT SANE to allow the Emergency Rescue system to take over the DK FPGA/CPU Boot PROM. J1006 Open for Normal Operation - when Installed the Emergency Rescue uProcessor will go to its In System Programming command handler at boot time. J1051, J1056 Are used to set the Reference Clock Frequency for the USB Phy Chip U1051. For a 24 MHz Reference Clock install: J1051, J1053, J1055, and Open J1052, J1054, J1056, i.e. all 3 pins are HI. J1057, J1058 Are used to set the Device vs Host operation of the USB Phy Chip. J1057 should be Open. Install J1058. J1171 Timing SFP Tx Laser is always ON. J1172 Timing SFP Tx Laser is forced OFF until DK FPGA/CPU is Sane and then this Tx Laser is controlled by the DK FPGA/CPU. J1173 ENet SFP Tx Laser is always ON. J1174 ENet SFP Tx Laser is forced ON until DK FPGA/CPU is Sane and then this Tx Laser is controlled by the DK FPGA/CPU. J1175 ENet SFP Tx Laser is forced OFF until DK FPGA/CPU is Sane and then this Tx Laser is controlled by the DK FPGA/CPU. J1176 Delayed_All_Power_Good AND DK_CPU_Is_Sane AND Run_TOMcat must all be asserted HI for the TOMcat to receive power. J1177 TOMcat receives power as soon as the Delayed_All_Power_Good is asserted HI. After that, assertion HI of both the DK_CPU_Is_Sane AND Stop_TOMcat is required to power down the TOMcat. J1501 When Open the 125 MHz Xtal Oscillator will always be Enabled. When installed the 125 MHz Xtal Oscillator can be turned OFF by asserting HI both: DK_CPU_Is_Sane AND Disable_125_MHz_Xtal_Osc. J1501 When Open the Spare Xtal Oscillator will always be Enabled. When installed the Spare Xtal Oscillator can be turned OFF by asserting HI both: DK_CPU_Is_Sane AND Disable_Spare_Xtal_Osc. ----------------------------------------------------------------- DATE: 17-Apr-2024 Topic(s): Over Voltage parts, Screw Block Placement, TOMcat work, Reference Designator clean up in the Emergency Rescue circuits. Final decision on what overvoltage protection parts to use: move to SMD varistor: Bourns PV95K4032 Vdc = 125, Vdc nom at 1 mA = 150, 10 Amps @ Vdc = 250, continuous power 0.25 W, Imax 8/20 usec = 1200, 440 pFd move to a 8mm Gas Tube: Littelfuse GTCS28-201M-R10 could also use GTCS28-231M-R10 GTCS28-251M-R10 Sparkover = 200, DC Holdover < 135, 20 Vnom at 1 A, 8/20 usec 10 hits 10kA, 10/1000 usec 300 hits 100 A, AC for 1 sec 10 hits 10 A, 1 pFd Made the required geometries and these parts are now in the design. PEM Screw Bocks ordered and these parts are now in the design. I did the "patch" on the TOMcat board and Michael tested it. He says that it is working OK. This patch is swapping the two sides of the differential TX signal to the SFP. In the FPGAs that I'm accustom to working with one can swap the sides of a High Speed Differential signal right inside the FPGA. I assume that the TOMcat Lattice part does not have this feature. Just started the reference designator clean up in the Emergency Rescue circuits, Drawings: 44, 47, 67, 68, 82, 83. ----------------------------------------------------------------- DATE: 16-Apr-2024 Topic(s): Interposer Lock work, TOMcat with Michael Another round of Interposer Lock details with Adam. This now looks stable enough that I made a geometry for the 4x PEM Screw Blocks that will go on the DK. They look OK and even with them there is still a little over 10 mm for the head of the center mounting screw on the North edge of the DK board. The M3 button head should be a little under 6.0 mm in diameter and with a built in washer 6.9 mm in diameter. I've setup the Screw Block geometry assuming that I will not solder the PEM parts to the DK board (doing so looks like it has a number of problems besides mechanical sstrength). Rather the idea is to drill and tap the PEM parts in the center of their bottom surface for an M2.5 machine screw. Their mechanical alignment pins will hold the screw blocks square to the North edge of the pcb. Got the TOMcat running with the rest of Michael's setup at MSU and he has finished loading new firmware onto it. I now need to do the patch, i.e. criss-cross the Tx lines to the SFP on the TOMcat. Lots of email messages today. ----------------------------------------------------------------- DATE: 15-Apr-2024 Topic(s): Work on the Interposer Connector Lock TOMcat ready for work Finished a detailed mechanical drawing of the of the Interposer Cable Lock setup on the DK board and send a note to Adam noting a couple of difference in dimensions compared to his notes and drawing - so this still needs a little more work. Also note that providing space for these 4 screw blocks on the DK will require moving the J4 and J5 Interposer connectors further apart from each other. Need to get some of the SMTRAM3-7-5ET parts and talk with the Machine Shop about drilling a center hole in them from the bottom to mount them. I do not want to use just a solder mount. The TOMcat is ready to leave setup for Michael to work on it but I will not power it up until morning when I can watch it for a day. ----------------------------------------------------------------- DATE: 13-Apr-2024 Topic(s): Work on the Interposer Connector Lock I'm currently drawing this as a 0.40 mm overhang of the front face of the DK connector (over the board edge) to make certain that the Interposer Cable can fully plug in, and a 0.0 mm setpack of the screw block (from the board edge) which gives a 0.15 mm clearance for the 0.25 mm thick M3 screw Retainer, i.e. the screw retainer is neither pinched nor is the rigid part of the Interposer cable bent when the locking screws are tightened. Currently setting the locking screw center to center as 51.0 mm which gives 1.0 mm of clearance on each side between the screw block and the external surfaces of the DK board mount connector for the Interposer. ----------------------------------------------------------------- DATE: 12-Apr-2024 Topic(s): Working on the Interposer Connector Lock, QFN packages on back side Working on the Interposer Connector Lock with Adam. Working on drawing for verification with Adam. I don't actuall like the PEM SMTRAM3-7-5ET part as a SMT assembled part because of: Zinc material, hand placement ?, and the peel strength being the only mechanical connection, large moment arm to peel the bracket off the pcb because the screw is 7.0 mm above the top surface of the pcb and the connector center is 3.15 mm above the pcb top surface. This system requires Adam to have 2 pairs of holes in the rigid part of his Interposer Cable but he seems to think this is OK. Alternative is to put the screw hole also 3.15 mm above the top surface of the pcb but that requires a custom bracket. The setup with a Shoulder screw with a Nylon Patch, Belleville washer, and Retainer for the Interposer Cable now looks very nice. I need to get some of the PEM SMTRAM3-7-5ET and look at it to see if it can be screw mounted to the DK or do I need to make a custom part. Need to talk with ONC about Zinc parts. Start Mech Drw 87. Using QFN parts on the bottom side has addition costs and complications, e.g. needing via plugs on both sides. Can all QFN components be moved to the top side and still make effective use of the space on the bottom side under the large polypropylene capacitors ? QFN comps must include these 8 items: BB ADC U1101, ER uProc U1101, RS-485 Power Supply U1004, USB Phy U1051, USB Switch U1052, DDR4 Term Supply U1921 U1941, Timing Gen U901. What can go under the polypropylenes and be routed single sided ? ----------------------------------------------------------------- DATE: 11-Apr-2024 Topic(s): Reference Designator work in Reset TOMcat work for Michael Ref Desig clean up in ER & RS-485 The Reference Designators for the Jumpers and for the Pull-Up or output series resistors in the Reset/Enable circuits are still a bit confusing. Final Plan. From the electronics point of view some of these items should be located at the target and some should be located in the Reset/Enable block of parts itself - thus assign Ref Desg in that way. Specifically: Drws 55, 56 PUs all within the block. Drw 84 Jumpers within block. Drw 85 Jumpers within block and series resistors at target. Drw 86 Jumpers and and PUs at target. 5 notes from Michael about making a patch to the TOMcat board. I got this done today but I'm not sure what to do next. The Emergency Rescue and RS-485 section needs to have its Reference Designators cleaned up since the Isolated RS-485 Power Supply was added. Need clean up before actuall entering this design into the CAD system. Drws. 44, 47, 67, 68, 82, 83. ----------------------------------------------------------------- DATE: 10-Apr-2024 Topic(s): 4 clock type inputs to the PMT ADC See also the 27-Mar-2024 log book entry for additional information about the 4 clock type inputs to the AD9083 PMT ADC. See AD9083 datasheet pages: 10, 13, 14, 15, 16, 25, 26, 32, 51. The TRIG input to the PMT ADC is never going to be used. New official final decision: give up on driving it from a differential ouput on the FPGA 1V8 bank, instead just tie it off to provide a 500 mV common mode and about a 100 mV Low input, i.e. about 499 Ohms up to 1V0 and 499 Ohms to Gnd. Page 15 says that the TRIG input pins, "can be left floating if disabled". They do not define "disabled". The function of the TRIG input is not well explained. There is a little information about it on pages: 41, 51, 74, 88, 89. The main issue with the TRIG input from the DK point of view is to not have it cause trouble for us. The CLK input to the PMT ADC is OK as is. It is AC Coupled so the PMT ADC sets the common mode at its input. Want to drive it with a nice clean 300 to 400 mV signal (note with the 1800 mV max signal specified in the datasheet. No change from the current design. The SysRef input to the PMT ADC has a probem in the current design before the Clock Gen and ADC are enabled. The pull-ups on the Clock Gen output to 1V8 will bump up agains the 1 diode drop about the 1V0 power supply to the Analog section of the ADC and pull about 1 or 2 mA through the ADC protection diodes. This is probably OK but we can do better. The intent is to tie the pull-ups for the Clock Generators SysRef output to either a 1V2 or 1V0 power bus on DK. Will study which is best to implement 500 mV common mode and 300 mV differential under running conditions and neither side of the clock line over 1.3 V under any conditions. 7.5 mA Sink 133 Ohm to 1.00 V --> 273 mV Diff 501 mV CM 7.5 mA Sink 187 Ohm to 1.20 V --> 296 mV Diff 499 mV CM 7.5 mA Sink 300 Ohm to 1.80 V --> 321 mV Diff 675 mV CM 7.5 mA Sink 347 Ohm to 1.80 V --> 328 mV Diff 499 mV CM 7.5 mA Source 133 Ohm to Gnd --> 273 mV Diff 499 mV CM The SyncInb input to the PMT ADC is OK, it is a real LVDS receiver and is driven by an FPGA 1V8 bank LVDS output. No AC capacitor coupling but does require and external 100 Ohm Terminator. No change from current design. Need to make changes to drawings: 16, 50, and 70. ----------------------------------------------------------------- DATE: 9-Apr-2024 Topic(s): Reset Circuit Reference Designators 12 Layer Stackup Need to re-package for the 3rd time the gates for the Reset Circuits into IC packages. Change the organization of these Reference Designators from having these parts in the range of their individual sub-systems to having all of the Reset Circuit type components in one group of their own. All of the Startup Reset comps will be in the Reference Designator range 1151:1199. Current Gate Counts: Drw Drw Drw Drw Drw Total Total Spare 55 56 84 85 86 Gates Packages Gates -- -- -- -- -- ----- -------- ----- Inv 1 - 1 1 - 3 1 3 OD Inv 4 3 - - 2 9 2 3 AND 5 3 1 2 - 11 3 1 NAND - - 1 1 2 4 1 0 TPS3808 - 1 - - - 1 (+2) 3 0 In the Reset/Enable section just above assign: U1151, U1152 TPS3808 Startup Supervisor U1153, U1154, U1155 AND 74LVC08A U1156 INV 74LVC04A U1157, U1158 OD Buf 74LVC07A U1159 NAND 74LVC00A U1160 TPS3808 Barnacle Master Reset Drw 12 Boot Mem Mux 1 Pkg 74LVC241A 0 Drw 13 JTAG 10 Gates 2 Pkg 74LVC14A 2 Drw 79 USB Power Ctrl 4 Gates 1 Pkg 74LVC08A 0 Drw 51 Interposer SPI 2 Pkg 74LVC244A 0 Drw 72 Interposer UART 8 Gates 2 Pkg 74LVC14A 1V8 4 Drw 73 Interposer 8 Gates 1 Pkg 74LVC244A 0 All Other Drw 44 + 82 Emergency 4 Gates 1 Pkg 74LVC08A 0 Rescue 2 Gates 1 Pkg 74LVC04A 4 12 Layer Stackup Draft: L1 Top Pads and Traces 1/2 oz L2 Ground Plane Upper Type 1/2 oz L3 Traces 1/2 oz L4 Traces and Fills 1/2 oz L5 Ground Plane Middle Type 1/2 oz L6 Power Fills 1 oz L7 Power Fills 1 oz L8 Ground Plane Middle Type 1/2 oz L9 Traces and Fills 1/2 oz L10 Traces 1/2 oz L11 Ground Plane Lower Type 1/2 oz L12 Bottom Pads and Traces 1/2 oz Issues with this Stackup: - L3, L4 and L9, L10 are not symmetric between Ground planes but need to be used with the fast DDR4. Is this OK from dispersion and from velocity match points of view. - Using L3, L4 and L9, L10 for the fast DDR4 means that the Via Stubs will be more significant than with the 10 layer stackup. Is this OK or does this force back-drilling ? - The 13 GHz links will need to run on the non-symmetric L3, L4 and L9, L10 or on one of the surface layers with their dispersion issue. Which is better ? For now to get going - fully move the DK design to this 12 layer stackup. Start work by removing all of the comps and nets from the previous incarnation of the Reset and Interposer I/F. Then add back in the new current version of these circuits. ----------------------------------------------------------------- DATE: 8-Apr-2024 Topic(s): Changes to Input Power Filter Change the Varistors from a THD to a SMD device, tentatively either: Bourns PV95K4032 or TDK B726660M0950K072 both are 4032 size components and can use the same layout geometry. Change the reverse polarity protection diode to an SMD part in the DO-214AA package, e.g. Diodes Inc S1GB-13-F recall the screwed up DO-214 numbering system: DO-214-AB, SMC, Largest: DO-214-AA, SMB, Middle: DO-214-AC, SMA, Smallest Move both the input overvoltage clamp varistor and the input reverse polarity protection diode from being adjacent to the Input Power Converter to being at the input to the Input Power Filter. ----------------------------------------------------------------- DATE: 5-Apr-2024 Topic(s): Chances to Enet SFP Tx Enable After discussion with Nathan we want a change to the control of the Etherent SFP Tx Laser Disable because claiming CPU Sanity could be a multi step process. ----------------------------------------------------------------- DATE: 4-Apr-2024 Topic(s): Circuit Diagram - Next Steps Circuit diagrams are basically stable. Need a final review with Nathan. Back to layout - start with defining the new stackup, dividing logic into packages, and Input Power Converter. Meeting with Darren and Nathan ----------------------------------------------------------------- DATE: 3-Apr-2024 Topic(s): Interposer Cable Locks, Elisa Note Working on the Locks for the Interposer Cables with Adam. ----------------------------------------------------------------- DATE: 27-Mar-2024 Topic(s): PMT ADC Clocks Common Mode voltage Settle the issue of the Common Mode input voltage for the various clock type inputs to the AD9083 PMT ADC. The AD9083 PMT ADC has the following 4 Clock type inputs: CLK on DK this is 125 MHz from the AD9546 Timing Generator SYSREF on DK this is 100 Hz sq wave from the Timing Generator TRIG on DK this is not used but is driven by DK's FPGA/CPU SYNCINB on DK this is not used but is driven by the DK's FPGA/CPU CLK is the timing reference for the AD9083 SYSREF aligns all of the dividers and such on multiple AD9083 TRIG is ?? not used in the DK application SYNCINB aligns or clocks the JESD204B output link from the AD9083 but is not used in the DK application. Page 10 of the AD9083 datasheet lists the specifications for all 4 of these Clock Type inputs. SYSREF, TRIG, and SYNCINB are all listed together and are called, "Logic Compliance = LVDS". The CLK input has the same specifications except that it is shown with a 800 mV typical input instead of the 700 mV typical input for the SYSREF, TRIG, and SYNCINB signals. Pages 14, 15, and 16 of the AD9083 datasheet shows the devices pinout. On page 15 SYSREF, TRIG, and SYNCINB are all explicitly called LVDS signals. Page 25 of the AD9083 shows that the input circuits for the: CLK, SYSREF, and TRIG are all the same and that they feed a 0.5 Volt common mode to both sides of the input through 172k Ohm. Page 26 of the AD9083 shows the input circuit for the SYNCINB signal and explicitly calls it a 1.8 V clamped LVDS receiver. --> So both page 10 and 15 both say that SYSREF, TRIG, and SYNCINB are LVDS compatible. --> Page 25 shows that CLK, SYSREF, and TRIG all have the same input circuit. Pages 32 and 51 have more incormation about the CLK and SysRef inputs. We have many choices for the AD9546 Timing Generator output signals. I would like to run with the 7.5 mA output (instead of with the 15 mA outputs) just to help keep down the electrical noise level and cross-talk and heat and give long life. 300 Ohm pull-ups --> 0.836 V Hi, 0.514 V Low, 0.322 V Delta, 0.675 V Comm Mode 332 Ohm pull-ups --> 0.725 V Hi, 0.400 V Low, 0.326 V Delta, 0.563 V Comm Mode The DK standard will be to use 300 Ohm pull-ups with 7.5 mA switch. If needed to make the 0.5 V Common Mode 330 Ohm pull-ups can be used. See also 26-May-2023 of the first DK log book. ----------------------------------------------------------------- DATE: 26-Mar-2024 Topic(s): More work on Geometries Write the geometries: wurth_7503196xy_iso_power_geom, ti_hvssop_10_pin_geom.txt, and soic_16_ti_wide_geom.txt all for the Isolated RS-485 and its Isolated Power Supply. ----------------------------------------------------------------- DATE: 25-Mar-2024 Topic(s): Transformers for the Isolated RS-485 Power Converter SN6507 All transformers are Wurth and have 2.5 KVolt AC insulation. All Wurth part numbers start with 7503... Part No. Application Part No. Application -------- ----------- -------- ----------- 19948 24 --> 30 19695 24 --> 12 19949 12 --> 30 19691 12 --> 12 19697 24 --> 24 19694 24 --> 5 19693 12 --> 24 19690 12 --> 6 19696 24 --> 15 20325 24 --> 3.3 19692 12 --> 15 20324 12 --> 3.3 The two that look most likely for our application are: 750319697 24 --> 24 and 750319691 12 --> 12 ----------------------------------------------------------------- DATE: 21-Mar-2024 Topic(s): Work on the Isolated RS-485 Work on the Isolated RS-485 connection for the Emergency Rescue system. Focus on: ISO1412DW, SN6507DGQR (Q1) ----------------------------------------------------------------- DATE: 20-Mar-2024 Topic(s): QFN-28-Hub Geom, Input Power Note Send note to Felix and Christian about power limits on the Input Power Converter. Finished for now all of the Geom work including the QFN-28-Hub. ----------------------------------------------------------------- DATE: 18,19-Mar-2024 Topic(s): Additional Geometries, Barnacle Review Make geometries for: Gas Discharge Tube, Varistor, 16 pin Header, and QFN-28 for the USB Hub. Preliminary Review for the Barnacle. ----------------------------------------------------------------- DATE: 15-Mar-2024 Topic(s): Main Cable Connector Change, and Hardware controlled Reset and Enable: The J1 Main Cable connector is officially changing from 26 pins to 16 pins because it now has only the following copper connections: Power-Feed and Power-Return RS_485 differential pair RS_485_Common Up and Down The connector type is not changing. The new connector is 3M part number: 3408-5302 for tails for a 62 mil board or 3408-5303 for tails for a 94 to 125 mil board. the x3xx longer type latch/eject ears that we need for the plug housings. The following items on the DK Board need to have Hard Wired logic control the Reset or Enable signals: FPGA/CPU_RESET_B DK_CPU_IS_SANE to all below and to Both Interposer Interfaces and to the Emergency Rescue circuits PMT_ADC_RESET_B CLK_GEN_RESET_B BB_AUDIO_ADC_RESET_B USB_RESET_B BARNACLE_MASTER_RESET_B DK_Control_1_to_Barnacle DK_Control_2_to_Barnacle Timing and ENet SFP Tx Disable (Hi --> Disable) jumper selectable: Always Enabled or Enabled only if CPU_Is_Sane AND control signal is Hi Xtal Oscillator Enable Signals (Hi --> Enable) jumper selectable: Always Enabled or Disable only if CPU_Is_Sane AND control signal is Hi TOMcat_RESET_B or TOMcat_ENABLE jumper selectable and note the change in the meaning of the CPU control signal Run_TOMcat Hi --> Send power to the TOMcat Stop_TOMcat Hi --> Stop sending power to the TOMcat Isolated RS-485 Power Control, require default at Module power up to be enable the RS-485 power Require: DK_CPU_IS_SANE AND STOP_RS_485_power to both be HI to shutdown the Isolated RS-485 Power The current Reset Circuits are in Drawings 55 and 56. It will require at least one more drawing to finish the functional block diagrams for the Reset and Enable signals. ----------------------------------------------------------------- DATE: 13-Mar-2024 Topic(s): Final Design Review for the DK DK's final design review by 3 or 4 external reviewers and with "observers" from p-one. The Confluence address is: https://p-one.atlassian.net/wiki/spaces/PONE/pages/514621469/Mainboard+-+Final+Design+Review ----------------------------------------------------------------- DATE: 8-Mar-2024 Topic(s): FPGA Timing Pins - Notes from Nathan FPGA Timing Pins - Notes from Nathan -------------------------------------- Cat signals ---------------- This routes through the high-speed IO (mezzanine) or from the SE PLL. The only solution I can find that lets us make them from the PLL or pull them straight through the FPGA without touching the fabric through the IO stuff is: - 125 MHz in on CLKIN_S_12 - 100 Hz in on CLKIN_S_13 - 125 MHz out on the F22/G22 version of CCC_SE_PLL1_OUT0 - 100 Hz out on CCC_SE_PLL1_OUT1 (single-ended) The 125 MHz and 100 Hz inputs could be swapped, but the outputs cannot be because of restrictions in the PLLs. > > 1. Microchip claims that their PLLs work best if the lower-numbered clock > outputs from the PLLs have higher frequencies on them. I can only > speculate about what exactly they mean by "best", but taking them at their > word suggests the specific assignment here for the Blackcat clocks and > that we would want to order the USB and audio ADC clocks by frequency. > > 2. There seem to be two CCC_SE_PLL1_OUT0 ports: I think we want pins F22 > and G22 for the 125 MHz out, which is also attached to the output clock > for that I/O bank. > >> >> TOMcat-ish stuff: >> ---------------- >> >> Blackcat 125 MHz OUT to AD9546: CCC_SE_PLL1_OUT0 >> Blackcat 100 Hz OUT to AD9546: CCC_SE_PLL1_OUT1 >> TOMcat 125 MHz IN to FPGA: CLKIN_S_12 >> TOMcat 100 Hz IN to FPGA: CLKIN_S_13 >> >> If they are in those specific places, the INs and OUTs are connected by a >> minimum-jitter hardware HSIO clock connection that is hardwired between >> the two, stays entirely in the I/O blocks, and never touches the fabric. >> That's probably the best we can do. For in-fabric Blackcat, the outputs >> are also hardwired to two outputs of a single PLL that can divide the 125 >> MHz directly to 100 Hz with a known phase and has direct access to the >> recovered Ethernet clock. As far as I can tell, this a unique set of >> ports (125 MHz and 100 Hz can be swapped, but otherwise there is no >> freedom) to accomplish both of these things. >> >> Specifically in the case of TOMcat, equivalent pins (but SW instead of >> SE) pins are externally accessible through connector J26 on the >> evaluation board we have. >> ----------------------------------------------------------------- DATE: 23-Feb-2024 Topic(s): Tentative final decision about the dual USB connections for the cameras Use a simple USB Hub controller - Microchip USB2412. There is no need in this application for the Multi Transaction type of Hub and the managed type of Hubs look more risky in design and software for their control. What does Felix call his 2 cameras so that we can name the signals in the same way on the DK Board. The DK's USB_Reset_B signal will reset both the USB3340 Phy chip and the USB2412 Hub. Use manual control of the power to the 2 downstream ports. Simple power control works because, "the data pins idle at 0V by the host until side the device side pulls the data lines up which it can not do that if it has no power". So turning its power Off is the same as unplugging it as far as the rest of the USB "stack" is concerned. There is the associated issue of removable and non-removable device side items - which can be set by jumpers on the USB2412 and I think is only needed for compliance testing. Felix's note from 5-Feb-2024 says that the camera will require 360 mA. His note from 14-Feb-2024 is the request for 2x USB connectors. It would be nice to use the same load switch component for the USB ports and for TOMcat - but there are some differences in requirements if DK supplies a number of low voltage buses to the TOMcat. USB really needs a switch with a built in current limit. TOMcat needs to go down to 1V8 (or 1V0) and thus switches with a separate Bias supply have a big advantage and are actually the rational way to do most switches. TPS22996 dual, down to 0.8V, external Bias also 22965, 22967 MIC2544-1YM default USB to this point MIC2026-1BM dual from USB2412 demo board also TPS256x dual TPS204xB default old TI switch Start work on new drawings of DK's USB system. ----------------------------------------------------------------- DATE: 22-Feb-2024 Topic(s): Tentative final Bump-Out design, SFP and Timing Gen comps moved Tentative final points in the Bump-Out are: 138.0, 0.0 138.0, -34.0 186.0, -34.0 235.0, 0.0 The 2nd USB connector is in and the USBs and SFPs now all have cables and Plugs on Sheet_Dielectric_9. The DCDC Converter for the PMT ADC is now vertical. SFP Comps and the Timing Generator Comps have been moved to approximate new locations. The Silk_Screen Tomcat and its real J10 connector are now in the design. comps 1266 nets 930 conn 3131 ----------------------------------------------------------------- DATE: 19-Feb-2024 Topic(s): Start the Bump-Out The x,y of the 3 points that determine the bump-out are: 135.0, 0.0 135.0, -33.0 186.0, -33.0 If necessary this can probably be pushed slightly further South or East by a mm or half mm. Mover the 340 mm limit guide circle from Silk_Screen to Sheet_Dielectric_9. The 1x2 cage that I'm using is AMP 2007263-1 and the connector is AMP 1888247-1. In the old vertical long axis placement of the cage, the cage to connector delta_x was 7.125 mm and 21.375 and the delta_y was 30.9 mm and the pcb edge to cage placement in y was 10.5 mm. Also: Remove the 9th mounting screw hole and for now move J11 to the east edge. Now Need to: Add 2nd USB connector, ad tomcat and its connector and its mounting holes, move the lower polypropylene capacitor up and then mode the Barnacle J7 connector West. Want to make the USB Cable Plug and the SFP Module and Cable with its Connector all on Sheet_Dielectric_9. comps 1263 nets 930 conn 3131 ----------------------------------------------------------------- DATE: 16-Feb-2024 Topic(s): Meeting Another Friday meeting with Elisa, Michael, and Sim Elisa says that she needs something fast rather than final and says that it is impossible to make something final right now. Basic plan is to give up: make a super set, and give up on setting up a full build plan for Nathan. I must learn to work down at their level. ----------------------------------------------------------------- DATE: 9-Feb-2024 Topic(s): Work on the Bumped Out design Make drawings 75 and 76 of the Bumped Out DK showing it with and without a standard current size TOMCat. The Stack heigth of the TOMCat and its support board that Nathan brought to me from Michael is probably 15 mm. The pcb ----------------------------------------------------------------- DATE: 8-Feb-2024 Topic(s): Work on drawing of the DK's mechanical layout: with New Tomcat or a Bump Make drawing 74 of a New Cantilevered TOMCat on a rectangular DK and Start work on a Bumped Out DK where its SPFs could live. ----------------------------------------------------------------- DATE: 7-Feb-2024 Topic(s): Meeting with Elisa, Michael, Sim Michael has the idea to put both SFP Cages on the Mezzanine and have two types of Mezzanines: plane for use with PON Timing & some kind of Enet Comm and a mezzanine with Lattice FPGA for TOMCat mode. 3 big advantages: I now need only one Tx Rx pair for the ENet, I do not need to slot the DK PCB, I do not need space for any SFP cages on the DK board, Disadvantages: The DK always requires a cantilevered mezzanine TOM card of some type with its issues of broken solder connections on its SMD mezzanine connector - that appear to work OK for a while because they are mechanically clamped together by the mezzanine's mounting screws but then fail after a period of time in operation. ----------------------------------------------------------------- DATE: 6-Feb-2024 Topic(s): Remove the Input Transformer I removed the Input Transformer with the binocular core. I cleaned up the even/odd naming issue in the config and template files. All in the PMT Analog Input section could then be slid 9 mm to the East and there may be a little more space available here. The tar backup from 5-Feb-24 is the last one that has the full design with Input Transformers. Comps 1261 Nets 930 Conn 3127 ----------------------------------------------------------------- Start of this log book