DK Log Book Started September 2024 -------------------------------------- The most recent entries appear first in this log book. ----------------------------------------------------------------- DATE: 26 through 31 -Mar-2025 Topic(s): Finished the first Harwin to 8x SMD adaptor cable and sent a note to Jeanne. Made additional design changes to the power supply for my testing of the DK boards - now has a single switch for DC On/Off and selecting between full length cable or short zero length cable. Start work on building 2 of these supplies. Start parts lists for: MSU Final Assembly of the DK Boards, and for parts required for operation of board SN #0. Review some of the testing setup on Thurs and Fri with Dan. I need to get the D-Zero Agilent 3499 Switch/Control system back from Wade's lab and pass it to Dan. Monday review the build Parts Kit for the first 40 DK boards with Brayden and Nathan. Nathan is setting up the delivery. Pass to them 36 Harwin PMT signal connectors. Still need to pass to them the Connector Mounting screws, washers, nust. Chris would like the Assembly Data so I went ahead and made a .zip file of what is available right now. Still missing are the Parts Kit Inventory and the Excel version of the overall Bill of Materials. Read back the .zip file, un-zipped it and diffed all 12 files. Send note to Chris. Approximately 17 items still on my DK To-Do list. End of this section of the DK Log Book. ----------------------------------------------------------------- DATE: 25-Mar-2025 Topic(s): Harwin - SMA Cables, +-48 V Power, Continue the PMT Analog Input study Worked making the Harwin to 8x SMA cables. The Johnson SMAs seem good to work with. Work on the machanical layout for the +-48 Volt power supplies. The differential trace pairs from the input circuit to the PMT ADC input pins are: 0.14 mm trace width on 0.40 mm centers and are 4 mils from their reference Gnd plane and have an air gap between pairs of 2.4 mm. Calculations for the diff pair to diff pair cross-talk indicate that this is good enough so that it should give 12 bit channel to channel isolation. The air gap is less than 2.4 mm right as these diff pairs approach and connect to the PMT ADC. These diff pair are probably not the source of whatever channel to channel cross-talk we will see. With lots of rivets and isolation strips even this diff pair to diff pair cross-talk could be reduced by a factor of 2 to 4. ----------------------------------------------------------------- DATE: 24-Mar-2025 Topic(s): Script for Top/Bot SMD only parts lists, more study of the PMT Analog Input Section Restore from durand to real moto the script to make the separate Top & Bottom SMD Comps only parts list - make_top_bot_smd_only_comps.sh Do this work on durand to remove any risk to the real design on moto. Additional points about the PMT Analog Input Section: - A fundamental problem with the analysis of the primary side of the PMT Analog Input section is how to handle its un-balanced input signal. In the trace pair that runs from the Harwin connector to the transformer Primary - only one side moves in Voltage wrt to Ground Planes. Thus the currents in this pair are probably not really balanced because the Hot side that does move in Voltage must also cause a current to flow in the real Ground Plane. - Thus during the rising or falling edge, the real currant flow balance must be something like: Hot side current = Return side current + current flow in the Ground Plane. During steady state - the Hot side and Return side currents will balance. But the cross-talk only happens while voltages or currents are changing so that is when we need to understand the balance to the Hot side current. - My cross-talk focus has been on the Harwin to Transformer Primary internal PCB trace layout. That is a mistake. The biggest Primary side current loop is probably above the top surface of the PCB and a lot of it could have been avoided by a better layout. Specifically the gull-wings of the transformer are about 10.5 mm apart when they lift above the top surface of the PCB. They they go up for about 1.5 mm. This makes a loop area of about 15.75 sq mm. But this loop area was made much worse in the PCB layout by running these signals down to internal layers immediately adjacent to the transformer's SMD pads instead of running these traces on the top layer to the center of the transformer and then down to internal layers. In the West column of transformers their primary traces run down to layers L9 - L10 which are on the average 1.484 mm below the surface of the PCB. The vias to get down to these inner layers are 9.2 mm apart. This gives an added loop area of 13.65 sq mm. The East column of transformers have their Primary traces down on layers L3 - L4 which average 0.398 mm below the top surface of the PCB. With the same 9.2 mm via separation this gives an added loop area of 3.66 sq mm. Within a column the transformers are 13.2 mm apart. Loops of 29.4 sq mm separated by 13.2 mm have an approximate mutual inductance of about 0.075 nH (probably a little less in our case). Given a full scale input signal of 16.2 mA with a rise time of 1 nsec and a mutual inductance of 0.075 nH you will couple 1.2 mV to the victum side of the mutual inductance. Given 810 mV on the aggressor side this is a 0.15% coupling to the victum. So this alone puts us short of even 1 in 1000 isolation. - Another question is how exactly are we going to quantify cross-talk between the PMT channels on the DK board. This really needs to be done with real input cables and PMTs on all channels and everything packaged up in the real final configuration. The bulk of the cross talk will most likely be from the backward going coupled signal that sees a reflection coeficient of +1 at the PMT. - Recall that in general for 2 parallel traces over a uniform Ground Plane that the mutual inductance caused cross-talk goes as: K / ( 1 + (D/H)**2 ) K is a constand, H is trace Height above the Ground Plane, D is the Distance between traces So mutual inductance caused cross-talk basically falls off as the square of the separation distance. This just follows from the current density distribution for the return current flowing under the aggressor signal. ----------------------------------------------------------------- DATE: 21-Mar-2025 Topic(s): Study of the PMT Analog Input Section A thin 30/50 mil 2 sided pcb may be just as good for the Shield Cover as something like 20 mil brass that we have used before. It would give 2 layers of skin effect instead of one with the brass. PMT Input Traces - Harwin to Transformer Primary: - are numbered 1:16 with the Odd being the Longer traces running to the West column of transformers and the even being the Shorter traces running to the East column of transformers. - the longest long traces to the West trans column are 60 mm long with a typical delta of 11.2 mm - the longest short traces to the East trans column are 40 mm long with a typical delta of 11.2 mm - the Hot Trace is 0.20 mm wide and about 0.102 mm from its Ground Plane. - the Return Trace is 0.40 mm wide and about 0.102 mm from its Ground Plane. - the Hot and Return trace surfaces are about 0.358 mm apart. - the longest close approach of Input Traces on the same routing layers is less than about 15 mm long. - the propagation constant on the inner routing layers is about 6.32 psec / mm. - so the overlap at the longest close approach lasts for about 100 psec. - 100 MHz on the inner routing layers has a wavelength of about 1582 mm (about 3 m in free space). - so the longest Input traces are about 1/26 of a wavvelength at the highest frequency of 100 MHz. - thus we can easily use bulk parameter analysis to calculate the cross-talk coupling coefficient. - the longest runs from the Input Transformer to the ADC input pins are about 99.8 mm long with a typical delta of about 8.7 mm this pcb trace length is about 1/16 of a wave length at the highest 100 MHz signal frequency. Turing the Transformers by 90 deg may not help because right now we have no Input trace cross overs at all. With the transformers rotated and thus their input traces spreading vertically (vs their current horizontal spread) we may be forced to Input trace cross over. I have restored the pre Fill generation Trc_592 file to the active Trc_602 file for faster layout investigation. Note received from Hughes that they got the approval emails from us. ----------------------------------------------------------------- DATE: 20-Mar-2025 Topic(s): Received Stakup and Check Plots from Chris Approval send to Hughes for the Stackup and Check Plots. ----------------------------------------------------------------- DATE: 19-Mar-2025 Topic(s): Get all of the DK Assembly files up to date and ready for release. Copy the Board Assembly files to the web. Note to Nathan and Brayden about: R1358 parts list change, Excel files, and the Kit Inventory. ----------------------------------------------------------------- DATE: 18-Mar-2025 Topic(s): Machine screw ... hardware note written, Shield Cover Drawing, File size blow up Finally got the note written to Dan and Brayden about the planned use of hardware at assembly time and at MSU Final Assembly time and at board mount into Module time. Finally get a first draft of the Shield Cover made that goes over the PMT Analog Input Section. The .tar file size blew up on Monday even through I've been getting rid of some obvious old useless junk files. The case is in the directory .../Disco_pcb/pcb/check/ where the tools leave check files even though you exit the tool without saving any files. I'm dumping the check file because they are of no long term use - it's only their summary that is of real use. ----------------------------------------------------------------- DATE: 17-Mar-2025 Topic(s): Continue checks on the release data Pushing on 3 checks of the release data: study Gerber Plots with the reference viewer, determine the design rule sets that will pass with zero errors both with and without the Fills using 10 paramaters for each of 4 Net Types in each of 3 Fill Resolution areas, verify that there are no errors in the DDR4 trace delay analysis. Note that these are just technical checks of the release data - they are not checks of the correctness of the DK design. When looking at the DDR4 signal delay analysis note that for some reason I re-ran the FPGA analysis on March 2nd, when the CPU trace length adjustments were just finished, but well after the FPGA trace length adjustments had been finished and the FPGA CA Bus Terminators connected. Thus the March 2 FPGA analysis file is useless for the CA Bus analysis and you need to look at the 21-Feb analysis report file. Ah - this March 2nd FPGA analysis was just a check to verify that the clock signals did not change when their serpentines were changed from 45 deg to smoothed uwave. Verify that going to the High Resolution Rules for all 4 Net Types gets us to zero DRC and Comp Placement errors. So with all Fills in the following will pass but I do not know how much tighter it can be. Default P V T F P 1.00 V 0.19 0.32 T 0.11 0.20 0.185 F 0.11 0.20 0.30 0.20 Diff_Analog P V T F P 1.00 V 0.20 0.28 T 0.11 0.30 0.21 F 0.11 0.20 0.30 0.20 Diff_HS P V T F P 0.50 V 0.38 1.00 T 0.12 0.26 0.21 F 0.25 0.23 0.35 0.20 Power_HV P V T F P 1.00 V 0.50 0.32 T 0.50 0.50 0.50 F 2.00 2.00 1.00 0.20 Note that the 0.11 mm Fill to Pin clearance is a red herring because this constraint blows up on L6 & L7 for the 0.8 mm pitch BGA dog-bone vias that do not actually have pads on these layers. The rest of the DRC scans are much faster to do with all Fills out. The not understood Comp Placement errors with the Fills in are just caused by pin to fill clearance errors for pins on those comps. The whole issue just comes from dropping back to more relaxed rules after the very tight rules to generate the Very High Resolution Fills. Did receive a confirmation note from Hughes - they have the released design. ----------------------------------------------------------------- DATE: 16-Mar-2025 Topic(s): Checking the design and release the files The only way to run the DRC with the Fills in and expect no violations is to setup with the Fill Rules for the "Very High Resolution" fills. Recall the highest resolution design rules with these rules shown in the order used by the change_net_rules function call: Very High Resolution: fill-fill fill-via fill-trc fill-pin --------- -------- -------- -------- 0.40 0.20 0.30 0.11 DEFAULT_NET_TYPE 0.40 0.23 0.35 0.11 Diff_Pair_HS The Diff_Pair_Analog and High_Voltage net types have their own rule sets for Medium, High, & Very High resolution fills. All afternoon work was on: checking plots, DRC with Fills in, and DDR4 signal delay match. I ran out of time before finishing all of the checking work that one could/should do. Set the date of all the files in the ../Production_Release/Bare_Boards/ directory to 18:00 on the ides of March 2025. Made a .zip with an obvious filename that holds the 24 other files in the bare board release directory. Sent the note to Hughes - it's ready to build bare boards (I hope). ----------------------------------------------------------------- DATE: 15-Mar-2025 Topic(s): Work on Release of Bare Board data Fix 3 witness line problems on Bot silk and 4 Ref Desig locations on Top silk. Edit Geometries: molex_header_2x20_2mm_90deg_thd_geom.txt and molex_header_2x20_2mm_90deg_thd_rev_geom.txt to move their Bottom side Silk Pin #1 triangle indicators which had overlap with some adjacent component pads. .tar_two Review the 7 Center Thermal Pad Geoms and find 4 with problems in their Thermal Vias: Timing Gen, BB ADC, Trans Drive, Mem Volt Reg. Repair these 4 geometry pin/pad stacks. Review the 2 Geoms for 0.8 mm Pitch BG parts to verify their correct setup for plugged Dog-Bone Vias. Both were OK. Did not review the 1 mm pitch BGA component but will check it in the plots. The details from these 2 Reviews are in the file: review_dk_center_pad_and_bga_geoms.txt .tar_three Having just repaired 6 Geometries it is time to start the Release Build. The starting file versions for this build are: comps_1129 & traces_592 <---- Attach the Shield Components to the SHIELD net. Counts at the start of this build, Shield components are currently assigned to the SHIELD net, there are no generated Fills yet: 1755 Comps 1416 Nets 0 UnConnected Pins 48 Shapes in pcb geom 4923 Conn 4176 Finished 168 Un-Finished 579 Guides Geom_Ver 579 Comps_Ver 1129 Nets_Ver 709 Trc_Ver 592 Tech 1511 Follow the written build instructions for Generating the Shield Fills. NOTE: The pre-build .tar archive was made After the two Shield Fills had been made. This was not the intent but there is not time to go back and redo it. The correct fully pre-build Trc version is 592. Move the Shield Comps to the GROUND net. Use the script to build the other 46 Fill Shapes and see: Signal Layer 11 Medium Resolution 15 Fractures Signal Layer 12 Medium Res Fill Space 5 Fractures traces_602 has all Fills 7841121 bytes Check the Counts to verify that it is OK to go ahead and generate the Gerber Plots and Drill Files Shield Comps are assigned to the GROUND net: 1755 Comps 1415 Nets 0 UnConnected Pins 48 Shapes in pcb geom 4447 Conn 4447 Finished 0 Un-Finished 0 Guides after merging 35 Fills Geom_Ver 579 Comps_Ver 1129 Nets_Ver 710 Trc_Ver 602 Tech 1521 This looks OK so Generate the Gerbers and Drills by following the written instructions. ./mfg/ starts out empty There were no missing apertures in any of the 20 plots but the following plots do have painted objects: 2,5,8,11,14-15,16-17 This looks OK so run the script to remove the un-wanted Thermal Apertures. Run the script to Generate the Drill Files. Run the script to add the .gbr filename suffix to the Gerber Plots. All of this is in the file of written release instructions. Copy Gerbers and Drills to the web release directory ----------------------------------------------------------------- DATE: 14-Mar-2025 Topic(s): Bottom side silk. DDR4 Shield Pins Review of the Un-Used Memory Interface Signals for the CPU and FPGA SDRAM. Verify correct used of the "Shield" signals. Only the FPGA Memory Controller has "Shield" pins and they are only on the Data Lanes - not on the CA Bus. polarfire_memory_controller_user_guide_vb_jun23.pdf Table 3-14 "SDRAM Interface Signals" about page 24 Figure 7-8 "DDR4 Interface Example" about page 149 polarfire_user_IO_user_guide_vc_feb24.pdf Section 7.1.12 "Sheild" about page 31 polarfire_packaging_and_pin_descriptions_user_guide_vb.pdd Table 1-8 "Special Pins" about page 16 package and pin table spreadsheet PPAT "Shield" is not mentioned as far as I can tell DK board Net Lists ddr4_fpga_bank_0_no_connection_nets_fcg1152.txt The following 4 unused Bank #0 pins are grounded in the DK pcb: U1-AF24 # Shield pin in Byte 7:0 HSIO Lane N8 Shield U1-AH23 # Shield pin in Byte 15:8 HSIO Lane N7 Shield U1-AN21 # Shield pin in Byte 23:16 HSIO Lane N6 Shield U1-AL18 # Shield pin in Byte 31:24 HSIO Lane N5 Shield All other unused Bank #0 pins are floating in the DK pcb. These pins are mostly for additional Data Lanes and spread into Bank #8. ddr4_cpu_bank_6_no_connection_nets_fcg1152.txt All unused Bank #6 pins are floating in the DK pcb. These pins are mostly for a Rank 2 memory system or for an ECC 32 bit memory system. Bottom side silk is now OK but not great but time is up. 2 witness lines still need to be fixed. End of day count on real moto, Shield components are currently assigned to the GROUND net, all Fills are obviouly out: 1755 Comps 1415 Nets 0 UnConnected Pins 48 Shapes in pcb geom 4878 Conn 4176 Finished 168 Un-Finished 534 Guides Geom_Ver 570 Comps_Ver 1128 Nets_Ver 708 Trc_Ver 592 Tech 1511 ----------------------------------------------------------------- DATE: 13-Mar-2025 Topic(s): Bottom side silk all day End of day count on real moto, Shield components are currently assigned to the GROUND net, all Fills are obviouly out: 1755 Comps 1415 Nets 0 UnConnected Pins 48 Shapes in pcb geom 4878 Conn 4176 Finished 168 Un-Finished 534 Guides Geom_Ver 563 Comps_Ver 1123 Nets_Ver 708 Trc_Ver 592 Tech 1511 ----------------------------------------------------------------- DATE: 12-Mar-2025 Topic(s): Working on silk for the release Rediscovered last night a known typo in the Net List. For months the net list has incorrectly labeled the reference clock input to the XCVRs as net name "XCVR_1A_REF_CLK_IN_ DIR/CMP". This is an incorrect name and may be yet another left over from the days of the FCVG784 days. The correct name is "XCVR_3A_REF_CLK_IN_ DIR/CMP". This was just a naming error - not an actual error in the design. This name has been correct in the drawings for some time and was only incorrect in the net list. To be clear the XCVR Ref Clk goes into the FPGA on its pins F29/F30 which are XCVR_3A_REF_CLK. I fixed this typo in the files: crystal_oscillator_nets_fcg1152.txt where it is just in a comment timing_generator_nets_fcg1152.txt where the net name was the incorrect 1A & all of the comments were correct 3A Rebuild the net list and verified no change in counts. Quick fix to a couple of remaining problems in Top Silk - including getting the last of the silkscreen ink off of the 13 GHz traces some of which came from the PMT ADC Geom itself. Now start work on Bottom Silk. There are more components on the back than on the front. End of day count on real moto, Shield components are currently assigned to the GROUND net, all Fills are obviouly out: 1755 Comps 1415 Nets 0 UnConnected Pins 48 Shapes in pcb geom 4878 Conn 4176 Finished 168 Un-Finished 534 Guides Geom_Ver 558 Comps_Ver 1119 Nets_Ver 708 Trc_Ver 592 Tech 1511 ----------------------------------------------------------------- DATE: 11-Mar-2025 Topic(s): Silkscreen Reference Designators Since about Monday noon it has been 100% work on Top side silkscreen Reference Designators with just a little work flipping around some connector labels so that they are right side up when read looking in from the perimeter. Top silk is basically ready - unless I spot some more problems. Added lots of witness line to make top silk readable. To Do: Bottom silk, verify all center pad and BGA geometries, hand check a couple of the DDR4 routes for both CPU and FPGA. End of day count on real moto, Shield components are currently assigned to the GROUND net, all Fills are obviouly out: 1755 Comps 1415 Nets 0 UnConnected Pins 48 Shapes in pcb geom 4878 Conn 4176 Finished 168 Un-Finished 534 Guides Geom_Ver 551 Comps_Ver 1116 Nets_Ver 707 Trc_Ver 592 Tech 1511 ----------------------------------------------------------------- DATE: 10-Mar-2025 Topic(s): working on release First 5 little steps then get into the Silkscreen Ref designators: 1. Rotated the wagon wheel spokes for the Harwin and USB Thermal Apertures back to 0 - 90 deg. Hand edit - Aperture Table stays at Rev 33. 2. Gave up on making the 2V5 Word Line Fill any wider in its NW corner. It's complicated because this is rigth in the area where this Fill changes Design Rules and I doubt that it gains us much - I think it is only 5 mA average per chip. 3. Fixed the XCVR Ref Clock trace width error. 4. Moved the CPU and FPGA Memory CA Bus Clock Terminators North by 1.2 mm now better clearance to the VTerm Fill. 5. Moved the Remote Sense pickup connection for the 3V3 converter from relatively close to DCDC6 to a location SE of it. The remote sense pickups for the other converters are all OK as is. This puts us at Trc_592 and Comps_1110 these are now the golden versions for silkscreen and release work. Starting by noon working on the Top Silkscreen Reference Designators. It's not hard work but this will take a while. ----------------------------------------------------------------- DATE: 9-Mar-2025 Topic(s): Working on production release Restore from durand to real moto aperture_table.apertt_33 This aperture table now has the Thermal Apertures that are actually used in the released Gerber Plots defined in a rational way. This file is a little long and complicated but now also has a lot of internal documentation. Recall: Thermal Aperture == Power Aperture and for DK there are 3 classes: - Thermal Apertures that are NOT used, i.e. they are removed from the released Gerber Plots and are left with their default definitions 16 of this class - Thermal Apertures that ARE used, i.e. they appear in the released Gerber Plots and have been given custom rational definitions, 7 of this class - A Thermal Aperture that does not appear to be used in any Gerber Plots, I do not know what it is for, I'm doing nothing to remove it from the released Gerber Plots, I'm leaving it with its default definition, 1 aperture in this class What is it for ? Should check other designs. Recall the basic intent with the Thermal Apertures on the Ground Plane layers: - THD component pins that are selectively soldered, e.g. DCDC Converter ground pins, and Connector ground pins, do have rational Thermal Apertures so that there are not pcb assembly problems. - The ground plane connections that are NOT soldered, e.g. BGA Dog-Bone vias do not have Thermal Apertures. While working on the 200 or so apertures I found 2 special ones to keep in mind and verify that they are OK: - The output side low voltage pins for the 20 Watt converter have a Pad Land diameter that is larger than the Plane Relief. That is OK in this case because they are never used on the same pcb layer and I want a large pad on this "high" current pin - but check it carefully in the plots. - The Harwin signal pins use a strange combination of Pad Land to Plane Relief diameters - but again this is OK because of the way that they actuall appear in the plots and I need it to run the center pin connections - but again check the plots carefully. Generate a new current Aperture Table Report to verify what is in it, and diff it with the old report from 15-Jan-25. The Gerber plots generated last Friday are all junk because of the irrational Thermal Apertures that were in the Aperture Table - but the Fills should all be OK. So: - Delete all of the artwork files from .../mfg/ - Generate a new set of all 20 Gerber files based on last Friday's Fills - Run the script to remove the un-wanted Thermal Apertures from the Ground Plane Gerber plots - Study the 20 new Gerber plots - Run the script to add the .gbr filename suffix - Copy all artwork and drill files to the web - Extract the various drill counts and such, update the bare board manufacturing document, and get it to the web. Start today's Gerber Plot Generation work from: 1755 Comps 1415 Nets 0 UnConnected Pins 48 Shapes in pcb geom 4447 Conn 4447 Finished 0 Un-Finished 0 Guides 35 Fills after merging Geom_Ver 541 Comps_Ver 1109 Nets_Ver 707 Trc_Ver 590 Tech 1508 Shield Components are currently tied to the GROUND net. Backout is to Trc_560 or TRC_570 which are the same. OK - the above steps all went OK and the new files are on the web. The bare board manufacturing instructions now even say good for production. Problems found during study of the Gerber plots: 1. I want to put the wagon wheel spokes for the Harwin and USB connector Gnd pins back to 0 - 90 deg (from its current 45 - 135 deg) - I think it will have a fuller conection to the Ground Planes that way. 2. It looks like I could make the NW corner of the 2V5 world line Fill a bit thicker - but does t actually make the connection any better by doing so ? 3. I have a trace width error in the reference clock feed to the high-speed serial XCVRs, a 0.13 section that should be 0.14 just East of the FPGA. 4. The Differential Terminators on the Memory CA Buse Clock lines for both the CPU and FPGA Memory are too close to the VTerm Fills on the Bottom side of the board. This is made worse because in this area a very high resolution Fill is being used. The best solution is probably to move the Clk Diff Term components all North by 1.2 mm and there is room to do so. On the good side all the step involved with the Ground Plane Thermal Apertures now appear to be working OK - I just want to change the rotational orientation of 2 types of them. Dump the plots, fills, and drills before backing up and restore the pre fill generation Trc file. ----------------------------------------------------------------- DATE: 7-Mar-2025 Topic(s): Work towards production release Restore from durand to real moto: disco_pcb_ground_plane_exclusions.txt added Harwin mounting screws and Center East Board Mount generate_dk_gerber_all_20_plots.sh Repaired the probem found yesterday yes - random use of echo can crash a script default_artwork_order_production Repaired the problem found yesterday a misssing prepreg layer Back out of all Fills, Drills, and Gerbers made yesterday Trc_560 --> Trc_570 Move the Rivet VR112 that pinches the 1V8 Fill but keep it in the design. Do this graphically so that we have a clean machine written Comps file. Start some work on the non Reference Designator part of the silkscreen: a rational box to write the serial number, label the power supply trim pots, PMT Input Channels, rest of the connectors ... We absolutely should label all of the Jumpers. Edit the script that removes Thermal Apertures from the 4 Ground Plane plots so that the assembly house does not have problems . We are Removing some of the thermal apertures and Keeping some of them. Don't get confused: Removing the Thermal Apature means that we Keep all of the Copper. Keeping the Thermal Apature means that we Remove some of the Copper. If you want to Keep the Thermal Aperture then Remove it from the sed take file. Basically Keep the Thermal Aperture if it is something that they Solder. Thermal Apertures that I will REMOVE FROM the Ground Plane Plots 16 types of them: I want 100% Copper ------------- NOT Soldered Diameter Used by Geometries Aperture mm D-Code i.e. these geoms contain "Power bla xyz" diameter -------- -------- ------ ----------------------------------------------------- 165 1.18 265 Via_0mm79 167 1.0 267 Via_0mm65 168 1.6 268 Rivet_Via_1mm3 & Via_1mm1 170 1.9 270 Via_2mm2 178 5.7 278 J1 and J7 Mounting Screws 179 0.85 279 Center Thermal Vias under most QFN parts BB Audio Time Gen 184 1.7 284 DCDC Converter Aux Ground Pins 190 2.1 290 PEM Screw Block & SFP Cage Grounded Mounting Pins 192 0.87 292 Term Via Array and Mem_Riv Ground Pins 193 0.65 293 0.8 mm Pitch BGA Grounded Dog-Bone Pins 195 0.82 295 1.0 mm Pitch BGA Grounded Pins & Cap_0402_THD Gnd Pins 196 0.8 296 FPGA straight East-West Ground Pins, e.g. AA1, E 33&34 197 5.2 297 TOMcat Mounting Screws 198 2.0 298 SFP Cage Mounting Pins Grounded 199 3.5 299 PMT Analog Shield Grounded Mounting Screws 200 3.75 300 J2, J3 PMT Signal Input Connector Grounded Mounting Screws Thermal Apertures that I will LEAVE IN the Ground Plane Plots 8 types of them: Limited Copper is OK ---------- Is Soldered Diameter Used by Geometries Aperture mm D-Code i.e. these geoms contain "Power bla xyz" diameter -------- -------- ------ ----------------------------------------------------- 171 3.3 271 USB Connector Mounting Pins 174 1.85 274 USB Gnd Pin Pin #4 180 2.8 280 Gnd Pin on DCDC20 Converter Pin #5 181 2.42 281 Ground Pins on J7 Barnacle Connector 185 2.3 285 DCDC Converter Main Ground Pin 189 4.2 289 NOT used in Ground Plane Plots - must verify 191 1.75 291 Interposer Connector J4, J5 Ground Pins 201 1.35 301 J2, J3 PMT Signal Input Connector Shield Ground Pins I need (must) edit the Thermal Apertures that I'm Keeping in the design to give them rational Tie Widths and Air Gaps but for today I will skip this and just use this build to verify that I'm keeping and removing the correct thermal apatures. Start another full build. All of the technical problems from yesterday should have been fixed last night. Use the Release steps documented in: dk_release_proceedures.txt Start at: 1755 Comps 1416 Nets 0 UnConnected Pins 48 Shapes in pcb geom 4923 Conn 4176 Finished 168 Un-Finished 579 Guides Geom_Ver 541 Comps_Ver 1109 Nets_Ver 706 Trc_Ver 570 Tech 1488 This runs without any errors. The Ground Plane Plots now look OK. I need to set the Thermal Apatures that we keep to have spokes at 45 & 135 deg not at 0 & 90 deg. ----------------------------------------------------------------- DATE: 6-Mar-2025 Topic(s): Work on getting ready for release Give up on re-routing the PMT Analog Input Section to reduce the trace length of the coax center conductor. There are too many other things that need to get done and checked for a Monday release. At the 12 bit 100 MHz level channel to channel cross-talk is very likey going to be a problem with this board. We need 72 dB of isolation and from previous high-speed ADC boards it is hard to imagine that we currently have more than 60 dB. For now assume that the bulk of the cross-talk is on the single ended input traces. Need to: go to a J Lead transformer to make it narrow enough to rotate by 90 deg, simulate which will give us better isolation in our layout edge coupled or broad side input traces, add grounded copper on the input layers L3-L4 and L9-L10, add Gnd Plane Fills on L6-L7, simulate if flipping every other channel over helps with isolation, e.g. Ch1 has L3 hot and Ch 3 has L4 hot even channels are on L9 & L10. Did some final length match on the lower speed differential traces for the: TOMcat ENet, PMT ADC Clock and Sys Ref, Transceiver Ref Clock, and FPGA CLKIN_W_1. All close to begin with and easy to match. Currently at the following and will try a full build from here: 1755 Comps 1416 Nets 0 UnConnected Pins 48 Shapes in pcb geom 4923 Conn 4176 Finished 168 Un-Finished 579 Guides Geom_Ver 536 Comps_Ver 1108e Nets_Ver 704 Trc_Ver 560 Tech 1478 The Shield Comps currently have the SHIELD net. I know that the following will be wrong with this build but we need to see if there are any other problems: - the silkscreen is not ready - the Ground Plane Thermal Apatures need to be re-included to match request from Hughes - some Ground Plane relieves will not be correct, i.e. Harwin mounting holes and center East board mounting hole. Save Trc_560 as it will get overwritten in the build process and it is our fall back. Generate the L1 & L12 Shield Fills using the biological robot script. Counts with the Shield Comps still assigned the SHIELD net: 1755 Comps 1416 Nets 0 UnConnected Pins 48 Shapes in pcb geom 4878 Conn 4176 Finished 168 Un-Finished 534 Guides 2 Fills now in the design Geom_Ver 536 Comps_Ver 1108e Nets_Ver 704 Trc_Ver 561 Tech 1479 Now move the Shield Comps to the GROUND net and look at counts: 1755 Comps 1415 Nets 0 UnConnected Pins 48 Shapes in pcb geom 4878 Conn 4176 Finished 168 Un-Finished 534 Guides 2 Fills now in the design Geom_Ver 536 Comps_Ver 1108e Nets_Ver 705 Trc_Ver 561 Tech 1479 The net count changed as expected - no significant warnings at startup Build the other 46 Fills using the script generate_all_fills_on_all_layers.sh The runs to completion without error and has the "normal" 2 warnings: Fills on Signal Layer 11 Medium Resolution Warning: This Fill_Area was fractured into 15 pieces. Fills on Signal Layer 12 Medium Res Fill Space Warning: This Fill_Area was fractured into 5 pieces. Now at traces_570 7841188 bytes The counts are: 1755 Comps 1415 Nets 0 UnConnected Pins 48 Shapes in pcb geom 4447 Conn 4447 Finished 0 Un-Finished 0 Guides 35 Fills now in the design after merging Geom_Ver 536 Comps_Ver 1108e Nets_Ver 705 Trc_Ver 570 Tech 1488 As in the past, now with all of the Fills in, this picks up an Invalid Component Placement for: all resistors and bypass capacitors in both of the DDR4 CA Bus Terminators and for the SFP Cage. I assume this is a Comp clearance violation of some kind but there is no time to dig it out. I assume that these come from adjusting the Design Rules to different values during Fill Generation process and then setting the design rules to require wider margins. Study the Fills - I do not like the placement of Rivet VR112 it's too big of a cut in the BULK_1V8 Fill. Move or remove it. Things look good enough to try making plots so ./generate_dk_gerber_all_20_plots.sh - This overall calling script blows up. The 20 individual scripts that do the actually work are working OK. So for today I just ran the 20 individual scripts one at a time. I did something on 31-Jan-2025 to "improve" the overall calling script that appears to have broken it. Check the log book. - Plot generation goes OK There were no missing apertures but both the Silkscreen and Solder_Mask plots chose to "paint" something. For the Solder_Masks this was a 3.00 mm diameter circle. I do not understand because the Aperture Table does have a 3.00 mm Circle / Flash apature. I think that I have seen this before. Study the Gerber Plots: L2 plot - It still has a ther Thermals as expected but I do <----- not see my Slits or relief around the Analog Section. Is the artwork order file screwed up ? L3 plot - This is a good way to look at the separation of the PMT input signals. L12 plot - the VTerm Fills for the CA Bus Terminators are getting rather close to the Clock Terminators. Can mv the Clk Terms ? or if necessary put a knotch in the Fill Shape. Generate the Drill Data: ./dk_drill_generate_table_and_drill_files.sh This goes OK and with a brief inspection looks OK. As expected once I add the .gbr filename suffix for the Hughes folks then my system stops being able to automatically locate these files. Not a serious problem. In the .../Manufacturing/Production_Release/ web directory make sub-directories Bare_Board and Board_Assembly. Put the appropriate existing files into these subdirectories and copy into the Bare_Board sub-directory all of the Gerber Plots and Drill Files that were made today. Known work list includes: ------------------------- - Fix the master calling Gerber Plot Generation script. I think that I know what is wrong and it is simple to fix. - Remove Gnd Rivet VR112 from the design - Find an repair the problem of missing Slits and missing East side relief in all 4 of the Ground Plane Gerber Plots. The same error is probably causing both problems. - Add the Ground Plane relief for the Harwin connector mounting screw holes and for the center East board mounting screw. - Set things up so that we can pull out the unwanted Thermal Apatures but leave in the one that Huges wants. The script currently pulls out all thermal apertures. This work includes editing the thermal apatures that Hughes wants to make them rational wagon wheel. - Put current date into the Mechanical Drwing Plot and into all of the plot labels. - Make the silkscreens usable - there is lots of work here. - Must check all of the geometries that use plugs, e.g. FPGA, Memory, PMT ADC, and all that have a center thermal pad. - Must check the .nls file and the net list build counts. - Must check with the ucamco reference gerber viewer. - Would like 10 more minutes of though and discussion about the PMT input center conductor routing. - Must update the Bare Board Manufacuring Instructions file to includ current counts, change to Red solder mask, and ... - DRC is currently passing OK but I must make multiple scans while tightening the screws. ----------------------------------------------------------------- DATE: 5-Mar-2025 Topic(s): Work on the Shield Ground Fills In the Generate Fills sub-directory write the instructions for generating the Shield Fills in the file: shield_fills_generation.txt For now these will be human instructions and not a machine script. The other 46 Fills are generated by machine script. Move the rest of the necessary component pins into the Net List files: shield_connections_shield_net.txt shield_connections_ground_net.txt shield_connections.txt There is a question about how to handle the mounting screw "pins" on the Harwin connectors and the JMP1B-2 pin for connecting the DK Signal Ground to sea water reference. For now I'm going to put these items in the above files so that they too move back and forth between the SHIELD net and the GROUND net. Thus when the file shield_connections_ground_net is in effect there is no SHIELD net in the design at all. A slight issue is that this will require manually excluding the Ground Planes from the Harwin mounting screw holes (easy to do) The main design issue is channel to channel cross-talk. I assume that the most risk is in the single ended section. Should I run shield traces on L6 & L7 ? Should I run Return traces on the same level as the center conductor, i.e. edge coupled instead of (or in addition to) broad side coupled ? Can I run the Shield Fill closer in, e.g. to connect with SH1 and SH2, but still keep them and their Ground Rivets away from the PMT ADC - it looks like there is some space on L1 Top at least. So now with all of the Shield Rivets, all Odd J2 J3 "Ground" pins, and JMP1B-2 in the shield_connections control files and with this set to the GROUND net, I have connected JMP1B-2 to J2-26, save Trc_557, and run DRC with only Warnings: 32x "Via via_0mm79 does not match Net Type Diff_Analog and 23x "two vertices are coincident" which I think are all in the duplicated DCDC Converter wiring. Switching the the Shield connections tied to the SHIELD Net and things are still fine. The counts flop back and forth: GROUND: 1748 1415 0 4878 4175 169 534 SHIELD: 1748 1416 0 4915 4175 169 571 Extend the Shield Fill Shapes to about the horizontal center of the PMT ADC and at that point add Rivets to connect the Shield Fills to the 4x Ground Planes and to the the Shield Cover Mounting Screw Holes SH1-1 and SH2-1. These added Rivets are centered over the vertical slit beteen the various PMT ADC power supply Fills. Meeting with Nathan - I will try to fix the longer than necassary center conductor traces in the Analog Input Section. The current idea is to swap all Transformer pins side to side - but need to figure out how to do this without loosing all of the associated routes. Estimate one day of work. Need to make a full test of building the design. Would like to add Fill Excluders to block the thin line of fill between the resistor networks. Concerned about such a thin fill line comming off of the board. End of day counts on real moto: Comps edited to move & change the number of Rivets connecting the Shield Fills to the inner Gnd Plns. The Shield Components are currently connected to SHIELD Nets. 1755 Comps 1416 Nets 0 UnConnected Pins 48 Shapes in pcb geom 4923 Conn 4176 Finished 168 Un-Finished 579 Guides Geom_Ver 535 Comps_Ver 1108e Nets_Ver 704 Trc_Ver 558 Tech 1476 ----------------------------------------------------------------- DATE: 4-Mar-2025 Topic(s): Work on the Shield Ground Fills Today's 4AM epiphany was that by swapping all connections to the transformers (side to side) that I can reduce cross-talk by eliminating about 1 cm of exposed input center conductor per channel. There is basically no change in any cross-talk on the differential Secondary side - just a net saving on the Primary side. Is there an easy way to do this without starting over with the Analog Input Section routing ? The current plan is to not connect the inner 4x analog Gnd planes to the coaxal PMT connector outer conductor shields. The intent is to keep the PMT coax cable outer conductor shield currents off of the 4x inner analog ground planes so that these planes are uni-potential and do not inject any common mode into the PMT ADC. But that leaves the risk that the East end of these 4x inner analog ground planes can flop around and thus allow channel to channel cross-talk. This is an issue because the "differential" traces from the PMT Connector to the Transformer Primary will have balanced currents but they will not have balanced voltage swings. For now mask out the 4x inner ground planes East of the PMT Input Connector - East of X = 232.9 May want to start this mask at about X = 228.9 Add a few more rivet vias in the area of the input signals to the PMT ADC. If I am going to connect the PMT Connector outer conductors to the inner 4x Gnd Planes (which I think that I need to do) then I must also be able to switch those Harwin connector pins back and forth between the SHEILD and GROUND nets - thus need to pull them out of the multi instance template. Start the net list files to swap rivet vias and Harwin pins back and forth between SHEILD and GROUND nets. Many many turn of the Rivet positions and the Shield Fill Shapes and it is strating to look OK. Note for building these 2 files are in a separate file. Except for getting the 16 Harwin pins and the JMP1B-2 net into the new setup this whole Shield Fill setup is about ready. These plan is to just do these 2 Fills by hand (the main load of 46 other Fills is all done via script). End of day counts on real moto: Comps edited to move & change the number of Rivets connecting the Shield Fills to the inner Gnd Plns. 1748 Comps 1416 Nets 0 UnConnected Pins 48 Shapes in pcb geom 4915 Conn 4175 Finished 169 Un-Finished 571 Guides Geom_Ver 530 Comps_Ver 1107e Nets_Ver 701 Trc_Ver 556 Tech 1475 ----------------------------------------------------------------- DATE: 3-Mar-2025 Topic(s): White space in Net Names, Finish connecting CPU Mem CA Bus Term, Start work to implement the Shield Gnd Fills Restore to real moto from durand: dk_clock_and_enet_diff_pairs.cfg nuk_all_logs_run_all_trace_diffs.sh While working last night on the Diff Traces I found 3 net names that include white space, i.e. they were missing an under_score character: NO_CONN_TVA1_pin B1 should be NO_CONN_TVA1_pin_B1 NO_CONN_TVA2_pin B13 " " NO_CONN_TVA2_pin_B13 Power Return " " Power_Return These nets appear to have been working OK (they are always quoted) but it is clearly a mistake and risky with other tools. Philippe's code for Diff Trace Pairs checks the format of the Net Name and found these errors. Edit the appropriate net list files and rebuild the overall net list and things are now OK. No change in counts. Finish re-connecting the CA Bus Terminators and it looks OK. Before starting the work on the L1 & L12 Shield Grounds capture the counts in case we have to backup. Counts right before starting Shield Gnd on real moto: Comps is edited 1747 Comps 1415 Nets 0 UnConnected Pins 47 Shapes in pcb geom 4894 Conn 4191 Finished 169 Un-Finished 534 Guides Geom_Ver 522 Comps_Ver 1106e Nets_Ver 693 Trc_Ver 553 Tech 1472 As a first baby step towards the Shield Gnd Fills go ahead and start a separate Fill Shape for the L12 Shield Gnd as in all scenarios the shapes (at least their East boarders) need to be different. Still many questions about the easiest cleanest way to implement the Shield Gnd Fills: must attach to some rivets of a given Net and isolate from others - can you do all of this with Slot Threshold and net Relief or where all may we need real excluders ? In all scenarios there is not currently enough space available between the East column of Transformers and the Harwin PMT input connector to have a meaningfully wide Shield Ground Fill. The problem is the space used by the Vias to attach: PMT Input Signal, ESD Diode on the bottom surface, the AKA component, & the trace pair to in the transformer primary. This is made more complex because the Net that connects to the Low side of the Transformer Primary can NOT be Ground because if it is then the via adjacent to that transformer pin will just tie directly to the local Gnd Plane and we will not have a "differential" feed from the PMT input connector to the transformer primary, i.e. all transformer primary currents will flow through the signal ground plane and mix together. The solution to this had been an AKA component and via adjacent to the PMT input connector - but that takes up too much space. So try: label the odd pin on each PMT input connector channel as Net GROUND and label the Even pin as Net CH_bla_Input_CMP. This requires hacking the Template files for the PMT Input Section multi instance generation. This goes OK for connecting the transformer's primary "diff pair" directly to the Harwin connector "center" and "Even Outer Conductor" pins. So next drop from the net list all connections to AKA1...AK16 and pull these components from the DK Comps file. A 2nd direct hand exit of Comps_1106. This looks OK and gives a lot of space to clean up the routing of the Diff Pairs to the Transformer Primaries. To the eye anyway the channel to channel isolation looks a lot better this way. Try a Fill on L1 by hand with a Slot Threshold of zero and a relief of 0.35 mm and it's not a bad looking first try. Dump it. The plan is: - Everything that will actually connect to the L1 & L12 Shield Gnd Fill will be on Net "Shield", i.e. the odd Harwin outer shield conductor pins, the J1B "Grounding" Jumper, and all of the Rivets that connect the Shield Fills to the 4x real Ground Planes. - All of the Rivets that connect the Shield Fills to the 4x real Ground Planes will need to be in their own net list file of which there needs to be 2 versions: a version to net SHIELD and a version to net GROUND. Only during the generation of the Shield Fills will the Shield version of this net list file be active - at all other time use the Ground version. - How will DRC work with this ? - There needs to be an East slice through the real 4x Gnd planes at about X = 225. What to do with the 4x real Gnd Planes East of this slice ? remove them ? This is all just in the area of the PMT Analog Input Section - not above or below. - Ref Desig of current Rivets to put into this special net list file: VR2, VR3, VR4, VR22, VR23, VR: 201, 202, 203, 204, 205, 208, 209, 210, VR: 211, 212, 213, 216, 217, 218, 219. There is space to add about 7 more rivets in this area to the design and note this list skips all rivets close to the PMT ADC and far out on the Analog Gnd Plane. The point is to keep the Analog Gnd Plane equal potential. End of day counts on real moto: New Comps because the PMT TVSs moved. 1731 Comps 1416 Nets 0 UnConnected Pins 48 Shapes in pcb geom 4897 Conn 4175 Finished 169 Un-Finished 553 Guides Geom_Ver 525 Comps_Ver 1107 Nets_Ver 695 Trc_Ver 556 Tech 1475 ----------------------------------------------------------------- DATE: 2-Mar-2025 Topic(s): Change FPGA DDR4 Clock Serpentines from the 45 deg type to uwave type, Tie down CPU VREF Input pin AE12, Connect the CPU Memory CA Bus Terminators Changed FPGA DDR4 memory Clock & Strobe Serpentines from the 45 deg type to the smoothed uwave type so that they match how I did the CPU memory. Ran a new "final" timing analysis on the FPGA Memory and storeded it in the memory timing analysis data directory but recall that the FPGA CA Bus Terminators are now connected so that none of the timing values for the FPGA CA Bus easily make any sense. Tied the CPU Memory Controller VRef input pin, AE12, to Ground via a new 10k Ohm resistor - R1358. This also involves: moving a Bank #6 BULK_1V2 bypass capacitor C143 that was in the way, making a new version of the FPGA Geometry file that now has pin AE12 with a SW dog-bone and via, hand editing the overall DK Comps file, and adding a new net in the fpga_power_and_ground_pins_fcg1152.txt file. This new pull-down R1358 is on Side 2 just West of the FPGA. Right before this work we were at: geoms_521, comps_1106, nets_689, and traces_550. Making the Tie-Down for VRef input pin AE12 also involved editing the ddr4_cpu_bank_6_no_connection_nets_fcg1152.txt file. While doing that I noticed that the two files: ddr4_cpu_bank_6_power_and_sundry_nets.txt ddr4_fpga_bank_0_power_and_sundry_nets.txt both have in comments that they are for the FCVG784 package. I think this is just a comment left over from when we were going to use the 784 pin package. I need to verify that and correct this comment. I found not other instances of the "FCVG784" string in the net list files. Start the work to re-connect the CPU Memory CA Bus Terminators and get it about 50% finished. The simple net list edits to re-connect the CA Bus Terminators are in the files: ddr4_cpu_bank_6_ca_bus_just_terms_nets_fcg1152.txt ddr4_cpu_bank_6_power_and_sundry_nets.txt When the CPU Memory CA Bus Terminators were re-connected all counts changed as expected: UnConnected pins went from 2 to zero Nets dropped by 25 SLI Guides increased by 27 End of day counts on real moto: Comps is edited 1747 Comps 1415 Nets 0 UnConnected Pins 47 Shapes in pcb geom 4894 Conn 4166 Finished 169 Un-Finished 559 Guides Geom_Ver 522 Comps_Ver 1106e Nets_Ver 692 Trc_Ver 552 Tech 1471 ----------------------------------------------------------------- DATE: 1-Mar-2025 Topic(s): Work List, Review 13 GHz traces, FPGA DDR4 Clocks (& Strobes) Known Work List: 0. DRC checks, Reference Disignator and other silkscreen work, ... 1. Fix the FPGA DDR4 Clock serpentines so that they are setup like the ones in the CPU Memory, i.e. smoothed uwave type serpentines. 2. Connect the CPU Memory CA Bus Terminators. 3. Add 2nd vias to the DDR4 2V5 Word Line interconnects. 4. Add a pul-down to pin AE12 - the CPU Memory Controller's unused VRef input. 5. Verify that the 13 GHz routing is OK especially at the FPGA end - specifically why does RX3 have only 3 sertentines for a best match while Rx 0,1,2 have 4 serpentines ? 6. Add the rest of the Diff Pairs (Reference Clocks and Enet) to the Diff Pair Trace Match programs configuration file. 7. Implement the PMT Analog Input Section "Shield Ground": - A significant issue with this is how to implement it in a simple clean way, i.e. some Gnd Rivets are connected while others (of the same net) are Isolated. Another issue is fining enough East-West board space between the East column of transformers and the ESD diodes on the bottom side. - Need to add more details to the Shield Gnd Shapes and the top and bottom Shapes need to be different from one another. - Could add Top and Bot Breakout Layer tabs (running West) to the Harwin pins - different top and bottom. - Need to add more Gnd Rivets just East of the PMT ADC. This will make about 34 rivets connecting the Shield Gnd to the 4 DK Gnd Planes. - Could either use real Fill Excluders - different top and bottom. This could be made to work because these Shiled Gnd Fills are the only L1 & L12 Fills in this area of the board - but there will be 10**9 of them - could place with the multi instance generator. OR can we make the Shield Gnd Fill on a separate net - temporarily move the Gnd Rivets that we want connected to that net - and use Slot-Threshold to automatically do all of the Fill exclusion in a rational way. Recall that Traces need to be saved with this Fill in the Design and thus with the connected Gnd Rivets in the wrong net. FPGA Memory Clock Serpentines: - The 45 deg serpentine currently used for the FPGA Memory Clocks and Strobes gives 0.1657 mm per step out. The smooothed uwave sertentine gives 0.225 mm per step out and has a smaller impedance bump. The difference is 0.0593 mm per step out. Review again the 13 GHz PMT ADC Data Diff Pairs: Specifically - how can it be that the match, both in total length and the perpendicular match are best with only 3 serpentines on Rx 3 at the FPGA end while RX 0,1,2 match best with 4 serpentines ? How can that be ? The details of implementing all of this are in the log book entries for 24, 17, 16 of Feb 2025 The current layout is: at the FPGA end: Rx0 is on the North side and Rx3 is on the South. ---- The CMP side of a pair is the longer one (goes to the further pad on the FPGA) for all 4 data lanes. The CMP side of a pair is on North side of the pair for all 4 data lanes. The serpentines are in the DIR side of a pair for all 4 data lanes. at the CPU end: The Out_0 pair is the Northern most diff pair. --- For the 0 data lane: The DIR is on the North side of the pair. The DIR goes to the further pad on the ADC. The serpentines are in the CMP side. The ADC DIR goes to FPGA CMP --> criss-cross. For the 1 data lane: The DIR is on the North side of the pair. The DIR goes to the further pad on the ADC. The serpentines are in the CMP side. The ADC DIR goes to FPGA CMP --> criss-cross. For the 2 data lane: The CMP is on the North side of the pair. The CMP goes to the closer pad on the ADC. The serpentines are in the CMP side. The ADC CMP goes to FPGA CMP --> NO criss-cross. The Out_3 pair is the Southern most diff pair. For the 3 data lane: The CMP is on the North side of the pair. The CMP goes to the closer pad on the ADC. The serpentines are in the CMP side. The ADC CMP goes to FPGA CMP --> NO criss-cross. The current match is: at FPGA end: Rx 0, 1, 2 have 4 serpentines at CPU end: Rx 0, 3 have 3 sertentines Rx 1, 2 have 4 serpentines This gives: The lengths and matching all in mm: Length to Total Errors FPGA End Coupling Cap ADC End Length FPGA ADC Length ------------- -------------- ---------------- ------- ------------------- XCVR3_RX0_CMP 57.91 6.73 ADC_Serout_0_DIR 64.64 0.09 0.19 0.28 XCVR3_RX0_DIR 57.82 6.54 ADC_Serout_0_CMP 64.36 XCVR3_RX1_CMP 54.38 9.74 ADC_Serout_1_DIR 64.12 0.09 0.05 0.14 XCVR3_RX1_DIR 54.29 9.69 ADC_Serout_1_CMP 63.98 XCVR3_RX2_CMP 54.80 9.69 ADC_Serout_2_CMP 64.49 0.06 0.01 XCVR3_RX2_DIR 54.74 9.74 ADC_Serout_2_DIR 64.48 0.05 XCVR3_RX3_CMP 58.30 6.54 ADC_Serout_3_CMP 64.84 0.25 0.06 XCVR3_RX3_DIR 58.05 6.73 ADC_Serout_3_DIR 64.78 0.19 I believe that there are 3 things that confuse ones initial guess about how this sould look: - The upper 2 signal paths include a criss-cross and the lower 2 do not. - Once the Diff Pairs have escaped the FPGA BGA then the 4 bends getting to the AC Coupling caps are not all the same and thus balanced - the bend adjacent to the coupling caps needs to be tighter. - The runs at 10 deg across the weave are not all the same length - because this is where the match is made between the 1.00 mm BGA to a 0.80 mm BGA. ----------------------------------------------------------------- DATE: 28-Feb-2025 Topic(s): Finish CPU Memory timing work, Quick meeting with Nathan Finished work on adjusting the CPU Memory timing. Saved a "Final" CPU Memory Timing Report in the memory timing analysis data directory. Executive summary of CPU Memory Timing - worst case numbers: CA Bus earliest -18.60 psec -2.94 mm latest 24.96 psec 3.95 mm D0:D7 " -11.64 -1.84 " 8.06 1.28 D8:D15 " -11.72 -1.85 " 12.34 1.95 D16:D23 " -7.91 -1.25 " 9.09 1.44 D24:D31 " -9.24 -1.46 " -1.52 -0.24 Numbers with a Negative sign mean that a Signal arrives before its Clock or that the signal trace is short. The timing situation with CPU Memory before it was worked on is shown in the 24-Feb-2025 log book entry. The "final" timing report for the FPGA memory is shown in the 21-Feb-2025 log book entry. Our DDR4 memory Design Rules are shown in yesterday's log book entry. I want to go back to the FPGA Memory and change how I did its 5 clocks to match how I did the CPU Memory clock (and strobe) trace adjustments. I will then need to make a new "final" timing report for the FPGA Memory - there should be almost no changes at all. Meeting with Nathan: - I will add a Pull-Down to pin AE12 - the CPU Memory Controller VRef input. This will be a pull-down only, i.e. no connection to any ref supply. Nathan has not yet heard back from MicroChip but has found additional DDR4 documentation that indicates that our DDR4 Timing Design Rules are correct. - I will start the work on the PMT Analog Input Section L1 & L12 "Ground Shields". We discussed their intent, i.e. to reduce any currents flowing in the real Analog Section Ground Planes that connect the Bias Network Gnd and the Terminator Network Gnd to the PMT ADC Analog Ground. The Shield pins in the PMT Connectors will connect only to these L1 & L12 "Ground Shields" and not to the Analog Ground planes in the Analog Input Section. Our design focus and our use of the pcb layer resources is aimed at reducing channel to channel cross-talk. End of day counts on real moto: 1746 Comps 1440 Nets 2 UnConnected Pins 47 Shapes in pcb geom 4864 Conn 4161 Finished 169 Un-Finished 534 Guides Geom_Ver 521 Comps_Ver 1106 Nets_Ver 689 Trc_Ver 549 Tech 1468 ----------------------------------------------------------------- DATE: 27-Feb-2025 Topic(s): CPU Mem CA Bus timing work Finished the Auxiliary Routing Data file for the CPU Memory last night and then worked on the CA Bus signal timing all day. Still looking for a way to fix a 1.41 mm late address signal before giving up and moving the clock. All CPU Memory Data Lanes are finished and look OK. Recal our design rules: CA Bus +- 25.2 psec +- 4.0 mm Data Lane +- 14.5 psec +- 2.3 mm End of day counts on real moto: 1746 Comps 1440 Nets 2 UnConnected Pins 47 Shapes in pcb geom 4864 Conn 4161 Finished 169 Un-Finished 534 Guides Geom_Ver 521 Comps_Ver 1106 Nets_Ver 689 Trc_Ver 545 Tech 1464 ----------------------------------------------------------------- DATE: 26-Feb-2025 Topic(s): CPU D0:D15 timing work, Pin AE12 CPU Mem VRef investigation It is possible to access FPGA pin AE12. It will require removing one of the 7 "under FPGA" BULK_1V2 bypass capacitors that service the CPU DDR4 Memory Bank #6. The FPGA DDR4 Memory Bank #0 has its own "under FPGA" BULK_1V2 bypass capacitors - 9 of them. The escape from AE12 (once it has a dog-bone and via) will not be too circuitous and there is space available for an 0603 resistor. Recommendation: Let's do it and tie the resistor to Gnd - not to the CPU Memory's 600 mV VRef supply. I do not want to risk tainting the CPU Memory's VRef supply by feeding it into some place were it is 99% probably not needed. I could look at a 2 resistor setup like on the Demo board if we want to. A good reason for adding this Pull- Down is just to get this topic off of the table so that we can focus other design issues. Working in the CPU D0:D15 data lanes. End of day counts on real moto: 1746 Comps 1440 Nets 2 UnConnected Pins 47 Shapes in pcb geom 4864 Conn 4161 Finished 169 Un-Finished 534 Guides Geom_Ver 521 Comps_Ver 1106 Nets_Ver 689 Trc_Ver 540 Tech 1459 ----------------------------------------------------------------- DATE: 25-Feb-2025 Topic(s): Restore from durand the L1 Ground Shield Shape with better rivet coverage on the North, West, and South and a first example of a Cutout for use in the PMT Analog Input Section. Build the DK PCB Geom with the new Ground Shield Shape - no errors CPU Mem D16:D23 timing is in trouble because of long far corner to far corner runs of D17 and D19. D19 can swap with D21. D17 is a more difficult problem. --> Recall again that the FPGA & CPU memory system Net Names are always based on the Memory Controller signal name - and not on the memory chip pin name. End up with a 5 way swap. CPU Mem D0:D7 had a very nice clean layout topologically but very poor timing match. End up with a 7 way swap. Nathan has checked through the Net List checks from the students. Two main points to date: - I need to check the Interposer Buffer and SPI wiring, e.g. is it correct and do the drawing match the net list at the level of which buffer is used for which signal. - We are still uncertain about what is actually required for the unused VRef input to the CPU DDR4 Controller - pin AE12 in Bank #6. I need to investigate how hard it would be to route it out. Working in the CPU D0:D15 data lanes. End of day counts on real moto: 1746 Comps 1440 Nets 2 UnConnected Pins 47 Shapes in pcb geom 4864 Conn 4161 Finished 169 Un-Finished 534 Guides Geom_Ver 521 Comps_Ver 1106 Nets_Ver 689 Trc_Ver 535 Tech 1454 ----------------------------------------------------------------- DATE: 24-Feb-2025 Topic(s): CPU Memory Timing and Analog Shield Fills Restore onto real moto the Gnd Shield Shape now with mitters and edges to get around the Power Via Array and some bypass capacitors. Both the L1 and the L12 Shapes can probably be the same on their North, West and South edges - only the simple straight East edge will need to be different. Currently the 13 GHz Rx3 data lane is different from the Rx0, 1, 2 data lanes in that it uses only 3 serpentines. I should also look at the numbers when I make all 4 lanes like Rx3 is currently layed out. The 3 serpentine layout could be cleaner and have good numbers for all 4 lanes. See log book entry 17-Feb-2025. Do I need to do anything with the Bank #6 VRef pin AE12 ? The some what equivalent pins for the XCVRs M26, P26 are tied off with an RC network. I do not think that there is an equivalent VRef Input pin for Bank #0. The package-pin spread sheet says that Bank #6 VRef AE12 must be tied off to Gnd through a 10K Ohm when not used. Their Deamo Board appears to either: - tie it to a 1k Ohm 1k Ohm 600 mV voltage divider from 1V20 memory or - let it float. I'm very certain that the external VRef Input for Bank #6 is NOT actually used - rather an internal VRef generator is used. Currently pin AE12 is a BGA Pad only and access to give it a dog-bone and via is blocked. There was a question last week about how bad were the DDR4 timing errors before the work to minimize them. I do not have the before clean up numbers for the FPGA memory but here I will record an executive summary of the CPU memory timing errors before any work was done to minimize them. Can compare to Final FPGA numbers in log book entry 21-Feb-2025. Executive summary of CPU Memory Timing before any work to minimize errors: D0:D7 earliest 25.60 psec 4.05 mm latest 22.10 psec 3.50 mm D8:D15 " 63.39 10.03 " 35.58 5.63 D16:D23 " 21.21 3.36 " 34.15 5.40 D24:D31 " 53.94 8.53 " 0.34 0.05 This is just for the CPU Memory Data Lanes - I do not yet have all of the information in the Aux Routing Data file for for the CPU CA Bus signals. Working in the D16:D31 data lanes. End of day counts on real moto: 1746 Comps 1440 Nets 2 UnConnected Pins 47 Shapes in pcb geom 4864 Conn 4161 Finished 169 Un-Finished 534 Guides Geom_Ver 520 Comps_Ver 1106 Nets_Ver 684 Trc_Ver 529 Tech 1448 ----------------------------------------------------------------- DATE: 23-Feb-2025 Topic(s): Restore files, PCB Geom, Bank #6 Delay files, Final FPGA Mem Timing Analysis files, Work to move the PMT Analog Input L1 traces to L6 / L7 Restore from moto durand to real moto the following files: build_disco_brd_geom.sh disco_fill_shapes_analog_shield_signal_1.txt clean_pack_package_delay_bank_6_data.sh package_delays_all_columns_bank_6.txt package_delays_all_columns_bank_6_ordered.txt package_delays_all_columns_bank_6_ordered_packed.txt Get Sierra's latest silkscreen file from late Friday the 21st and build a fresh DK PCB Geom - now with the latest silkscreen and with a draft Shape for the PMT Input Section Shield Fill. The pcb geom builds without error. Move the 4x Bank #6 Delay related files to the .../Work/Memory_Delay_Data_Prep/ directory. I now have all of the files that are required to start Delay Analysis on the Bank #6 CPU DDR Memory except for the Auxiliary Routing Data file for Bank #6 CPU Memory. I should keep in this directory a copy of the final FPGA Memory Timing Analysis Report and Check files that were made last Friday rigth before the FPGA Memory Terminators were re-connected. So, move into .../Work/Memory_Delay_Data_Prep/ the files: fpga_memory_check_final_21feb25.txt fpga_memory_report_final_21feb25.txt Move the L1 traces in the PMT Analog Input Section down to L6 or L7. Use the 2 layers to minimize coupling (Pri to Sec and Channel to Channel). This move requires moving some of the PMT Connector to Transformer Primary traces. Push to minimize coupling between the PMT Input Traces. This now looks a lot better but need to still work on minimizing Channel to Channel coupling (as that is probably more important to Physics than any signal distortion caused by Pri to Sec Coupling). End of day counts all Ver on on real moto: 1746 Comps 1440 Nets 2 UnConnected Pins 47 Shapes in pcb geom 4864 Conn 4161 Finished 169 Un-Finished 534 Guides Geom_Ver 519 Comps_Ver 1106 Nets_Ver 684 Trc_Ver 526 Tech 1445 ----------------------------------------------------------------- DATE: 22-Feb-2025 Topic(s): Work on the Fill Shape for the Shield over the PMT Analog Input Section and on extracting and ordering the Back #6 Package Delay Data The current intent for layers L1 and L12 is to use them as grounded Shields over the PMT Analog Input Section. That is, they will be Fills that are connected to the Perimeter Ground Rivets around the PMT Analog Input Section - but will not be connected to the Ground Vias for the Transformer Center Tap Bias Networks or to the Transformer Secondary Terminator Networks. The Ground for the Bias and Terminator Networks will be to only the 4 "normal" Ground Planes. The intent of the L1 and L12 Shield Fills is to shield these Analog Ground Planes from external noise. For now it looks like the best way to make this Shield Fill is to use "Excluders" around the Transformer, Bias, and Terminator components. This is a lot of excluders and entering them by hand could cause errors. Review the most recent desigh that used a lot of Excluders (the CMX card for Atlas with 525 Excluders) to recall how it is done. Do the hand editing to get the Bank #6 Package Delay data into the correct order and format for the Timing Analysis program. ----------------------------------------------------------------- DATE: 21-Feb-2025 Topic(s): Finish FPGA Memory, Connect the Terminators for the FPGA Mem CA Bus Make some small tune ups on the FPGA DDR4 timing and bring the Auxiliary Routing Data file for the FPGA Memory up to data and double check it. Generate a "final" timing report for the FPGA memory. Executive summary of FPGA Memory Timing worst case numbers: CA Bus earliest 12.49 psec 1.98 mm latest 18.62 psec 2.95 mm D0:D7 " 6.04 0.96 " 5.78 0.91 D8:D15 " 10.13 1.60 " 11.78 1.88 D16:D23 " 6.74 1.07 " 8.86 1.40 D24:D31 " 7.29 1.15 " 11.24 1.78 For our anticipated Data Lane Data Valid Time of 290 psec (out of the 625 psec per data transfer) our design rules are: CA Bus +- 25.2 psec +- 4.0 mm Data Lane +- 14.5 psec +- 2.3 mm Work on the FPGA DDR4 is finished for now so edit the net list so that the CA Bus Terminators are connected to the bus and route it. The CA Bus Clock is re-connected in the file: ddr4_fpga_bank_0_power_and_sundry_nets.txt 1 Diff Pair signal The CA Bus Address and Control signals are re-connected in the file: ddr4_fpga_bank_0_address_and_command_term_fcg1152.txt 25 se signals The counts before re-connection match the end of the day yesterday. After the CA Bus is re-connection in the Net List but none of it has been routed the counts are: 4857 Conn 4127 Finished 170 Un-Finished 560 Guides I do not know why the number of Conn dropped by 3, Guides increasing by 27 is exactly the expected number. Issues during the routing to the CA Terminators: I had put one easy to fix trace in the way, I had put the Clk Terminators on the wrong side (now fixed for both FPGA and CPU), I saw a slightly better way to do the CA Bus connections between the two memory chips - that still has equal 2D length for all 25 runs but has slightly less overlap (now implemented for both FPGA & CPU memory), one memory Gnd Rivet under a DDR chip was in the way of the Clk run to its terminators. End of day counts with all FPGA Mem routed including its Terminator connections all Ver on on real moto: 1746 Comps 1440 Nets 2 UnConnected Pins 46 Shapes in pcb geom 4856 Conn 4153 Finished 169 Un-Finished 534 Guides Geom_Ver 518 Comps_Ver 1106 Nets_Ver 684 Trc_Ver 525 Tech 1444 Nets dropped by 25 as expected Un-Connected dropped from 4 to 2 as expected Conn increased by 26 expected 27 Finished increaded by 26 expected 27 UnFinished dropped by 1 and Guides increaded by 1 who is it ? It looks like I lost a trace but I have not found it yet. I need to build the full design - it has been a couple of weeks since the last full build with Fills and such. Short meeting with Nathan about remaining steps before release - will pass to him the student Geom and Net List reviews. ----------------------------------------------------------------- DATE: 20-Feb-2025 Topic(s): Almost finish FPGA Memory traces, DK PCB Geom - up to date I brought Sierra's silkscreen work as of close of business yesterday and new Shape files from moto durand for the East Column of PMT ADC Fills into the official file set on real moto and build a fully current DK PCB Geom. These PMT ADC East Column files are setup to work well with the recently added Ground Rivets on the east side of the PMT ADC that help clamp the Gnd Planes together over the PMT differential ADC input traces. Basically finished the FPGA Memory timing matches. All looks good but I need to recalculate the Fraction on Surface Layer for Adrs Lines 4, 5, 7. May still shift the CA Bus Clock by 0.3 mm but that is about it. End of day counts all Ver on on real moto: 1746 Comps 1465 Nets 4 UnConnected Pins 46 Shapes in pcb geom 4830 Conn 4127 Finished 170 Un-Finished 533 Guides Geom_Ver 518 Comps_Ver 1105 Nets_Ver 683 Trc_Ver 520 Tech 1439 ----------------------------------------------------------------- DATE: 19-Feb-2025 Topic(s): Work on FPGA Mem CA Bus, Sierra works on silkscreen logos Trimming the delays in the FPGA CA Bus has required a lot of work, e.g. re-routes of 8 signals to improve just one of them. The general work sequence is now pretty clear: work on the current longest route to shrink it until you reach a trace that you can not shrink (i.e. its already a direct run with max 45s and no other paths are available), then stretch the Clock to just put the max delay trace in range, the stretch all of the required signal traces that are too short to be in range. For the data buses we are using a range limit of +- 14.5 psec or +- 2.3 mm. for the CA Bus I'm using +- 4 mm. For the FPGA memory CA Bus this will require stretching 5 signals. Sierra is working on the logos. End of day counts all Ver on on real moto: 1746 Comps 1465 Nets 4 UnConnected Pins 46 Shapes in pcb geom 4828 Conn 4125 Finished 170 Un-Finished 533 Guides Geom_Ver 517 Comps_Ver 1105 Nets_Ver 683 Trc_Ver 516 Tech 1439 ----------------------------------------------------------------- DATE: 18-Feb-2025 Topic(s): Menory trace match work, Silkscreen All data lanes of the FPGA Memory are now well matched and I'm working on its CA Bus which should be easier. I'm currently double checking the "auxiliary routing data" 4 x 71 values all collected or calculated by hand Sierra was in to work on the logo part of the silk. I moved the current file set to her maching without trouble - it inculdes all of her work up to date. She is now using the Librarian to directly look at just the pcb geom so that she can quickly see the logo work. 1746 Comps 1465 Nets 4 UnConnected Pins 46 Shapes in pcb geom 4828 Conn 4125 Finished 170 Un-Finished 533 Guides Geom_Ver 517 Comps_Ver 1105 Nets_Ver 683 Trc_Ver 514 Tech 1437 ----------------------------------------------------------------- DATE: 17-Feb-2025 Topic(s): Review of uWave routing, Quick review of the 13 GHz routing to verify that the length numbers in yesterdays log book are correct and that I did not "over compensation" in any of the runs. There is in fact one case of over compensation and that is in the XCVR3_RX3 FPGA run. This is a very small over compensation of only 0.02 mm but still it is stupid to include a serpentine that pushes things over the edge. So I will pull out the 4th serpentine in the XCVR3_RX3_DIR trace run. This leaves us with: The lengths and matching all in mm is now: Final Numbers Length to Total Errors FPGA End Coupling Cap ADC End Length FPGA ADC Length ------------- -------------- ---------------- ------- ------------------- XCVR3_RX0_CMP 57.91 6.73 ADC_Serout_0_DIR 64.64 0.09 0.19 0.28 XCVR3_RX0_DIR 57.82 6.54 ADC_Serout_0_CMP 64.36 XCVR3_RX1_CMP 54.38 9.74 ADC_Serout_1_DIR 64.12 0.09 0.05 0.14 XCVR3_RX1_DIR 54.29 9.69 ADC_Serout_1_CMP 63.98 XCVR3_RX2_CMP 54.80 9.69 ADC_Serout_2_CMP 64.49 0.06 0.01 XCVR3_RX2_DIR 54.74 9.74 ADC_Serout_2_DIR 64.48 0.05 XCVR3_RX3_CMP 58.30 6.54 ADC_Serout_3_CMP 64.84 0.25 0.06 XCVR3_RX3_DIR 58.05 6.73 ADC_Serout_3_DIR 64.78 0.19 Now back to the FPGA Memory trace length work - working on D24-D31. Meeting with Nathan: yes to move the PMT Analog Input L1 traces to L6,L7 yes to Fill with Gnd L1 and L12 in the PMT Analog Input section End of Day Counts with all Fills OUT - All Ver are from real moto --------- DQ24 is currently an SLI 1746 Comps 1465 Nets 4 UnConnected Pins 46 Shapes in pcb geom 4828 Conn 4124 Finished 170 Un-Finished 534 Guides Geom_Ver 517 Comps_Ver 1105 Nets_Ver 683 Trc_Ver 511 Tech 1434 ----------------------------------------------------------------- DATE: 16-Feb-2025 Topic(s): Continue 13 GHz trace work Save Trc_506 on real moto. Restore Trc_508 durand onto real moto as Trc_506 and verify the content and counts. Recall from yesterday's routing work: VR111 had to be moved 1.1 mm East. The now slanted vertical runs have an X shift of 2.0 mm over their vertical length of about 19.5 mm or about 5.86 deg. The smoothing for the 45 deg bends at each end of the slant verticals is 72 Segments with a 3 mm radius thus each segment is a 5 deg bend. The segment adjacent to the connection to the slant verticals has been deleted so that the smoothed 45 deg bend matches into the slant vertical. Currently I have 4 of our nominal serpentine step outs on the short trace of all 4 pairs at the FPGA end. At the ADC end I have 4 of the serpentine step outs on the center 2 diff pairs and only 3 step outs on the outer 2 diff pairs - because that is all that fit into the available space. All ADC end serpentines are between the Coupling Caps and the ADC. All of these serpentines have been smoothed by the parameters described in the routing details. You can not get a length measurement accurate at the 0.1 mm level without first smooting. The lengths and matching all in mm is now: to be checked Length to Total Errors FPGA End Coupling Cap ADC End Length FPGA ADC Length ------------- -------------- ---------------- ------- ------------------- XCVR3_RX0_CMP 57.91 6.73 ADC_Serout_0_DIR 64.64 0.09 0.19 0.28 XCVR3_RX0_DIR 57.82 6.54 ADC_Serout_0_CMP 64.36 XCVR3_RX1_CMP 54.38 9.74 ADC_Serout_1_DIR 64.12 0.09 0.05 0.14 XCVR3_RX1_DIR 54.29 9.69 ADC_Serout_1_CMP 63.98 XCVR3_RX2_CMP 54.80 9.69 ADC_Serout_2_CMP 64.49 0.06 0.01 XCVR3_RX2_DIR 54.74 9.74 ADC_Serout_2_DIR 64.48 0.05 XCVR3_RX3_CMP 58.30 6.54 ADC_Serout_3_CMP 64.84 XCVR3_RX3_DIR 58.32 6.73 ADC_Serout_3_DIR 65.05 0.02 0.19 0.21 I realized that I had burried the BB ADC I2C Address Select traces and connection where we could not access them if necessary - so fixed that. Counts with all Fills OUT - All Ver are from real moto --------- 1746 Comps 1465 Nets 4 UnConnected Pins 46 Shapes in pcb geom 4828 Conn 4125 Finished 170 Un-Finished 533 Guides Geom_Ver 517 Comps_Ver 1104 Nets_Ver 683 Trc_Ver 508 Tech 1431 ----------------------------------------------------------------- DATE: 15-Feb-2025 Topic(s): Work on 13 GHz routing There are serious faults in the existing 13 GHz routing: - There is no consideration for weave effect in the longest vertical runs and that is a problem because we do not know for certain at this time what the L1-L2 laminate will be. - The current setup treats the North 2 pair differently than the South 2 pair: . The difference is at the ADC end of the runs and it is nice because it helps get the pairs spread out as quickly as possible but . It builds in a 1.95 mm trace length miss-match that is hard to recover from specifically: . The South 2 pairs are basically overall length bananced, i.e. the Long side from the Coupling Cap to the FPGA is the Short side from the Coupling Cap to the ADC, thus the 2 sides of the Diff Pair start out almost overall length matched - but not perpendicular matched. . The North 2 pairs start out with a 1.95 mm overall length miss-match, i.e. the Short side from the Coupling Cap to the FPGA is also the Short side from the Coupling Cap to the ADC, the total error is about 1.95 mm in length and they are not perpendicular matched either. 1.95 mm is a lot to make up with serpentines, i.e. increments of about 0.225 or 0.265 mm. More back ground: - In both the North or South cases, adding serpentines to get a perpendicular match also pushes you to an overall length match. - See this log book for: 11-Jan-25, 31-Jan-25, 8-Feb-25 and 13-Feb-25. - Recall that the UI expressed in trace length is about 12.7 mm and thus we strongly care about stuff at the 0.6 mm level - What did AD do on their Demo board: all escapes are in the same sence, i.e. there is no North South 2 pairs difference. They did manage to keep their Coupling Caps within about 5 or 6 mm trace length of the package pin - but this is still about 1/2 of the UI - we are currently about 5.8 shortest up to about 9.7 longest (but have better separation). Their only serpentines are at the far side of the Coupling Caps and 3 of the 4 pairs has serpentines. They probably imposed on themselves No Polarity Flips just to avoid confusing stupid customers. They used full uwave laminate (megatron or something like that) and used via in pad layout. - Right now at the FPGA end we escape all 4 pairs the same way, i.e. CMP is North of DIR and I can not change the Nothern 2 pairs without also changing the Southern 2 pairs. - At the ADC end: for the Northern 2 pairs, DIR is North of CMP for the Southern 2 pairs, CMP is North of DIR - On the FPGA: CMP pins are to the West DIR pins are to the East - On the ADC: CMP pins are to the West DIR pins are to the East Record the ssituation right now all in mm and in layout order: Length to Total FPGA End Coupling Cap ADC End Length ------------- -------------- ---------------- ---------- XCVR3_RX0_CMP 58.61 6.73 ADC_Serout_0_DIR 65.34 XCVR3_RX0_DIR 57.61 5.78 ADC_Serout_0_CMP 63.39 XCVR3_RX1_CMP 55.11 9.74 ADC_Serout_1_DIR 64.85 XCVR3_RX1_DIR 54.11 8.79 ADC_Serout_1_CMP 62.90 XCVR3_RX2_CMP 55.52 8.79 ADC_Serout_2_CMP 64.31 XCVR3_RX2_DIR 54.52 9.74 ADC_Serout_2_DIR 64.26 XCVR3_RX3_CMP 59.02 5.78 ADC_Serout_3_CMP 64.80 XCVR3_RX3_DIR 58.02 6.73 ADC_Serout_3_DIR 64.75 Path forward: Implement the weave metigation and install the required length match serpentines and see how ridiculous it looks. I'm moving the tops and bottoms of the long vertical runs 1.0 mm West at the Top and 1.0 mm East at the Bottom. Doing this requires moving VR111 about 1 mm East to keep the clearance. Installed our nominal Diff Pair length match serpentines as described in routing details. ----------------------------------------------------------------- DATE: 14-Feb-2025 Topic(s): FPGA DDR4 trace match work, more PMT Analog Input layout ideas Still working on the FPGA DDR4 trace match. It takes many more loops through the: trc edit, measure, decide what to change next cycle than I expected. The main issue has been - you do not just need to match but you must do it cleanly and without adding any significant overlap in the layer pairs L3-L4 or L9 - L10. The first 3 lanes D0...D23 now easily obey the match rules of: 14.5 psec or 2.3 mm. Nathan & I both remain concerned that the PMT Analog Input section layout is not good enough for true 12 Bit resolution with 125 MHz analog signals and with 450 uVolt LSB. Serious folks would have stayed focused on this since day one. Some of the ideas are: - Cans over the Transformers or at least get Vias or Pads to mount such cans into the design now so they are on the pcb if needed. Note that with the recent addition of the return current vias adjacent to both primary side trasformer terminals we have already moved in the direction of providing vias to mount cans. - Move the routing of the transformer secondary side outer terminals from their currently exposed L1 layer to one of the internal (and other wise unused in this area) Power Fill layers, i.e. L6 or L7. That will get these analog traces under Gnd Plane and allow better differential routing of these signals and it will allow tucking all of the transformer pad connections to vias under the transformers, i.e. it will make the exposed transformer connections as compact as possible. Can we reduce the Transformer geometry pad size ? This is an obvious step to take. - Make Gnd Fills on both L1 and L12 over the whole PMT Analog Input section out as far North and South as the Gnd Plane Slits. This will both stiffen the Gnd Plane structure in the PMT Analog Input section and it could provide pads for soldering on Cans over the Transformers if SMD Pads are useful for transformer Can mounting. Note that unlike trying to use the L6 L7 Power Fill layers to stiffen the Gnd Structure in the Analog Input area - where there is no direct path to connect added L6 L7 Gnd Fills to the existing Analog Gnd Planes under the ADC (because L6 L7 are fully used for Power Fills under the ADC) - Gnd Fills on L1 and L12 could naturally connect down to the Analog Gnd Planes via the wall of Gnd Rivets just East of the PMT ADC. - Provide mounting vias or pads for shields over the likely aggressors, e.g. the memory and any other high digital noise area. - Because we realy realy care about analog signals in the range of 125 MHz should we be running the on-board clocks at a much lower frequency and then multiply up only in the FPGA and PMT ADC ? How low could we run them ? The few clock signals are probably small potatoes compared to the 142 digital signals in the DDR4 all banging around with random data as hard as possible. Counts with all Fills OUT - All Ver are from real moto --------- 1746 Comps 1465 Nets 4 UnConnected Pins 46 Shapes in pcb geom 4827 Conn 4124 Finished 170 Un-Finished 533 Guides Geom_Ver 517 Comps_Ver 1103 Nets_Ver 683 Trc_Ver 506 Tech 1429 ----------------------------------------------------------------- DATE: 13-Feb-2025 Topic(s): Drawngs and Issues to Investigate Worked on Time Gen drawings: 23, 50, and 70 to get them up to date with the Clock discussion that Nathan and I had yesterday. Clean up was needed and additional specific information could be added now that layout is done. Other issues discovered in the design: - A net list error, two net names currently clame that U1 pins F29 & F30 are "XCVR_1A_REF_CLK_IN" and this sould be XCVR_3A. All actual pins look OK - I think that it is only a net name error - but this needs to be understood and fixed. I think that XCVR_1A was going to be used for JESD back when the smaller FPGA package was in the design. - I think that the PMT ADC has some 0.13 mm wide traces escaping between pins. I think that these need to be 0.12 mm for routes within the 0.8 mm BGA. I need to verify the 0.8 mm pitch BGA dog-bone via pad diameter and need to understand what is going on and why DRC has not complained. Something is not right. - Need to revisit the 13 GHz Diff Pair traces. I needed / wanted to do this anyway (to reduce risk of weave effect) but from running the length match program on them again this morning it's clear that things are not good enough. We need basically a perfect match at the AC Coupling Caps when coming from either direction. What length matters: 12.7 GHz is a UI of about 78.74 psec or about 12.72 mm on a DK pcb surface trace where I expect the Propagation Constant to be about 6.19 psec/mm. We need to care about 1/20 of this. 1/20 is 0.63 mm. <--- Another way to think of this is that a lambda/4 error at the 5th harmonic will kill it and we want/need the 5th. I also need to verify and make certain the the 13 GHz JESD data polarity flips are documented and that Nathan has signed off that the firmware is OK with them. ----------------------------------------------------------------- DATE: 12-Feb-2025 Topic(s): DDR4 Trace Analysis & Routing rework Sign off meeting about Clocks, Other Clean up Clock meeting topics: 4x operating scenarios, jumpers, traces and signals in each scenario, most critical signals, verify pins on FPGA/CPU and on Timing Gen, Drawings - missing, wrong, not clear. Action items: In the drawings - Time Gen Output 1B drop the Spare and call it 125 MHz, Check TC 34/36 125 MHz as an aggressor - routing is OK, Time Gen M4 will be an output in the most likely scenarios ---> move series term R902 from the FPGA end to the Time Gen end. Other Clean Up: Add one more Ground Rivet up above VR107 at the end of the Gnd Split, Clean up TRN7 pin #1 routing, See and implement a slightly cleaner ADC Clock route escape at the PMT ADC, move R904 Time Gen M4 series term down to Time Gen. At this point - All clean ups above are finished, All FPGA DDR4 data lane matches are under way: Counts with all Fills OUT - All Ver are from real moto --------- 1746 Comps 1465 Nets 4 UnConnected Pins 46 Shapes in pcb geom 4827 Conn 4124 Finished 170 Un-Finished 533 Guides Geom_Ver 517 Comps_Ver 1103 Nets_Ver 683 Trc_Ver 503 Tech 1426 ----------------------------------------------------------------- DATE: 11-Feb-2025 Topic(s): DDR4 Trace Analysis, Routing work - clean up and DDR4 match Added to the DDR4 Timing Analysis program an Timing Error report that is based just on the longer of the 2 Clock signals in a Bus Group. Because I basically can not "improve" any of the Clock/ Strobe routing (it is already chalk snap line) and is frequently too long (because it routes on the L12 layer, the clearest information for improving the DDR4 routing is a direct compare to the existing and unchangable clock routes. Finished flipping every other PMT Input from L9,L10 to L4,L3 to improve the signal isolation. Added 8 more Ground Rivets in the PMT Analog Section by the Input Return pin of the East row of Transformers - these are VR221 : VR228. At this point - before starting the DDR4 trace work - the counts: Counts with all Fills OUT - All Ver are from real moto comps is edited --------- --------------- 1745 Comps 1465 Nets 4 UnConnected Pins 46 Shapes in pcb geom 4827 Conn 4124 Finished 170 Un-Finished 533 Guides Geom_Ver 517 Comps_Ver 1102 Nets_Ver 682 Trc_Ver 500 Tech 1423 This looks OK - so jump in to the DDR4 trace match work. Start the battle with FPGA Data Bus D0:D7 which starts out with: Pin Net Delay Error Error Number Name psec psec mm AE23 DDR4_FPGA_DQS0_DIR 304.71 -4.03 -0.65 AD23 DDR4_FPGA_DQS0_CMP 308.74 0.00 0.00 AD21 DDR4_FPGA_DM0_B 296.89 -11.85 -1.87 AF23 DDR4_FPGA_DQ0 295.56 -13.18 -2.09 AD25 DDR4_FPGA_DQ1 288.17 -20.57 -3.26 AD24 DDR4_FPGA_DQ2 273.72 -35.02 -5.54 AF22 DDR4_FPGA_DQ3 273.98 -34.76 -5.50 AE22 DDR4_FPGA_DQ4 279.49 -29.25 -4.63 AG21 DDR4_FPGA_DQ5 290.53 -18.21 -2.88 AG22 DDR4_FPGA_DQ6 278.01 -30.73 -4.86 AE21 DDR4_FPGA_DQ7 275.91 -32.84 -5.20 After one round and now at Trc_501 we have: AE23 DDR4_FPGA_DQS0_DIR 307.81 -0.93 -0.15 AD23 DDR4_FPGA_DQS0_CMP 308.74 0.00 0.00 AD21 DDR4_FPGA_DM0_B 300.56 -8.18 -1.29 AF23 DDR4_FPGA_DQ0 299.73 -9.01 -1.43 AD25 DDR4_FPGA_DQ1 302.07 -6.67 -1.06 AD24 DDR4_FPGA_DQ2 289.02 -19.73 -3.12 AF22 DDR4_FPGA_DQ3 289.91 -18.83 -2.98 AE22 DDR4_FPGA_DQ4 293.59 -15.15 -2.40 AG21 DDR4_FPGA_DQ5 294.76 -13.98 -2.21 AG22 DDR4_FPGA_DQ6 284.77 -23.97 -3.79 AE21 DDR4_FPGA_DQ7 288.48 -20.26 -3.21 Sequence for generating the Memory Delay Error Report currently is: - in Layout Report --> Traces --> Net_Length and write this to a rational file like .../Memory_Delay_Data_Prep/trace_length_report_11feb25.txt - working in .../Memory_Delay_Data_Prep/ cp trace_length_report_11feb25.txt trace_length_input_file.txt ./extract_fpga_ddr4_trace_lengths.sh this makes a new mem_fpga_2d_trace_lengths.txt cp the mem_fpga_2d_trace_lengths.txt to .../Memory_Delay_Analysis - now working in .../Memory_Delay_Analysis use the new mem_fpga_2d_trace_lengths.txt with the existing: aux_fpga_memory_routing_data.txt and package_delays_all_columns_bank_0.txt and generate a new Delay Error Report using mem_time_full_prog.exe study this programs report output file Note that you should only need to change the aux_fpga_memory_routing_data.txt file if you make a major change to a trace routing, e.g. change the pcb layer that it is routed on. Just adding a serpentine to an existing trace or re-routing an existing trace on its current layer does NOT require and edit to the aux routing data file. ----------------------------------------------------------------- DATE: 10-Feb-2025 Topic(s): DDR4 Trace Analysis, BOM and Comps Description files New BOM and Comps Description files, with out the 15 and 30 mOhm 4-wire resistors are now on the web in the Production Release area. Work on the Aux Routing Data for the FPGA Memory and on verifying the program, e.g. verifying the loop start & stop points and using know test data to check results. Example of the current output for the FPGA Memory looking at its 4 Data Buses. The best estimate from the various datasheets is that for the 625 psec Unit Interval for these data buses that either the Memory Controller or the Memory Chips should provide stable data for at least 290 psec. What fraction of the 290 nsec should be give up to un-equal trace delays ? Average CA Bus Delay = 375.08 psec Average D0-D7 Bus Delay = 283.58 psec Average D8-D15 Bus Delay = 281.11 psec Average D16-D23 Bus Delay = 407.16 psec Average D24-D31 Bus Delay = 365.10 psec Pin Net Delay Error Error Number Name psec psec mm AE23 DDR4_FPGA_DQS0_DIR 304.71 21.13 3.41 AD23 DDR4_FPGA_DQS0_CMP 308.74 25.16 4.06 AD21 DDR4_FPGA_DM0_B 296.89 13.31 2.11 AF23 DDR4_FPGA_DQ0 295.56 11.97 1.89 AD25 DDR4_FPGA_DQ1 288.17 4.58 0.73 AD24 DDR4_FPGA_DQ2 273.72 -9.86 -1.56 AF22 DDR4_FPGA_DQ3 273.98 -9.60 -1.52 AE22 DDR4_FPGA_DQ4 279.49 -4.09 -0.65 AG21 DDR4_FPGA_DQ5 290.53 6.95 1.10 AG22 DDR4_FPGA_DQ6 278.01 -5.57 -0.88 AE21 DDR4_FPGA_DQ7 275.91 -7.68 -1.21 AH22 DDR4_FPGA_DQS1_DIR 295.57 14.46 2.34 AH21 DDR4_FPGA_DQS1_CMP 292.10 10.99 1.78 AJ21 DDR4_FPGA_DM1_B 323.98 42.87 6.78 AJ23 DDR4_FPGA_DQ8 305.05 23.94 3.79 AK23 DDR4_FPGA_DQ9 264.10 -17.01 -2.69 AK22 DDR4_FPGA_DQ10 249.85 -31.26 -4.95 AJ19 DDR4_FPGA_DQ11 253.49 -27.62 -4.37 AH19 DDR4_FPGA_DQ12 313.75 32.64 5.16 AJ20 DDR4_FPGA_DQ13 295.98 14.87 2.35 AK20 DDR4_FPGA_DQ14 256.14 -24.97 -3.95 AK21 DDR4_FPGA_DQ15 267.66 -13.45 -2.13 AN22 DDR4_FPGA_DQS2_DIR 401.32 -5.84 -0.94 AM22 DDR4_FPGA_DQS2_CMP 409.23 2.07 0.33 AM21 DDR4_FPGA_DM2_B 382.89 -24.27 -3.84 AN24 DDR4_FPGA_DQ16 418.26 11.10 1.76 AP24 DDR4_FPGA_DQ17 393.76 -13.40 -2.12 AL23 DDR4_FPGA_DQ18 400.72 -6.44 -1.02 AL22 DDR4_FPGA_DQ19 414.18 7.03 1.11 AN23 DDR4_FPGA_DQ20 415.51 8.35 1.32 AP23 DDR4_FPGA_DQ21 403.66 -3.50 -0.55 AP21 DDR4_FPGA_DQ22 417.28 10.12 1.60 AP20 DDR4_FPGA_DQ23 418.15 11.00 1.74 AN18 DDR4_FPGA_DQS3_DIR 361.56 -3.54 -0.57 AP18 DDR4_FPGA_DQS3_CMP 343.42 -21.68 -3.50 AL17 DDR4_FPGA_DM3_B 396.42 31.32 4.96 AM20 DDR4_FPGA_DQ24 360.69 -4.41 -0.70 AL20 DDR4_FPGA_DQ25 343.54 -21.56 -3.41 AP19 DDR4_FPGA_DQ26 331.36 -33.74 -5.34 AN19 DDR4_FPGA_DQ27 345.05 -20.06 -3.17 AM19 DDR4_FPGA_DQ28 370.37 5.27 0.83 AL19 DDR4_FPGA_DQ29 388.04 22.94 3.63 AN17 DDR4_FPGA_DQ30 373.03 7.93 1.26 AM17 DDR4_FPGA_DQ31 377.42 12.31 1.95 Holding the delay errors to +- 5% of the 290 psec UI (+- 14.5 psec) will require a trace length match on the order of 2.3 mm. The full details of what is being calculated and how it is being calculated are in the introduction.c program section. All of this depends on a somewhat detailed understanding of the pcb stackup. I'm currently studying solutions to the most obvious problems, executive summary: D0:D7 OK but Strobe is long by about 2mm D8:D15 DM1_B, DQ8, DQ12 are long DQ9, DQ10, DQ11, DQ14 are short D16:D23 DM2_B is short by about 2mm all else is OK D24:D31 DM3_B, DQ29 are long DQS3_CMP, DQ25, DQ26, DQ27 are short Recal: the average delay in a Bus Group is based on the "data type" signals in that Bus Group - specifically excluding the Clock/Strobe. I.E. tighten up the data type signals then adjust the Clock/Strobe to match their average. The current worst values are +42 psec and -33 psec which imply about a 74% horizontally open window. Try to fix the long paths first. ----------------------------------------------------------------- DATE: 9-Feb-2025 Topic(s): DDR4 Trace Analysis Work on the analysis program - getting the Group Average Lengths for the Data Type signals in each of the 5 groups. Work on the Aux Routing Data file for the FPGA Memory, extracting the routing layer (via lengths) and the Fraction on a Surface Layer data. ----------------------------------------------------------------- DATE: 8-Feb-2025 Topic(s): Merge Sierra's Silk file and Comps file back into the "official file set on moto, Remove the 15 & 30 mOhm 4-wire, ToDo layout work list Sierra's Silk file and Comps file build without error on moto_too office but have drifted far apart from the file set on real moto. I need to merge her Comps file with all of the changes that I have made to the design on real moto, verify everything on real moto, and then put a copy of the "official" design back onto her moto_too so that it is ready for her on Monday. The most recent previous merge of out independent work was on 25-Jan-2025. Reacll that I have kept a list of the required changes to her Comps file in sierra_comps_edits_required.txt There are about 54 hand edits for moves and additions that need to go in without any typos. Once that is done I then need to make the Comps changes to remove the 15 and 30 mOhm 4-wire current sense resistors. Starting status on real moto Counts with all Fills OUT - All Ver are from real moto comps is edited --------- --------------- 1737 Comps 1465 Nets 4 UnConnected Pins 46 Shapes in pcb geom 4827 Conn 4124 Finished 170 Un-Finished 533 Guides Geom_Ver 516 Comps_Ver 1102 Nets_Ver 681 Trc_Ver 499 Tech 1422 The files brought over from Sierra's moto-too work are: comps.comps_1109 comps.comps_1109_eob_5feb25 disco_pcb_sierra_silkscreen.txt_eob_5feb25 disco_pcb_sierra_silkscreen.txt_mid_8feb25 Verify that the trasfer contents are OK then: mv disco_pcb_sierra_silkscreen.txt_eob_5feb25 to the real DK pcb geom directory on real moto, replace the existing sierra_silkscreen file, and build the DK pcb geom, and replace it in the Library, and verify that there are no errors. mv comps.comps_1109 to comps.comps_1109_sierra (still in the working directory) verify it again against comps.comps_1109_eob_5feb25 then start the hand edit of the about 54 items in: sierra_comps_edits_required.txt In the official ../pcb/ directory mv comps.comps_1102 comps.comps_1102_old Finally mv ../working/comps.comps_1109_sierra .../pcb/comps.comps_1102 Diff .../pcb/comps.comps_1102 with the pre_edit .../working/comps.comps_1109_sierra and see the expected. Now verify that the CAD system like it Counts with all Fills OUT - All Ver are from real moto comps is edited --------- --------------- 1737 Comps 1465 Nets 4 UnConnected Pins 46 Shapes in pcb geom 4827 Conn 4124 Finished 170 Un-Finished 533 Guides Geom_Ver 517 Comps_Ver 1102 Nets_Ver 681 Trc_Ver 499 Tech 1422 This looks OK - so I think that the merge of the silkscreen work and my layout work is complete. Now must remove/change the 15 and 30 mOhm 4-wire resistors - specifically: R1731 for DCDC2 the 1V05 Converter moves from 15 mOhm to 20 mOhm R1821 for DCDC5 the 2V5 Converter moves from 30 mOhm to 25 mOhm Make these changes and verify that the counts are as just above - OK. ---> I still need to run a new BOM and edit the Comps Descriptions file. Change some directory organization in the DK Work directory area: mv Memory_FPGA_Delay_Analysis Memory_Delay_Data_Prep Memory_Delay_Data_Prep holds the data prep for both FPGA and CPU memory create Memory_Delay_Analysis and dump into it the .tar from prospero the delay analysis program is about ready to use Started a dk_release_proceedures.txt in ../Text/ because currently the instructions for how do do some of this stuff (e.g. generate a BOM, or make Plots) is spread all over this log file, e.g. 28-Jan-2025 and 24-Jan-2025 I think that everything has been written out it just needs to be collected in one place. Recall what else is still missing from my layout work: - Fuse_SMD_2A Geom needs to be modified so it could also hold a PTC 0805 or 1206 comp - The East edge of the East Column of all PMT ADC Fills needs to move 0.2 or 0.3 mm further East - see 28-Jan-2025 - I need another serious look at the PMT input pairs - currently all pairs are on L9-L10 - but for isolation we probably want every other pair on L3-L4. - Official decision that I want to at least try of implement a weave avoidance slant to the vertical sections of the 13 GHz High-Speed Diff Pairs, see 31-Jan-2025 - I have not yet done DRC runs where I tighten the screws. - Still an open question about DDR4 trace delay match errors and if there is a significant problem how long will it take to fix it. - Put the required Thermal Apertures back into the Ground Plane Plots. ----------------------------------------------------------------- DATE: 5:7-Feb-2025 Topic(s): Work on DDR4 delay analysis code - it's getting very close to providing useful output, added correct suffix to 74LVC part numbers, Drop the 15 and 30 mOhm 4-Wire Current Sense Resistors, work some with Sierra on Silkscreen, Notes with Hughes: Solder Mask will be Red, 42 is the correct number of bare boards, bare boards and assembly will both be in one go. ----------------------------------------------------------------- DATE: 3,4-Feb-2025 Topic(s): Almost 100% swamped with non DK work ----------------------------------------------------------------- DATE: 2-Feb-2025 Topic(s): Work on DDR4 Trace Checks Work on getting the DDR4 as currently routed trace data and the FPGA Package Delay data ready to combine into one overall DDR4 signal delay analysis. This goes OK but takes time to pull all of the data together. I'm doing both FPGA and CPU where it is clear what to do. Where it is not so clear I'm pushing on just the FPGA Memory section. The data so far includes: 2D routed trace length, normal escape via and come back to top surface via length, where an addional via is used it length, estimated pcb propigation delays psec/mm for: surface layers, internal layers, and vias, and the Package Table propigation Delays to the BGA pins in Banks #0 and #6. All lengths are in mm and all delays are in psec. Must work out each signal's overall delay time in psec (because of the various Propigation Velocities along it route) and then convert to an error expressed in terms of a route length error in mm for a layer where it is possible to make an adjustment. ----------------------------------------------------------------- DATE: 31-Jan-2025 Topic(s): To Do lists - I must get the DDR4 trace analysis pushed along. This has to be #1 task as I still have not yet proven that it is currently good enough and we know everyting that we are going to know for now about stackup. Nothing more will be known until we give the OK. - I have decided that it's worth the effort to worry about veave effect in the 13 GHz differentail pairs - just in their long vertical section. So to take this off the table I will look at trying to implement a "standard" 10 deg slant. An issue is that I do not know what Weave Construction code the top laminate will have until we OK the stackup - so to isolate the design from a non-optimal top wave I will look at implementing a 10 deg slant. The "long" vertical run is about 17.0 mm max --> about 3.0 mm slant. The longest continuous horizontal run is about 6.5 mm do this whole and possiblely non-issue is dominated by the vertical run. - I need to dig into the 4 wire resistor and 74LVC part number issue and have answers on Monday. Make a script in the .../Generate_Gerbers/ directory to re-name all 20 Gerber files in the ....mfg/ directory so that the new filename is the same as before but includes a ".grb" suffix. The .grb suffix is for the Production Build files that will be released to Hughes. They preferre a .grb filename suffex. Note that the mentor Gerber Viewer will not automatically pick up the files once the .grb suffex is added to their filename. Edit the Gerber Generation calling script to add better separation in the screen outut of the individual calls. --> I need to plow Sierra's Ref Desig work back into the main line file set before she works again. Fills have been dropped and all Trc with Fills deleted and all Gerber and Drill files deleted (except on the web) Counts with all Fills OUT - All Ver are from real moto comps is edited --------- 1737 Comps 1465 Nets 4 UnConnected Pins 46 Shapes in pcb geom 4827 Conn 4124 Finished 170 Un-Finished 533 Guides Geom_Ver 516 Comps_Ver 1102 Nets_Ver 681 Trc_Ver 499 Tech 1422 ----------------------------------------------------------------- DATE: 30-Jan-2025 Topic(s): Hughes meeting Notes from Hughes meeting transcribed in random order: - Chris is going to get us a price for a domistic build of the pcb so that we can compare it to the price on the RFQ from Fall 2024 and make up our own minds about what we want to do. His off shore board house and his domistic board house (near Chicago) are the same wrt: quality, working and understanding what we want and giving us feedback, and on being around over the expected duration of the DK builds. - The plugged vias will be done by a different (newer) method on the DK board than we have done previously. I should start calling them Resin Filled Vias. This new type of plugging is the same as the initial steps of making Via-in-Pad boards duh they have combined both goals into one process. In the BGAs I can 100% cover the Dog-Bone Vias with Solder Mask. For the QFNs I 100% relieve Solder Mask over the whole center thermal pad and can 100% cover on the back side. Recall: All BGAs and all QFNs on the DK are Top side mount so that keeps things simple and I need to remember that the cap_0402_thd is providing Vias in the BGAs and thus must be handled like a BGA dog-bone via. - Mounting Screws for connectors - yes they would like to have them and they will optionally install them before doing the Selective Soldering of the connector THD pins. The issue is how close is this mounting hardware to the connector pins and it looks like there is room to install first and then do the Selective Solder. Points: It may be easiest just to let Hughes install SS metal screws on both sides of the J1 Main Cable connector and then we replace the hot one with Nylon in house In any case I need to either: find vibration proof nuts or screws or plan on super gluing all of these screws. - Yes they can handle the PEM screw blocks - I left one of the big polypropylene capacitors with Chris and he will verify that their normal assembly glue will stick to its case. I need to send to Chris the part number of the 3M glue that I used. - Yes Hughes can store left over parts between builds in controlled conditions. They do that for other of customers. - The Feeder counts look OK so far for a single pass through pick and place. - Our SMD X,Y data format is OK for them it ingest into their pick and place programming system. - He prefers Thermal Apatures on the THD pin vias that connect to power & Gnd planes - especially where even heating/cooling of the area could be a problem. Note that in general it is both the Heating and the Cooling that must both be kept in balance and the various pins on a device. If one end cools too much faster - then the part pulls in that direction and the trouble starts. Thus I must put some of the Thermal Apatures back into the 4 Gnd Plane Plots. - They can use Kaptan tape pre-cut circles to provide the insulation that I'm worried about over the leads that go under the Input DCDC converter mdoule. I must put in Silscreen where I want these installed. They come in rational sizes e.g 3/8" 1/2" ... - They want the inventory stuff in spread sheet data format and it would be nice if we could make 3 versions: - Overall DK BOM and Component Descriptions - Top side SMD only BOM - Bottom side SMD only BOM These top / bottom SMD only BOMs help in checking the pick and place programming. It may take a couple of trys to get the format 100% they way that works best for them - so we sould make an early Draft test - Besides the individual files to look at on the web he wants an all in one zip file - He wants a .grb file name extension added to the 20 Gerber files. - He will check on the BGA under fill to learn is serious people are using it. So far he has not seen it in the auto proto-type stuff. - He has not seen it but thinks that relieving the Solder Mask over the 13 GHz traces is OK wrt bare board manufacture and assembly. - From his view the Isola FR408HR is a normal rational material to use for this kind of a build. Yes - the Draft stackup drawing is OK / helpfull to get things starting with the bare board house. The specified 80 to 85 mil thinkness is OK and for assembly reasons he prefers this range of thickness for this size board. He will specify break off rails perferated with drills - so I we want absolute edge smoothness then they (or we) could sand the edge. - Everything looks right for our size DK build and it is relatively easy and fast to get to Hughes. ----------------------------------------------------------------- DATE: 29-Jan-2025 Topic(s): Work to get ready for Hughes meeting In the Component Descriptions file there are: 17 types of Capacitors 10 types of Connectors 11 types of Inductors 9 types of Power Supply Components 41 types of Resistors + 37 types of Semiconductors ------- 125 and this 125 matches the component type counts in other DK board documents Of these 125 items listed in the Component Descriptions file 116 of them are marked as SMD and 9 are marked as Through Hole. 116 SMD and 9 THD matches the other DK component files. 16/17 Caps are SMD, 5/10 Connectors are SMD. 11/11 Inductors are SMD 6/9 PS Comps are SMD, 41/41 Resistors SMD, 37/37 Semicond are SMD Brayden, Nathan, and I had a quick meeting about the parts orders and the other work required to get the assembly kit put together. So far the 4 terminal resistors from Ohmite and not easily available and the 74LVC stuff seems to have a different suffix than what I put in the Comps Description file. I'm responsible for figureing out what to do about the 4 terminal resistors and Brayden is going to send me the full part number of the proposed 74LVC parts and I need to confirm that they are OK or not. Dropped Fills and now correctly routed the CNST-3V3 to U1151-6. This is now Trc_499. All Fills should now complete. ----------------------------------------------------------------- DATE: 28-Jan-2025 Topic(s): More clean up, build the design, Finish the clean up in the Iso-RS-485 and re-do its Ground Slit boarder. This involved moving some components in the Iso-485 and in the Power Input Filter. Add more Ground Rivets in the PMT Analog Input section. A big concern is the channel to channel isolation. That was OK on the AD demo board but things are a lot more crowded on the DK and they are intermixed, e.g. single-ended inputs run adjacent to diff feeds to the ADC. The demo brd is 100% radial. How good does the channel-channel isolation need to be for Physics ? Currently this does not really look like 100 MHz 12 bit stuff. There is now a ton of edits that need to go into Sierra's Comps file to make it useable in the real design. All details are in .../Text/sierra_comps_edits_required.txt Start work to make a full build - everything except a new BOM. Recovery is to traces_489_pre_fill_gen Counts with all Fills OUT - All Ver are from real moto comps is edited --------- 1737 Comps 1465 Nets 4 UnConnected Pins 46 Shapes in pcb geom 4828 Conn 4125 Finished 170 Un-Finished 533 Guides Geom_Ver 516 Comps_Ver 1102 Nets_Ver 681 Trc_Ver 489 Tech 1412 No errors when running the Fill Generation script - "normal" 15/5 Fracture Counts with all Fills IN - All Ver are from real moto --------- 1737 Comps 1465 Nets 4 UnConnected Pins 46 Shapes in pcb geom 4397 Conn 4396 Finished 0 Un-Finished 1 Guide after merge: 33 shapes and 33 Fills Geom_Ver 516 Comps_Ver 1102 Nets_Ver 681 Trc_Ver 498 Tech 1421 Issues with the Fills: - Again U1151 pin #6 failed to connect. There was a via sitting there waiting to connect but something in the process blows the via out and leaves it with an SLI. I will pull out all associated routing and try again next time. Ah - the via is too close to the CNST_3V3 boarder. The via must be put back immediately North of the pin #6 pad. this will be only 5.0 mm of HV clearance. - The new Gnd Rivets in the PMT Analog Input section are right near the East boarder of the East Column of PMT ADC Fills. All of these Fills: Sig_11 ADC_ANALOG_1V0, Sig_11 ADC_ANALOG_1V8 Sig_12 ADC_ANALOG_1V0, Sig_12 ADC_ANALOG_1V8 moving 0.2 or 0.3 mm will be OK. Run the script to Generate Gerbers even with these two problems listed above. There were no errors and no missing apertures but: artwork_16_solder_mask_top artwork_17_solder_mask_bot shows Note: The objects with the following sizes will be painted Height(Y) Shape Type Diameter Width(X) Orientation Mirror Power circle flash 3.000000 0.000000 0 false false Why is it all fired up about painting this aperture ? Also note that: qfn_48_thd_pin_56sq, vson_10_thd_pin, HVSSOP_thd_pin, qfn_24_thd_pin_27sq are Not defined on SOLDER_MASK_2 and sould be as they are pluged from the top. Run the script to remove the Thermal Apertures from the Ground Planes. Run the script to Generate Drill data - log shows no missing drill sizes. Now generate a fresh set of SMD data: working in the .../Tools/ directory - by hand copy metor land active comps to .../Tools/dk_smd_mentor_comps_copy.txt This will be an interesting test of the scripts as this mentor land comps file was written by layout and then hand edited to add rivets. - In Tools ./dk_smd_1_mentor_to_script_format.sh This makes dk_smd_input_to_smd_xy_gen.txt - In Tools ./dk_smd_2_installed_comps_files.sh This makes the temporary Top and Bottom side files: _comps_all_data.txt _comps_list.txt _comps_types.txt _usage_counts.txt and this step provides on screen the Count of Types and the total Count of Placements per side. - In Tools ./dk_smd_3_generate_xy_data.sh This makes the temporary Top and Bottom side files: _smd_xy_place_data.txt - Finally by hand copy, rename, and add the canned headers to the appropriate files into their place in the Release Directory. e.g. mv ../Tools/temp_smd_top_side_usage_counts.txt ./dk_smd_component_counts_top.txt mv ../Tools/temp_top_smd_xy_place_data.txt ./dk_smd_xy_data_top.txt Work on the Assembly and Bar Board Instruction files. There are still open questions about both of these steps to be answered at the Hughes design review meeting. ----------------------------------------------------------------- DATE: 27-Jan-2025 Topic(s): Yet more clean up, PMT Analog work Hughes meeting scheduled Dump the Fills from yesterday, mv C1011 South 0.2 mm, mv Iso RS Gnd South 0.2 mm, mv USB Reset North, add the missing via to U, look at mv FPGA East Channel reset West, pull out the rest of the high current duplicate routing. Verify counts. Things are now stable so pass the full file set back to Sierra. In the PMT Analog Input section: Swap the L3 and L10 differential traces that feed from the Analog Input Circuits to the PMT ADC Inputs because I can get better isolation for the odd numbered channels this way. Drop the 0.6 mm stubs on the Term Resistor pads for 0.4 mm stubs as that is big enough and has a smaller capacitance bump. Add Ground Rivets VR161...VR168, VR171...VD178, VR181...VD188, VR192...VD198, with one rivet adjacent to each transformer primary hot side feed, i.e. a current return Gnd Via and better isolation between the Hot Trans feed and the closest diff signal pair. These Ground Rivets must be added to Sierra's Comps file when it comes back to real moto. Trace clean up of the long runs for USB: power, power control and Data from the SW corner to the NW corner. This makes better use of the space available and better isolation. There is another clean up that I can do in the ISO-RS-485 section. C1006 can more about 1.0 mm West. That will tighten up the Vcc bypass on the Iso RS-485 transceiver but more important it will allow a smoother Ground Slit at the NE corner of the Iso-RS-485 section. Note: I will need to add today's Ground Rivets to Sierra's Comps ----- file and I will have to hand edit the move of C1006 West. Ran DRC with the default rules and it is now 100% clean except for duplicate routing from the Current Shunt Resistors to the 6x DCDC Converter inputs, i.e. a non-issue. Current DRC results are in: .../Text/drc_report_temp.txt - much cleaner than this weekend. Counts with all Fills OUT - All Ver are from real moto comps is edited --------- 1718 Comps 1465 Nets 4 UnConnected Pins 46 Shapes in pcb geom 4829 Conn 4126 Finished 170 Un-Finished 533 Guides Geom_Ver 514 Comps_Ver 1100 Nets_Ver 680 Trc_Ver 487 Tech 1410 Hughes meeting is this Thursday Jan 30th at 1:30 PM. ----------------------------------------------------------------- DATE: 26-Jan-2025 Topic(s): More HV Clearance work, Work on DRC problems, run a new set of Fills, Gerbers, and new Drills Last night on moto durand I started some runs of DRC. It found a couple of (3) fatal errors unders the FPGA, all easy to fix, and some not unexpected duplicate routing in the "high" current fanouts. All easy to fix. I have not started the serious DRC studies to verify that things are uniform. Fix the above and do more HV Clearance work and look at a single run of DRC again and see just the semi expected duplicate routing in the high current fanouts (this is just a single DRC look still not yet a serious study). Now want to run: Fills, Gerbers, Remove Thermals, and Generate SMD X,Y data, Generate Drills just to verify that nothing is broken in the design. Counts with all Fills OUT - All Ver are from real moto --------- 1687 Comps 1465 Nets 4 UnConnected Pins 46 Shapes in pcb geom 4830 Conn 4127 Finished 170 Un-Finished 533 Guides Geom_Ver 514 Comps_Ver 1099 Nets_Ver 678 Trc_Ver 472 Tech 1395 See the "normal" 15, 5 Fracture in the Fill Gen but no errors. Now at: Counts with all Fills IN - All Ver are from real moto --------- 1687 Comps 1465 Nets 4 UnConnected Pins 46 Shapes in pcb geom 4399 Conn 4398 Finished 0 Un-Finished 1 Guides <--- after merge 33 Shapes and 33 Fills Geom_Ver 514 Comps_Ver 1099 Nets_Ver 678 Trc_Ver 481 Tech 1404 So as expected I had broken a route - I'm missing via on U1151-6 move forward without it. Generate Gerbers - The logs have No Error and No Missing Apertures but - artwork_16_solder_mask_top and/or artwork_17_solder_mask_bot show that something is going to be "Painted". This is a new warning and basically should not be there (but it is probably OK) but I do need to dig out what is going on. Remove ALL Thermal Apertures from Gnd Plane plots. Recall this in in .../Tools/ Just have time for a warp speed look at Plots. Generate new Drill data --- No missing drill tool sizes. Run out of time to make new SMD placement data. ----------------------------------------------------------------- DATE: 25-Jan-2025 Topic(s): Merge Sierra's Silkscreen work into real moto file set Bring the comps file and the sierra_silkscreen file from Sierra's moto_too machine to real moto and merge into her comps file the new X,Y coordinates for the Memory Rivets that I moved yeasterday. Moved the sierra_silkscreen file into the .../Geometries/Design_Disco_PCB/ directory and rebuilt the DK pcb geom. Verified no librarian errors. Burn an hour doing all of this before starting real work. To check: Verified the transfers and verified that no counts changed. Counts with all Fills OUT - All Ver are from real moto --------- 1687 Comps 1465 Nets 4 UnConnected Pins 46 Shapes in pcb geom 4832 Conn 4129 Finished 171 Un-Finished 532 Guides Geom_Ver 513 Comps_Ver 1097 Nets_Ver 678 Trc_Ver 469 Tech 1392 Must move a complete DK file set to Sierra's moto_too before she starts work next week. Now finish FPGA memory clean up on L4 and then finally move the CONST_3V3 and Barnacle_Reset_B components so that I get the clearances that I want around the polupropylene cap terminals. Dig around for more clearance around the rest of the Power Input Filter. Move more comps and traces to try to gain a little clearance. End at: Counts with all Fills OUT - All Ver are from real moto --------- 1687 Comps 1465 Nets 4 UnConnected Pins 46 Shapes in pcb geom 4833 Conn 4130 Finished 170 Un-Finished 533 Guides Geom_Ver 514 Comps_Ver 1098 Nets_Ver 678 Trc_Ver 471 Tech 1394 So I've changed something but that was not expected: now I have 1 more connection in the design, 1 more Finished trace, 1 less Un-Finished trace, and 1 more Guide - a strange conbination when you were expecting no changes at all. ----------------------------------------------------------------- DATE: 24-Jan-2025 Topic(s): BOM and Jumpers files, How to make BOM, FPGA Memory clean up work Make a new BOM and edit the Jumpers Description file to pick up the new JMP1 A & B from yesterday that control connecting the DK's Ground Planes to Mounting Screw Holes. For now, for assembly purposes, we will install JMP1B for the Center-East mounting screw hole and not install JMP1A for the NE mounting screw hole. Recall how to make a new BOM: 1. Remane the actual current active Mentor comps_ver to comps_ver_orig_real - and don't loose this file. 2. Copy comps_ver_orig_real to .../Work/Tools/temp_1_file.txt 3. Run .../Work/Tools/dk_bom_1_make_comps_file_for_bom.sh 4. mv .../Work/Tools/temp_comps_file.txt to Mentor directory comps_ver i.e. make the temp_comps_file.txt the active Mentor comps_ver file 5. Run .../Work/Tools/dk_bom_2_generate_bill_of_materials.sh Note this step makes a new: bill_of_materials_cleaned_current.txt file in the .../Text/ directory. If you want to keep a copy of the previous version of the BOM, e.g. to make a diff, you need to have renamed it or something to save it. 6. Run .../Work/Tools/dk_bom_3_clean_up_bom_file.sh Note this step makes a new: bill_of_materials_cleaned_current.txt file in the .../Text/ directory. If you want to keep a copy of the previous version of the BOM, e.g. to make a diff, you need to have renamed it or something to save it. 7. In the Mentor directory restore the original real comps file: i.e. delete comps_ver and mv comps_ver_orig_real to comps_ver Note: Don't forget this 7th step or you will be left with a broken design. Major clean up session in the FPGA memory section working to get wider Gnd Webs and to make best use of the available space wrt trace separation and minimum trace length. I want this as clean as possible before doing the DDR4 trace length analysis and matching. Doing this work involved moving some Memory Rivets, specifically MR 1 through 8 and MRs 21, 22, 23 and maybe MR20. The issue is that Sierra was editing Ref Desig at the same time so now her comps file and mine on real mote have drifted apart again and will need to be spliced back together. Copies of her latest work are in .../Trace_Work/ on real moto which is otherwise unused. The FPGA memory section is now almost as clean as the CPU memory. Still can do a little more cleanup on L4. Counts with all Fills OUT - All Ver are from real moto --------- 1687 Comps 1465 Nets 4 UnConnected Pins 46 Shapes in pcb geom 4832 Conn 4129 Finished 171 Un-Finished 532 Guides Geom_Ver 513 Comps_Ver 1097 Nets_Ver 678 Trc_Ver 469 Tech 1392 As expected no count changes. ----------------------------------------------------------------- DATE: 23-Jan-2025 Topic(s): Silkscreen work, Clean up details Sierra works on the Reference Designators and on the silk lines and such to make it unambiguous what part is what. Work starts with the full DK file set on moto_too being the same as on real moto. I finished all of the details with making the "hot" mounting screw on the J1 connector have smaller pads and wiring up the JMP1 A & B for connecting 1 or 2 Board Mounting Screw Holes to the DK Ground Planes. Counts with all Fills OUT - All Ver are from real moto 1687 Comps 1465 Nets 4 UnConnected Pins 46 Shapes in pcb geom 4832 Conn 4129 Finished 171 Un-Finished 532 Guides Geom_Ver 513 Comps_Ver 1096 Nets_Ver 678 Trc_Ver 468 Tech 1391 Remaining major tasks: DRC Runs and Verify DDR4 Trace Lengths ----------------------------------------------------------------- DATE: 22-Jan-2025 Topic(s): Note to Christian Interface & MacArtney Ground Jumpers, J1 Pad, Rivets, R921 Sierra Ref Desig - Comps work merge Finally add the Ground Jumpers JMP1A and JMP1B that allow the Ground Planes within the DK board to be electrically connected to one of its Mounting Screws and thus to the Module Frame & sea water. JMP1A is in the NE corner - JMP1A ties the Ground Planes to the North-East Mounting Screw JMP1B is between the two PMT Analog Signal Input Connectors JMP1B ties the Ground Planes to the Center-East Mounting Screw I'm note sure which Grounded Mounting Screw option we may want to use - that's why I provided 2 options. One option flows any Ground Current through the PMT Analog Section but ties the Ground Plane in that section to the Frame. The other options leaves the PMT Analog section without the flow of Ground Currents but sets the Frame Ground to the potential of another point on the DK board's Ground Plane. Need to make a geom for an "electrical" mounting screw hole. Need to make a much smaller mounting screw pad diameter at the Pin #1 end of the 3M 16 pin J1 Main Cable connector. Moved the R921 Differential Terminator on the Timing SFP signals going into the REFB input to the Timing Generator both to get the terminator closer to the TG chip and to allow some cleaner routing South of the TG chip. Dump all of the Gerber Plots and Drill Files and the with Fills Trc file. For part of the day I worked editing the layout, specifically moving and adding some comps. This was done starting from Sierra's most recent Ref Design comps file form the 17th. She arrived and worked on the Reference Designators so the designs on the two machines drifted apart. To merge things back together I started with Sierra's comps_1097_sierra_cob_22jan25 from moto_too and modified it to have X,Y data from the layout work on real moto for the following components: C311, C312, C341, C342, C412, C438, C439, C440, C442, C452, MEM_RIV_58, MEM_RIV_59, MEM_RIV_60, MEM_RIV_61, R921 And I added one more more rivet and two more Jumpers: VR133, JMP1A, JMP1B Counts on Moto before the merge: Counts with all Fills OUT - All Ver are from real moto - Before Merge 1685 Comps 1463 Nets 6 UnConnected Pins 46 Shapes in pcb geom 4830 Conn 4125 Finished 171 Un-Finished 534 Guides Geom_Ver 507 Comps_Ver 1096 Nets_Ver 677 Trc_Ver 467 Tech 1390 cp /home2/designs/boards/Disco/Work/Traces_Work/comps.comps_1097_sierra_cob_22jan25_edited ./comps.comps_1096 Counts with all Fills OUT - All Ver are from real moto - Merged with Sierra current Ref Desigs 1685 Comps 1463 Nets 6 UnConnected Pins 46 Shapes in pcb geom 4830 Conn 4125 Finished 171 Un-Finished 534 Guides Geom_Ver 507 Comps_Ver 1096 Nets_Ver 677 Trc_Ver 467 Tech 1390 So the merge looks OK so far. Verify that things are OK then copy the whole DK file set from real moto to moto_too so that Sierra will be working from the 100% current real setup. ----------------------------------------------------------------- DATE: 21-Jan-2025 Topic(s): Fix drawings, Note to Christian Fix Drawings: 2, 70, and 81 Note to Christian about Main Cable Interface Control Document. Meeting with Nathan about the design checks. ----------------------------------------------------------------- DATE: 20-Jan-2025 Topic(s): All work was on the Stackup and Zo ----------------------------------------------------------------- DATE: 19-Jan-2025 Topic(s): Work on the Bare Board Manufacturing and Board Assembly Instructions Work to make these 2 document match the current design. They are almost ready. I think that we then will have a full set of Draft documents on the web. The stackup stuff is in .../Components/DK_PCB/ and will move to Production Release soon. ----------------------------------------------------------------- DATE: 17-Jan-2025 Topic(s): Work on Stackup, Thermal_Apertures, uWave Traces, New Gerbers Added two warnings at the start of the Generate_All_Fills script about making certain that the Trc file pre_fill_generation is saved. The Ground Plane Thermal Aperture Removal Script is finished for now and is removing 23 of the 24 following Thermal Apertures from all 4 Graound Plane plots: L2, L5, L8, L11 Diameter Used by Geometries Aperture mm D-Code i.e. these geoms contain "Power bla xyz" diameter -------- -------- ------ ----------------------------------------------------- 165 1.18 265 Via_0mm79 167 1.0 267 Via_0mm65 168 1.6 268 Rivet_Via_1mm3 & Via_1mm1 170 1.9 270 Via_2mm2 171 3.3 271 USB Connector Mounting Pins 174 1.85 274 USB Gnd Pin Pin #4 178 5.7 278 J1 and J7 Mounting Screws only 1 on Main Cable J1 179 0.85 279 Center Thermal Vias under most QFN parts BB Audio Time Gen 180 2.8 280 Gnd Pin on DCDC20 Converter Pin #5 181 2.42 281 Ground Pins on J7 Barnacle Connector 184 1.7 284 DCDC Converter Aux Ground Pins 185 2.3 285 DCDC Converter Main Ground Pin 189 4.2 289 NOT used in any Ground Plane Plots - must verify 190 2.1 290 PEM Screw Block & SFP Cage Grounded Mounting Pins 191 1.75 291 Interposer Connector J4, J5 Ground Pins 192 0.87 292 Term Via Array and Mem_Riv Ground Pins 193 0.65 293 0.8 mm Pitch BGA Grounded Dog-Bone Pins 195 0.82 295 1.0 mm Pitch BGA Grounded Pins & Cap_0402_THD Gnd Pins 196 0.8 296 FPGA straight East-West Ground Pins, e.g. AA1, E 33&34 197 5.2 297 TOMcat Mounting Screws 198 2.0 298 SFP Cage Mounting Pins Grounded 199 3.5 299 PMT Analog Shield Grounded Mounting Screws 200 3.75 300 J2, J3 PMT Signal Input Connector Grounded Mounting Screws 201 1.35 301 J2, J3 PMT Signal Input Connector Shield Ground Pins I need to find out what DCode 289 is used for. Recall ---> Do NOT generate a new Aperture Table because doing so could cause all of this work to fall apart and there should be no need for a new Aperture Table. ---> Do NOT generate a new Drill Table because there is no current need to do so and making a new table risks loosing our current understanding of which drill is for which function. With Sierra's Silscreen work through about 14:00 Friday loaded onto real moto as Comps_1095 (Sierra's work comes from moto_too office Comps_1097) I ran a new set of Gerbers, then ran the Thermal Aperture Removal Script on them, then coppied them to the web Production_Release. I verified Sierra's comps_1097 contents and the Counts w & wo it loaded. Recall that traces.traces_466_no_fills & traces.traces_457_pre_fill are identical Trc files. With all Fills IN and the existing real moto Comps file: 1682 Comps 1463 Nets 4 UnConnected Pins 46 Shapes in pcb geom 4398 Conn 4398 Finished 0 Un-Finished 0 Guides After merging: 33 Shapes and 33 Fills Geom_Ver 507 Comps_Ver 1095 Nets_Ver 675 Trc_Ver 466 Tech 1389 With all Fills IN and a copy of Sierra's Comps_1097 from 14:00 today loaded onto real moto as Comps_1095: 1682 Comps 1463 Nets 4 UnConnected Pins 46 Shapes in pcb geom 4398 Conn 4398 Finished 0 Un-Finished 0 Guides After merging: 33 Shapes and 33 Fills Geom_Ver 507 Comps_Ver 1095 Nets_Ver 675 Trc_Ver 466 Tech 1389 All looks OK so generate the new Gerbers with one click. ./generate_dk_gerber_all_20_plots.sh I see no missing apertures or errors in the log files - so ./remove_most_ground_thermal_relief.sh Go back to the 466 Trc file WithOut Fills to make it faster to study the new Gerbers. Not a serious Gerber study yet but things look OK enough to copy to web. - I need to drop the Surface copper from the mounting screw on the Main Cable J1 connector that is at +50 Volts, i.e. the Southern one. Silkscreen has made a nice step forward. Work on stackup under separate cover. ----------------------------------------------------------------- DATE: 16-Jan-2025 Topic(s): Work on Stackup and Thermal_Apertures Thermal Aperture details are in the script in the Tools directory. Sierra working on Reference Designator Silkscreen. Another set of Geoms to Brayden. ----------------------------------------------------------------- DATE: 15-Jan-2025 Topic(s): Comps files, Drill Files, Stackup, Thermal Apertures, Repaired the Comps files so that we now have a version, comps.comps_1096_correct_geoms that has all of Sierra's work from the 14th AND the full set of correct Geometries in it. That version Comps file is now checked and running on real moto as 1095 and on Sierra's moto_too office as 1096. All content and counts checked. Reviewed the contents/function of dk_drill_generate_table_and_drill_files.sh and then ran it. Like a stump I had the Fills out when I ran it but that should not make any difference and this is still not the official final drill file set. Check the Fablink Log File: - There were no missing Drill Size during the drill file generation but - Removed duplicate hole at location (120.1, 95) need to check this ---> There are overlapping Mem_Rivs at this location: #58 and #59 Need to look at: #56 through #61 Unplated: 20 Holes Position Size Count -------- ---- ----- 9 1.00 4 # Connector Alignment PS Mon & Access (J11 & J12) 14 1.45 4 # Connector Alignment ER uProc & TOMcat (J8 & J10) 15 1.55 4 # Connector Alignment 2x SFP (J13 & J14) 20 3.20 8 # Board Mounting Holes Plated: 3799 Holes Position Size Count -------- ---- ----- 1 0.23 702 # 0.8mm Pitch BGA & Term Via Array & Via_0mm52 & Mem_Riv 2 0.30 1462 # 1mm Pitch BGA & Via_0mm65 3 0.40 716 # Via_0mm79 4 0.46 193 # PVA Vias 5 0.60 258 # Via_1mm1 6 0.70 170 # Rivet Vias & PMT Signal Connector Pins (J2 & J3) 7 0.80 42 # 6x DCDC Converter Aux Pins 8 0.90 118 # Main, Interposer, Barnacle, & USB Connector Pins # (J1, J4, J5, J7, J15, J16) 10 1.10 26 # Via_2mm2_HV & SFP Cage Mounting 11 1.20 17 # Polypropylene Cap Vias & SFP Cage Mounting 12 1.30 8 # USB Connector Mouunting Holes (J15 & J16) 13 1.40 68 # 6x DCDC Converters and PEM Screw Blocks (K1:K4) 16 1.60 6 # Input Power DCDC20 Converter 17 2.30 6 # PMT Signal Connector (J2 & J3) & Shield Mounting 18 2.70 4 # Main Cable and Barnacal Connectors (J1 & J7) 19 3.20 3 # TOMcat Mounting Should check this against the RFQ release. I do NOT want to change the Drill Table again (and should NOT need to) - so I have commented out that section of the Drill Generation script: dk_drill_generate_table_and_drill_files.sh I want a quick look at how many Thermal Apertures I need to remove from the 2 types of Ground Planes. I had previously dumped all of the Gerber plots so run just: generate_dk_gerber_2_layer_L2.sh generate_dk_gerber_11_layer_L11.sh so that I can see the two types of Gnd Planes. The current Aperture Table is ver 33 from 17-Dec-2024. That sould be recent enough that it does not need to be updated (but stay on the outlook for missing apertures). Make an Aperture Table Report to the Work Text directory. See that the "Power" Apertures are numbers: Position D-Code Position D-Code -------- -------- -------- -------- 165 265 190 290 167 267 191 291 168 268 192 292 170 270 193 293 171 271 195 295 174 274 196 296 178 278 197 297 179 279 198 298 180 280 199 299 181 281 200 300 184 284 201 301 185 285 189 289 The in the table at the top of the Aperture Table Report it lists position 189 as a "Power" aperture but then in the following set of Power Aperture Descriptions it does not include position 189 as a Power Aperture ? Artwork #2 & #5 include D-Codes: 265, 267, 268, 270, 271, 274, 278, 279, 280, 281, 284, 285, (Not 289), 290, 291, 292, 293, 295, 296, 297, 298, 299, 300, 301. I verified that Artworks #8 & #11 use the same full set of Thermal Apertures. So 23 thermal apertures to worry about in each type of Gnd Plot. I verified the operation of the Thermal Aperture removal script in the ../Work/Tools directory. That all looks straight forward. Which ones if any will Hughes want in for assembly. ----------------------------------------------------------------- DATE: 14-Jan-2025 Topic(s): SMD & X,Y Data, Release Files, Reference Designator Silk work resumes Generation of the SMD and X,Y Placement Data was broken because the scripts for generating that data assumed a Script Built Comps file as input. The fastest solution was to make an additional sed / awk script to convert the Mentor Comps file format to a Script built Comps file. So the process for generating the SMD and X,Y Placement data is now 4 steps: - copy the current active Mentor Comps file to: .../Work/Tools/dk_smd_mentor_comps_copy.txt - Then in the .../Work/Tools/ directory run: dk_smd_1_mentor_to_script_format.sh dk_smd_2_installed_comps_files.sh dk_smd_3_generate_xy_data.sh Recall that most of the non-SMD and not actually installed comps get thrown out because of their NOT_IN_BOM or NOT_A_Part properties but that the dk_smd_2_installed_comps_files.sh script has to explicitly remove some other comps that are not actual installed SMD Comps. ---> Some additional editing of the comps to be removed may be needed. These files need to be checked. Ther current SMD Placement counts are: Top: 565 placements of 87 component types Bottom: 782 placements of 52 component types Must look and see how close this is to the RFQ Release estimate. Sierra and Brayden are here to work on the silk so I fire up moto_too office edition and load onto it the 13-Jan-2025 backup. So far it is running OK. But ... Unfortunately the 13-Jan-2025 .tar backup that I loaded onto that moto_too machine had the Comps file that is just for generating the BOM file loaded and active. Thus Sierra has spent the past hour editing Silkscreen Reference Designators in a Comps file that I can NOT load directly back onto real moto and have the DK design work. When I get the Comps file back from Sierra I have have to hand edit about 40 components in that Comps file to give them back their correct Geometries. I have stored the edits that I will need to make in the file: comps_to_fix.txt Recall: BOM generation sorts on both Company Part Number AND on Geometry. Thus, if the same actual part is used with two or more different Geometies, then it will appear as two or more separate items in the BOM file. In may designs we use the same componet with two or more different geometries on purpose, e.g. the Company Part Number: Cap_100_nFd_16_V_0402 is used with the: cap_0402, cap_0402_smlr, and cap_0402_thd geometries. But we want all of these to appear as just one item in the BOM file - one line ot order all of the Cap_100_nFd_16_V_0402 on the board. This is accomplished by setting the Geometry for ALL instances of Cap_100_nFd_16_V_0402 in a special version of the Comps file to cap_0402. It is that special version of the Comps file that I passed to Sierra to edit silkscreen on. As usual, throwing people at a project at its very end does not speed things up. ----------------------------------------------------------------- DATE: 13-Jan-2025 Topic(s): Work on Release data and Hughes Review The only 10 nFd cap left in the design was C1975 - the Reference bypass for the CNST_3V3 supply. I will moved C1975 to 33 nFd. There already had to be a 33 nFd cap - specified as that value by AD for the PMT ADC C709. Change C1975 to 33 nFd in the actual design. Pull the 0402 10 nFd cap out of the components description file. Still need to edit Drawing #7 - the CNST 3V3 supply. Official decision to have the assembly house install the K1...K4 PEM screw blocks and to dump the idea of adding a M2 through board screw to the bottom of these blocks to make an even stronger mechanical connection of the Interposer Cables to the DK board. Thus the PEM Screw Blocks will be an SMD Component in the design: Need to be in the BOM to the assembly house, Need to be in the Component Description file, Need to have their Geom edited to remove the M2 screw from their foot print i.e. from the pcb and probably from a Drill File size. Pin #3, the grounded through board mounting screw that I was going to add to the PEM Screw Blocks, must also be removed from the Nets List. When I did that it let me see another clear crisp example of a change in the number of Through Hole Component Pins directly connected to a Plane or Fill without a change in the number of design "Connections" reported by Layout. That is Layout only considers a Net List connection to be a "Connection" if it requires routing in the Trc file. This all makes sense but needs to be kept in mind. Build a new BOM and put it and the new version of the Components Description file in the Production Release web site. Work on Stackup Drawing and update CNST_3V3 drawing #7. Send a list of 10 more Datasheet vs Geom to Brayden. I will need to review all of the QFN Geoms using his notes. "Released" the files: dk_bill_of_materials_assembly.txt and dk_component_descriptions_assembly.txt to Brayden and Nathan OKed for assembly parts purchase. These are now Controlled files. ----------------------------------------------------------------- DATE: 12-Jan-2025 Topic(s): Work on 99% Release Data Want to include the current draft of the PMT ADC's uwave traces in the 99% Release Data - so: Drop the Fills and implement the PMT ADC's uwave traces on real moto - Trc_447_pre_pre_fill ---> Trc_456 - verify content Counts are: Counts with all Fills OUT - All Ver are from real moto - Before uWave 1682 Comps 1463 Nets 4 UnConnected Pins 46 Shapes in pcb geom 4828 Conn 4125 Finished 171 Un-Finished 532 Guides Geom_Ver 506 Comps_Ver 1095 Nets_Ver 674 Trc_Ver 456 Tech 1379 Counts with all Fills OUT - All Ver are from real moto - Now with uWave 1682 Comps 1463 Nets 4 UnConnected Pins 46 Shapes in pcb geom 4828 Conn 4125 Finished 171 Un-Finished 532 Guides Geom_Ver 506 Comps_Ver 1095 Nets_Ver 674 Trc_Ver 457 Tech 1380 Start Fill Generation - it runs to completion wo errors - 15/5 Fractures. Trc file is _466 of 6006600 bytes. Back out to Trc_457_pre_fill. 1682 Comps 1463 Nets 4 UnConnected Pins 46 Shapes in pcb geom 4398 Conn 4398 Finished 0 Un-Finished 0 Guides After merging: 33 Shapes and 33 Fills Geom_Ver 506 Comps_Ver 1095 Nets_Ver 674 Trc_Ver 466 Tech 1389 A very quick look and nothing jumps out - so Generate Gerbers Set the Fills to the side so that it is faster to look at the new Gerbers Trc_466 ---> Trc_466_with_fills Trc_457_pre_fill ---> Trc_466 Very fast look at Gerbers: big issue is the Ground Plane Thermal relieves, also see that all plot #20 Plug Flashes are not the same size, Fills look OK. Move on to generating the rest of the release data. Bill of Materials: Things have changed because: - There are now additional equivalent parts, e.g. Cap_0402_thd is just a cap_0402 geometry - This must now run from the Mentor Comps file and not from the script generated comps file (all trash was forced by the early work on the Silkscreen Ref Desigs). So: remane the actual current active Mentor land comps_ver to comps_ver_orig_real copy comps_ver_orig_real to .../Work/Tools/temp_1_file.txt run the edited today .../Work/Tools/dk_bom_1_make_comps_file_for_bom.sh mv .../Work/Tools/temp_comps_file.txt to Mentor land comps_ver run .../Work/Tools/dk_bom_2_generate_bill_of_materials.sh run .../Work/Tools/dk_bom_3_clean_up_bom_file.sh in Mentor land delete comps_ver mv comps_ver_orig_real comps_ver - I.E. BOM generation is no longer a one click process. I would backup before doing the above - you are by hand playing with the active comps file. - There are clearly at least a couple of errors in this BOM file that I need to fix. Try to generate the SMD and X,Y placement data but that process does not apprear to be working. It works fine from the script version of the Comps file but not from the MG Comps file that includes modifications to the Silkscreen Reference Designators. This is probably a problem early in the process of generating the SMD and X,Y placement data. ----------------------------------------------------------------- DATE: 11-Jan-2025 Topic(s): PMT ADC uWave Traces On durand work through 10**9 scenarios for converting the PMT ADC's plain differential pair traces into uwave traces. Converge to: ADC Column #1 1st bend 0.54 @ 24 seg ADC Column #2 1st bend 0.43 @ 24 seg ADC Column #2 2nd bend 0.43 @ 24 seg NT AC Coupling Caps 0.23 @ 24 NT NT AC Coupling Caps 0.28 @ 24 must go in first NT NT NT Coupling Caps 0.80 @ 36 seg on both sides driven by Ch #2 FPGA Far Pin 0.54 @ 24 FPGA start the spread 0.28 @ 24 must go in first Finish spread back Horz 0.23 @ 24 Open long run bends 3.0 @ 72 seg Observations: Length match is good - about 0.04 or 0.05 mm. Perpendicular match is not as good - must verify edge-coupling percent vs ground-coupling percent. Could reduce edge-coupling but that requires space. Fighting that - could squeeze pairs closer to make smoother cap exit bends. No fast perfect solution. As currently setup, in the bulk of the run, we have a full 2.0 mm open air gap between pairs. Setup the configuration files for Philippe's Differential Pair analysis program in the DK .../Trace_Analysis sub-directory with the config aimed at the PMT ADC Diff Pair nets. This runs OK. There is the not un-typical question of, "Are the HS Dif signals isochronous at their pin pairs ?". The MicroChip "pin table" indicates - yes and I have assumed that the PMT ADC is a - yes. ----------------------------------------------------------------- DATE: 10-Jan-2025 Topic(s): Work on 99.x% Release The Gerbers from yesterday look OK except for the known wagon wheel problem on the ground planes. I check to verify that the cap_0402_thd parts are plotting OK, i.e. connecting to the Gnd Plane or Fills where they should and relieved by the proper amount on the other planes and fills. Added 8 more bypass caps. There was space to add 10 uFd ceramic at the input to the BULK_5V0 Filter for 5 or the 6 DCDC Converters so I added those. Must double check the max allowed capacitance on the output of the 100V to 5V converter when it does not have a resistive real load on it. Added 22 uFd at the upper far end of that Fill (lower far end was already in good shape. Added 22 uFd at the upper far end of the BULK_1V8 Fill where there is only a light load but the rail sould be kept free of moise and added 22 uFd at the end of the BULK_1V8 Fill that feeds the input to the 1V8 Filter for the Timing Generator. I need to check the DC resistance of that Fill vs the 440 ma pull to the Timing Generator. The Timing Gen 1V8 Feed Fill is about 11.2 mm x 109 mm or about 9.7 squares. I think 1 oz copper is about 0.5 mOhm per square. If so then 440 mA x 5 mOhm ---> not a problem. Now build all new Fills starting from: Counts with all Fills OUT - All Ver are from real moto and none edited: 1682 Comps 1463 Nets 4 UnConnected Pins 46 Shapes in pcb geom 4828 Conn 4125 Finished 171 Un-Finished 532 Guides Geom_Ver 505 Comps_Ver 1095 Nets_Ver 674 Trc_Ver 438 Tech 1361 Runs without any errors. "Normal" 15-5 Fractures. Looks OK but I forgot to try to fix the poor relieves on L7 in the BULK_1V2 Fill. So dump these fills. Recover Trc_438_pre_fill --> Trc_447 Counts with all Fills OUT - All Ver are from real moto and none edited: 1682 Comps 1463 Nets 4 UnConnected Pins 46 Shapes in pcb geom 4828 Conn 4125 Finished 171 Un-Finished 532 Guides Geom_Ver 506 Comps_Ver 1095 Nets_Ver 674 Trc_Ver 447 Tech 1370 Completes with out error and has the "normal" 15 & 5 Fractures. Now at Trc 456 5992075 bytes. Back out to Trc 447_pre_fill. 447_pre_fill is the same as 438_pre_fill but I screwed up and dumped 438_pre_fill. The original (best evidence 438_pre_fill) is in today's .tar two. After that .tar version it is ecovered versions of Trc_438. 437_pre_fill is that same as 438 except for missing routes to C1665. 1682 Comps 1463 Nets 4 UnConnected Pins 46 Shapes in pcb geom 4398 Conn 4398 Finished 0 Un-Finished 0 Guides After merging: 33 Shapes and 33 Fills Geom_Ver 506 Comps_Ver 1095 Nets_Ver 674 Trc_Ver 456 Tech 1379 This set of Fills look OK - the BULK_1V2 problems closed up nicely. This weenend I must get the 99.x% release on the web. ----------------------------------------------------------------- DATE: 9-Jan-2025 Topic(s): Work on Fills and Gerber Plots There are 2 obvious problems with yesterdays plots: - I had written but not updated the library with the Artwork Order file for the new rational way of making the 20 plots. - The "Art" labels in the Board Geometry and on the plots themselves have not been updated to the new scheme. Both problems are easy to fix and then generate the plots again. A quick look at the plots: - Some of the Plot Labels are so long that they overlap the plot itself. Move their origin West by 8mm i.e. start 2mm East of zero. - As expected, there are lots of wagon wheel type thermal apertures. This all needs to be decided on and cleaned up. A question for Hughes e.g. wrt things like the DCDC-20 converter. - Is there an unnecesary tight spot on L3 at about 150, 227 ? - Although it's not necessary the fills typically show a pad flash where a via on comp pin connect to them. On L4 I do not see these pad flashes for the via_0mm58 - another indication that the design system realy does not consider them connected to the Fill (even though they are flodded into it). - Why are the Thermal Center Pad Vias on things like the Time Gen and BB ADC so different that the Time Gen has discrete relieves and the BB ADC has a single block relief ? Is there a foot print error ? In any case I need to tune the Slot Width. - All 20 plots have the correct content and labels so there are no problems at that level. Drop these plots. Drop yesterday's Fills Trc_414_pre_fill ---> Trc_423 While there is still some problem with the via_0mm58 properly connecting to the Fills there is a more fundamental problem with this setup, i.e. I'm mindlessly wanting these Vias to obey the Component Pin design rules for Fill Generation. I've gotten around that before by the kludge of having 2 versions of the special via (or comp type bla): one distorted version to instance just for fill generation and a normal version with its correct dimensions for everything else e.g. DRC and Plot Gen. The cleaner more rational way to do this is to make a THD version of the 0402 cap with its SMD pads connected to its Component Pins on the normal breakout layer. That way everything just works in a natural way with the rest of the design system. Test this first with just one of the 3 caps on the Analog_2V5 bus that use the via_0mm58 for their connections to Gnd and Rail. These caps are: C264 vert 90 deg @ 113.2 157.5 vias to right so will need 270 deg C265 vert 90 deg @ 113.2 154.5 vias to right so will need 270 deg C266 horz 0 deg @ 113.5 152.8 vias are below so will need 0 deg Rip out the routing for these 3 caps ---> now Trc_424 ---> Note that this new cap_0402_thd is not symmetric so you can not just randomly rotate it in the comps file, e.g. 90 deg and 270 deg are NOT the same. But you can still rotate it to 0 or 90 in the pick and place file. As it was C264-2 was upper and hot will now need to be C264-2 is lower and Gnd --> pin swap As it was C265-1 was lower and hot will now need to be C265-1 is upper and Gnd --> pin swap As it was C266-2 was left and hot remains same --> no swap Swap C264 and C265 pins, to keep the optimal locations for the actual connections to the Gnd Plane and Analog_2V5 Fill, and make new net list. They look OK in the layout: the cap_0402_thd Pins are exactly the same as the FCG-1152 Dog-Bone Pins and the system knows that the cap_0402_thd Pins are connected to the correct nets. Make a quick test by generating just the L4 Signal_3 Fill which is the ANALOG_2V5 Fill that covers these 3 capacitors. Counts with all Fills OUT - All Ver are from real moto: 1674 Comps 1463 Nets 4 UnConnected Pins 46 Shapes in pcb geom 4820 Conn 4121 Finished 173 Un-Finished 526 Guides Geom_Ver 505 Comps_Ver 1093 Nets_Ver 671 Trc_Ver 424 Tech 1347 Run just the generate_fills_signal_3_high_res.sh to make just the Analog_2V5 Fill on L4. Generating just this one Fill runs to completion without errors at Trc_425 1034714 bytes. Backout is to Trc_424_pre_fill Counts with jus the ANALOG_2V5 Fill IN - All Ver are from real moto: 1674 Comps 1463 Nets 4 UnConnected Pins 46 Shapes in pcb geom 4804 Conn 4121 Finished 173 Un-Finished 510 Guides 1 Shape and 1 Fill Geom_Ver 505 Comps_Ver 1093 Nets_Ver 671 Trc_Ver 425 Tech 1348 Everything looks good: all of Analog_2V5 is connected including these 3 bypass capacitors and their THD pins look exactly the same (e.g. wrt Fill clearance and such) as the FPGA Pins. That was the goal - these bypass cap pins just blend into the sea of FPGA BGA Pins. Back out of this Analog_2V5 only Fill and make the same cap_0402 to cap_0402_thd swap on the remaining 8 under FPGA bypass caps that use via_0mm58 vias for their connection to the bus Fill and Gnd Plane. Then verify: - That via_0mm58 no longer appears in the DK board design. - That the new cap_0402_thd components are in the correct locations, have the correct orientations, and that their pins are correctly connected. Now build all Fills starting from: Counts with all Fills OUT - All Ver are from real moto: 1674 Comps 1463 Nets 4 UnConnected Pins 46 Shapes in pcb geom 4812 Conn 4113 Finished 167 Un-Finished 532 Guides Geom_Ver 505 Comps_Ver 1093 Nets_Ver 672 Trc_Ver 426 Tech 1349 Fill Generation runs to completion with out error and has the "normal" 15 & 5 Fractures. Now at Trc 435 5971736 bytes. Back out to Trc 426 now in today's plain .tar if needed. 1674 Comps 1463 Nets 4 UnConnected Pins 46 Shapes in pcb geom 4382 Conn 4382 Finished 0 Un-Finished 0 Guides After merging: 33 Shapes and 33 Fills Geom_Ver 505 Comps_Ver 1093 Nets_Ver 671 Trc_Ver 435 Tech 1358 There are a couple of poor looking relieves on the South edge of the diagonal slit in the BULK_1V2 Fill under the FPGA. They may close if the points 106.3 130.4 & 106.7 130.4 move North by 0.1 mm and 113.7 137.9 & 114.2 137.8 move West by 0.1 mm. I think they can close without causing other problems. The DDR4 CA Bus Terminator Fills on L1 and L12 now look fine - but I can get slightly better trace clearance on L12 at 137 81. Generate a set of Gerbers to verify that the bypass connections in them look OK and to start a more serious check of the Gerbers. Drop the Fills to make it faster to look at Gerbers Trc_426_pre_fill --> Trc_435 save the w Fill version Some of the To Do list: Edit - Fix - Eliminate the Thermal Apertures so that we have rational Ground Planes. Start DRC Runs. 13 GHz trace study and match and clean up. DDR4 trace study and match and clean up. Generate the rest of the 99% release data. SilkScreens get them ready. Whatever we are doing on foot print and net list verification. Stackup Drawing. Improve surface clearances around the polypropylene capacitor vias. Check Gerbers with the official Ucamco viewer. ----------------------------------------------------------------- DATE: 8-Jan-2025 Topic(s): Work on clean up Fills and Plotting Edited the 9 Fill Generation scripts so that they now know about the via_0mm58 (a new via that is used only for the bypass capacitors under the FPGA). Yesterday's error in the Fill Generation makes sense, i.e. the Geom Library knew the geometric description of the new via and I had put its design rules in the Tech file but the Fill Generation scripts did not know about via_0mm58 so when these scripts modify the design rules for fill generaation the new via was dropped for the allowed set of routing vias. Reposition the Ground vias for the CORE_1V05 bus just South of the FPGA so that the Fills will close up better. Move C157, C161, C164, C264, C273 from 100 nFd to 470 nFd so that I now think that all 7 for the FPGA power rails have both 100 nFd caps under the FPGA and at least one 470 nFd cap under the FPGA. For the DK board those are the only 2 values of "high frequency" bypass caps that I will use. I will not use any of the 10 nFd and similar size caps, as in previous designs, because this FPGA has "in package" bypass caps which I assume are specifically for the high frequency range. Except for the two DDR4 buses this design should have very few simultaniously switching outputs. Move some traces just East of the FPGA DDR4 CA Bus Terminator Fills to give more space for those VTerm and Gnd Fills. Edit the Shape of all 8 CPU & FPGA, L1 & L10, VTerm & Gnd Fills. This changed the available "unique X,Y IDs" on 6 of these Fills. Edit generate_fills_signal_1_10_high_res.sh with the new unique X,Y IDs for the CA Bus Terminator Fills. Counts with all Fills OUT - All Ver are from real moto: 1674 Comps 1463 Nets 4 UnConnected Pins 46 Shapes in pcb geom 4823 Conn 4124 Finished 175 Un-Finished 524 Guides Geom_Ver 501 Comps_Ver 1093 Nets_Ver 670 Trc_Ver 414 Tech 1337 Fill Generation runs to completion without errors at Trc_423 5973385 bytes 21 bytes bigger than yesterday. Backout of Fills to Trc_414 which if lost is in today's .tar 2. As usual Signal_11 Medium Res Fractures 15 pieces Signal_12 Medium Res Fill Space Fractures 5 pieces Counts with all Fills IN - All Ver are from real moto: 1674 Comps 1463 Nets 4 UnConnected Pins 46 Shapes in pcb geom 4404 Conn 4393 Finished 8 Un-Finished 3 Guides after merging: 33 Shapes and 33 Fills Geom_Ver 501 Comps_Ver 1093 Nets_Ver 670 Trc_Ver 423 Tech 1346 A similar but slightly different problem than yesterday. Now it can find and access the correct set of design rules but it has an issue with what it finds there. From one of the log files: Warning: Via Padstack (via_0mm58) is Not defined on (PHYSICAL_3). But it is defined on Physical_3 so I must just have a typo or something like that. - Another point is that the relief from the Fills to the via_0mm58 does not match the relief from the Fills to the normal Dog-Bone vias. Via_0mm58 is less. Duh - the BGA Dog-Bone "Vias" are actully component "Pins" and use those design rules where as the via_0mm58 is actually a Via and uses those design rules. Get the design rules right and all of this will work. - Another point is that it will now let me complete these routes by hand. Yesterday it would not let me complete them by hand because it was trying to enforce via_2mm2 rules. Ignore this for now (because the fills actually do look basically OK) and push on making a set of plots. The DDR4 CA Bus VTerm and Gnd Fills now look good and are making use of the available space. The Gerber Generation scripts are ready to try. This is the new 20 file version as defined in log book entry 19-Dec-2024. Give it a first try but have little time to study the plots. ----------------------------------------------------------------- DATE: 7-Jan-2025 Topic(s): Add more FPGA bypass capacitors: Add 1 more to the FPGA_1V8 bus just North of the FPGA Add 2 more to the FPGA_CORE_1V05 bus under the FPGA 470 nFd Add 4 more to the BULK_1V2 bus under FPGA 470 nFd 2 each for Banks #0 and #6 This completes the FPGA bypass capacitor work. I believe that the 100 nFd & 470 nFd, close in, actually under FPGA, bypass capacitor counts are now: 8x CORE_1V05 16x XCVR_1V05 4x Digital_2V5 6x Analog_2V5 16x BULK_1V2 caps for DDR4 Banks #0 & #6 10x BULK_3V3 caps for Banks 1,2,3,5,7 9x FPGA_1V8 caps for Bank 9 and other 1V8 FPGA loads All of the Bulk Bypass ( 1 uFd and larger) are in addition to the above. Remove from Comps the capacitors that I've been using to study placement options, i.e. pull out: C111...C119 and C126...C129. These parts had never been in the Net List. A concerning point is that there are still 4 unconnected pins in the design. I believe that these are the unconnected pins on the 4 terminating resistors for the DDR4 CA Buses for FPGA & CPU Memory. They are still unconnected for trace length match. The previous survey of unconnected pins is in the 19,20-Oct-2024 log book entry. Work on three of the Fill Shapes so that they walk around the Top and Bottom Middle Mounting Screws. disco_fill_shapes_bulk_1v8_signal_12.txt disco_fill_shapes_bulk_3v3_signal_11.txt disco_fill_shapes_bulk_5v0_signal_12.txt There is now a minimum "air gap" of 2.4 mm between any Fill and the edge of the mechanical hole for the Mounting Screws. All instances have at least a 3.4 mm air gap except for the BULK_1V8 Fill around the Top Center Mounting Screw where for now I kept it tighter to the hole to provide wide access of the BULK_1V8 bus to the J4 J5 Interposer Connectors. Once I look at this I may be able to also relieve this clearance to 3.4 mm. The Ground Fills on L1 and L12 for the CA Bus Terminator bypass caps should now look better. I think this Fills East-West dimension was being limited by design rule clearance to adjacent trace and not by Fill Shape. Generate a set of Fills to see if any of the recent work has broken things. To back out of these Fills revert to Trc_403 which if lost is available in .tar 3 from today. Counts with all Fills OUT - All Ver are from real moto: 1674 Comps 1463 Nets 4 UnConnected Pins 46 Shapes in pcb geom 4823 Conn 4124 Finished 175 Un-Finished 524 Guides Geom_Ver 500 Comps_Ver 1093 Nets_Ver 670 Trc_Ver 403 Tech 1326 Fill Generation runs to completion without errors at Trc_12 5973364 bytes. Signal_11 Medium Res Fractures 15 pieces Signal_12 Medium Res Fill Space Fractures 5 pieces Counts with all Fills IN - All Ver are from real moto: 1674 Comps 1463 Nets 4 UnConnected Pins 46 Shapes in pcb geom 4404 Conn 4393 Finished 8 Un-Finished 3 Guides after merging: 33 Shapes and 33 Fills Geom_Ver 500 Comps_Ver 1093 Nets_Ver 670 Trc_Ver 412 Tech 1335 I do not understand the problem with the un-finished traces and guides. - I believe that in all cases these are associated with the new under FPGA bypass capacitors that use the via_0mm58 for connection to the Gnd Plane and Fill. - I believe that in all cases that the problem is with the Fill end of the capacitor. - I believe that in all cases that the Fill actually does connected to the capacitor but the software does not "see" the connection for some reason. - In no cases do I see something just stupid like the via connection to the Fill being outside of the Fill Shape. - I actually do see 11 SLIs. - If I select the SLI and try to hand route it to the approprate Fill Layer it says that there is a Design Rule violation because the DRC thinks this is a via_2mm2 but if you just graphically select the via it says that it is a via_0mm58. - The log file from Fill Generation shows the obvious problem. The design rule changes within the Fill Generation scripts do not yet have the new via_0mm58 in them. Thus the Tech file is not right. 9 scripts to edit - make current. - Dump these Fills Trc_403_pre_fill ---> Trc_412 My rework of the 4x 2.2 uFd CORE_1V05 caps south of the FPGA made a mess of the Fill on Signal_12. Need to move them out by 0.1 mm. Still need to work on the L1 Fills for the CA Bus Terminators. The inner edge of all 4 Fills on L1 should move in by 0.3 mm or so and be made even for the VTerm and Gnd Fills. Both L1 Gnd Fills have the space to move in by about 1.2 mm and thus pick up an additional Gnd rivet. VTerms can move in by 0.5 mm. The trace DDR4_FPGA_VREF_CA needs better routing as it pinches with the VTerm Fill on L12 for the FPGA Mem. L12 Fills should be edited to have even inner boarders. ----------------------------------------------------------------- DATE: 6-Jan-2025 Topic(s): Restore from durand to the real moto: default_artwork_order_production, via_0mm58, generate_dk_gerber_all_20_plots.sh, and tech.tech_1313 Drop the Fills from last Friday: trc_390_pre_fill ---> trc_399 Work on placing additional bypass capacitors for the FPGA starting with its Analog and Digital 2V5 rails. While looking at capacitor locations recall that I wanted to rotate pin N5 from a NW to a NE dog-bone as that allows some cleaner escapes on Signal_1. Added 3 mid range bypass caps to each: FPGA_1V8, ANALOG_2V5, DIGITAL_2V5 Added 3 under FPGA bypass caps to ANALOG_2V5 Added 2 under FPGA bypass caps to DIGITAL_2V5 The under FPGA bypass caps should now be: 6x CORE_1V05 caps could increase by using by using vias within BGA 16x XCVR_1V05 caps probably at its maximum 4x Digital_2V5 caps probably now at its maximum 6x Analog_2V5 caps probably now at its maximum 12x BULK_1V2 caps for DDR4 Banks #0 & #6, near its max 10x BULK_3V3 caps for Banks 1,2,3,5,7 near its max 8x FPGA_1V8 caps for Bank 9 and other 1V8 FPGA loads near its max These now all look OK and that packs in the top half of the FPGA. The area of remaining concern is the CORE supply where I have space to pack in under Bank #8 by using the via_0mm58 within the BGA array. Counts with all Fills OUT - All Ver are from real moto: 1680 Comps 1463 Nets 30 Float Pins 46 Shapes in pcb geom 4809 Conn 4117 Finished 169 Un-Finished 523 Guides Geom_Ver 499 Comps_Ver 1092 Nets_Ver 669 Trc_Ver 402 Tech 1325 ----------------------------------------------------------------- DATE: 4,5-Jan-2025 Topic(s): Push on adding the additional required bypass capacitors, and setting up the Gerber plot generation to match the file set described in the 19-Dec-2024 log book entry. Creat a routing via that may be used within the FPGA foot print at locations where the Dog-Bone via is not present. Such a routing via will allow placement of 0402 bypass capacitors within the BGA foot print at locations where Dog-Bone vias are not present AND where the adjacent Dog-Bone vias do not provide access to the required Ground and Power planes. Finally get work started on the Artwork Order file and the scripts to generate a rational set of 20 Gerber files. ----------------------------------------------------------------- DATE: 3-Jan-2025 Topic(s): DL area clean up, Test Fills again Restore from durand: Trc_381 to real mote Trc_389 verify contents and counts: 4777 4090 166 521 The Trc file that was restored to real moto from the durand machine this morning has all of the routes completed - but this is just to prove that this can be done. There are still problem in the Discrete Logic area with clearances to the polypropylene capacitor pins. - With more work I think that on the surface layers everything can be held back by 6 mm from the pads for the Polypropylene capacitor Pads. - On the inner routing layers, where nothing is exposed to the atmosphere or contamination, then the clearance to the polyprop pads will be smaller, about 3 or 4 mm, but IPC guide lines allow you to make it a lot smaller on the inner protected layers, e.g. 0.25 mm for a 500 V peak operation. For reference for up to 500 V AC, DC, Peak for external uncoated for sea level to 3050 m they require 2.5 mm. - I had completely mixed up the Clearances for the Ground Plane Layers and the Fill Layers. For the Ground Plane Layers this clearance is completely controlled by the "Power" diameter in the Pin/Pad Stack and for the Fill this is controlled by the specified clearance between the Pad and the Fill but the pads will not be printed on the Fill Layers so this turns into a Fill to Drill Hole clearance. Do a little mild trace clean up in the Discrete Logic section. The DL section still needs a major Comps clean up to improve the clearances around the pins of the polypropylene capacitors - but there is no point in pushing the traces clean up until the comps situation is straightened out. Fix the concerns from yesterday's Fills about the Word Line Link Fill East edge position, the two routing vias, and the rivet in the middle of the BULK_1V8 feed down to the Time Generator. To back out of the Fills go to Trc_390 which if lost is in .tar two from today (and 2 other storage places). Counts with all Fills OUT - All Ver are from real moto: 1666 Comps 1463 Nets 30 Float Pins 46 Shapes in pcb geom 4777 Conn 4090 Finished 166 Un-Finished 521 Guides Geom_Ver 497 Comps_Ver 1090 Nets_Ver 667 Trc_Ver 390 Tech 1313 Fill Generation runs to completion without errors at Trc_399 5902346 bytes. Signal_11 Medium Res Fractures 15 pieces Signal_12 Medium Res Fill Space Fractures 5 pieces Counts with all Fills IN - All Ver are from real moto: 1666 Comps 1463 Nets 30 Float Pins 46 Shapes in pcb geom 4358 Conn 4358 Finished 0 Un-Finished 0 Guides after merging: 33 Shapes and 33 Fills Geom_Ver 497 Comps_Ver 1090 Nets_Ver 667 Trc_Ver 399 Tech 1322 Study the Fills and such: - I should double via the Word Line Link between the FPGA and the CPU memory arrays. It's no cost and there is space to do it. - Shape boarders look smooth and the new rivet locations look OK. - Still should fatten the Memory Terminator top and bottom Ground fills to use all of the available space. - The current Fill to Polypropylene capacitor drill hole edge clearance is about 3.8 mm. It looks OK and it is not really creating any tight necks. The Fill to HV Net_Type Pad design rule is only effecting the fill boarder at the polyprop caps. - The Fill to Mechanical Drill Hole for the Mounting Screws is too tight. It is only about 0.3 mm gap. Which rule controls this ? It is only the Top and Bottom Center Mounting holes that the Fill are designed to approach as controlled by the Fill Shapes. The Shapes themselves avoid the 3 West side holes and the 3 East side holes and could be edited to avoid the Top and Bottom Center holes. - I believe that the Top and Bottom edges of the CNST_3V3 Fill could both be reduces by 1.0 mm (or 1.1 mm) and still make a nice good connection to all pins in this net. This would give an extra couple of mm to the BULK_5V0 net at its thin point. To Do List Includes: - Fix the Gerber Generation Scripts so that they directly make the 20 files as listed in the 19-Dec-24 log book entry. - Figure out what to do with the Power Apertures and decide which methode to use to Flood most of the Ground Pins into the Ground Planes. - Make a Drawing of the Stackup so that it is stable for DDR4 analysis and well communicated to the pcb house. - Fix the top and bottom Silkscreen layers so they are usable. - Work on FPGA bypass capacitors. Some buses are fine but others need help mostly in mid band. Some buses have enough placements under the FPGA that some of the 0402s sound be moved to 47 nFd or 10 nFd e.g. the XCVR_1V05 bus. Is the single Tant on the: Analog_2V5, Digital_2V5, and FPGA_1V8 going to be a problem ? Those are also the buses that need the most mid band help. Review the FPGA's "in package" bypass caps to keep them in mind. - Smooth and then length match analyze the 13 GHz Diff Pairs. - Once stackup of stable length / time analyze the DDR4 Data bus and CA bus traces. How bad are they. Was enough space saved for the required surpentines ? - Start work on DRC checks and edits - zeor done so far. - What's going to happen with Geometry and Net List design checks ? - Is there any Drill Table or Aperture Table concatination work still needed or possible ? ----------------------------------------------------------------- DATE: 2-Jan-2025 Topic(s): DL Routing, Fill Scripts, Test the Fill Generation Restore from durand: Trc_383 to real mote Trc_377 verify contents and counts: 4764 4051 172 541 Before finishing the Discrete Logic area routing I need to bring the Fill Generation Scripts up to date (to include the 2V5 Word Line Link) so that I can test generating a new set of Fills to look for any problems. The required Fill Generation Script changes are: - Include the new "Link Fill" for the 2V5 Word Line supply link in the script for Medium Resolution on layer Signal_11. - Verify that none of the Shape boarders that I had to move break any of the unique X,Y ID points that are used in the scripts: XCVR_1V05, BULK_1V05, BULK_3V3. I think that these are all in the Signal_11 Medium & High Res scripts. I needed to fix the unique X,Y IDs for High Res XCVR_1V05 and BULK_1V05. Both are now in what should be more stable X,Y locations. I believe that there are about 6 SLIs left - all inside the DL and all involved with components that I would like to move to increase the surface air gap to the big polyprop capacitors. Specifically I would like to move: input LC to the CNST 3V3 supply, the South part of the Barnacle Master Reset circuit, and two Jumpers. Those parts currently have the smallest air gap to the power input filter caps. Generate a set of Fills both to test the DDR4 Word Line supply link generation and to see if any other problem have come up. For comparision the previous run of Fill Generation was on 24-Dec-24. To back out of the Fills go to Trc_380 which if lost is in .tar three from today (and 2 other storage places). Counts with all Fills OUT - All Ver are from real moto: 1666 Comps 1463 Nets 30 Float Pins 46 Shapes in pcb geom 4775 Conn 4082 Finished 170 Un-Finished 523 Guides Geom_Ver 496 Comps_Ver 1089 Nets_Ver 667 Trc_Ver 380 Tech 1303 Fill Generation runs to completion without errors at Trc_389 5888483 bytes. As expected - no new Fractures because of the new DDR4 Word Line Fill. Signal_11 Medium Res Fractures 15 pieces Signal_12 Medium Res Fill Space Fractures 5 pieces Counts with all Fills IN - All Ver are from real moto: 1666 Comps 1463 Nets 30 Float Pins 46 Shapes in pcb geom 4356 Conn 4350 Finished 4 Un-Finished 2 Guides after merging: 33 Shapes and 33 Fills Geom_Ver 496 Comps_Ver 1089 Nets_Ver 667 Trc_Ver 389 Tech 1312 ---> Note the correct number of Post Merge Fills is now 33 (compared to the previous 34). This is because the new DDR4 Word Line Supply Link Fill allows the DIGITAL_2V5 Fill to merge with the DDR4 Word Line Fills. Need to move the long East edge of the new DDR4 Word Line Supply Link Fill further to the East by 0.5 mm & need to move the routing vias on the FPGA_TO_TG_REF_IN_A_CAP_ DIR/CMP East by 0.2 mm. ---> I still need to move rivet VR107 out of the neck in the BULK_1V8 Fill that runs down to the Time Generator. I need to calculate the voltage drop on that Fill. ---> To stiffen the Ground Fills on the DDR4 Terminator Supply on the Bottom side I could widen them to the East and West by about 0.2 and 0.8 mm. I do see the expected 6 SLIs - all in the DL section. ----------------------------------------------------------------- DATE: 1-Jan-2025 Topic(s): Final routing in & into SE Sorner Finished the routing in and into the SE Corner. Start work on the remaining point to point routes within the Discrete Logic. Clean up work in the SE Corner. Rational SE Corner routing is difficult because of the completely useless TOMcat. The Dual SFP Cage by itself does fit nicely on the board without a bump out. Note to self - don't get involved in a project if its leadership has a bad combination of technical ignorance and pushyness. Counts with all Fills OUT - All Ver are from durand: 1666 Comps 1463 Nets 30 Float Pins 46 Shapes in pcb geom 4764 Conn 4051 Finished 172 Un-Finished 541 Guides Geom_Ver 496 Comps_Ver 1087 Nets_Ver 667 Trc_Ver 383 Tech 1300 ----------------------------------------------------------------- DATE: 31-Dec-2024 Topic(s): Routing FPGA NW, DL, & SE Corner Restore from durand: Trc_375 to real mote Trc_373 verify contents and counts: 4757 4007 196 554 All FPGA & ER uProc to SE corner is now routed as far as adjacent to the SE end points and some of it is connected. Small edit to clean up some Signal_1 traces to the South end of the Discrete Logic and to make a stable all moto version then hack all of the FPGA NW Signal_8 traces to get them in the order described in the 28,29 log book entry. Make the FPGA pin Swaps as indicated in the 28,29 log book entry: - Note that all swaps, except for pins J4 K8 are in Bank #1 and are made in the file: fpga_cpu_bank_1_floating_nets_fcg1152.txt For all signals that change pins in Bank #1 all of those signals remain in Bank #1. - Note that for the swap of pins J4 K8 that both pins are in Bank #7 the swap is made in the file: fpga_cpu_bank_7_floating_nets_fcg1152.txt For all signals that change pins in Bank #7 all of those signals remain in Bank #7. - During this major 12 pin swap - no signals are moved between Banks. All signals that started in Bank #bla remain in Bank #bla. I trust that this will be relatively transparent to the firmware. Counts with all Fills OUT - All Ver are from real moto: 1666 Comps 1463 Nets 30 Float Pins 46 Shapes in pcb geom 4758 Conn 4016 Finished 189 Un-Finished 553 Guides Geom_Ver 496 Comps_Ver 1087 Nets_Ver 667 Trc_Ver 377 Tech 1300 ----------------------------------------------------------------- DATE: 30-Dec-2024 Topic(s): Work on the remaining routes outside of DL Restore from durand: Trc_379 to real moto Trc_371 verify content and counts: 4750, 3987, 209, 554 Restore from durand: pin_numbers_of_in_use_pins_with_smd_pad_only.txt Still need to do the FPGA pin swaps for escape on Signal_8 as indicated in the previous log book entry. Counts with all Fills OUT - All Ver are from real moto: 1666 Comps 1463 Nets 30 Float Pins 46 Shapes in pcb geom 4750 Conn 3993 Finished 203 Un-Finished 554 Guides Geom_Ver 496 Comps_Ver 1087 Nets_Ver 665 Trc_Ver 373 Tech 1297 ----------------------------------------------------------------- DATE: 28,29-Dec-2024 Topic(s): Routing West FPGA Channel Moved: link for Bulk_1V8, VMon_CNST_3V3, Clok_Gen_Reset_B, PMT_ADC_Reset_B, and Converter_Track Ramp all to Signal_3 to clear the FPGA West Channel for routing on Signal_ 1, 2, and 8. The FPGA escapes all look OK. On Signal_8, 12 of the 13 escapes from the FPGA must be ordered as follows to allow direct connections into the Discrete Logic. That is, I must map the specified Function to the Specified FPGA pin in order to provide direct routes into the Discrete Logic. The exception is FPGA pin G9 "FPGA_CPU_RESET_B" which is a fixed function Bank #3 pin. All of the 12 West Channel routes on Signal_8 run into the Discrete Logic. Starting from the Top North most escape: NEW This Signal FPGA Must Provide Signal Had Been On Pin DL Function FPGA Pin ---- ------------------------ ----------- F7 DK_CPU_IS_AWAKE G6 E7 RUN_PMT_ADC E3 C7 RUN_CLOCK_GENERATOR D3 D6 DK_CPU_IS_AWAKE_B F5 C6 BARNACLE_CONTROL_1 E7 E5 RUN_USB_INTERFACE C6 D3 BARNACLE_CONTROL_2 C7 E3 RUN_BB_AUDIO_ADC D6 F5 RUN_BARNACLE F7 G6 POWER_B_CAMERA E5 J4 SFP_TIMING_TRANS_ENABLE K8 K8 SFP_ENET_TRANS_ENB_DIS J4 23 Traces run from the West Channel into the SE corner: 7 on Signal_1 all from the FPGA 7 on Signal_2 from the FPGA 6 on Signal_2 from the ER uProcessor 3 on Signal_9 from the Discrete Logic Near DCDC- 2 & 3 to provide direct through routes for these signals - moved the feedback for DCDC-3 and 5 VMon traces to other layers mostly Signal_3. Now all 23 of these traces have direct routes from West Channel to the SE Corner. Counts with all Fills OUT - All Ver are from real moto: 1666 Comps 1463 Nets 30 Float Pins 46 Shapes in pcb geom 4750 Conn 3987 Finished 209 Un-Finished 554 Guides Geom_Ver 495 Comps_Ver 1086 Nets_Ver 665 Trc_Ver 378 Tech 1295 ----------------------------------------------------------------- DATE: 27-Dec-2024 Topic(s): Routing West Channel, Bank #9 Bypass Restore durand Trc_371 to real moto Trc_370 Confirm and check counts: 4734 3969 191 574 Bank #9 routing is complete and other things in that area are stable so work on placing bypass caps on the FPGA_1V8 bus under the FPGA. These caps are in the range C171:C178 and were added directly to the Comps file. C171 was already in the Comps - I added 7 more FPGA_1V8 caps today. See the log book entries from 4-Dec and 12-Dec for notes about other bypass caps under the FPGA. I think that the total list of bypass caps under the FPGA is now: 6x CORE_1V05 caps probably at its maximum 16x XCVR_1V05 caps probably at its maximum 2x Digital_2V5 caps probably at its maximum 3x Analog_2V5 caps probably at its maximum 12x BULK_1V2 caps for DDR4 Banks #0 & #6, probably near its maximum 10x BULK_3V3 caps for Banks 1,2,3,5,7 probably near its maximum 8x FPGA_1V8 caps for Bank 9 and other 1V8 FPGA loads near its max More work on the Top layer BGA Pads Only escapes from the FPGA NW corner. Edited the "in use pads only" part of the FCG-1152 Geometry to: C6 goes back to a normal Dog-Bone because it can not escape on Top N5 goes back to a Dog-Bone. It is a Ground pin and thus it should never have been made a "Pad Only" pin - But it needs to chane from a NW Dog-Bone to the NE Dog-Bone. N6 Needs to become a Pad Only pin because it can escape on Top I believe that currently make a total of 13 Top lyaer escapes for these runs to the SE corner and to the Discrete Logic. I moved the required comps so that it is now rational to try to generate the Link Fill that connects the DDR4 Word Lines buses to the Digital_2V5 supply. Still need a final decision about Mem_Riv_112 but it is OK where it is for now. Counts with all Fills OUT - All Ver are from real moto: 1666 Comps 1463 Nets 30 Float Pins 46 Shapes in pcb geom 4749 Conn 3983 Finished 191 Un-Finished 575 Guides Geom_Ver 495 Comps_Ver 1086 Nets_Ver 665 Trc_Ver 371 Tech 1295 ----------------------------------------------------------------- DATE: 26-Dec-2024 Topic(s): Restore durand log to real moto log file. Drop the Fills on real Trc_360_pre_fill_gen ---> Trc_369 Edit the FCG1152 Geom with the new list of "in use pins with pads only" i.e. the first order draft at new NW escapes. Implement the new Fill Link on Signal_11 for the 2V5 Word Line DDR4 supply with its own private Shape file so that I minimize the risk to all of the Fill stuff that currently looks OK. Move a couple of other shape edges by tenths of a mm to close relieves around vias. - Do not yet edit the Fill Generation Scripts to include the new Link Fill for 2V5 Word Line supply. - Must verify that none of the shape edge move clean up broke a unique ID point to identify a Fill Shape. Clean up some stupid routing around the ISM303DAC sensor. Route out the last 4 Reset_Bs from the North section. All of North is now finished - except for any needed clean up. Counts with all Fills OUT - All Ver are from real moto: 1659 Comps 1463 Nets 30 Float Pins 46 Shapes in pcb geom 4733 Conn 3964 Finished 184 Un-Finished 585 Guides Geom_Ver 494 Comps_Ver 1085 Nets_Ver 663 Trc_Ver 370 Tech 1294 ----------------------------------------------------------------- DATE: 25-Dec-2024 Topic(s): Organize the remaining routes All remaining signals are low speed, mostly static logic levels, and not FPGA pin specific. SE Corner refers to the area with the dual SFPs and the TOMcat. - FPGA W-NW to the SE Corner: 14 Trcs on Top, Green, or Blue - ER uProcessor to SE Corner: 6 Trcs on Green, Blue, or maybe Red - Discrete Logic - SE Corner: 3 Trcs on - Total to SE Corner: 14 + 6 + 3 = 23 Traces - Upper Section to Discrete Logic: 4 Trcs 2x Xtal Enb, Ramp/Track, on Tan Interposer Buffer Enb - FPGA N-NW to Discrete Logic: 20 Trcs about 2 to 4 are mostly W-NW Esc & Route on Top, Blue Esc & NOT Route on Grn, Red, Tan - FPGA escapes to the North are completely blocked from making the turn and going South in the channel by: Grn, Red, Tan, Bot - The FPGA end must be ordered for convinient escape - The SE Corner has space to put signals into required order - The FPGA to Discrete will need to use FPGA pin swap to get order - May need/want swap layers for the current lower traces to West Channel: Ramp/Track Grn, VMon_CNST_3V3 Green, BULK_1V8 Blue, PMT_ADC_Reset_B Blue, Timing_Generator_Reset_B Blue - The remaining routes within the Discrete Logic are done on any available layer - all are open for this use - 3 mm min from HV on surface layers and 2.5 mm minimum on internal layers. - A possible route for the 2V5 Word Line for the DDR4 is a Fill on Signal_11 that would run between the legs of L102. Most of this run could be 3 to 5 mm wide with the run through L102 about 1.4 mm wide (or up to 2 mm wide by moving PVA102 A:D and C241). Vertex at about: 148,4 , 168.0 119.0 , 168.0 119.0 , 163.0 143.4 , 163.0 143.4 , 121.2 129.7 , 121.2 129.7 , 113.0 131.6 , 113.0 131.6 , 119.8 148.4 , 119.8 and return home. This requires at a minimum move of the fills through L102: Y of 120.0 down to 119.4 Y of 121.0 up to 121.6 - More bypass is needed on the rails: Digital_2V5, Analog_2V5, and FPGA_1V8. Space is very limited. There is some top side space above: C281, C282, C283, C284, C285, C286. Space for additional Ground Vias would be required. - First order estimate of now to be routed FPGA pins that will escape on the Top layer, i.e. "in use pins with BGA pads only": A5, A7, B6, B7, C6, G1, H1, J1, K1, K3, M5, N5 If there was space available in the West Channel then: J5, K5, L5 may also be able to escape on the Top layer. The tightest West Channel pinch is probably by C1653 at about 12.0 mm. That allows a 3 mm clearance for C1653. 0.18 trace on 0.6 mm centers is 15.4 traces in 12 mm or 17.6 traces on 0.5 mm centers. ----------------------------------------------------------------- DATE: 24-Dec-2024 Topic(s): Routing Bank #9 and Timing Generator All of Bank #9, the Timing Generator, and the FPGA East side channel are now routed and in fairly good shape. Perhaps just a little space optimization and overlap minimization work still needs to be done in this area. Test Fill Generation again. Before doing so change the global design rule for the HV Net Type to enforce a 2 mm minimum gap between Fill to Pin and between Fill to Via. Previously this had been set at 1 mm. I think that this is an easy way to control the Fill to Pad relief for the big polyprop capacitors as I believe that those are the only HV Net Type Pins or Vias that are in an area where Fills are generated To back out of the Fills go to Trc_360 which if lost is in .tar one and two from today. Counts with all Fills OUT - All Ver are from real moto: 1659 Comps 1463 Nets 30 Float Pins 45 Shapes in pcb geom 4729 Conn 3961 Finished 182 Un-Finished 586 Guides Geom_Ver 491 Comps_Ver 1084 Nets_Ver 663 Trc_Ver 360 Tech 1284 Fill Generation runs to completion without errors at Trc_369 5619169 bytes. For comparision the previous run of Fill Generation was on 20-Dec-24. Signal_11 Medium Res Fractures 15 pieces Signal_12 Medium Res Fill Space Fractures 5 pieces Counts with all Fills IN - All Ver are from real moto: 1659 Comps 1463 Nets 30 Float Pins 45 Shapes in pcb geom 4312 Conn 4229 Finished 18 Un-Finished 65 Guides after merging: 34 Shapes and 34 Fills Geom_Ver 491 Comps_Ver 1084 Nets_Ver 663 Trc_Ver 369 Tech 1293 Yes, 34 is the correct number of Fills - see the list in log book entry for 21-Dec that is: Signal_3 1 Fill Signal_11 13 Fills Signal_12 12 Fills Signal_1 4 Fills Signal_10 4 Fills Yes, the Fill relief around the polyprop cap pins is now 2 mm so that did track as it should have. I now need to "prove" that nothing else changed and then crank this up to 2.5 or 3 mm. ----------------------------------------------------------------- DATE: 23-Dec-2024 Topic(s): Routing in Bank #9 and the Time Gen. Must return dog-bones to pins: A24, B24 to now escape on Signal_8. End of the day counts with all Fills OUT - All Ver are from real moto: 1659 Comps 1463 Nets 30 Float Pins 45 Shapes in pcb geom 4726 Conn 3948 Finished 188 Un-Finished 590 Guides Geom_Ver 490 Comps_Ver 1084 Nets_Ver 663 Trc_Ver 358 Tech 1281 ----------------------------------------------------------------- DATE: 21,22-Dec-2024 Topic(s): Work on Routing Before dumping the Fills that were generated on Friday do a careful look at them. Except for a corner or two things look in pretty good shape. - I see nothing on Signal_11 that looks actually Fractured. - All merged, to a novice, Signal_11 looks like 13 Fills - On Signal_11: BB_ADC has a nice rectangular relief shape, the PVAs at the DCDC Conv inputs have under 1/2 height points, the USB I/F has < 1/3 height points, the: USB Hub, Trans Driver, ER uProc, and Time Gen all 4 have individual circles. Could try adjusting Min Slot Width. - I see nothing on Signal_12 that looks actually Fractured. - All merged, to a novice, Signal_12 looks like 12 Fills - On Signal_12: clearance to the Top Center mounting screw vs the BULK_5V0 Fill is wrong, clearance of the big polyprop caps leads is probably wrong, In the neck of the BULK_1V8 Fill I have a couple of Ground vias, that make the neck even thinner, and can probably be moved. - Signal 1 and 10 both have what most folks would call 4 Fills each, and Signal_3 has one Fill. Back out of the Fills, i.e Restore real traces.traces_344 to traces.traces_353 on real and check counts: 4728 3942 194 592 The scheme as of last Friday for routing the "active" signals from the FPGA down to the Time Gen is a train wrech at the Time Gen end. The New plan is: - Escape the Time Gen area in a very clean way that gives best possible distance between important signals and potential noise sources. - 7 traces (6 signals) will go South of the Time Gen. - from the North: TG_Aux_IN_M0_via_JMP, the TG_Aux_IN_M 3 & 4 in either order, then FPGA_to_TG_Ref_IN_A_Cap Dir & Cmp with Dir prefered to the North, then TOMcat_CFG 0 & 1 either order. The TOMCFG may route on Signal_8. - The important Clock FPGA_CCC_SW_CLK_IN_W_1 Dir & Cmp will run in the middle on Signal_10. - North and East of that Clock will be in order: Time Gen I2C Data then Clk, TG_Aux_IN_M6, TG_Aux_IN_M5. - The current TOMcat_100_Hz_to_TG_Aux_M0 needs to be moved from its current Signal_10 route to a route on Signal_ 2 or 8 and kept well away from important signals on adjacent layers. - The Time_Gen_1V2 feed currently on Signal_10 needs to be moved, to Signal_ 1 or 8. - Rivet VR101 needs to be moved for this and other reasons and perhaps replaced with 2 smaller size rivets. - At the FPGA end of things: Time Gen I2C Data & Clk, and TG_Aux_IN_M 5 & 6 all need to run North of FPGA_CCC_SW_CLK_IN_W_1 Dir & Cmp. The solution for the M 5 & 6 signals is easy - a solution is needed for the I2C signals. Counts with all Fills OUT - All Ver are from real moto: 1659 Comps 1463 Nets 30 Float Pins 45 Shapes in pcb geom 4726 Conn 3940 Finished 193 Un-Finished 593 Guides Geom_Ver 490 Comps_Ver 1080 Nets_Ver 663 Trc_Ver 354 Tech 1277 ----------------------------------------------------------------- DATE: 20-Dec-2024 Topic(s): East side routing, Fills & Plots Restore durand traces.traces_342 to traces.traces_341 on real Verified contents and counts: 4723 3935 195 593 Last night the PS Monitor stuff all routed in on the FPGA East side and looks OK. Today the active signal stuff on Signal_10 train wrecked at the Timing Generator end of the runs. Solutions present themselves but I don't want to do something random and screw up the current pretty nice Time Gen layout. Recall that during Physcis that the I2C Bus to the Time Gen and the M0, M1, M2, M3 could be (will be) active at some level so they must be kept well back away from things. M4, M5, M6 should be static. Counts with all Fills OUT - All Ver are from real moto: 1659 Comps 1463 Nets 30 Float Pins 45 Shapes in pcb geom 4728 Conn 3942 Finished 194 Un-Finished 592 Guides Geom_Ver 490 Comps_Ver 1079 Nets_Ver 663 Trc_Ver 344 Tech 1267 Test the Generation of Fills just to verify that things have not fallen apart. Back out of the Fills to Trc ver 344 and if necessary to .tar number one from today. Fill Generation runs to completion without errors at Trc_353 5585803 bytes. Signal_11 Medium Res Fractures 15 pieces Signal_12 Medium Res Fill Space Fractures 5 pieces Counts with all Fills IN - All Ver are from real moto: 1659 Comps 1463 Nets 30 Float Pins 45 Shapes in pcb geom 4308 Conn 4210 Finished 27 Un-Finished 71 Guides after merging: 34 Shapes and 34 Fills Geom_Ver 490 Comps_Ver 1079 Nets_Ver 663 Trc_Ver 353 Tech 1276 For comparision the previous run of Fill Generations was on 17-Dec-24. I see: Microscopic SLI at about 170.6 222.0 R1484. All Power Distribution connections look made up except for the expected Memory Word Line supply The only SLIs from the North or East are: BB_AUDIO_ADC_RESET_B, DCDC_CONVERTER_TRACK, INTERP_SPI_ADRS_BUF_ENB_B, and the two XTAL_OSC_ENABLES. Give up on making Gerbers today as there is no time to study them and I still need to edit the 21 script files and 1 Artwork Order file to implement the new Gerber scheme for DK - see log book entry 19-Dec-2024. ----------------------------------------------------------------- DATE: 19-Dec-2024 Topic(s): More clean up and East side routes The Plot Labels are now all fixed. These labels are held in one of the files that is built into the overall DK PCB Geom file. For the back side lables use the @nomirror property to get the label to display correctly. The error in the plot naming in the Gerber Generation scripts is fixed but I want to make an overall change to how the Gerber Files are handled. DK has only 4 Ground Planes so I will make a separate Gerber file for each Ground Plane (vs the method used when we had 10 or more Ground Planes. Thus the new list of Gerber Plots: PCB Signal Stackup Art Layer Layer Content --- --------- ------- -------------------------- 1 Signal_1 L1 Top Traces and Pads 2 Power_1 L2 Ground Plane Upper Type + PP_1 3 Signal_2 L3 Traces 4 Signal_3 L4 Traces and 1x Power Fill 5 Power_1 L5 Ground Plane Upper Type + PP_1 6 Signal_11 L6 ?x Power Fills 7 Signal_12 L7 ?x Power Fills 8 Power_1 L8 Ground Plane Lower Type + PP_2 9 Signal_8 L9 Traces 10 Signal_9 L10 Traces 11 Power_1 L11 Ground Plane Lower Type + PP_2 12 Signal_10 L12 Top Traces and Pads 13 Drawing_1 - PCB Mechanical Drawing 14 SilkScreen_1 - Top Silk Screen 15 SilkScreen_2 - Bottom Silk Screen 16 Solder_Mask_1 - Top Solder Mask 17 Solder_Mask_2 - Bottom Solder Mask 18 Paste_Mask_1 - Top Paste Stencil 19 Paste_Mask_2 - Bottom Paste Stencil 20 PrePreg_5 - Top Via Plugs To implement this will be a significant re-write of the Gerber Generation scripts and of the Art Work Order file but it will make a lot more sense for other people to understand in the future. With only 4 Ground Planes in DK there just is no advantage in using the same Gerber file for multiple stackup layers. I can do this re-write from durand. Ignore it for today. Press on the East side routes: Time Gen. Aux Inputs: M0 : M6 7 signals FPGA to Time Gen Ref A Input 1 differential Time Gen I2C Clk and Data 2 signals PMT ADC SPI Bus 3 Wire 3 signals PMT ADC RESET_B 1 signal going down TOMcat CFG0, CFG1 2 signals Voltage and Current Monitor 9 signals of DCDC 1, 2, 3 Voltage Mon of Both DDR4 Ref 2 signals Voltage Mon of CNST_3V3 1 signal DCDC Converter Ramp Track 1 signal Signal_1 Top is the 13 GHz data Signal_2 is mostly free but Signal_3 currently carries: TOMcat 125MHz and 100 Hz to FPGA and Spare Time Gen Clk to FPGA so must minimize any overlap. Signal_8 could carry PMT ADC SPI Bus for a full length route or just its horizontal stub into the PMT ADC itself but Signal_9 carries: SFP ENet to/from the HS Transceivers, Time Gen to XCVR 1A Ref Clk Input, Time Gen to PMT ADC System Reference Clock Input Time Gen to PMT ADC main Clock Input FPGA to PMT ADC Sync Input _B So Signal_9 has some verious stuff so any overlap with Signal_8 would need to be minimal Signal_10 Bottom is mostly free Final Desisions for the FPGA East Routing Channel: 12 PS Monitors go on Signal_2 PMT ADC SPI Bus stays on Signal_8 (its never active) All possible active signals (e.g. TG Aux M*) so on Signal_10 I think there is an even cleaner way to escape the 13 GHz traces at their FPGA end. It will require considerable time to spin more dog-bone to implement this new scheme so I need to study it before trying to implement it. A visit today from Nathan to talk about the design checking and the trip to Hughes. He did some more checks of FPGA pins and sent me a note of perhaps 50 things to look at. Many of these are HS Serial Rx Inputs and HS Serial Clk Inputs wanting 100k Ohm pull downs. I do not recall seeing these in their Demo Brd but need to check. I think that Nathan's design checks are 100% FPGA centric and not overall design checks. Working too fast and I accidently did a save all and thus lost the stable startup context that I want. Counts with all Fills OUT - All Ver are from real moto: 1659 Comps 1463 Nets 30 Float Pins 45 Shapes in pcb geom 4720 Conn 3929 Finished 195 Un-Finished 596 Guides Geom_Ver 490 Comps_Ver 1076 Nets_Ver 662 Trc_Ver 341 Tech 1263 ----------------------------------------------------------------- DATE: 18-Dec-2024 Topic(s): Fix known problems from yesterday, Start the final East side traces. Revert to No Fills traces.traces_326_pre_fill_gen ---> traces.traces_335 Fix the "micro SLI" in the 1V8 distribution to the pull-up resistors and re-route it in a way that does not use any space in the West FPGA routing channel. Fix the unpleasantness in the DCDC20 output distribution, i.e. one via of wrong size in the 5V0 and one output ground link that interferes with other routing. Now it looks OK. Fix the two Gerber Generation scripts that have file naming errors. Edit the DK PCB Geom to: move the Ground Slit as described yesterday and to add some width to the BULK_1V8 Fill under L604 that feeds down to the Timiing Generator. I can even add another 1 mm to the width of of this 1V8 Fill for the Timing Generator if I cut into just the very top of the Digital_1V8_PMT_ADC Fill but I have not done that yet. Moved CPU DDR4 Memory ADRS_5 pin AA3 to be a BGA Pad only pin because it escapes on the Top layer. Did a manual trace edit to match. The rectangular Thermal Pad just West of the FPGA at 62, 147 is the Transformer Driver for the Isolated RS-485 supply, it is OK. The too fat traces on the bypass caps under the Timing Generator are all OK - these are all Gnd traces that are going to or are already inside the side 2 Thermal pad for the Timing Generator, i.e. I was looking at a same net clearance "error". Counts with all Fills OUT - All Ver are from real moto: 1659 Comps 1463 Nets 30 Float Pins 45 Shapes in pcb geom 4707 Conn 3903 Finished 198 Un-Finished 606 Guides Geom_Ver 489 Comps_Ver 1074 Nets_Ver 662 Trc_Ver 337 Tech 1259 ----------------------------------------------------------------- DATE: 17-Dec-2024 Topic(s): Clean up problems found yesterday Generate Fills and full Gerber set Revert to No Fills traces.traces_315_pre_fill_gen --> traces.traces_324 Cleaning up the problems found yesterday included adding a new bypass cap (C1166) for the 1V8 pull-up R1175,6,7,8 which are various O.D. Reset_B outputs from the discrete logic and swapping pins on the Z Ref resistor R329 in the FPGA memory array. Also have moved the traces for the escape of the "Spare Clk" input to the FPGA (that comes from the Timing Generator 1B Output) to Signal_10 from Signal_3 and that should fix the problem of the ANALOG_2V5 Fill on Signal_3 from Fracturing. Ready to try Fill Generation again. Starting from traces_326 which is in today's .tar_two if needed. Counts with all Fills OUT - All Ver are from real moto: 1659 Comps 1463 Nets 30 Float Pins 45 Shapes in pcb geom 4688 Conn 3883 Finished 199 Un-Finished 606 Guides Geom_Ver 486 Comps_Ver 1073 Nets_Ver 662 Trc_Ver 326 Tech 1248 To back out of the Fills - restore traces_326 Fill Generation runs to completion without errors at Trc_335 5550185 bytes the ANALOG_2V5 Signal_3 Fill is now OK and Signal_11 Medium Res Fractures 15 pieces Signal_12 Medium Res Fill Space Fractures 5 pieces I don't think that these are "real fractures" just removed Islands under the QFN packages. Counts with all Fills IN - All Ver are from real moto: 1659 Comps 1463 Nets 30 Float Pins 45 Shapes in pcb geom 4269 Conn 4150 Finished 34 Un-Finished 85 Guides after merging: 34 Shapes and 34 Fills Geom_Ver 486 Comps_Ver 1073 Nets_Ver 662 Trc_Ver 335 Tech 1257 For comparision the previous run of Fill Generations was on 16-Dec-24. Note that it now shows 34 Fills. Was the previous 35 Fills from the real fracture of ANALOG_2V5 ? Carefully scan all Fill Layers & Power Bus Nets for any remaining SLIs. I see only: the expected feed to the DDR4 Word Line Fills, and a microscopic SLI at the via to the BULK_1V8 feed to the O.D. pull-up R1175:R1178 (I should redo this anyway and have separate feeds for R1175,6 and for R1177,8.) The Fill edges look OK. I still need to see things after the rest of the FPGA bypass caps are in, especially the FPGA_1V8 and any additional CORE_1V05 caps that I can put in under Bank #8 using their own private special vias within the BGA - is that legal ? ---> In the corner of the BULK_1V8 fill under L604 I can improve the thin neck by about 1.7 mm if I just change that shape by adding an extra boss on it at the West end under L604. ---> With the move of the Access connector North I should now move the Ground Slit along the North edge of the Isolated RS-485 further North by about 0.7 mm this is the Gnd Slit that runs just North of C1011 and D1002. The rest of the Gnd Slit vs Fill Boarders look OK for now. ---> Note that FPGA Pin AA3 should be changed to BGA Pad Only. This will require hand edit so that we do not dump the attached trace. Things look OK enough that I will try an all up generation of the Gerber plots. Nothing should have changed in the Aperture Table requirements since the 50% Bid Release but I will make a 100% fresh Aperture Table to start this Production Release but will NOT edit any of the Power Apertures at this time. The instructions for starting the Aperture Table are in the 22-Aug-2024 log book entry. Recall that we are Flaching the Complex PadStacks and that you need to save the Aperture Table. The Aperture Table is now: aperture_table.apertt_33 The .../mfg/ directory is empty. Check the Gerber Plots: - Most are missing their labels - need to fix pcb geom. - Art 8, L12 Bot looks like an undetected design rule violation at the NW corner of the Timing Generator. Need to run DRC. - Need to verify 0.12 mm trace width signals in Memory Array e.g. on L3 FPGA side. - Check the under Timing Generator bypass cap trace width. - Wrong name on the Art 4 file - just fill - no trace. Wront name on the Art 3 file - needs trace & fill - Fill clearance on the HV polyprop looks like only 7 mm Is a special Geom on the polyprop needed only during Fill Generation ? - The Ground plots have Thermals - a known issue but which of the various solutions to take ? - The Plug plot has different size flashes within the FPGA and there is a not square array to the West of the FPGA at about 62, 147 a screwed up geom ? ----------------------------------------------------------------- DATE: 16-Dec-2024 Topic(s): Work on CPU Memory routes and Test Fill Generation & Plot Generation Edit the production version of the Art Work Order file to remove the L1 Backside metal reference for QFN packages placed on the Bottom of the pcb. Do this because for the DK board all of its QFN packages are placed on its Top side. Restore on real moto the Shape file for the DK pcb for the BULK_5V0_L7 fill. In the new version I have changed the BULK_5V0 shape so that the metal for this fill on the L7 Signal_12 layer is excluded from the area of the Barnacle connector. Do some additional clean up of the CPU DDR4 traces. This is starting to look in OK shape. The off sets of the L3 vs L4 traces and of the L9 vs L10 traces looks OK. The rest of the topology of this routing is starting to look OK for now. Generate a trace length report. So with things in better shape I want to try Fill Generation and the Plot Generation scripts. Counts with all Fills OUT - All Ver are from real moto: 1658 Comps 1463 Nets 30 Float Pins 45 Shapes in pcb geom 4677 Conn 3858 Finished 200 Un-Finished 619 Guides Geom_Ver 486 Comps_Ver 1071 Nets_Ver 661 Trc_Ver 315 Tech 1237 This immediate pre fill gen version is backed up in today's .tar_two and .tar_three To back out of the Fills - restore traces_315 Fill Generation ends at traces_324 which is 5541683 bytes. Look at the Fill Generation Log files: Signal_3 fractured into 11 pieces Signal_11 Medium Res fractured into 15 pieces Signal_12 Medium Res Fill Space fractured into 5 pieces Compare this to the previous run of Fill Generations on 13-Dec-24. The Signal_3 layer fill is still fracturing The log files show no actual Errors during Fill Generation. Counts with all Fills IN - All Ver are from real moto: 1658 Comps 1463 Nets 30 Float Pins 45 Shapes in pcb geom 4256 Conn 4121 Finished 39 Un-Finished 96 Guides after merging: 34 Shapes and 35 Fills Geom_Ver 486 Comps_Ver 1071 Nets_Ver 661 Trc_Ver 324 Tech 1246 With the Fills IN scan looking for missing Gnd and Power connections: U1251-15 missing a Gnd FPGA Boot PROM Mux OE_B L1051-2 to C1051-1 missing connection USB Transceiver 3V3 R1971-2, U1151-6, R1174-1 missing connection to CNST_3V3 ER and Discrete R1161-2, R1179-2, U1160-6, C1160-2 missing connection to BULK_5V0 Discrete R1175-1, R1176-1, R1177-1, R1178-1 missing BULK_1V8 connection Discrete L901-1 and -2 links to their PVA Timing Generator Memory Array Word-Line supply DIGITAL_2V5 known layout issue R329-1 missing Ground FPGA Memory array U1-M15 or U1-U18 missing an ANALOG_2V5 connection (shape error ?) U1454-14 & C1455-1 to Via to BULK_1V8 has microscopic SLI in Via No chance to test the Plot Generation today. Plan: fix the above trace issues tonight, then re-generate the Fills on Tuesday, then test the Plot Generation. ----------------------------------------------------------------- DATE: 15-Dec-2024 Topic(s): Work on CPU DDR4 routing clean up Resetore from Durand to real moto - and verify and check counts: durand Comps_1072 to real moto Comps_1069 durand Trace_318 to real moto Trace_313 durand 1-18 plot script to real moto generate gerber sub-directory Work on clean up of the CPU DDR4 routing - especially clean up of the current return rivets and associated with the routing vias. Counts with all Fills OUT - All Ver are from real moto: 1658 Comps 1463 Nets 30 Float Pins 45 Shapes in pcb geom 4677 Conn 3858 Finished 200 Un-Finished 619 Guides Geom_Ver 483 Comps_Ver 1070 Nets_Ver 661 Trc_Ver 314 Tech 1236 ----------------------------------------------------------------- DATE: 14-Dec-2024 Topic(s): Routing Clean Ups, Plotting Script Work on routing cleanup - specifically: Move the VMon series resistor for: BULK_1V8, BULK_2V5, BULK_3V3, and BULK_5V0 so that they same not at the PS output but closer to the Load. Some series VMon resistors moved close to J11 PS Mon. Move Feedback connection for the BULK_2V5 from open space to the inputs to its output Filter inductors. Should be L outputs ? Move some FPGA to Interposers A & B traces from Signal_3 to Signal_2 so that the L4 ANALOG_2V5 can be saved from fracture. Associated clean up of the Time Gen output routing to FPGA. Connect Ground and 3V3 to the 5x Pull Resistors on FPGA West side. Finish clean up of the generate all 18 plots script. Not tested. End at Durand: Comps_1072, Traces_318, and new overall plot script. Counts: 4677, 3858, 200, 619. ----------------------------------------------------------------- DATE: 13-Dec-2024 Topic(s): Add bypass to TG Pull-Ups, CPU Mem Clean, Check Fill Generation, Write another Net List check note The goal today is to check Fill Generation. First add the bypass to the Time Generator I2C Pull-Ups and do some at least cosmetic clean up in the CPU Memory area. This still needs serious work. Counts with all Fills Out - All Ver are from real moto: 1658 Comps 1463 Nets 30 Float Pins 45 Shapes in pcb geom 4679 Conn 3855 Finished 200 Un-Finished 624 Guides Geom_Ver 483 Comps_Ver 1069 Nets_Ver 661 Trc_Ver 304 Tech 1226 This immediate pre fill gen version is backed up in today's .tar_two To back out of the Fills - restore traces_304 Now do a fully scripted generation of all Fills. The saved pre-Fill traces file is ver 304. Fill Generation runs to completion in about 9 minutes. Trc Ver 304 is pre fill gen and is about 0.73 MB Trc Ver 313 is with all Fills and is about 5.56 MB. Recorded the following "Fractures" in the log files: Signal_3 7 pieces Signal_11 Medium Resolution 15 pieces Signal_12 Medium Res Fill Space 5 pieces Counts with all Fills IN - All Ver are from real moto: 1658 Comps 1463 Nets 30 Float Pins 45 Shapes in pcb geom 4256 Conn 4117 Finished 40 Un-Finished 99 Guides after merging: 34 Shapes and 35 Fills Geom_Ver 483 Comps_Ver 1069 Nets_Ver 661 Trc_Ver 313 Tech 1235 With fills in it picked up and Invalid Placement for the Dual SFP Cage - I don't yet know why. Big major screw up - to make the FPGA North side routing extra clean I had moved some Interposer A & B signals to L4 - but they exactly block the Signal_3 Fill for ANALOG_2V5. Of the various ways to recove from this it is hard to think of which one is best. Also I picked up Comp Clearance errors on all Termination Resistors in both CA Buses. I expect this is a Design Rules issue and tight clearance is required to allow Fill Generation between the Term Res. The new Fill Shapes for the CA Bus Term Resistors look OK and the new Rivets in these 8 Fills look OK. Fill Boarders on Signal_11 and Signal_12 look pretty good. May want to exclude the area of Barnacle connector J7 as I think that it will still leave the 5V0 Fill wide enough. Move 5V0 VMon Resistor. ----------------------------------------------------------------- DATE: 12-Dec-2024 Topic(s): BULK_3V3 Bypass Caps, Net List Check Banks #1, #2, #3, #5, and #7 all run on 3V3. These are now fully enough routed that I can try to pack in some bypass capacitors for BULK_3V3 right under the FPGA and in any available spaces close to the FPGA. Today added 8x 0402 BULK_3V3 caps under the FPGA and 5x caps adjacent to the FPGA on the top side - 2x 1206 and 3x 0603. See the 4-Dec-2024 log book entry for notes about the previous work getting bypass close to and under the FPGA. Wrote a long note about net list checking of Power & Ground and memory system connections to the FPGA. I finally added the "Link" connection for the power input to the Ref & Term supply for the FPGA DDR4 memory and did a little clean up around the Access Connector. I need to add a bypass for the T.G. Pull-Up for its I2C and the 2x TOMcat Config signals. Need to do the first order clean up of the CPU mem and its current return vias. Counts with all Fills Out - All Ver are from real moto: 1657 Comps 1463 Nets 30 Float Pins 45 Shapes in pcb geom 4676 Conn 3850 Finished 202 Un-Finished 624 Guides Geom_Ver 483 Comps_Ver 1068 Nets_Ver 660 Trc_Ver 301 Tech 1221 ----------------------------------------------------------------- DATE: 11-Dec-2024 Topic(s): Routing: Access Connector Restore Durand Trc 298 to real moto as Trc 295 with counts: 4650 3816 206 628 verified Routing from the FPGA pins to the Access Connector is difficult as is - things are basically inverted from being a straight route. Edit the associated net list and in all cases keep the same set of FPGA pins just assign them to different access functions. The "high quality" differential access connector FPGA pins remain the same they just swap between Diff Access 1 and 2. Current SLIs: about 16 East side, about 25 West side to SFP area, about 25 West side to Discrete Logic area. The channels look to be just barely OK. The current routing pinch is just under the Accesss Conn and USB I/F down to the start of the isolated area for the RS-485. The only way to clean this up is to move the Access Connector North by 4 mm. Doing that and getting everything re-connected or connected for the first time to the Access Conn required all day. All of the acosiated UART stuff is now also routed. There is now rational clearance between all of the USB control stuff, & Access signals, & UART signals and the Isolated RS and PS. Counts with all Fills Out - All Ver are from real moto: 1644 Comps 1463 Nets 30 Float Pins 45 Shapes in pcb geom 4650 Conn 3829 Finished 198 Un-Finished 623 Guides Geom_Ver 483 Comps_Ver 1067 Nets_Ver 659 Trc_Ver 299 Tech 1221 ----------------------------------------------------------------- DATE: 10-Dec-2024 Topic(s): Continue Routing Restore Durand Trc 291 to real moto as Trc 290 with counts: 4627 3768 199 660 verified Restore Comps_1064 from too_office to real moto as Comps_1062 verify counts. This gets all of Sierra's Ref Desig work as of Friday 6-Dec-24 restored to real moto. Working on the V/I Monitor runs for the upper PS and on the remaining FPGA East side traces. Need to get in a relatively protected PS Ramp signal. Counts with all Fills Out - All Ver are from real moto: 1644 Comps 1463 Nets 30 Float Pins 45 Shapes in pcb geom 4647 Conn 3807 Finished 199 Un-Finished 641 Guides Geom_Ver 483 Comps_Ver 1065 Nets_Ver 658 Trc_Ver 295 Tech 1217 ----------------------------------------------------------------- DATE: 9-Dec-2024 Topic(s): Routing Work Restore Durand Trc 295 to real moto as Trc 286. Still need to restore Sierra's Comps file from last Friday. Continue North Tier routing. Counts with all Fills Out - All Ver are from real moto: 1644 Comps 1463 Nets 30 Float Pins 45 Shapes in pcb geom 4626 Conn 3761 Finished 205 Un-Finished 660 Guides Geom_Ver 482 Comps_Ver 1062 Nets_Ver 655 Trc_Ver 290 Tech 1213 ----------------------------------------------------------------- DATE: 7,8-Dec-2024 Topic(s): Routing Work On the North side finished routing the FPGA fixed pin connections, e.g. JTAG, CPU Boot PROM, FPGA Boot PROM and Mux, Emergency connection to Boot PROM Mux. Start the routing of the: A and B Interposers, Interposer UARTs, Interposer B Muon, BB Audio ADC. No component moves. Finish at Trc 295 counts: 4623, 3734, 229,660. ----------------------------------------------------------------- DATE: 6-Dec-2024 Topic(s): Routing, Sierra worked on Ref Desig Sierra was back to work more on the Reference Designators. Her last work had been just before the start of the Thanksgiving break. I passed the full design from the real mote to moto too office. So I can not change the Comps file on real moto until I re-incorporate her work today back onto the real mote. Routing work today was still on the fixed pin devices. Counts with all Fills Out: 1644 Comps 1463 Nets 30 Float Pins 45 Shapes in pcb geom 4622 Conn 3714 Finished 215 Un-Finished 693 Guides Geom_Ver 482 Comps_Ver 1062 Nets_Ver 655 Trc_Ver 286 Tech 1209 ----------------------------------------------------------------- DATE: 5-Dec-2024 Topic(s): Correct Drawings, Routing Correct mistakes in Drawings: 1, 12, 50, 64, and 80. Mistakes included: L104, L105 were swapped, in one place the FPGA_Reset_B signals was tied to pin H9 should be G9, inconsistent pin number and signal name of the 100 Hz output from the TOMcat - should be pin 29 and name is 100 Hz not PPS. Restart the final routing work - routing the fixed pin number signals to the FPGA, e.g. USB bus, all Bank #3 e.g. JTAG and Boot PROM. ----------------------------------------------------------------- DATE: 4-Dec-2024 Topic(s): Under FPGA Bypass Capacitors, Drawings Work on errors tha Jeanne and Dan have found it the DK drawing set. Work on packing 0402 bypass capacitors under the FPGA. These are bypass capacitors that are tied directly across adjacent FPGA Power-Ground pin pairs. I believe that there now are 42 caps under the FPGA: 6x CORE_1V05 caps probably at its maximum 16x XCVR_1V06 caps probably at its maximum 2x Digital_2V5 caps probably at its maximum 3x Analog_2V5 caps probably at its maximum 12x BULK_1V2 caps for DDR4 Banks #0 & #6, probably near its maximum 2x BULK_3V3 caps for Banks 1,2,3,5,7 1x FPGA_1V8 caps for Bank 9 and other 1V8 loads There is or should be a lot of space for more BULK_3V3 and FPGA_1V8 caps under the FPGA but there is no point in adding them until routing of signals to the FPGA is finished. On the Rails where it was possible to place a significant number of caps and these Rails supply high frequency loads we should consider using multiple values of 0402 caps, e.g. 100, 33, and 10 nFd. XCVR_1V05 and BULK_1V2 are probably the obvious candidates for this. Need to ask Nathan about Emergency Rescue uProcessor code for initial tests or, just count on the ER_IS_SANE signal to keep it out of our hair, or make the R1005 into something that can disable the ability of ER to take over the Boot PROM. Counts with all Fills Out: 1644 Comps 1463 Nets 30 Float Pins 45 Shapes in pcb geom 4621 Conn 3696 Finished 223 Un-Finished 702 Guides Geom_Ver 482 Comps_Ver 1060 Nets_Ver 655 Trc_Ver 280 Tech 1203 ----------------------------------------------------------------- DATE: 3-Dec-2024 Topic(s): Generate Gerbers, Un-Used Bank #8 Power Pins, Work on 0402 bypass caps under the FPGA Restored on moto real the full Generate Gerbers sub-directory from moto durand. Bank #8 is not used or powered in the DK design. Bank #8 has only a 10k Ohm pull-down from its VCC pins to Ground as indicated in the MicroChip documents. The question is - do I need to connect all of the Bank #8 VCC pins to this pull-down or is it OK to connect just a few of them. I do not have a MPFS250T-1FCG1152I to probe to verify that all of its per Bank VCC pins are tied together in the package substraight but I have probed their smaller FCGV784 part both its Banks #1 and #8 and this appears to be true. The maximum current flow should be about 300 uAmp so in Bank #8 I will connect the 10k Ohm pull-down to only a couple of its VCC pins. Specifically I will connect to pins: AJ12, AK9, and AN10. and drop the connection to pins: AD17, AE14, AH15, AL6, and AP7. The Bank #8 VCC pins where I have dropped the pull-down connection will become NO_CONN pins in the design and will have only a BGA Pad (no dog-bone or via). This provides a lot more space on the bottom side for bypass caps under Bank #8. The same issue exists for Bank #4 VCC pins and its Aux supply pins. Worked on placing and routing the 0402 bypass caps that go under the FPGA and are tied directly to its adjacent Power and Ground pins. Got about 22 of them placed and routed: 6x on CORE_1v05, 12x on BULK_1V2 (Banks #0 and #6 the DDR4 Banks), 2x on ANALOG_2V5, and 2x on DIGITAL_2V5. Things are open enough so that I should be able to pack in some for all rails. Did not yet work on errors in the Drawings which I must get fixed. Counts with all Fills Out: 1624 Comps 1463 Nets 30 Float Pins 45 Shapes in pcb geom 4575 Conn 3643 Finished 223 Un-Finished 709 Guides Geom_Ver 482 Comps_Ver 1058 Nets_Ver 653 Trc_Ver 278 Tech 1201 Why did I pick up 5 Net Names wrt yesterday ??? That should not have changed. Need to diff the script generated Net List files today vs yesterday. Duh I intentionally dropped 5 of the Bank #8 VDD pins that are now named as unique NO_CONN pins. ----------------------------------------------------------------- DATE: 2-Dec-2024 Topic(s): Merge Comps, Fix some known issues, Meeting with Jeanne and Dan Moto real is now running from the merged Comps that includes all of Sierra's Ref Desig work up through 30 Nov. I;m now directly editing comps as needed. Script build comps has ended for the DK. The BOM and XY Placement will have to come from MG Comps file. Worked on all of the "known issues" at the end of yesterday's note and working on FPGA bypass caps. Recall that lots of FPGA bypass caps are not in the design at all at this time. ---> Pull-Down Resistors for the un-powered FPGA I/O Banks. I started this for Bank #8 with the intent that I'm NOT going to tie the 10k pull-down to all VCC pins for an un-powered Bank but rather just tie it to a few (3 or 4) of the VCC pins and count on all VCC pins for the Bank being tied together in the FPGA substraight. I need to prove that this is OK. Doing this helps a lot in making space for under FPGA bypass caps. Meeting with Dan and Jeanne to review their work on checking net list files. This is hard work for a person new to this and they have done a nice job. I have a number of things to dig into e.g. stuff that is not even consistent in my drawings. I do not yet know how far the rot goes but it is clear that there could be fatal problems deep down in the net list files. Working on the Gerber generation script and art work order file. The plan is: Art Signal Layer Content --- ------ ----- ------- 1 1 L1 L1 Top Traces, Pads, and CA Term Fills 2 2 L3 L3 Traces 3 3 L4 L4 Traces and one Fill 4 11 L6 Power Fills 1 oz 5 12 L7 Power Fills 1 oz 6 8 L9 L9 Traces 7 9 L10 L10 Traces 8 10 L12 L12 Bottom Traces, Pads, and CA Term Fills 9 L2, L5 Upper Ground Planes 10 L8, L11 Lower Ground Planes 11 Mechanical Drawing 12, 13 Silkscreen Top, Bottom 14, 15 Solder Mask Top, Bottom 16, 17 Paste Stencil Top, Bottom 18 Plugs Top Counts will all Fills Out: 1608 Comps 1458 Nets 42 Float Pins 45 Shapes in pcb geom 4535 Conn 3593 Finished 221 Un-Finished 721 Guides Geom_Ver 481 Comps_Ver 1056 Nets_Ver 650 Trc_Ver 275 Tech 1198 ----------------------------------------------------------------- DATE: 1-Dec-2024 Topic(s): Brought last night's moto durand work to moto real and verified that all files in: Generate_Fills, DK PCB Geom, and FPGA FCG1152 Geom are correct. The design on moto real is now fully up to date except for the reference designator silkscreen work from moto too office from Sierra. Fixed the file permissions on some of the script .sh files in the .../Design_FPGA_FCG1152/Rev_3_Full_Custom/ directory. That was the cause of the problem when I could not build the FPGA BGA 1152 Geom yesterday. I must have screwed up the file permissions when I brought files over from a FAT thumb drive. The error messages were useless without one possessing extreme clairvoyant powers. Everything looks OK and the counts are (all Fills are out): 1590 Comps 1458 Nets 50 Float Pins 45 Shapes in pcb geom 4493 Conn 3549 Finished 213 Un-Finished 731 Guides Geom_Ver 481 Comps_Ver 1052 Nets_Ver 647 Trc_Ver 261 Tech 1184 Fills are all out - but when you need to remove fills then for now restore: traces.traces_240 tech.tech_1163 ---> OK try running the full build of all Fills: Running requires about 7:32 but about 1/2 of that run time is from the pauses between calling the sub-script files. Running moves us from trc_261 to trc_269. Signal Layer 11 Medium Resolution shows 17 Fractures but I think it is OK - things just do not close in under things like the QFP thermal vias (as expected) but I need to look at adjusting the minimum slot width parameter in the Fill Gen design rules. OK wait - the signal_12_medium_res_fill_space sub script did not get called. There are a total of 9 sub scripts. Edit the generate_all_fills_on_all_layers.sh script so that it now includes a call to signal_12_medium_res_fill_space For now to get a quick complete picture of all Fills just run signal_12_medium_res_fill_space by hand. Now all 9 of the log files have a current date/time. This signal_12_medium_res_fill_space fill has 5 Fractures but again I expect that everything is actually OK & as expected. I saw no errors during this build of the Fills. Look at the counts with all of the Fill in the design: 1590 Comps 1458 Nets 50 Float Pins 45 Shapes in pcb geom 4076 Conn 3786 Finished 71 Un-Finished 219 Guides 34 Shapes 34 Fills Geom_Ver 481 Comps_Ver 1052 Nets_Ver 647 Trc_Ver 261 Tech 1184 Note that the above MG count of Shapes and Fills is after they have been merged. There are actually 45 Shapes in the DK pcb Geom and 46 Fills in the layout. Know things that need to be fixed: - Rivet together the L1 and L12 VTERM Fills for the CPU and FPGA memory - e.g. one mem-riv rigth above each 0402 cap. - There are a couple of missing BULK_3V3 connections just above the 2x SFP connectors. - The BULK_5V0 connections to the Interposer J4 & J5 need to be made up and the BULK_1V8 and BULK_3V3 connections checked over. - The BULK_3V3 connection to the DDR4 Ref and VTERM for the FPGA memory is missing and will need to be made via a link. - There are a couple of CNST_3V3, Rescue_3V3, and BULK_5V0, BULK_3V3, and BULK_1V8 connections in the discrete logic area / ER area that will need to be made up with links but this is all small current stuff (e.g. pull-ups) and the sources are mostly all pretty close by. - The 2V5 Word Line supplies to the DDR4s are still a problem. Give up for today as email calls. Plan is to: immediately dump this set of Fills, Fix the easy power feed stuff and thus make a new master "Fills-Out" traces file, dig into merging the Ref Designator Silkscreen work by Sierra with the real moto design so that I can have too_office ready for her on Monday. ----------------------------------------------------------------- DATE: 30-Nov-2024 Topic(s): Work putting the overall design back together on Moto real Files that are part of DK have now developed on 3 different computers (moto real, moto too office, moto durand) and I need to put things back together in a way that captures all of the work: - From Sierra's work on silkscreen reference designators on moto too office I need the Components file to capture its Ref Design information and verify that all of its X, Y, Side, Orientation, and Properties information still fits with the Comps file on moto. A new verified current and correct Comps file needs to be put on all 3 machines. This is complicated because I will need to stop using my comps management system and move fully to the MG comps management system. All in all a bit early to do this because I still have more comps work to do (move a few Comps to match the new Fill Shapes and I know that there are a few close in bypass to add around the FPGA). - 8 files came from moto durand (shapes, fill gen, and FPGA BGA 1152 Geom dog-bone center shift) to merge back into the moto real machine. That is currently broken because on the moto real machine the overall build script for the FPGA BGA 1152 no longer works. So far I do not understand what is broken. Give up working on this for today. Backup with things in a bit of a mess. Counts should not have changed but I have not checked yet. ----------------------------------------------------------------- DATE: 29-Nov-2024 Topic(s): Work on L1 L12 Fill Gen script Work on the script for generating the 8 Fills for the DDR4 CA Bus Terminators. Issues getting these Fills to be correcet: - The Shape is too tight on the West side to make thermal-ties to the West most bypass cap. Edit these Shapes. - The "Vias" in these Fills are not "Flooding" correctly but duh these are actually mem-rivet ground pins. Edit the Thermal-Tie design rules for generauting these Fills. - The Termination Resistors themselves have only 1 tie. This is because these 0603 resistors are so close together on a 1.2 mm pitch. Edit the Fill - (pin, via, trace) design rules to bring the fill in tight - now about 0.25 mm of fill between Term Resistors. ----------------------------------------------------------------- DATE: 28-Nov-2024 Topic(s): Work on Fill Clean Up under the FPGA 10**9 loops through: Gen Fills, study the resulting Fills, edit PCB Geom to change Shapes, edit FPGA BGA 1152 Geom to rotate Dog-Bones, and edit Fill Design Rules where that's useful. Now things look pretty nice under the FPGA: cleaner fill connection to power pins, more room for under FPGA bypass caps, better fill separation where possible, and better use of the available pcb space. Note that under the PMT ADC you must control the Diff_ANALOG Net-Type Fill Gen Design Rules. This was missing from one of thoese fills. ----------------------------------------------------------------- DATE: 27-Nov-2024 Topic(s): More work on Fill Generation I currently think that the only fill-fill separation that needs to be controlled by the design rules at fill generation time is for the embed fills in the Signal_12 BULK_5V0 fill. All other fill-fill separation is (can be) controlled by the Shapes. Specifically the High Res Fill-Fill design rule for the Fills under the FPGA needs to be set below 0.2 mm. The under FPGA Fills that should be separated by 0.2 mm look a lot lot better if they are via drill lined up rather than BGA pad lined up (i.e. right now I have a bunch of them backwards). For zero cost I could widen the CORE_1V05 fills under the DDR4 by 0.3 mm in the direction of the gap between Data Bus and CA Bus. Can/should increase the size of the power relief on the polypropyene capacitors even more. There is room to do it. ring now only about 2.8 mm of drill-hole edge to edge of Fill. Need to understand again Slot Width parameter. In general all of the power nets are completing OK. A little known about work to do for the Interposer feeds and about 3 connections are missing in the SFP TOMcat area, (e.g. power to the LVDS-CMOS translators), and R1004 in the Rescue uProcessor area. Now work on the L1 L12 fills and their thermal relief. When the Fills are in then the traces file blows up by about 10x, i.e. the design is about 90% Fills. Need to fix Drawing #1 swap L104 - L105. Currently to removed all Fills restore to the versions: traces.traces_240 tech.tech_1163 Currently with 15 Fills turn ON: 1590 Comps 1458 Nets 50 Float Pins 45 Shapes in pcb geom 4180 Conn 3784 Finished 73 Un-Finished 323 Guides 26 Shapes 26 Fills Geom_Ver 478 Comps_Ver 1052 Nets_Ver 647 Trc_Ver 261 Tech 1184 ----------------------------------------------------------------- DATE: 26-Nov-2024 Topic(s): More Test Runs of Fill Generation Still adjusting many boarders to get things to look rational. So far I've only worked with the Medium and Very High resolution Fills. All of the PMT ADC now looks OK. None of the under FPGA Fills are turned on yet. DDR4 word-line fills look OK. Fill merging is working OK. Noticed some points: - The comp outline for the dual SFP package goes illegal placement once the main Bulk_3V3 Fill is turned on. Why ? - C1611 is the off grip comp that I've seen in the startup messages. It is a close in bottom side cap for one of the SFP packages. It is off grid by 20 nano-meters. One of the scripts is not rounding its Y value correctly. - I changed the Medium Resolution Fill-Via value from 0.25 mm to 0.20 mm - this is still more than enough Drill Hole Edge to Fill clearance but generally works out better. - I edited yesterday's entry about the changes necessary to implement the Very_High resolutions fills. I can not just embed a fill of net Bla into a larger fill of the same net and get the desired output. Doing so just gives the rational result of last fill generated wins the design rule contest. Currently to removed all Fills restore to the versions: traces.traces_240 tech.tech_1163 Currently with 15 Fills turn ON: 1590 Comps 1458 Nets 50 Float Pins ?? Shapes 4423 Conn 3693 Finished 127 Un-Finished 603 Guides 15 Shapes 15 Fills Geom_Ver 473 Comps_Ver 1052 Nets_Ver 647 Trc_Ver 253 Tech 1176 ----------------------------------------------------------------- DATE: 25-Nov-2024 Topic(s): Power Fill Generation - Very High Res Making 8 more Shapes because I need the Very High resolution Fills under both the DDR4 Memory Chip area and under the area under the PMT ADC. Specifically: - Split up the existing CORE_1V05 fill 3 sections (2 new) all on Signal_11: Make a High res section under the FPGA. Make a Very_High res section under just the DDR4 chips themselves. Make a High res section under the CA Bus terminators and down into L101. Recall - you can not embed a Fill of net Bla into a larger Fill of the same net. The design rules of the last fill generated (the output one) will just be used for all of the fill area - including the inner embeded fill. - Split up the ADC_ANALOG_1V8 fill into 2 sections both on Signal_11 Add a Very High resolution section just under the PMT ADC itself Notch the existing ADC_ANALOG_1V8 fill to just overlap the new shape. - Split up the ADC_DIGITAL_1V0 fill into 2 sections both on Signal_11 Add a Very High resolution section just under the PMT ADC itself Notch the existing ADC_DIGITAL_1V0 fill to just overlap the new shape. - Split up the ADC_DIGITAL_1V8 fill into 2 sections both on Signal_12 Add a Very High resolution section just under the PMT ADC itself Notch the existing ADC_DIGITAL_1V8 fill to just overlap the new shape. - Split up the ADC_ANALOG_1V0 fill into 2 sections both on Signal_12 Add a Very High resolution section just under the PMT ADC itself Notch the existing ADC_ANALOG_1V0 fill to just overlap the new shape. - Split up the existing BULK_1V2 fill 3 sections 5 sections (4 new) all on Signal_12: Make 2 a High res sections under the FPGA. Make 2 Very_High res section under just the DDR4 chips themselves. Make a High res section under the CA Bus terminators and down into DCDC3. I think that we are now at about 45 Fill Shapes. Run a large number of Fill Generation Tests - fix various boarders. When this is finished, removed all Fills by restoring to the versions: traces.traces_240 tech.tech_1163 Once restored to these versions the routing counts should read: 1590 Comps 1458 Nets 50 Float Pins 43 Shapes 4493 Conn 3549 Finished 213 Un-Finished 731 Guides ----------------------------------------------------------------- DATE: 23,24-Nov-2024 Topic(s): Power Fill Generation I've rewritten all of the Fill Generation script files so that there are more of them but each one is simpler and easier to maintain. The Fill Generation scripts are now: generate_fills_signal_11_very_high_res.sh generate_fills_signal_11_high_res.sh generate_fills_signal_11_medium_res.sh generate_fills_signal_12_very_high_res.sh generate_fills_signal_12_high_res.sh generate_fills_signal_12_medium_res.sh generate_fills_signal_3_high_res.sh Generates 1 Fill from 1 Shape generate_fills_signal_1_and_10_medium_res.sh generate_all_fills_on_all_layers.sh Because of their notes and comment lines for now I also need to save the otherwise not used files: generate_test_fills.sh save for comments and notes generate_all_fills_on_signal_3.sh save for comments and notes ----------------------------------------------------------------- DATE: 22-Nov-2024 Topic(s): Work on Generating the Fills, There are two remaining issues: - The scripts are too complicated because they are handling too many fills at one time. This weekend I will convert to using more scripts but each one will be simple and handle only a small number of directly related Fills - I need to finalize the Fill Design Rules for Fill generation: Notes: 1. So far we are Not embeding traces in any of the DK Fills. Thus I do not really care about the Fill-Trace Design Rule - just make it something reasonable. 2. So far we have Not allowed any of the Fills to approach either the Power Input "High Voltage" section or the PMT Analog Input section - thus when Generating the Fills I do Not need to adjust the Design Rules for either the Diff_ANALOG or the POWER_HV Net_Types. 3. I only need to adjust the Design Rules for the Diff_Pair_HS and the DEFAULT_NET_TYPE Net_Types. 4. The 13 GHz traces are Not part of any Fill issues because they are only on the Top L1 layer and they do Not involve any drills or vias. P.S. Should I remove the Solder Mask over the 13 GHz traces ? 5. The Fill-Fill Design Rule matters in many locations but it matters in two different ways: - The fills under the FPGA need to have a 0.1 mm fill-fill design rule to allow the actual Shape boarders to control the Fill boarders. - The Fills that have an embeded Fill, e.g. the BULK_5V0 Fill with its embeded CNST_3V3 and ER_3V3 Fills need to have a Fill-Fill Design Rules that actually controls this separation, e.g. 0.4 or 0.5 mm. 6. The Fill-Pad and Fill-Via Design Rules need to be set per Net_Type and for the various fill resolutions that are needed. This is complicated by the fact that the Fill-Pad & Fill-Via relief that is specified in the Design Rules is wrt pads that generally do Not exist on the pcb layers where we are making these Fills (note the L1 L12 Fills for the DDR4 Terminators are an exception). ---> That is we specify the desired gap between Fill and Pad but what we care about is the gap between Fill and the perimeter of the Drill Hole because the pad is not there. For the Medium resolution Fill we will generally be working around Pins or Vias of the size: via_0mm60, via_0mm65, or via_0mm79. The Drill Dia and Pad Dia for these is: Actual Gap between the Edge of the Drill Hole and the Fill resulting from a Fill-Bla Design Rule of: Drill Pad ------------------------------------- Dia. Dia. 0.14 0.18 0.20 0.25 0.30 Design Rule ----- ----- ----- ----- ----- ----- ----- via_0mm60 0.30 0.60 0.29 0.33 0.35 0.4 0.45 Actual Gap via_0mm65 0.30 0.65 0.315 0.355 0.375 0.425 0.475 Actual Gap via_0mm79 0.40 0.79 0.335 0.375 0.395 0.445 0.495 Actual Gap For the High resolution Fill we will generally be working around Pins or Vias of the size used in the 1.0 mm Pitch BGA Geometry for the FPGA. The Drill Dia and Pad Dia for this is: Actual Gap between the Edge of the Drill Hole and the Fill resulting from a Fill-Bla Design Rule of: Drill Pad ------------------------------------- Dia. Dia. 0.13 0.14 0.18 0.20 0.25 Design Rule ----- ----- ----- ----- ----- ----- ----- 1.0 mm Pitch 0.30 0.58 0.27 0.28 0.32 0.34 0.39 Actual Gap "normal" Dog-Bone Via Resulting Fill Web Width 0.16 0.14 0.06 none none Web Width between 1.0 mm spaced adjacent pins For the Very High resolution Fill we will generally be working around Pins or Vias of the size used in the 0.8 mm Pitch BGA Geometry for the PMT ADC and for the DDR4 memory chips. The Drill Dia and Pad Dia for this is: Actual Gap between the Edge of the Drill Hole and the Fill resulting from a Fill-Bla Design Rule of: Drill Pad ------------------------------------- Dia. Dia. 0.105 0.11 0.115 0.14 0.18 Design Rule ----- ----- ----- ----- ----- ----- ----- 0.8 mm Pitch 0.23 0.44 0.21 0.215 0.22 0.245 0.285 Actual Gap Dog-Bone Via PMT ADC & DDR4 Resulting Fill Web Width 0.15 0.14 0.13 0.08 none Web Width between 0.8 mm spaced adjacent pins Important Notes: --> For a given Fill Generation Resolution the Drill Hole Edge to Fill Clearance is typically (almost always) the smallest for the smallest via or pin under consideration. That is because all of the larger vias or pins have a thicker ring width (donut width) around their drill hole than the smallest via or pin has. The Drill Hole Edge to Fill clearance is the sum of the ring width and the Fill to Bla design rule clearance specification. Thus in setting the design rule specification for generating the various Fill resolutions you basically only need to consider the smallest pin or via that is used in the area that is covered by that Fill resolution. --> The important reason for for having different design rules for Fill-Via and Fill-Pin is not the clearance around their Drill Hole but rather the spacing between them. Vias are frequently spaced further apart than Pins, thus for a given Drill Hole to Fill clearance I typically have a thicker Web with the Vias, thus you can often aford a larger Drill Hole to Fill clearance with the Vias and still have a sufficiently thick Web for good power plane conductivity. --> Where possible it is a good idea to hold the Fills further back from the High-Speed Differential signals to minimize the impedance bump of the vias and pins in thesse routes. Note: The rest of the details about generating Fills is in ----- the comments in the file: generate_test_fills.sh For now to get started I will use the following Design Rules for the Fill to Bla separation (the arguments are shown in the order used by the change_net_rules function call: Medium Resolution: fill-fill fill-via fill-trc fill-pin --------- -------- -------- -------- 0.50 0.25 0.30 0.25 DEFAULT_NET_TYPE 0.50 0.35 0.35 0.35 Diff_Pair_HS High Resolution: fill-fill fill-via fill-trc fill-pin --------- -------- -------- -------- 0.40 0.20 0.30 0.13 DEFAULT_NET_TYPE 0.40 0.25 0.35 0.14 Diff_Pair_HS Very High Resolution: fill-fill fill-via fill-trc fill-pin --------- -------- -------- -------- 0.40 0.20 0.30 0.11 DEFAULT_NET_TYPE 0.40 0.23 0.35 0.11 Diff_Pair_HS For reference the Hub Fill design rules were: fill-fill fill-via fill-trc fill-pin --------- -------- -------- -------- 0.50 0.21 0.30 0.25 Norm - Med Res 0.50 0.35 0.35 0.35 HiSpd - Med Res 0.40 0.20 0.30 0.14 Norm - Hi Res 0.40 0.23 0.35 0.18 HiSpd - Hi Res ----------------------------------------------------------------- DATE: 21-Nov-2024 Topic(s): Work on Generating the Fills, Meeting with the new design check students I had major problems getting the Fill Generation Scripts running. There was an issue of the "Logical Name" for the design - it has a "0" in it that I do not understand - but I do understand why I may have never seen this problem before. The main problem was getting straight the order of the 10 basic numeric arguments that describe the Design Rules for a given Net_Type. The order of these 10 numeric values is different between a call to the function that Sets them and the order in which they are stored in the Technology file. All of this is now fully understood and working. I also had a lack of full understanding of the argument list in the call to Setup the Shape to Area Fill conversion and the call to Setup the Thermal-Ties. I had notes from previous designs about all of the above but more features are needed for the DK desigh (e.g. surface layer Fill with SMD component connections). Full details are in the comments in the file, "generate_test_fills.sh", in the .../Work/Generate_Fills/ sub directory. I'm not going to copy these notes to this log file at this time. Had a meeting with Dan Salazar and the two new students. One will start on the Datasheet vs Geom and the other on the Silk Ref Desig. The Moto_too is running OK for now and I found a better tube for it. ----------------------------------------------------------------- DATE: 20-Nov-2024 Topic(s): More Fill Work, Meeting with Juanne and Dan, Moto_too Last night finished up the FPGA Dog-Bone rotations so that I could now move and clean up the Fills under the FPGA and Signal_11. This now looks a lot better. Recall that the Fills under the FPGA are: L6 Signal_11 XCVR_1V05 CORE_1V05 BULK_3V3 Banks: #1, #2, #3, #5, #7 DIGITAL_2V5 Bank #9 Aux L7 Signal_12 BULK_1V2 Banks #0 & #6 FPGA_1V8 Bank #9, Program & HSIO Aux L4 Signal_3 ANALOG_2V5 FPGA PLLs & PNVM (whatever that is) XCVR Plls & XCVR Clk Buffers A big issue is that it will take 3 separate resolutions for each Net_Type - not 2. We need an even higher resolution under the 0.8 mm pitch DDR4 and PMT ADC chips. So I need: Medium Resolution for the normal general stuff High Resolution for the 1.0 mm FPGA Very High Resolution for the 0.8 mm DDR4 and PMT ADC I *think* that I can just add simple rectangular fills at Very High Resolution around the DDR4 and PMT ADC, do them first, and then do the complicated fills at High & Medium resolution and everything will merge and work out OK. All existing Fill Shapes are now stable enough to have a unique point identified and put into the Generation Scripts. I think that I want to make a simple test script (e.g. just one Word Line Fill or something like that) and verify that things are working OK. For reference the Hub Fill design rules were: fill-fill, fill-via, fill-trc, fill-pin --------- -------- -------- -------- 0.40 0.23 0.35 0.18 HiSpd - Hi Res 0.40 0.20 0.30 0.14 Norm - Hi Res 0.50 0.35 0.35 0.35 HiSpd - Med Res 0.50 0.21 0.30 0.25 Norm - Med Res Had a 2nd meeting with Dan and Juanne about: check Geoms, check Nets, place Silk Ref Designators. They have now seen each job. Moto_too office edition turned back ON OK today. It had been last started on 31-July-2024 for the previous attempt and checking the design. I put today's current version of all design files on Moto_too and on the DK web site. Geom_Ver 463 no other changes ----------------------------------------------------------------- DATE: 19-Nov-2024 Topic(s): More Fill work, meeting with Dan and Juanne More work on the Bulk 1V8, 3V3, 5V0 power Fills and things are finally starting to look rational. Now working on the FPGA center re-arranging the dog-bones for a better connection to the Fills. Specifically rotate: P17, R17, T17, U17, V17, W17, Y17 to be SE R18, T18, U18 " " " P19, R19, T19, U19 " " " R20, T20, U20 " " " P21, R21, T21, U21 " " " R22, T22, U22 " " " P23, R23, T23, U23 " " " R24, T24, U24 " " " I will make these 31 dog-bone rotations in a separate file to keep them separate from the other reasons that there are dog-bone rotations in this desing, i.e. so it is easy to remove if I need to. The point of this is to give a much better fit on L6 Signal_11 for: CORE vs DIGITAL_2V5 to the North - Bank #9 Aux supply CORE vs Bulk_3V3 to the West and to the North Banks #1, #2, #3, #5, and #7 Juanne, Dan, and I talked about help getting the design out the door: check geoms, check net list, and silkscreen reference designators. They will stop by on Wednesday at 1:30 for a demo of each of these work baskets. 1590 Comps 1458 Nets 50 Float Pins 35 Shapes 4493 Conn 3549 Finished 213 Un-Finished 731 Guides Geom_Ver 459 Comps_Ver 1052 Nets_Ver 647 Trc_Ver 239 ----------------------------------------------------------------- DATE: 18-Nov-2024 Topic(s): Net_Types and Design Rules I need to clean up the various Net_Types and their Design Rules that are used in the DK design and get all of these values correctly entered into the Fill Generation scripts. Recall that there are typically 3 sets of Design Rules for each Net_Type: normal of Routing and DRC runs, Medium Resolution Fill Generation, and High Resolution Fill Generation. Currently the DK Net_Types Design Rules that are in effect are: Power Fill DEFAULT ------------------------------------------------- ROUTING MEDIUM Res. HIGH Res. ---------------------- ---------------------- ---------------------- PIN VIA TRC FILL PIN VIA TRC FILL PIN VIA TRC FILL PIN 1.0 VIA 0.19 0.32 TRC 0.11 0.2 0.185 FILL 0.35 0.35 0.5 0.5 Power Fill DIFF_ANALOG ------------------------------------------------- ROUTING MEDIUM Res. HIGH Res. ---------------------- ---------------------- ---------------------- PIN VIA TRC FILL PIN VIA TRC FILL PIN VIA TRC FILL PIN 1.0 VIA 0.2 0.28 TRC 0.11 0.3 0.21 FILL 0.14 0.2 0.3 0.4 Power Fill DIFF_PAIR_HS ------------------------------------------------- ROUTING MEDIUM Res. HIGH Res. ---------------------- ---------------------- ---------------------- PIN VIA TRC FILL PIN VIA TRC FILL PIN VIA TRC FILL PIN 0.5 VIA 0.38 1.0 TRC 0.12 0.26 0.21 FILL 0.35 0.35 0.5 0.5 Power Fill POWER_HV ------------------------------------------------- ROUTING MEDIUM Res. HIGH Res. ---------------------- ---------------------- ---------------------- PIN VIA TRC FILL PIN VIA TRC FILL PIN VIA TRC FILL PIN 1.0 VIA 0.5 0.32 TRC 0.5 0.5 0.5 FILL 1.0 1.0 1.0 0.8 There are a number of obviously problems with these Design Rule values. I can not imagine where some of these numbers came from. I will wait until doing the 10**9 runs of the DRC to correct these Design Rule values. Currently the differential clocks and differential 1 GBps Enet are using just the default rules - which may be a very bad idea. The CA and Data Memory Buses should have had their own Net_Type(s). Vias Enabled for Routing: via_2mm2_hv, via_2mm2, via_1mm1, via_0mm79, via_0mm65, via_0mm60, Physical Layers Enabled for Routing: L1 Signal_1 Physical_1 L3 Signal_2 Physical_2 L4 Signal_3 Physical_3 L9 Signal_8 Physical_11 L10 Signal_9 Physical_12 L12 Signal_10 Physical_13 There are "High Voltage" nets in the Power Input Filter that were never assigned the (NET_TYPE, 'POWER_HV') Net_Type. Edit the power_input_net_list.txt file to fix this and to more clearly label the input power as + & - 50 Volt. Push on clean up of the Fills especially the Bulk_3V3 and the Bulk_5V0 around the perimeter. That went OK and now a bunch of little stuff (e.g. L1101 in the BB ADC and L1463 feeding J4 are connected) and the Bulk_1V8 is connected to the input of the Timing Generator filters - but there is NO path for a Bulk_1V8 to the filters that feed Interposer J4 and J8. I can fix this at some cost to the Bulk_5V0 distribution and the Bulk_1V8 path to the USB Phy and Port Hub is going to be a bit thin but it only feed the Clock level set circuits for the USB components. There still is NO path to get BULK_3V3 to the Term & Ref supply for FPGA DDR4. There still is NO path to get the Digital_2V5 to the 2x Fills that distribute the DDR4 Word Line supplies. Both of those are hopeless at this time. The basic plan of the BULK_1V8 re-route is to do it on Signal_12: the Northern boarder of the BULK_5V0 fill on Signal_12 will be moved South so that it is just above the feed points for DCDC Converters #4, #5, and #6. The BULK_1V8 Fill Addition will be between this new BULK_5V0 boardwer and the North edge of the board and can wrap around the West edge to feed the USB Phy and Port Hub Clock level set circuits.. The 5V0 feeds to Interposer J4 and J5 will have to be via "linked" connections perhaps on L1 or L12 but that sould be OK. This new added BULK_1V8 fill around the very North edge will also pick up the various Level Translators in this area: i.e. U1455, U1456, U1457, and U1458. 1590 Comps 1458 Nets 50 Float Pins 35 Shapes 4493 Conn 3549 Finished 213 Un-Finished 731 Guides Geom_Ver 453 Comps_Ver 1052 Nets_Ver 647 Trc_Ver 239 ----------------------------------------------------------------- DATE: 13:16-Nov-2024 Topic(s): P-ONE University of Chicago Meeting ----------------------------------------------------------------- DATE: 12-Nov-2024 Topic(s): Work on the Power Fills The Bulk_3V3 fill is now in pretty good shape. It merges with the 3V3 Fill under the FPGA pretty will. I believe that there are only 2 "linked" connections: FPGA DDR4 Ref & Term Supply and the BB Audio ADC. It may be possible to connect BB Audio ADC via a Fill but not the FPGA DDR4 Ref & Term Supply. The Bulk_5V0 still has a number of problems; - The thin strips of this Bulk_5V0 Fill that are West of the CNST_3V3 & RESCUE_3V3 Fills are of almost no use - too thin. - Must focus on the BULK_5V0 Fill that is East of the CNST_3V3 & RESCUE_3V3 Fills but that is only about 13.0 mm wide but could be wider by about 2 mm. - There are some BULK_5V0 loads within the CNST_3V3 Fill on Signal_12 and these will need to be "linked" out (all low current). 1590 Comps 1458 Nets 50 Float Pins 35 Shapes 4493 Conn 3549 Finished 213 Un-Finished 731 Guides Geom_Ver 447 Comps_Ver 1052 Nets_Ver 646 Trc_Ver 239 ----------------------------------------------------------------- DATE: 11-Nov-2024 Topic(s): Fill Shapes and Perimeter Rivets Finish upper and lower USB connectors This target is making a good match between the Gnd Isolation Slits and the boarders of the Power Fills. 1590 Comps 1458 Nets 50 Float Pins 35 Shapes 4493 Conn 3549 Finished 208 Un-Finished 736 Guides Geom_Ver 443 Comps_Ver 1052 Nets_Ver 646 Trc_Ver 238 ----------------------------------------------------------------- DATE: 9,10-Nov-2024 Topic(s): Work on Gnd Isolation and Fill Shapes ----------------------------------------------------------------- DATE: 8-Nov-2024 Topic(s): Routing work Clean up the Ground Slits for the Isolated RS-485 and Power Input. I should have done this much earlier as the final location of these ground slits drives a lot of other routing details. Clean up the Isolated RS-485 Power Supply routing and component placement so that I can have more rational ground isolation slits. Clean up other routing that is associated with or located near the ground isolation slits. Work on the 3V3 fill. Notes that the "source code" for a number of fills (e.g. 3V3 & 1V8) is in a number of sections. These different sections frequently require different fill properties, e.g. different resolutions. The various sections of the fill for a given net are set to "Merge" at plot generation time. I do not think that the order of generation of the various fills for a given net makes any difference (but I may have forgotten something). There are other situations where the order of fill generation makes a big difference. 1584 Comps 1458 Nets 50 Float Pins 35 Shapes 4493 Conn 3544 Finished 212 Un-Finished 737 Guides Geom_Ver 443 Comps_Ver 1050 Nets_Ver 645 Trc_Ver 236 ----------------------------------------------------------------- DATE: 7-Nov-2024 Topic(s): Working on routing and its cleanup and the remaining required Ground Isolation slits. Need to work on making Release #3 data before the Chicago trip. Nathan said that he may have a new student to start working on checking the DK design. 1584 Comps 1458 Nets 50 Float Pins 34 Shapes 4493 Conn 3544 Finished 212 Un-Finished 737 Guides Geom_Ver 438 Comps_Ver 1048 Nets_Ver 645 Trc_Ver 233 ----------------------------------------------------------------- DATE: 6-Nov-2024 Topic(s): Routing and clean up of Diff Signals Barbarians are at the gate. 1584 Comps 1458 Nets 50 Float Pins 34 Shapes 4467 Conn 3473 Finished 211 Un-Finished 783 Guides Geom_Ver 437 Comps_Ver 1040 Nets_Ver 642 Trc_Ver 227 ----------------------------------------------------------------- DATE: 5-Nov-2024 Topic(s): Routing the Differential Signals, e.g. Enet and Clocks Not current in the Comps files: R921, R922, C955, C956, C955B, C956B, C1623, and C1624. 1584 Comps 1458 Nets 50 Float Pins 34 Shapes 4468 Conn 3463 Finished 212 Un-Finished 793 Guides Geom_Ver 437 Comps_Ver 1036 Nets_Ver 642 Trc_Ver 222 ----------------------------------------------------------------- DATE: 4-Nov-2024 Topic(s): Continue work on final placement and routing Restore from Durand: fpga_cpu_and_bypass_comps.txt timing_generator_comps_fixed.txt timing_generator_nets_fcg1152.txt disco_fill_shapes_timing_gen_signal_11_12.txt 1584 Comps 1458 Nets 50 Float Pins 34 Shapes 4463 Conn 3436 Finished 219 Un-Finished 808 Guides Geom_Ver 436 Comps_Ver 1029 Nets_Ver 642 Trc_Ver 217 ----------------------------------------------------------------- DATE: 2,3-Nov-2024 Topic(s): Timing Gen and FPGA Bulk Bypass Comps, Edit and add to Time Gen Power Fills 1584 Comps 1458 Nets 50 Float Pins 34 Shapes 4440 Conn 3383 Finished 190 Un-Finished 867 Guides ----------------------------------------------------------------- DATE: 1-Nov-2024 Topic(s): Routing in the Timing Generator 1580 Comps 1458 Nets 50 Float Pins 33 Shapes 4428 Conn 3383 Finished 197 Un-Finished 848 Guides Geom_Ver 433 Comps_Ver 1019 Nets_Ver 637 Trc_Ver 212 ----------------------------------------------------------------- DATE: 31-Oct-2024 Topic(s): Routing in the Timing Generator Another Interposer Cabling meeting at noon today. They are still quite interested in an adaptor board. 1580 Comps 1458 Nets 50 Float Pins 33 Shapes 4423 Conn 3339 Finished 177 Un-Finished 907 Guides Geom_Ver 433 Comps_Ver 1011 Nets_Ver 634 Trc_Ver 207 ----------------------------------------------------------------- DATE: 30-Oct-2024 Topic(s): Add more perimeter rivets, Route more first level LC power filters, Route Crystal Oscillators, 6x DCDC Converter wider input L traces, Edit 6 of the File Shape Files 1580 Comps 1458 Nets 50 Float Pins 33 Shapes 4420 Conn 3291 Finished 175 Un-Finished 954 Guides Geom_Ver 433 Comps_Ver 1003 Nets_Ver 632 Trc_Ver 202 ----------------------------------------------------------------- DATE: 29-Oct-2024 Topic(s): Route the 6x DCDC Converters and add the edge rivets North and West Interposer Cable meeting with lots of people. Nothing decided. Folks like adapter brds and lots of versions of them. Folks do not like actual EE analysis or thinking about actual EE questions. Running the mechanical Finite Element Analysis to learn what is actually possible in the design of the steel stiffening plate is not thought to be a good idea so we must choose solutions without knowing what is possible. 1553 Comps 1458 Nets 50 Float Pins 33 Shapes 4399 Conn 3247 Finished 171 Un-Finished 981 Guides Geom_Ver 432 Comps_Ver 998 Nets_Ver 630 Trc_Ver 199 ----------------------------------------------------------------- DATE: 28-Oct-2024 Topic(s): Work on DCDC-5 Converter Routing Work on cleaning up the DCDC Converter routing. Move 5 comps in the converter for cleaner route. Input filter comps are as tightly coupled to the converter's Vin and Gnd as I can get them. The output filter caps are split between Vout - Converter Gnd and Vout - board Ground Planes. 1536 Comps 1458 Nets 50 Float Pins 33 Shapes 4140 Conn 2672 Finished 165 Un-Finished 1303 Guides Geom_Ver 431 Comps_Ver 990 Nets_Ver 626 Trc_Ver 195 ----------------------------------------------------------------- DATE: 26,27-Oct-2024 Topic(s): Work on Memory and Power Supplies Change the 2V5 Memory Fills so that the CPU fill goes further West and the FPGA fill goes further East. This is needed for the new scheme of feeding the Word-Line supply into the memory array. Start work on the final placement of the bulk bypass for Banks #0 and #6. There is nice clean space for this especially on Bank #6. These are the bulk caps outside of the BGA array. Start routing of the 6x DCDC Converters with DCDC-5. These should all be 99% the same and require only L1 and L12. Still the issues of: how directly to tie the output caps to the DCDC Converter's Ground pin vs DK's 4x Ground Planes and whether or not to slot the Ground Planes around the sides of the converters ? Bring Trace and Comps files from Durand to Office. ----------------------------------------------------------------- DATE: 25-Oct-2024 Topic(s): Memory System Clean Up Work Cleaning up a lot of the auxiliary type stuff (e.g. word 2V5 power routing and bypass cap connections) in the CPU Memory and then in the FPGA Memory. There is a lot of this kind of work to do. Learn via Nathan that there is a new cabling scheme to connect the Interposers to the DK board. 1536 Comps 1458 Nets 50 Float Pins 33 Shapes 4100 Conn 2573 Finished 164 Un-Finished 1363 Guides Geom_Ver 430 Comps_Ver 986 Nets_Ver 625 Trc_Ver 191 ----------------------------------------------------------------- DATE: 24-Oct-2024 Topic(s): Memory system work Gave up and moved the DDR4 Reference and Terminator power supplies again. Work on the bulk bypass caps mostly in the CPU memory. Work on CPU Mem: Reset_B, TEN, Alert_B, Ref, & Term connections. 1536 Comps 1458 Nets 50 Float Pins 33 Shapes 4099 Conn 2566 Finished 159 Un-Finished 1374 Guides Geom_Ver 430 Comps_Ver 984 Nets_Ver 625 Trc_Ver 189 ----------------------------------------------------------------- DATE: 23-Oct-2024 Topic(s): DDR4 Terminator & Reference Supplies Restore the disco_fill_shapes_filters_2V5_signal_11.txt file. Make final components placements for the CPU and FPGA DDR4 Reference and Terminator power supplies and route them. Recall that on DK I've been using: 0402 0.4 mm trc & 0mm65 via, 0603 0.6 mm trc & 0mm79 via, 1206 0.8 mm trc & 0mm79 via, V case Nx 1.2 mm trc & 1mm1 via. 1536 Comps 1458 Nets 50 Float Pins 33 Shapes 4086 Conn 2513 Finished 148 Un-Finished 1425 Guides Geom_Ver 430 Comps_Ver 973 Nets_Ver 623 Trc_Ver 185 ----------------------------------------------------------------- DATE: 22-Oct-2024 Topic(s): CPU Memory and other Clean Up Moved DCDC2, DCDC3, and L101 North by 1.5 mm. This gives more clearance for the TOMcat fiber optic connector and can now move R1731 back East by a few tenths mm so that it lines up. Fully straightened out the CPU and FPGA memory clocks and strobes in the net lists. For now, just for net length calcualations, all memory clocks and strobes are not connected to their Terminators. They must be re-connected once final trace lengths are calculated. In the net lists - the signals: TEN, RESET_B, ALERT_B are all connected to their Pull-Up and Pull-Down resistors and these resistors by be put into final posistion and connected via trace. As noted before: TEN, RESET_B, and ALERT_B have no skew or trace length match requirements. There is some confusion about the required value of their Pull-Up or Pull-Down resistors. TEN - Micron: if NOT used then directly Ground if Used then 1k Ohm PD to Ground Xilinx: 500 Ohm PD to Ground MicroChip: 10k Ohm PD to Ground RESET_B - Micron: Requires a PD to Ground to keep it Low during power supply ramp up. Xilinx: 4.7k Ohm PD to Ground MicroChip: 10k Ohm PD to Ground ALERT_B - Micron: Requires a PU Xilinx: 50 Ohm PU to 1V2 (Why the 50 Ohm Term ?) MicroChip: 4.7k Ohm PU to 1V2 Disco-Kraken is using: TEN - for CPU Mem 22 Ohm PD to Ground (CPU DDR4 Controller does not support or drive the TEN signal) for FPGA Mem 4.7k Ohm PD to Ground RESET_B - 4.7k Ohm PD to Ground ALERT_B - 4.7k Ohm PU to 1V2 Power Fill Work: Make a slight correction to the location of the CA Bus Terminator fill locations on L1 and L12. Add the CA Bus Terminator BYPASS fills on L1 and L12 for both the CPU and FPGA Memories. Add the 2V5 Wordline fills on L6 Signal_11 for both CPU and FPGA. Typing too fast and I lost the file disco_fill_shapes_filters_2V5_signal_11.txt I will recover it from the machine at home tonight instead of from tar. There should now be 33 fills in the design but until I recover that file 2 of them will be gone. 1536 Comps 1458 Nets 66 Float Pins 33 Shapes 4063 Conn 2324 Finished 143 Un-Finished 1596 Guides Geom_Ver 425 Comps_Ver 965 Nets_Ver 618 Trc_Ver 183 ----------------------------------------------------------------- DATE: 21-Oct-2024 Topic(s): Work on CPU Mem bypass caps Working on Fills for both the power and ground to both CA Bus Terminator arrays. Looking at Digital_2V5 fills on L6 Signal 11 for both DDR4 memory arrays. That would fix the local wordline distribution but it's still not clear how to get 2V5 down below the FPGA/CPU. There is enough space that I need to move: DCDC2, DCDC3, and L101 with its 8x PVAs all North by 2 or 3 mm to provide more clearance for the TOMCat Optical Cable. 1520 Comps 1458 Nets 51 Float Pins 28 Shapes 4062 Conn 2324 Finished 143 Un-Finished 1595 Guides Geom_Ver 421 Comps_Ver 961 Nets_Ver 617 Trc_Ver 183 ----------------------------------------------------------------- DATE: 19,20-Oct-2024 Topic(s): Work on close in bypass caps for the CPU Memroy & adding current return vias Work on understanding the unconnected pin count. The current unconnected pin count is the 23 capacitors C107:C129 is 46 pins of unconnected FPGA bypass caps (yet to be assigned FPGA bypass caps) and currently unconnected R326, R327, R426, R427 DDR4 Memory Clock Terminator resistors. 1500 Comps 1458 Nets 51 Float Pins 28 Shapes 4062 Conn 2254 Finished 143 Un-Finished 1655 Guides ----------------------------------------------------------------- DATE: 18-Oct-2024 Topic(s): CPU Memory, SMA, PMT ADC & cables Work on the CPU Memory: Terminators and close in bypass capacitors. Talk with Nathan about PMT ADC analog input signal protection, cable routing and Harwin connectors. Made the first Harwin to SMA cable for the test setup. 1487 Comps 1458 Nets 56 Float Pins 28 Shapes 4050 Conn 2254 Finished 143 Un-Finished 1653 Guides Geom_Ver 420 Comps_Ver 948 Nets_Ver 610 Trc_Ver 180 ----------------------------------------------------------------- DATE: 17-Oct-2024 Topic(s): CPU Memory Routing In the CA Bus weave between the two memory chips (both CPU and FPGA) it looks like at the edges one could straighten out some of the jogs - where there is no issue of overlap. But recall that we want the exact same delay, on all CA Bus Signals, between the two memory chip. So keep the routing of the weave the same for all CA Bus Signals - even if it looks like you could remove some jogs at the East and West edges. A route of the CPU Mem CA Bus is now in the design but it can still be improved a lot. Current return vias are not in. 1487 Comps 1431 Nets 82 Float Pins 28 Shapes 4027 Conn 2229 Finished 143 Un-Finished 1655 Guides Geom_Ver 420 Comps_Ver 937 Nets_Ver 607 Trc_Ver 178 ----------------------------------------------------------------- DATE: 16-Oct-2024 Topic(s): CPU Memory Routing All 4 CPU Memory Data Buses are in and look OK. They basically look better than the Data Buses in the FPGA Memory. Start the CPU Memory Command & Address Bus. The main CA Bus routing issue at this time is escaping the FPGA. We have to go into the 14th ring, the Data Buses are just to the South and Bank #5 (Clock and TomCat Enet) is just to the North right at the perimeter. Recall that Bank #4 (unused small CPU I/O Bank) is also just to the North. On the West side, the split between NW and SW Dog-Bones is at the U to V boarder. A plain to help with the CA Bus escape is to rotate the Dog-Bones for Bank #5 and for the unused Bank #4 to the NW. This should be easy because Bank #5 is small and the only dog-bones in bank #4 that need to rotate are only a couple of power and grounds. The unused "BGA Pad Only" pins do not need to be rotated. So look at rotating the following pins to have NW dog-bones: Bank #5 V3 W2, W3, W4, W5 Y2, Y3, Y4 AA5, AA6 Bank #4 AA11 (and maybe Y9) To allow the above rotations I must also rotated in Bank #2: V3, V4, V5, V6, opt V7, V8, V9 W6, opt W7, W8, W9 This is a total of about 16 pins (22 with options) and the rotations can be done more or less autonatically in the final_manual_dog_bone_rotations.take file. The West 2 columns (columns 1 &2) can be setup for escape on the Top layer by the following: AA1 to a West dog this is a ground pin AA2 to a pad only AB1 & AB2 to pad only AC1 & AC2 are clock pins and will remain SW dog-bones AD1 to pad only AD2 is a Ground pin and will remain SW dog-bone 1487 Comps 1431 Nets 82 Float Pins 28 Shapes 4027 Conn 2204 Finished 168 Un-Finished 1655 Guides Geom_Ver 420 Comps_Ver 936 Nets_Ver 607 Trc_Ver 173 ----------------------------------------------------------------- DATE: 15-Oct-2024 Topic(s): CPU Memory Routing It is now clear that the CPU Memory Data Buses are not routable as the components are currently arranged. Some of the D0-D15 vs D16-D31 over lap can be cleaned up by swapping U401 & U402. Before making this swap backup the traces 161 and dump the old special backups.. Three of the CPU Memory Data Buses are now in and look OK - working on the 4th. 1487 Comps 1406 Nets 218 Float Pins 28 Shapes 3916 Conn 2172 Finished 148 Un-Finished 1596 Guides Geom_Ver 418 Comps_Ver 935 Nets_Ver 604 Trc_Ver 170 ----------------------------------------------------------------- DATE: 14-Oct-2024 Topic(s): Routing CPU Memory I've used straight South and straight West dog-bones so that the outer ring can via into the pcb while the 2nd ring escapes on L1 - but I need to make these pin/pad stacks with both a signal version (thinner dog-bone) and a power/ground version (thicker dog-bone). The FPGA/CPU chips pin out for the CPU's DDR4 memory is a mess. Not only does the D0:D15 need to cross over the D16:D31 but also D16:D23 needs to cross over D24:D31. No rotation of the memory chips fixes this cross over and does not result in a CA Bus cross over - except to put the chips on the bottom side. 1487 Comps 1406 Nets 218 Float Pins 28 Shapes 3916 Conn 2161 Finished 141 Un-Finished 1614 Guides Geom_Ver 417 Comps_Ver 931 Nets_Ver 596 Trc_Ver 161 ----------------------------------------------------------------- DATE: 12,13-Oct-2024 Topic(s): Work on the Fill Generation scripts, Routing CPU Mem D24:D31 For DK I will keep the Fill Generation scripts in their own directory as they are getting rather complicated. Include an aa_text file with just: Phys Layer, Signal Layer, NET, Resolution, Unique X,Y Point, i.e. a crisp description of all Fills that need to be generated. 1482 Comps 1388 Nets 249 Float Pins 28 Shapes 3898 Conn 2145 Finished 148 Un-Finished 1605 Guides Geom_Ver 415 Comps_Ver 929 Nets_Ver 593 Trc_Ver 157 ----------------------------------------------------------------- DATE: 11-Oct-2024 Topic(s): Work on the large bulk filter caps, talk with Hughes The first order bulk filter caps are now in for the FPGA_1V8 from L103, the Analog_2V5 from L104, and the Digital_2V5 from L105. Still the issue of Digital_2V5 getting to the distribution wiring for this net in the DDR4 array. Need to push the card wide routing of 1V8 and 3V3. Card wide 1V8 is started on Signal_12 that it shares with card wide 5V0. The perimeter on Signal_11 is open for 3V3 which matches the Signal_11 feed of 3V3 under the FPGA. Signal_3 is only used for the Analog_2V5 feed under the FPGA and North to L104. Note that this fill on Signal_3 does limit signal routing over the top of the FPGA and into Bank #9 - but there is no other solution. Recall that you can use 2 or more fill shapes for one net on a given pcb physical layer and that they will merge OK. That is a lot easier to handle than one super complex fill shape. May also want to use Fills to ground the bypass caps in the DDR4 CA Bus Terminators. 30 minute talk with Hughes today. 1482 Comps 1388 Nets 249 Float Pins 27 Shapes 3898 Conn 2143 Finished 141 Un-Finished 1614 Guides Geom_Ver 413 Comps_Ver 926 Nets_Ver 593 Trc_Ver 155 ----------------------------------------------------------------- DATE: 10-Oct-2024 Topic(s): Work on Power Fill, Debron Bid Work on connecting the FPGA_1V8, Digital_2V5, and Analog_2V5 fills to their filter inductors. That is now all in and looks OK until more final adjustments are made. Made version of miter.py for less than a 1 mm champher. This is all working OK. All is OK for the non 90 degree corners just as long as you allow for the cut back in the vertex that enters the non 90 degree run. The vertex at the end of the non 90 degree run is OK and stays in its desired final position. There is a question of re-doing the 7 fills for the PMT ADC with a miter of less than 1 mm. You gain nothing under the PMT ADC by doing this but do gain a little bit in the bypass cap fields so I should probably do this. I was finally able to talk with DCA/Debron. They are out. 1479 Comps 1388 Nets 255 Float Pins 27 Shapes 3886 Conn 2143 Finished 141 Un-Finished 1602 Guides Geom_Ver 413 Comps_Ver 925 Nets_Ver 592 Trc_Ver 155 ----------------------------------------------------------------- DATE: 9-Oct-2024 Topic(s): Work on the VTERM supply to the DDR4 Termination Resistors, work on CPU memory routing for D16:D31 2nd zoom about cabling, call vendors For the FPGA Memory I have the Term_Via_Array and the Termination Resistors and associated bypass capacitors in their final position so verify that I can use a Area Fill on L1 and on L10 to connect them to the DDR4_FPGA_VTEM power supply. This all looks like it will work OK but: need more tests to adjust "spoke widths" and will need to adjust Pad_to_Fill design rules when making the fills. The horizontal pad to pad spacing is just over 0.6 mm so during Fill Generation I probably need about: 0.2 mm Fill_to_Pad clearance and about 0.3 mm Spoke Width. Still need final placement of R330, R331, R332 pull up/down resistors for Alert_B, Reset_B, and TEN still need final placement and then the DDR4 Ref Supplies can probably move about 2 mm North. 2nd zoom call about cabling - module assembly - aluminum mounting plate for DK. Summary - I do not understand the mechanical setup. Did talk with some one at Debron/DCA. It appears that the old gaurde is gone. They say that they will call me back. 1476 Comps 1388 Nets 249 Float Pins 25 Shapes 3886 Conn 2143 Finished 141 Un-Finished 1602 Guides Geom_Ver 408 Comps_Ver 922 Nets_Ver 592 Trc_Ver 155 ----------------------------------------------------------------- DATE: 8-Oct-2024 Topic(s): Routing the CPU DDR4 memory, term_via_array, OK from MSU Purchasing Routing the CPU memory starting with it 5 clock signals. Much movement of the CPU Memory bypass caps as this layout is a 180 rotation from FPGA memory layout. CPU Memory CA Bus and 4x Data Busses are out of the design right now. Made a via_array for connecting the 27 CA Bus Termination Resistors. Got the OK from MSU Purchasing to talk with 2 assembly vendors. 1477 Comps 1345 Nets 372 Float Pins Comps_Ver 918 Nets_Ver 583 3847 Conn 2118 Finished 141 Un-Finished 1588 Guides 21 Shapes Trc_Ver 153 Geom_Ver 406 ----------------------------------------------------------------- DATE: 7-Oct-2024 Topic(s): Work on DDR bulk bypass, and CA Bus Termination layout Moved the comps for a 2 sided CA Bus Termination and tested trying to connect it. 1476 Comps 1406 Nets 76 Float Pins Comps_Ver 910 Nets_Ver 581 4016 Conn 2104 Finished 141 Un-Finished 1771 Guides 21 Shapes Trc_Ver 150 Geom_Ver 405 ----------------------------------------------------------------- DATE: 6-Oct-2024 Topic(s): Work on the 5V0 power fill shape, and start work on the CPU DDR4 Add a draft shape for the 5V0 power fill to the design, There are still a number of shapes to work on: overall 1V8 and overall 3V3 and the two shapes that go under the Timing Generator, and the connection of 2V5 to the DDR4 memory chips. The general layout of the FPGA memory still looks OK so start the work on the CPU DDR4. CPU DDR4 is in its final position so drop its relatively placed comps set. Still a big issue of details about connection of the CA Bus to its Terminators. ----------------------------------------------------------------- DATE: 5-Oct-2024 Topic(s): Work on the Timing Gen layout Verify that the Timing Generator is in its final location and then drop the relatively placed comp set from the Timing Generator. Any remaining fine tuning of placements will be on individual comps. ----------------------------------------------------------------- DATE: 4-Oct-2024 Topic(s): FPGA related bypass capacitor placement, Power Fill work, and PVAs now on all of the large power filter inductors Lots of capacitor and fill boundary moves at the 1 mm level. Fills associated with the FPGA now look better. Verifying that all of this support stuff will fit before doing the CPU DDR4 routing. 1476 Comps 1406 Nets 76 Float Pins Comps_Ver 901 Nets_Ver 579 4014 Conn 2071 Finished 135 Un-Finished 1808 Guides 20 Shapes Trc_Ver 146 Geom_Ver 404 ----------------------------------------------------------------- DATE: 3-Oct-2024 Topic(s): Memory bypass cap clean up, Power Fill clean up Adjusted the bypass capacitor setup on the DDR4 chips: VRef_CA pin - now has only 1x 100 nFd cap on each chip and this cap is tied to Ground (not to the 1V2 rail). Note that the CA Bus Clock Terminator center point will be referenced to the 1V2 rail. This setup is a compromise between: Micron recommendations on pg 17, JEDEC specification (for DDR4 modules), and what MicroChip actually did on their Demo Brd. This compromise makes sense because all CA Bus pcb traces are referenced to Ground planes not to 1V2 power planes. There is also a single 100 nFd cap C1927 at the source of the VRef_CA supply U1921. This overall bypass setup is within the TI recommendation for their TPS1200 DDR4 reference supply chip. VRef_CA - net action - dump C328 and C329 (and their per memory chip equivalents) from the design. There will be no C328 or C329 or their per chip equivalents in the design. Vpp aka 2V5 for the Word Lines - keep the 1x 100 nFd on each of the 2 Vpp pins per memory chip and keep the 1x 1 uFd and the 1x 10 uFd bulk capacitors per memory chip. Dump the "extra 100 nFd per memory chip caps. This setup more than satisfies the Micron recommendation. Vpp aka 2V5 - net action per chip - Dump C322 & C324 then Change reference designators as follows: C323 --> C322, C325 --> C323, C326 --> C324. There will be no C325 or C326 in the design. Notes Now all DDR4 bypass capacitors are tied to Ground. The Bulk bypass caps for the DDR4 chip 1V2 supply are immediately adjacent to the Bulk bypasss caps for the 1V2 supply to Banks #0 (or Bank #6) so they are really all part of a single Bulk bypass network per Bank and its memory chips. It's pretty clear that I need to change the 1V2 power fill so that it is allowed to come out East of the BGA, i.e. pass through the un-unsed part of the XCVR pin array so that I can locate the Bank #0 Bulk bypass caps in that area. I do want to split (slice) the 1V2 power fill and make them common only South of about Y = 85 mm, slice down the center at X = 110 mm, slice at an angle through unused Bank #8 from about: 114.0, 138.0 to about 106.5, 130.5 then due South ti about Y = 126.5 then over to the 110 center. So the 1V2 power fill has a common feed area and is then sliced between Bank #0 with its memory chips and Bank #6 with its memory chips. The Ground planes are not sliced - the 4 Ground planes are continuous and not sliced West of the fast PMT ADC. Still may want a slice East of the FPGA Memory. 1450 Comps 1406 Nets 100 Float Pins Comps_Ver 894 Nets_Ver 577 3912 Conn 2071 Finished 135 Un-Finished 1706 Guides 19 Shapes Trc_Ver 146 Geom_Ver 402 ----------------------------------------------------------------- DATE: 2-Oct-2024 Topic(s): FPGA DDR4 and Power Fills Added ground return rivets within the memory chip array and under the memory chips. Added Ground Rivets around the estimated perimeter of the FPGA DDR4 area - the intents are keeping the 4 Ground Planes clamped together for ground current return on the DDR4 signals and for noise controll - both CPU vs FPGA memory noise control and DDR4 memory noise leaking into the PMT Analog Input section or into the High-Speed PMT ADC Serial Links. All rivets are now tied to Ground. Finally wrote the special use of logical layers note - currently have 11 special layers in use. Worked on cleaning up the Power Fills - note that all of the under FPGA Fills have changed because the FPGA was moved 5 mm East on 23-Sept-2024 to what I strongly hope is its final position. Connected the BULK_1V2 fill to its DCDC3 converter and added the fill to connect DCDC2 to L101 and L102 and then to CORE and XCVR loads. Now have 19 fills with more to go. With these fills now visible at about the right locations a new big issue comes up - where to put the larger bypass caps for the FPGA: CORE_1V05, Bulk_1V2, and XCVR_1V05 supplies ? XCVR is maybe OK just West of the FPGA, but all of the area covered by the CORE and BULK_1V2 Fills is already taken up by DDR4 related traces so there is no space for capacitor connections to the Gnd or Power layers. 1466 Comps 1406 Nets 100 Float Pins Comps_Ver 892 Nets_Ver 575 3944 Conn 2071 Finished 135 Un-Finished 1738 Guides 19 Shapes Trc_Ver 146 Geom_Ver 399 ----------------------------------------------------------------- DATE: 1-Oct-2024 Topic(s): Bypass caps in FPGA DDR4 Moved the bypass caps for the FPGA DDR4 memory chips into final positions and connected them. There are 29 bypass caps per memory chip with 18 being immediately adjacent to or under each memory chip. These bypass caps are for: 1V2 memory power, 2V5 word line power, and the VRef for the CA Bus. 1435 Comps 1406 Nets 100 Float Pins Comps_Ver 886 Nets_Ver 574 3944 Conn 2071 Finished 135 Un-Finished 1738 Guides 18 Shapes Trc_Ver 145 Geom_Ver 394 ----------------------------------------------------------------- DATE: 30-Sept-2024 Topic(s): FPGA DDR4 Routing Work on clean up of the FPGA DDR4 CA Bus. I believe that there are no more obviously poor routes in this layout but everytime one looks there are still better ways to do things. As planned, I still have the 3 "control" type signals to work on: DDR4_FPGA_ALERT_B, DDR4_FPGA_TEN, and DDR4_FPGA_RESET_B. The Xilinx information about routing of ALERT_B, and RESET_B is on pages 67 and 68 of their DDR4 documentation. For the ALERT_B they explicitly say, "does not have any skew or length matching requirments". It's obvious the TEN and RESET_B do not have skew or length match requirements so routing for all three of these signals may be more relaxed. Microm wants ALERT_B pulled-up with a resistor to 1V2. Micron reminds that ALERT_B is an Open-Drain output for CA Parity and for Write CRC but it is a CMOS input for TEN. Micron wants RESET_B tied to Gnd with a pull-down resistor to make sure that it stays Low and the power supplies ramp up and the Memory Controller wakes up. Micron shows an 8 layer stackup with the center most two layers being offset striplines on page 24. The outer two layers are microstrip and then a power/ground pair in each half. Points: - Still the issue of AC coupling the center point of the CA Bus Clock to GND or to 1V2 ? I've seen both in examples. - To avoid confusion I need to change my net name, "DDR4_VREF_FPGA" to "DDR4_FPGA_VREF_CA" so that it reminds you that it is the CA Bus VRef and has the same naming format as the other signals. - Should the By-Pas caps on VRef-CA be to Gnd or to 1V2 I seee both options taken is examples. - Need to add Rivet Vias around the DDR4 especially between the FPGA DDR4 - the Gnd Slit - and the PMT Analog Input. - Need to slit the 1V2 Plane so that: Bank #0 and the FPGA DDR4 chips are on one side and Bank #6 and the CPU DDR4 chips are on the other side. The other things that must be explicitly routed for each of the FPGA DDR4 chips are: ZQ Reference Resistor, VREF (CA Bus Reference), and the 2V5 Volt Vpp Word Line supply. I'm dropping the relatively placed component set from the FPGA DDR4 components as they are not going to be moved again and it makes fine tuning the bypass cap placement a little easier. 1429 Comps 1406 Nets 100 Float Pins Comps_Ver 868 Nets_Ver 568 3932 Conn 2002 Finished 135 Un-Finished 1795 Guides 18 Shapes Trc_Ver 140 Geom_Ver 394 ----------------------------------------------------------------- DATE: 29-Sept-2024 Topic(s): Routing FPGA DDR4 CA Bus Still a day long fight for rational routes in the FPGA Mem CA Bus. ----------------------------------------------------------------- DATE: 27-Sept-2024 Topic(s): Routing FPGA DDR4 Memory The 4x Data Buses are starting to clean up OK. Fighting the CA Bus. All 5x Clock signals are now on L2 and that looks better. Minimizing the overlap between the 2 FPGA memory chips in a uniform way, but which layer is used for which run varies from column to column depending on which FPGA signals I can land in a given column without a 3rd via. 1424 Comps 1406 Nets 100 Float Pins Comps_Ver 862 Nets_Ver 565 3930 Conn 1961 Finished 148 Un-Finished 1821 Guides 18 Shapes Trc_Ver 135 Geom_Ver 393 ----------------------------------------------------------------- DATE: 26-Sept-2024 Topic(s): Routing FPGA DDR4 Memory 1414 Comps 1406 Nets 95 Float Pins Comps_Ver 859 Nets_Ver 563 3935 Conn 1942 Finished 135 Un-Finished 1858 Guides 18 Shapes Trc_Ver 129 Geom_Ver 392 ----------------------------------------------------------------- DATE: 25-Sept-2024 Topic(s): Routing the 4 FPGA DDR4 Data Buses Note: Within a Data Bus Byte Lane - bit swaps are used to facilitate cleaner routing. Even with these bit swaps, the Net Names in the Net List files remain based on the Net Name of the FPGA Controller Pin, i.e. bit_x on the FPGA remains net name bit_x but with the swap is connected to bit_y on the memory chip. 1415 Comps 1381 Nets 238 Float Pins Comps_Ver 855 Nets_Ver 560 3819 Conn 1928 Finished 135 Un-Finished 1756 Guides 18 Shapes Trc_Ver 122 Geom_Ver 388 ----------------------------------------------------------------- DATE: 24-Sept-2024 Topic(s): Placement Adjustments and DDR4 Route Yet more minor placement adjustments, DDR4 Ref supplies and CORE XCVR filter components now in better/final locations and now look OK. Data Bus routing into FPGA DDR4 U302 - perhaps now final version. Using Rules: 0.60 mm Signal to Signal on same layer 0.60 mm Clock to Signal on opposite layer 0.90 mm Clock to Signal on same layer 1407 Comps 1406 Nets 95 Float Pins Comps_Ver 851 Nets_Ver 555 3937 Conn 1909 Finished 135 Un-Finished 1893 Guides 18 Shapes Trc_Ver 116 Geom_Ver 385 ----------------------------------------------------------------- DATE: 23-Sept-2024 Topic(s): FPGA DDR4 Data Bus Routing Finish adding marker lines to the 96 pin DDR4 chip geom and to the FPGA geom to help guide the eye to which bus section is which. Is the FPGA and DDR4 properly centered ? This is the final chance to move it before permanent routes to it. - The North-South center of the FPGA and DDR4 looks OK. Additional routing space South of the DDR4 CA Bus Terminators will open up once I move 1/2 of these Terminators to the back side of the board. There are about 37 routes that must run East-West either between the Terminator Power supplies and DCDC2, DCDC3 or else South of DCDC2, DCDC3. The East-West placement of DCDC2, DCDC3 looks OK for now. Recall that DCDC3 1V2 is to the West and DCDC2 1V05 is to the East. Want to move the L101 filter for the CORE supply to just North of DCDC2. - The East-West center of the FPGA and DDR4 still looks wrong. There are about 37 signals that still need to be routed to the East of the FPGA & DDR4 and there is about 20 mm avalable for this on about 4 or 5 layers. But this includes the Clock Signals and other fancy stuff. There are about 24 signals that still need to be routed down the West side of the FPGA & DDR4 and then head East. There are about 24 signals that still need to be routed down the West side of the FPGA & DDR4 and then head West. In addition I believe that all of the CPU DDR4 CA Bus must escape the FPGA to the West and then route South into the CA side of the DDR4 Chips. This is 30 high-speed signals. The space available is about 15 mm up by the ER uProcessor and about 10 mm down by the DDR4. Actions: Move the FPGA/CPU 5 mm further East. Move the CPU DDR4 chips 2.5 + 5 mm East = 7.5 mm so their the CA Bus section of the CPU DDR4 chips hangs West of the West edge of the FPGA/CPU. The intent is that the fly-by route of the CPU CA Bus through the DDR4 chips will all be West of the FPGA. Move the FPGA DDR4 chips 2.7 + 5 mm East = 7.5 mm so their East edges line up CPU to FPGA DDR4 chip East-West spacing is not changing. The intent is that both D16:D31 DDR4 Data Buses will run between the DDR4 chips. The bulk of the DDR4 bypass caps will need to be under the DDR4 chips and use their power and ground vias. The Timing generator probably will need to move about 5 mm to the East to provide a better routing channel to the West of it. L101 the CORE Filter must go down by DCDC2 L102 the XCVR Filter must tuck in up by the FPGA but South of the PMT ADC Made a trace length report with only SLIs in the DDR4 and FPGA DDR4 CA Bus Terminators are out of the Net List. 1407 Comps 1406 Nets 95 Float Pins Comps ver 845 Nets ver 553 3937 Conn 1896 Finished 135 Un-Finished 1906 Guides 18 Shapes Trc Ver 111 ----------------------------------------------------------------- DATE: 22-Sept-2024 Topic(s): FPGA Data Bus DDR4 Work on the D16:D31 escape order and pass through area. ----------------------------------------------------------------- DATE: 21-Sept-2024 Topic(s): DDR4 Data Bus Routing From routing the FPGA DDR4 Data Buses yesterday and then more thinkning about it - I think there is a better set of rules for just the Data Buses. - Overlaps are the only routing issue that I know of right now and they are only an issue in the FPGA BGA region. Everything else looks OK. - Overlaps only couple from the aggressor to the victum trace when the aggressor is changing states. The exception is a Reverse going wave that reflects from the Sending end and arrives at the Receiving end after a delay equal to the line length (and will persist for 2x line length). - Even in the FPGA BGA region the worst rational case overlap is about 9 mm. This is about 59 psec. The Xilinx example of a 1200 MHz CA Bus shows a good full eye opening of about 500 psec (i.e. 333 psec for transistion and settling time). Scale this to our 800 MHz CA Bus and we may be able to expect a good fully open CA Bus eye of 750 to 917 psec and a good fully open Data Bus eye of 292 to 375 psec (all depending on how you think about the scaling, is everything proportional or is it fixed transition + settling time). - From the FPGA Data Bus routes to the further DDR4 chip, D16:D31, the maximum length of the DQ traces is about 40 to 60 mm, or about 260 to 390 psec. Clearly this is a system that fully requires "incedent wave switching". - So route the Data Bus as follows: A given Byte Lane will use either L3, L4 or L9, L10. Want to maintain good isolation between Byte Lanes. Clock (Strobe) is highest priority and it must not receive any cross-talk, especially cross-talk from signals in a different Byte Lane, thus Clocks must escape the FPGA BGA on L1 or L12, then after a short run transition to either L3, L4 OR L9, L10 depending on which adjacent pair this Byte Lane is using DMx_B point to point signal is next routing priority DQ0 (LSB of the Byte Lane) is next point to point priority Last is DQ1 : DQ7 where full swapping is allowed. Accomplish this swapping by escaping these 7 signals from the FPGA BGA and cleanly routing them to a transition area where there is also space for Gnd Return Rivets. From there swap as necessary for clean runs into the DDR4 chip. - Within a Byte Lane it is clear that the length of DQ0:DQ7 and DMx_B must all match - but must they match the Clock (Strobe) for that Byte Lane ? Why ? How does the Training actually work ? time in the DQs or time in the returning Clock ? I must learn and understand this. - Trace clearances recommented by Xilinx (in the main pcb route aka non-escape areas) (I assume this is Air Gap and not C to C): In the CA Bus: signal to signal 0.20 mm signal to clock 0.51 mm to another signal group 0.76 mm In the Data Bus: signal to signal 0.20 mm signal to clock 0.51 mm to another byte lane 0.51 mm to another signal group 0.76 mm Within FPGA escape area: signal to signal 0.10 mm signal to clock 0.20 mm CA signal to clock 0.10 mm Data - The Xilinx DDR4 constraints are: DQx and DMx_B in a Lane to that Lane's Strobe +- 10 psec +- 1.5 mm Strobe_Dir to Strobe_Cmp 2 psec 0.3 mm Data Lane Strobe to CA Clock: CA Clock route can be up to 149 psec shorter up to 22 mm shorter CA Clock route can be up to 1796 psec longer up to 273 mm longer CA Signals to CA Clock +- 8 psec +- 1.2 mm CA Signals do NOT include: Reset_B, TEN, Alert_B Clock_Dir to Clock_Cmp 2 psec 0.3 mm - Recall that total flight time is the sum of the Package Delay and the pcb Trace Delay. So start over on the FPGA Data Bus routing again. ----------------------------------------------------------------- DATE: 20-Sept-2024 Topic(s): Routing in the FPGA DDR4 Implement geoms for the Differential_Via_Comp and Via_0mm52. Route the 4 Data Bus Lanes first before the CA Bus. Route the Clocks for the Data Bus Lanes first. Route the DDR4_FPGA_DM?_B next. Route the LSB Bit in each lane next. Finally Route the 7 remaining data bits in each lane and use all of the bit swapping within a lane that you want. Now I need to enforce firm design rules for the signal spacing: spacing from the Clocks, Spacing between data bits within a layer, and spacing required when signals are face to face, i.e. L3-L4 or L9-L10. Finish up a very poor job of the D16:D31 memory chip so that I can "report" their trace lengths so that I can convert to signal delay times and see how things are working out. 1407 Comps 1406 Nets 95 Float Pins Comps ver 837 Nets ver 553 3937 Conn 1951 Finished 168 Un-Finished 1818 Guides 18 Shapes Trc Ver 107 ----------------------------------------------------------------- DATE: 19-Sept-2024 Topic(s): Clean up errors in Release_2 data Samtec ERF8-025 vs ERF8-050 Correct the component_description file R1163 61.9k vs 62.8k Correct: real design files, drawing #5, and documentation files: BOM, Component_Descriptions, smd_comonent_counts_bottom, and smd_xy_data_bottom Molex 87832-4020 vs 87332-4020 Correct: Component Description and dk_aaa_bare_pcb_description files ----------------------------------------------------------------- DATE: 18-Sept-2024 Topic(s): DDR4 Routing A big issue is that with a 12 layer stackup there is no Gnd plane between L3-L4 or between L9-L10. Will the trace to trace coupling (face to face coupling) be large enough to cause trouble ? There are a lot of routing constraints that can be imposed to help reduce this parasitic coupling but can these constraints coexist along with all of the other constraints that are required just to make the DDR4 buses routable ? In the FPGA BGA escape region the overlaps could/will be about 5 mm long at a maximum. In the memory chip region the overlaps will be about 3 mm long at maximum. Propigation velocity is about c / sqrt ( Er x Ur ) Er is relative permittivity and Ur is relative permeability which it typically 1.0 for the non-magnetic pcb laminates. Thus the signal velocity is just c / sqrt( Er ). For the anticipated laminates we should have: Solder Mask is about 3.90 Er ---> 6.58 psec/mm Core Laminate is about 3.77 Er ---> 6.47 psec/mm PrePreg Laminate is about 3.44 Er ---> 6.18 psec/mm Based on c being 3 E+11 mm/sec ---> 3.33 psec/mm Thus for the 5 mm long overlap estimated about the signal distortion may persist for about 32 psec. 800 Mhz is 1250 psec period 1600 MHz is 625 psec So these distortions could be as small as about a 5% effect. Within the BGA pin fields the traces are forced to overlap. Outside of these areas these traces can be offset e.g. by +- 0.2 mm so that there is about 0.27 mm of air gap space between them which, considering their large Z axis spacing, is enough to minimize their trace to trace coupling. Recall that Z is expected to be about 17 mils 0.43 mm. See the 10 Sept 2024 stackup estimate entry. Mitigations of the Overlap Issue: - In the Data Bus regions of the DDR4 Chips there are 9 routing channels and only 22 signals - so this is 2.44 signals per routing channel (at the channel exit) so things are not too bad. Rule in the DDR4 Chip Data Bus sections - never overlap 2 signals from different Byte Lanes. This should be easy to enforce. - In the CA Bus regions of the DDR4 Chips there will be complete overlap in all 7 routing channels. It's still not clear whether the traces of an overlap pair (L3-L4 or L9-L10) should both service adjacent columns in the DDR4 Chip (i.e. service columns 2, 3 or 7, 8) or should one trace in the overlap service a pin in one pair of adjacent columns and the other trace service a pin in the other pair of adjacent columns. Signals: Alert_B, Reset_B, and TEN are good to overlap because they are static. Currently I swing the column 2, 3 pins in opposite directions and the column 7, 8 pins in opposite directions. There may be a shorter overlap if 2, 3 both swing in one direction and 7, 8 swing in the other direction. This may only be of benefit in te CA Bus region. Note that the CA Bus region will not have space for added ground rivets. All space is used by the 27x 800 MHz signals plus 3 static signals. Can rivet ground on the East of the routes and maybe on the West between CA and Data Buses. - In the escape from the FPGA BGA you have the least overlap using the order (starting from the outer ring): L1 (no choice about this), L3, L9, L12, L4, L10 or one of the obvious equivalents to minimize the L3-L4 and L9-L10 overlaps. - For the 5 Differential Clock signal pairs In all of the above signal groups, the differential Clock signals have top priority. Some exceptions to the above FPGA BGA escape order may be needed In the memory chip region, one may be able to route these clocks as edge coupled differential pairs with no aggressor on the adjacent un-shielded layer (e.g. route on L3 with nothing on L4) just becaue of the nice memory chip pinout, i.e. the rows adjacent to the clock pin rows are not fully occupied, i.e. one does not need all 4 layers to route them. Using the above would require an edge coupled escape from the FPGA BGA which would need to be on L1 or L12. ----------------------------------------------------------------- DATE: 17-Sept-2024 Topic(s): FPGA DDR4 The notes about the "Shield" pins in the DDR4 Memory connections are in the 17-May-2024 log book entry. Recall: as far as I currently know, this Shield pin stuff if only for the FPGA memory (not for the CPU memory) and only for the 4 Data Lane buses in the FPGA memory (4 pins total) I do not know why it is not for the CA Bus for the FPGA memory potentially 5 or 6 additional Shield pins. Get a copy of the Cadence X View aka Allegro Physical Viewer so that I can see how MicroChip did things in their soc kit demo board. Cadence X Viewer lets you look at: board files .brd design partitions .dpf module definitions .mdd and symbol drawings .dra Figure out enough Windows junk to load this onto Nathan's lab Windows machine and it barfs when trying to read the MicroChip .brd file - it says, "Design is version 16.6 and must be updated using DB Doctor Error SPMHBB-181" - but DB Doctor is part of the real Allegro stuff - not part of their free physical viewer. www.cadence.com/ko_KR/home/tools/allegro-downloads-start.html gets you to a place where you can down load an old version of their free viewer called, Cadence Design Systems Allegro Free Physical Viewer 16.6 That works OK to see the MicroChip SOC Kit .brd file. The design is by Pactron in Santa Clara and is the 2nd rev from Aug 2021. It's 14 layers and 62 mils thick L2, L4, L6, L9, L11, L13 Gnds L7, L8, Power L1, L3, L5, L10, L12, L14 Signals So its the same stackup as DK but they included the two GND planes that I would like to have and when with micro thin laminate. The board is all FR4 except for the top and bottom dielectric which is high-speed stuff. Their FPGA and DDR memory chip foot prints use dog-bones not via-in-pad. In the 1mm pitch FPGA BGA foot print they have used some double track. The FPGA memory stuff looks completely confusing but then I remember from my earlier notes that they used the NW Anchor for their layout. I have 99% looked only at the NE Anchor because I understood it to be more standard. Must check this. The 2 problems with with the NW Anchor are that it requires you to use both Banks #0 and #8 for a 32 bit wide data path (Bank #0 for: CA Bus D0:D7 D8:D15 and use Bank #0 D16:D23 D24:D31) and that the use of Bank #8 blocks the escapes for Bank #6 the CPU DDR4 bank which forces the CPU DDR4 chips to be placed around on the West side of the FPGA/CPU which we do not have space for. They have their DDR chips rotated so that the data end of them faces the FPGA. This makes their layout quite wide, wider than we have space for on the DK. Their terminators must all be on the bottom. They have a lot of surpentines a lot more than should be necessary from my current understanding. They run edge coupled differential clocks and tend to keep a byte lane all on one layer. They do swap data bits within a lane. In the CA Bus runs between the 4 memory chips they have surpentines in a bunch of places. I would think that rational consistent layout would result in all CA Bus runs between the 4 memory chips just naturally all being the same length. Why didn't they keep these runs uniform ? They do swap layers on the CA Bus Clock from the FPGA escape to the run through the 4 DDR chips. They have some nice bone rotation in the DDR chip foot print to line up the clock pins correctly. They equalize the Strobe Clock signals with just one big loop right as they exit the FPGA BGA. The CA Bus Terminators are right under the last DDR chip in the string of 4 with effectively zero length traces from the last DDR chip dog-bone vias to the Terminator resistor terminal. Can you really stack 0402 resistors on a 0.6 mm pitch ? ----------------------------------------------------------------- DATE: 16-Sept-2024 Topic(s): FPGA DDR4 I assumed that the .brd file for the MicroChip soc kit demo board was from the Eagle. Kicad can import Eagle .brd files so load Kicad onto the white desmo computer. Does not work. Can not open the MicroChip .brd file - dies at line #1 - says it is not an XML file. Dig more and learn that a bunch of companies name files with the .brd extension. The soc kit .brd file is just binary data from the unix file command. Try unix strings command and find a string that clearly says that it is a Cadence Allegro .brd file. Cadence makes a Windows only viewer for their Allegro .brd files. ----------------------------------------------------------------- DATE: 15-Sept-2024 Topic(s): Working on FPGA DDR4 routing Pick the Face Coupled differential trace arrangement for the 5 clock signals and start trying to implement it. The main concerns are: - The Zo in the range of 60 to 65 Ohms for the face coupled differential Clock signals - but Xilinx is running these same signals at 66 Ohm in their recommended DIMM layouts. - Escaping the FPGA BGA on the correct layers - but I will not know if this is possible without trying to implement it. The main concern about the edge coupled differential clock signals was keeping the noise from the other closely packed signals out of the clocks. The Xilinx document worries about this a lot. When reading the various documents about recommended DDR4 layout they often do not state whether their recommendations are for DIMM layout or component memory layout. Recommendations that are imposible for component memory layout do work for DIMM (because it is spread out, has a wider pitch, and has a weave through only two rows of pins. Goals: Data buses have priority Use only 3 vias maximum in the full route for the Data Buses and 5 vias maximum for the CA Bus (1 for the 2nd memory chip and 1 for the Terminator). Use the L1 and L12 layers only to escape the FPGA BGA and only on its perimeter pins (where the higher velocity of L1 and L1 will help balance the longer run at slower velocity to the FPGA's substrate perimeter). Start work to colect and organize the pin delay data from the MicroChip pin .xlsx file for Bank #0. ----------------------------------------------------------------- DATE: 14-Sept-2024 Topic(s): Working on FPGA DDR4 routing Working on making the FPGA CA Bus Clock differential and making the 4 Data Bus Strobes all differential and in the correct order to route into the memory chips. Try and fail to Finalize the decision on which type of differential routing to use, i.e. normal side coupled or face coupled. - Side Coupled would be about 0.13 mm trace width, with C to C spacing of ?? mm, about 0.13 mm from one Reference Plane, about 0.58 mm from the other Reference Plane, with often an aditional agressor signal about 0.43 mm overhead. The Zo of the side coupled pair will be about 100 Ohms. Using Side Coupled requires escaping the FPGA BGA and entering the Memory Chip BGA with both signals on the same layer, either: L3, L4, L9, or L10. - Face Coupled would be about 0.13 mm trace width, with each trace about 0.13 mm from its Reference Plane, and the trace Faces separated by about 0.43 mm, with often an aditional agressor signal about 0.60 mm C to C on either side. The Zo of the Face Coupled pair will be about 60 Ohms which is driven by the 0.13 mm spacing to their Reference Planes. Using Face Coupling requires the Differential signals to escape and be routed on either: L3-L4 or L9-L10 Neither choice looks very good. A basic problem is the lack of a Gnd Plane between L3-L4 and between L9-L10. A basic question is can we run the Clock Differentail Zo down at 60 Ohms ? - can the drivers handle it ? Will go away and also consider trying to route these 5 clock pairs on L12. Review of routing priorities and required time/length match groups: 4 Data Buses 11 signals each highest speed highest priority CA Bus 27 signals total half the speed middle priority ALERT_B, RESET_B, TEN/EVENT_B low priority ALERT_B is FPGA pin AM25 \ No length match required RESET_B is FPGA pin AG26 | Required only rational medium TEN/EVENT_B is FPGA pin AL25 / speed signal routing ----------------------------------------------------------------- DATE: 11:13-Sept-2024 Topic(s): Working on FPGA DDR4 routing First try was just to prove that it was possible to route the FPGA side of the DDR4 memory, i.e. I need to go in 11 rings on the FPGA BGA to pick up all of the signals and I have at most 6 routing layers and want to keep most of these 74 signals on just 4 layers. Second try put too much emphasis on the Command Address Bus and made the routing of the 4 byte wide (11 signals) Data Buses into a real mess. Third try is focused on rational Data Bus routing (they must work at twice the speed of the CA Bus) and focused on having the signals escape the FPGA BGA array in a more rational order than the first 2 tries. Recall that the memory chips themselves have been rotated so that the CA Bus and Data Buses are at the rational East-West ends of the layout. Note that the plan for the D16:D23 & D24:D31 Data Buses is to have them enter the memory chip foot print from the West (not from the North). Clean up drawings 89 and 90 and merge in the overall Blk Diag .dgn file from home. The nets to the FPGA CA Bus Terminators are currently out of the design. 1406 Comps 1406 Nets 95 Float Pins Comps ver 831 Nets ver 552 3935 Conn 1924 Finished 209 Un-Finished 1802 Guides 18 Shapes Trc Ver 104 ----------------------------------------------------------------- DATE: 10-Sept-2024 Topic(s): Review the Tentative Stack-Up The nominal thickness is 80 to 90 mils (work in mils for now) so call it 85 mils. 1/2 oz is 0.65 mils 1 oz is 1.3 mils thick and the board has 4 planes of 1/2 oz and 2 planes of 1 oz so this is a total of 5.2 mils of copper leaving 80 mils for dielectric. There are 11 layers of dielectric so this is a nominal 7.25 mils per dielectric layer. Review what is required to hit the target impedances based on 100 Ohm differential from 1.4 mm trace width spaced 0.4 mm C to C. This requires for the L1-L2 and L11-L12 dielectrics about a 4 mil thickness assuming a Dk of 3.6 For a 50 Ohm microstrip traces on L1 or L12 this dielectric requires about a 0.155 mm width. 0.11 mm width is 60 Ohm, 0.19 mm is about 44 Ohm To reduce the L3 to L4 (and L9 to L10) signal coupling I would like the L3-L4 and L9-L10 dielectrics to be rather thick. To increas the coupling between the Power Planes L6 and L7 and their adjacent Gnd Planes L5 and L8 I would like the L5-L6 and L7-L8 dielectrics to be rather thin - lets pick 4 mils. To reduce the Power Plane to Power Plane coupling I would like the L6-L7 dielectric to be rather thick - lets pick 10 mils. 80 mils minus 4 mils each for L1-L2 and L11-L12 minus 4 mils each for L5-L6 and L7-L8 minus 10 mils for L10 leaves 54 mils which is divided into 2 equal uses 27 mils for: L2-L3 + L3-L4 + L4-L5 27 mils for: L8-L9 + L9-L10 + L10-L11 So looking at just the upper example - possible choices that add to 27 mils are: Resulting Zo for L2-L3 or 0.156 mm width L4-L5 L3-L4 0.5 oz Dk 3.6 -------- ------- ---------------- 8 mils 11 mils 59.9 7 13 58.6 6 15 55.4 5 17 50.4 4 19 43.2 So if you make the L2-L3 (L4-L5) dielectric 5 mils then how strong is the dependance on the L3-L4 thickness ? stripline 0.156 mm width Dk 3.6 one dielectric 5 mil thick other dielectric thick mil 10 15 17 20 25 Zo Ohms 47.6 49.8 50.4 51.0 51.6 As hoped this is a rather weak dependance. Order of magnitude the stackup should look about like: L1 1/2 oz Traces and Pads 4 mil L2 1/2 oz Ground Plane Upper Type 5 mil L3 1/2 oz Traces 17 mil L4 1/2 oz Traces and Fills 5 mil L5 1/2 oz Ground Plane Upper Type 4 mil L6 1 oz Power Fills 10 mil L7 1 oz Power Fills 4 mil L8 1/2 oz Ground Plane Lower Type 5 mil L9 1/2 oz Traces and Fills 17 mil L10 1/2 oz Traces 5 mil L11 1/2 oz Ground Plane Lower Type 4 mil L12 1/2 oz Traces and Pads This will give about 85 mil total thickness 2.16 mm 0.14 mm C to C 0.4 mm will give about 100 Ohm Zo differential 0.16 mm will give about 50 Ohm Zo Single Ended Dk should be about 3.6 L1 and L12 will plate up to about 1 oz. For the DDR4 routing the distance down to L10 is about 1.93 mm i.e. about 4x the match tolerance. 1406 Comps 1406 Nets 70 Float Pins Comps ver 831 Nets ver 550 3960 Conn 1908 Finished 209 Un-Finished 1843 Guides 18 Shapes Trc Ver 95 ----------------------------------------------------------------- DATE: 9-Sept-2024 Topic(s): Working on FPGA DDR4 Routing An escape from under the FPGA BGA of the 74 signals for the FPGA DDR4 is now in place. At this time it used 5 signal on L1 and 4 signals on L12. All other signals are on L3, L4, L9, and L10. To escape the FPGA DDR4 signals requires going in 11 rings. Made a complete new placement of the CABus Terminator components so that they are now in a rational order without a large amount of criss-cross. The Y ctoc spacing of the two FPGA DDR4s is 17.0 mm which gives about 9 mm of open space between them. There is about 13 mm between the FPGA pin array and the upper DDR4 pin array so maybe the upper DDR4 should move South to give more space for the surpentines. The escapes from under the 1.0 mm pitch FPGA BGA are 0.13 mm wide and under the 0.8 mm DDR4 BGA are 0.12 mm wide. ----------------------------------------------------------------- DATE: 8-Sept-2024 Topic(s): Working on FPGA DDR4 Routing Working on a rational escape, actually any escape, from the FPGA. Want D16:D13 on the West, D0:D15 in the Center and the Command/Address Bus on the East. The FPGA DDR4 chips will remain with the orientation that they have. Turn back on all of the FPGA DDR4 nets and change their Dog-Bones on the South side of the FPGA into BGA Pads only. In theory, with a 1 mm pitch BGA, one could escape 2 traces on the top side between BGA only Pads using 0.12 mm rules (like in the 0.8 mm pitch BGA layout). Shifting all D16:D31 from SE to SW dog-bones and setting AN 22, 23, 24 & AP 23, 24 to Pad Only and setting AP 22 to a straight South Dog-Bone. I will need L1 and L12 to make the DQ part of the escape work, i.e. I need the layers will the least understood properties for the highest speed signals. Need to save Traces_87 in case I need to backup. ----------------------------------------------------------------- DATE: 6-Sept-2024 Topic(s): Last entry in the previous log book