SPI, I2C, and UART Buses on the DK Board ------------------------------------------ Initial Rev. 21-Apr-2023 Current Rev. 25-Apr-2023 The intent of this file is to describe all of the SPI and I2C buses on the Disco Kraken board. This includes a description of all of the SPI and I2C Controllers in the MPFS250T FPGA/CPU and a description of all of the SPI and I2C targets on the DK board. - Start with a list of the SPI and I2C Controllers. - The next section describes the SPI and I2C Targets on the DK board and then has a summary of these Targets. - The next section describes which SPI/I2C Targets are connected to which SPI/I2C Controller. - The next section is notes about 3-wire vs 4-wire SPI buses, which SPI Targets on the DK board are 3-wire only, and whether or not the SPI Controlers in the MPFS250T FPGA/CPU can operate in 3-wire mode. - The final section of this file describes the UARTs in the FPGA/CPU and what the various UARTs are connected to. SPI and I2C Controllers: ------------------------ All of these serial bus Controllers are on the MPFS250T- FCVG784 FPGA/CPU. All but one of these serial bus Controllers is operated by the CPU section of this chip. - System Controller SPI Controller - QSPI Controller - SPI Controller 0 - SPI Controller 1 - I2C Controller 0 - I2C Controller 1 SPI and I2C Targets: -------------------- The following list shows each of the serial bus Targets and shows the basic capabilities of each Target. - Fabric Configuration Memory: SPI, 3V3 Must be on the System Controller SPI bus - CPU Configuration Memory: SPI, 3V3 - Interposer this hemisphere: SPI, 3V3 - Interposer other hemisphere: SPI, 3V3 - Setup of the AD9083 PMT ADC: Datasheet page 53, SPI, 1V8, single SDIO pin only AD9083 data is carried on a separate JESD204B bus. - Setup of the AD9546 Timing Generator: Datasheet page 181, 199, SPI or I2C, 1V8 or 3V3 SPI can be single SDIO or separate MISO and MOSI. I2C Address: 0x48, 0x49, 0x4A, 0x4B. Also needs a 52 MHz clock. - Setup of the TLV320ADC6140 BB Audio ADC: Datasheet page 57, SPI or I2C, 1V8 or 3V3 I2C Address: 0x4C, 0x4D, 0x4E, 0x4F SPI uses separate MISO and MOSI pins TLV320ADC6140 data is carried on a separate TDM, I2S, or left-justified (LJ) bus. - Setup and Data to/from ADIN2111 Ethernet Phy & Switch: Datasheet page 16, 21, SPI with separate MISO and MOSI 1V8 or 3V3 Supports both OPEN Alliance SPI Mode and the Analog Devices SPI Mode. Operation of this part may require a separate Interrupt line and input pin on the FPGA/CPU. The Ethernet Phy needs a 25 MHz clock. - Setup and Data to/from TDC7200 TDC: Datasheet page 21, 41, SPI (4 wire only), 3V3 only Also needs an external 16 MHz clock 3V3 single ended. Has an Enable pin that must Not go High until all power supplies are stable. Power consumption: Enable Low ==> 0.3 uAmp, Enable HI and Converting ==> 1.35 mAmp, Enable Hi and Not converting ==> 80 uAmp. - Magnetometer ??? probably I2C - Accelerometer ??? probably I2C - Bluetooth ??? Needs a UART connection and a 26 MHz source. Does not need SPI or I2C - USB Phy Chip USB3340 uses a private ULPI connection with the FPGA/CPU but needs a 26 MHz clock Summary of the SPI and I2C Targets: ----------------------------------- Target SPI and/or I2C I/O Voltage ----------------- ------------------ ----------- Config Memory SPI 4 wire 3V3 Interposer SPI 4 wire 3V3 PMT ADC SPI 3 wire 1V8 Timing Generator SPI 3 or 4 wire or 1V8 or 3V3 I2C 0x48:0x4B BB Audio ADC SPI 4 wire or 1V8 or 3V3 I2C 0x4C:0x4F Ethernet Phy Swch SPI 4 wire 1V8 or 3V3 TDC SPI 4 wire 3V3 Magnetometer ??? assume I2C ? Accelerometer ??? assume I2C ? SPI/I2C Targets on each of the SPI/I2C Controllers: ----------------------------------------------------- - System Controller SPI bus is connected to only the Fabric Configuration Memory via a 4 wire 3V3 SPI bus. - QSPI bus is connected to: - SPI Controller 0 bus is connected to: - SPI Controller 1 bus is connected to: - I2C Controller 0 bus is connected to: Timing Gen and BB Audio ADC at 1V8 - I2C Controller 1 bus is connected to: 3-Wire vs 4-Wire SPI Buses: --------------------------- The normal SPI Bus definition uses 4 Signals which are normally labeled with the following names: - SCLK the clock from the Master to the Slave - MOSI the data from Master to Slave, Master Out Slave In - MISO the data from Slave to Master, Master In Slave Out - SS_B the low active Chip Select aka Slave Select Even with this simple original definition of the signals there appears to be complete chaos between various implementations of SPI, e.g. - Do you send LSB or MSB first ? - Is the quiescent state of the SCLK Hi or Low ? - Which edge of the SCLK moves data and/or latches in received data ? - Does SS_B need to be released and then re-asserted for each transfer in a sequence of transfers ? The "solution" to this chaos was to put control registers in the Master so that the user could adjust their Master so that it would work OK with a variety of Targets (Slaves). With this facade of rationality some one said, let's dump the 2 uni-directional data lines and instead have a single bi-directional data line that we will call SIO. That is what AD did for example in the AD9083 PMT ADC. The problem is that it is not clear to me that the SPI Controllers in the MPFS250T can operate in this 3-Wire mode. The CPU Technical Reference Manual says it is, "compliant with the Motorola SPI, Texas Instruments synchronous serial, and NationalSemiconductor MICROWIRE formats", all of which a 4-wire versions of SPI. I have not yet found a bit in a SPI control register that would make it operate in 3-wire mode. For the SPI link to the Ethernet Phy Switch chip there is another layer of SPI chaos: OPEN Alliance with Protection, OPEN Alliance Without Protection, Generic SPI with 8-bit CRC, Generic SPI Without 8-bit CRC. List of UARTs in the FPGA/CPU that are used on the DK Board: ------------------------------------------------------------ For details about the UARTs in the MPFS250T-FCVG784 see page 79 of the "MSS Technical Reference Manual". For now make the following UART assignments: - UART_0 - Console port to the RS-485 Emergency Recovery - UART_1 - to the Interposer in this hemisphere - UART_2 - to the Interposer in the other hemisphere - UART_3 - to the Bluetooth Transceiver - UART_4 - not used