Signal vs FPGA Pin Swaps Mostly in the Control Signals to the Discrete Logic 14 Swaps 31-Dec-2024 Bank #1: -------- NET 'DK_CPU_IS_AWAKE' # Wait for DK CPU was U1-G6 GPIO174PB1 NET 'DK_CPU_IS_AWAKE' # Wait for DK CPU now U1-F7 GPIO180PB1 NET 'DK_CPU_IS_AWAKE_B' # to wake up was U1-F5 GPIO174NB1 NET 'DK_CPU_IS_AWAKE_B' # to wake up now U1-D6 GPIO179PB1 NET 'RUN_PMT_ADC' # Power Up was U1-E3 GPIO171PB1 NET 'RUN_PMT_ADC' # Power Up now U1-E7 GPIO180NB1 NET 'RUN_CLOCK_GENERATOR' # and Run was U1-D3 GPIO171NB1 NET 'RUN_CLOCK_GENERATOR' # and Run now U1-C7 GPIO182PB1/DQS NET 'RUN_BB_AUDIO_ADC' # signals to was U1-D6 GPIO179PB1 NET 'RUN_BB_AUDIO_ADC' # signals to now U1-E3 GPIO171PB1 NET 'RUN_USB_INTERFACE' # various DK was U1-C6 GPIO179NB1 NET 'RUN_USB_INTERFACE' # various DK now U1-E5 GPIO176NB1/DQS NET 'RUN_BARNACLE' # sub-sections was U1-F7 GPIO180PB1 NET 'RUN_BARNACLE' # sub-sections now U1-F5 GPIO174NB1 NET 'BARNACLE_CONTROL_1' # Barnacle was U1-E7 GPIO180NB1 NET 'BARNACLE_CONTROL_1' # Barnacle now U1-C6 GPIO179NB1 NET 'BARNACLE_CONTROL_2' # Control was U1-C7 GPIO182PB1/DQS NET 'BARNACLE_CONTROL_2' # Control now U1-D3 GPIO171NB1 NET 'POWER_B_CAMERA' # Camera "B" Power Control was U1-E5 GPIO176NB1/DQS NET 'POWER_B_CAMERA' # Camera "B" Power Control now U1-G6 GPIO174PB1 Bank #7: -------- NET 'SFP_TIMING_TRANS_ENABLE' # Timing SFP Laser Enable was U1-K8 GPIO148PB7 NET 'SFP_TIMING_TRANS_ENABLE' # Timing SFP Laser Enable now U1-J4 GPIO150PB7 NET 'SFP_ENET_TRANS_ENB_DIS' # Ethernet SFP Laser Enb/Dis was U1-J4 GPIO150PB7 NET 'SFP_ENET_TRANS_ENB_DIS' # Ethernet SFP Laser Enb/Dis now U1-K8 GPIO148PB7 Bank #9: -------- NET 'TG_AUX_IN_M5_via_Term' # TG M5 to/from FPGA was U1-A24 GPIO52NB9 NET 'TG_AUX_IN_M5_via_Term' # TG M5 to/from FPGA now U1-B24 GPIO52PB9 NET 'TG_AUX_IN_M6_via_Term' # TG M6 to/from FPGA was U1-B24 GPIO52PB9 NET 'TG_AUX_IN_M6_via_Term' # TG M6 to/from FPGA now U1-A24 GPIO52NB9