# # CB_Fan PCB Nets # # General Purpose Input 4 Signals Nets # ---------------------------------------- # # # Original Rev. 9-Mar-2012 # Most Recent Rev. 14-Apr-2012 # # # # This file holds the netss that make the # 4 General Purpose Input Signals. # # Start the section that has the nets that allow # the CB-Fan to receive 4 general purpose input lines, # as either LVDS, Diff_ECL, or single ended 3.3V logic, # and return these signals to the Control H-Clk card # on the same lines that are used for Scaler System # Almost_Full_1_2 and LNE_Event. # # Conn J13 is used to receive these 4 General Purpose # input lines as single ended 3.3V logic. # # Conn J12 is used to receive these 4 general Purpose # input lines as LVDS or Diff_ECL. # # Conn J7 is for the cable that returns 4 signals, # either Scaler System Almost_Full_1_2 and LNE_Enable # or these 4 general purpose input signals to the # Control H-Clk card. # Start by Grounding the even number pins on J13. NET 'GROUND' J13-2 J13-4 J13-6 J13-8 J13-10 # Connect the odd number pins on J13, i.e. the single # ended 3.3V logic signals, to the input of the LVDS Driver. NET 'GP_IN_1_TO_DRIVER_IN' J13-1 U56-7 # General Purpose 3.3V In 1 NET 'GP_IN_2_TO_DRIVER_IN' J13-3 U56-6 # General Purpose 3.3V In 2 NET 'GP_IN_3_TO_DRIVER_IN' J13-5 U56-3 # General Purpose 3.3V In 3 NET 'GP_IN_4_TO_DRIVER_IN' J13-7 U56-2 # General Purpose 3.3V In 4 # We also have pull-down resistors on these 4 General Purpose # Input signals which are needed on these CMOS inputs when # no real signal is connected to them. NET 'GP_IN_1_TO_DRIVER_IN' R171-2 # General Purpose Input #1 Pull-Down NET 'GP_IN_2_TO_DRIVER_IN' R172-2 # General Purpose Input #2 Pull-Down NET 'GP_IN_3_TO_DRIVER_IN' R173-2 # General Purpose Input #3 Pull-Down NET 'GP_IN_4_TO_DRIVER_IN' R174-2 # General Purpose Input #4 Pull-Down NET 'GROUND' R171-1 R172-1 R173-1 R174-1 # Ground the Pull-Downs # Connect the outputs from the 4 General Purpose Signal # LVDS Drivers to the pins are the J7 connector that run # these 4 General Purpose Input signals back to the Control # H-Clk card. At the same time pick up the pins on J12 # that allow you to receive the 4 General Purpose Input # signals at ECL or LVDS levels. Recall the the first # two pin pairs on J7 (going back to the Control H-Clk card) # may also be used to carry the Almost_Full_1_2 from the # Scaler System Control Bus. NET 'FULL_1_SCLR_OR_GPIN_1_DIR' U56-10 J12-1 # GP Signal #1 DIR back to the NET 'FULL_1_SCLR_OR_GPIN_1_CMP' U56-9 J12-2 # GP Signal #1 CMP Control H-Clk NET 'FULL_2_SCLR_OR_GPIN_2_DIR' U56-12 J12-3 # GP Signal #2 DIR back to the NET 'FULL_2_SCLR_OR_GPIN_2_CMP' U56-11 J12-4 # GP Signal #2 CMP Control H-Clk NET 'GPIN_3_DIR' U56-14 J12-5 J7-5 # GP Signal #3 DIR back to Control H-Clk NET 'GPIN_3_CMP' U56-13 J12-6 J7-6 # GP Signal #3 CMP NET 'GPIN_4_DIR' U56-16 J12-7 J7-7 # GP Signal #4 DIR back to Control H-Clk NET 'GPIN_4_CMP' U56-15 J12-8 J7-8 # GP Signal #4 CMP # Jumpers to enable the outputs of the 65LVDS391 # LVDS driver chip for the 4 General Purpose Input Signals. # Either or both pairs of LVDS outputs from the 65LVDS391 # may be separately enabled. NET 'GPIN_4_DRV_12_ENB' U56-1 R138-1 R139-2 # ENAB 65LVDS391 sections 1,2 NET 'GPIN_4_DRV_34_ENB' U56-8 R136-1 R137-2 # ENAB 65LVDS391 sections 3,4 NET 'VDD' R137-1 R139-1 # Pull-Up for EN NET 'GROUND' R136-2 R138-2 # Pull-Down for EN