CB-Fan Design Points Definition of the CB_Fanout Card ------------------------------------ Initial Rev. 8-Dec-2010 Current Rev. 17-May-2012 The following points define the structure of and the components used on the CB-Fan card. - The CB-Fan card is a 6U x 160mm double width VME-64X type card. It has 5 column 160 pin P1 and P2 VME backplane connectors. It does not have a P0 VME connector. It requires +3.3V and +5V power from the VME bus - We are building 14 CB-Fan cards. - The CB-Fan card will provide the following functions: 1. Make 8 standard Control Buses. 6 of these are ECL level Control Buses for the CAEN TDC cards and 2 of these are LVDS Control Buses for the trigger system (or other equipment to be built for HAWC. Each of these Control Buses receives 4 common signals from the Control H_Clk card: CRST, TRG, CLR, and CLK and can send back to the Control H-Clk card 2 individual signals: Almost_Full_1 and Almost_Full_2. Notes that Almost_Full_2 shares the same path to the Control H-Clk card as the 8 SBC_n_Busy signals noted below. 2. Make 1 additional special Control Bus for the Scaler System. This is called the 9th Control Bus. This Control Bus is special in a number of ways: It uses Load_Next_Event signal instead of the TRG signal that is on the standard Control Busses. The Almost_Full_1 and 2 signals from this 9th Control Bus are sent back to the Control H-Clk card on a separate path (J7) from the other Control Buses. One can either send the normal CRST and CLR signals to the 9th Control Bus or select to have these lines locked to the Low logic level on the 9th Control Bus. 3. Provide 16 bits of LVDS to ECL or ECL to LVDS conversion. This is specifically aimed at allowing external NIM signals to pass through a commercial NIM to ECL converter and then into an H-Clk card. The direction of the generic LVDS <--> ECL conversion is easy to change in the field. All 16 bits on a given CB-Fan card are either ECL --> LVDS or LVDS -->ECL. 4. Provide control of up to 8 SBCs by sending to them a Read_Now signal. This signal like the other control signals comes from the Control H-Clk card. Read Now is a single ended 3.3V logic level 110 Ohm back terminated signal. All 8 individually driven copies of this signal are sent out together, i.e. there is not individual control over sending Read_Now to each of the SBCs. The Read_Now signal may arrive on the CB-Fan card are either the 4th pair on connector J6, the Load_Next_Event / Read_Now signal or as the 5th pair on J6, the separate Read Now signal. 5. Provide individual SBC_n_Busy status signals from up to 8 SBCs to the Control H-Clk card. The SBC_n_Busy signals are received on the CB-Fan card as 3.3V single ended logic signals. They are converted to LVDS and sent to the Control H-Clk card on the same lines that can carry the 8 standard Control Bus Almost_Full_2 signals to the Control H-Clk. One can select to send either the SBC_n_Busy signals or the Almost_Full_2 signals to the Control H-Clk card. 6. The CB-Fan card send 4 additional signals to the Control H-Clk card. The source of these signals can be basically any combination of: the Almost_Full_1 and Almost_Full_2 signals from the special 9th Control Bus or 4 General Purpose Input Signals. The 4 General Purpose Input signals can be received on the CB-Fan card as either Diff ECL, LVDS, or single ended 3.3V logic level signals. - The CB-Fan card has the following 15 connectors: P1 and P2 are the VME backplane connectors. They make only power and ground connection to the backplane and loops through the VME Bus_Grant and IACK signals. J1 and J2 are the LVDS level standard Control Bus connectors. They are both standard 16 pin headers. Their pin out matches that used by the CAEN TDC cards. The J1 and J2 pin out is shown below. J3 and J4 are the ECL level standard Control Bus connectors. They are both standard 50 pin headers. In sections of 16 pins their pin out matches that used by the CAEN TDC cards. The J3 and J4 pin out is shown below. J5 is a standard 34 pin header. It carries the Almost_Full_1 signals and either the Almost_Full_2 signals or the SBC_n_Busy signals from the CB-Fan to the Control H-Clk card. The 40 MHz clock from the Control H-Clk card arrives on the CB-Fan card on pins 33, 34 of J5. The pin out of J5 is shown below. J6 is a standard 10 pin header. It carries the: CRST, TRG, CLR, Load_Next_Event / Read_Now, and separate Read_Now control signals from the Control H-Clk card to the CB-Fan card. Its pin out is shown below. J7 is a standard 10 pin header. It carries 4 signals to the Control H-Clk card. These signals may be basically any combination of: Almost_Full 1 and 2 signals from the special 9th Control Bus and the 4 General Purpose Input signals. The J7 pinout is shown below. J8 is the connector for the special 9th Control Bus for the Scaler system. It is a standard 16 pin header. The properties of the special 9th Control Bus were noted above. The J8 pin out is shown below. It matches the CAEN TDC. J9 is the ECL connector for the 16 bit ECL <--> LVDS converter. It can be either and ECL input or output. It is a standard 34 pin header. J9 pin out is shown below. J10 is the LVDS connector for the 16 bit ECL <--> LVDS converter. It can be either an LVDS input or output. It is a standard 34 pin header. The J10 pin out is shown below. J11 is the connector to the 8 SBCs. It carries both the 8 common Read_Now signals and the 8 individual SBC_n_Busy signals. All of these are 3.3V single ended logic level signals. J11 is a standard 34 pin header. The pin out of J11 is shown below. J12 is the input connector for 4 General Purpose Input signals if they are either ECL or LVDS signal levels. It is a standard 10 pin header. The J12 pin out is shown below. J13 is the input connector for 4 General Purpose Input signals if they are 3.3V single ended logic level signals. It is a standard 10 pin header. The J13 pin out is shown below. - Note that a compact functional summary of these 15 connectors is given near the end of the document: cb_fan_general_description.txt - Note that there is no "per Control Bus" control of the CRST, TRG, or CLR signals. Whenever the Control H-Clk card asserts one of these signals - it is sent out by the CB-Fan card to all of its Control Buses. Note that the Special #9 Control Bus for the Scaler System can be configured not to send the CRST and CLR signals. - The 40 MHz Clock signal is sent out to all Control Busses all of the time. There is no way to stop the 40 MHz Clock signal except by powering down the Control H-Clk card or the CB-Fan card. - On the CB-Fan card the Control Busses are numbered #1 through #9. #1 and #2 are standard LVDS level Control Buses. #3 through #8 are standard ECL level Control Buses. #9 is the special Control Bus for the Scaler System - ECL levels. - The LNE_Enable can land on the CB-Fan card as one of the General Purpose input signals and from there be routed to the Control H-Clk card. - There are a number of single ended 3.3V logic level input signals to the CB-Fan card. These include the 8 SBC_n_Busy signals and the 4 3.3V General Purpose Input signals. These inputs all have 50k Ohm pull-down resistors so it is safe to leave them floating if your application of the CB-Fan card does not require their use. - Because of the mixture of signal levels (3.3V CMOS, TTL, LVDS, and Negative ECL) the CB-Fan card has a significant number of power distribution voltages: GND, +5V Vcc, +3.3V Vdd, two -2V Vtt buses, and two -4.5V Vee buses. Using a separate power plane for each power supply voltage would require many physical layers in the CB-Fan card and thus make it an expensive card to manufacture. Instead of separate physical layers the power distribution was done using area fills with complicated shapes on 2 physical layers. 2 other physical layers are 100% ground planes. The -2V and -4.5V buses for the ECL logic are generated by on board power converters near the P1 backplane connector. - Maximum Skew Estimates: The CRST, TRG, CLR, and CLK signals are all fanned out to the Control Buses in the same way on the CB-Fan card. This fanout involves: Receive the signal from the Control H-Clk card with a DS90LV110T LVDS input, LVDS output, low skew, low jitter clock distribution chip which makes up to 10 copies of the signal. 144 psec typ jitter 35 psec typ skew The LVDS Control Buses are directly driven by outputs from the DS90LV110T distribution chip. In each ECL section of the CB-Fan distribution system the signal is receive with a SN65LVDT34D LVDS input, 3.3V CMOS output, receiver chip. 200 psec propagation high-low vs low-high skew 1 nsec part to part skew On the ECL Control Busses this is followed by a 100324QC TTL input, negative ECL output driver chip. 1.2 nsec max skew - The pinout of the Control-Bus as defined by CAEN is the following: Pins CAEN Name HAWC Function Signal Direction ------ --------- ------------------ ---------------- 1,2 CRST Bunch Reset Signal to the TDCs 3,4 TRG Trigger Signal to the TDCs 5,6 CLR Clear Signal to the TDCs 7,8 CLK 40 MHz Clock to the TDCs 9,10 L2_Acp Not Used No Connection 11,12 L2_Rej Not Used No Connection 13,14 Out_Prog Almost_Full_1 from the TDCs 15,16 AUX Almost_Full_2 from the TDCs As with most ECL connector systems the Odd numbered pin is the Direct side of the signal and the Even numbered pin is the Complement side of the differential ECL signal. The signals that are inputs to the TDC are terminated with 110 Ohm resistors inside the TDC. ECL pull-down current is not provided by these TDC inputs. The ECL output signals from the CB-Fan card have pull-down current provided on the CB-Fan card. The ECL signals that are outputs from the TDC have ECL pull-down current provided by the TDC. The CB-Fan card terminates its ECL inputs with 110 Ohm resistors. - Detailed Connector Pinouts: J1 and J2 Pinout 16 pin LVDS standard Control Buses Pins CAEN Name HAWC Function Signal Direction ------ --------- ------------------ ---------------- 1,2 CRST Bunch Reset Signal to the TDCs 3,4 TRG Trigger Signal to the TDCs 5,6 CLR Clear Signal to the TDCs 7,8 CLK 40 MHz Clock to the TDCs 9,10 L2_Acp Not Used No Connection 11,12 L2_Rej Not Used No Connection 13,14 Out_Prog Almost_Full_1 from the TDCs 15,16 AUX Almost_Full_2 from the TDCs J3 and J4 Pinout 50 pin ECL standard Control Buses J3 has Control Busses #3, #4, #5 J4 has Control Busses #6, #7, #8 J3-J4 J3-J4 J3-J4 C-Bus C-Bus C-Bus 3,6 4,7 5,8 Pins Pins Pins CAEN Name HAWC Function ------- ------- ------- --------- ------------- 1,2 17,18 33,34 CRST Bunch Reset 3,4 19,20 35,36 TRG Trigger 5,6 21,22 37,38 CLR Clear 7,8 23,24 39,40 CLK 40 MHz Clk 9,10 25,26 41,42 L2_Acp Not Used 11,12 27,28 43,44 L2_Rej Not Used 13,14 29,30 45,46 Out_Prog Almost_Full_1 15,16 31,32 47,48 AUX Almost_Full_2 Connectors J3 and J4 have pins #49 and #50 grounded on the CB-Fan card. J5 Pinout 34 pin Status signals to the Control H-Clk card J5 Pin Numbers Signals Sent to the Control H-Clk Card ------- -------------------------------------------------- 1,2 Almost_Full_1 from Control_Bus_1 3,4 Almost_Full_2 from Control_Bus_1 or SBC_1_Busy 5,6 Almost_Full_1 from Control_Bus_2 7,8 Almost_Full_2 from Control_Bus_2 or SBC_2_Busy 9,10 Almost_Full_1 from Control_Bus_3 11,12 Almost_Full_2 from Control_Bus_3 or SBC_3_Busy 13,14 Almost_Full_1 from Control_Bus_4 15,16 Almost_Full_2 from Control_Bus_4 or SBC_4_Busy 17,18 Almost_Full_1 from Control_Bus_5 19,20 Almost_Full_2 from Control_Bus_5 or SBC_5_Busy 21,22 Almost_Full_1 from Control_Bus_6 23,24 Almost_Full_2 from Control_Bus_6 or SBC_6_Busy 25,26 Almost_Full_1 from Control_Bus_7 27,28 Almost_Full_2 from Control_Bus_7 or SBC_7_Busy 29,30 Almost_Full_1 from Control_Bus_8 31,32 Almost_Full_2 from Control_Bus_8 or SBC_8_Busy 33,34 40 MHz Clock from H-Clk to CB-Fan J6 Pinout 10 pin Control signals from the Control H-Clk card J6 Pin Numbers Signals Received from the Control H-Clk Card ------- -------------------------------------------------- 1,2 CRST 3,4 TRG 5,6 CLR 7,8 Load_Next_Event / Read_Now 9,10 separate 5th pair Read_Now J7 Pinout 10 pin Status signals to the Control H-Clk card J7 Pin Numbers Signals Sent to the Control H-Clk Card ------- -------------------------------------------------- 1,2 Almost_Full_1 from Scaler Control Bus #9 or General Purpose Input #1 3,4 Almost_Full_2 from Scaler Control Bus #9 or General Purpose Input #2 5,6 General Purpose Input #3 7,8 General Purpose Input #4 9,10 no connection J8 Pinout 16 pin Control Bus #9 to the Scaler System Pins CAEN Name HAWC Function Signal Direction ------ --------- ------------------ ---------------- 1,2 CRST Bunch Reset Signal * to the Scalers System 3,4 TRG Trigger Signal to the Scalers System 5,6 CLR Clear Signal * to the Scalers System 7,8 CLK 40 MHz Clock to the Scalers System 9,10 L2_Acp Not Used No Connection 11,12 L2_Rej Not Used No Connection 13,14 Out_Prog Almost_Full_1 from the Scalers System 15,16 AUX Almost_Full_2 from the Scalers System * --> CRST and CLR may be locked to Low logic level J9 Pinout 34 pin ECL side of the ECL <--> LVDS Converter J9 Pin Numbers Differential ECL Signals In or Out ------- -------------------------------------------------- 1,2 ECL <--> LVDS Converter Signal #1 ECL side 3,4 ECL <--> LVDS Converter Signal #2 ECL side 5,6 ECL <--> LVDS Converter Signal #3 ECL side 7,8 ECL <--> LVDS Converter Signal #4 ECL side 9,10 ECL <--> LVDS Converter Signal #5 ECL side 11,12 ECL <--> LVDS Converter Signal #6 ECL side 13,14 ECL <--> LVDS Converter Signal #7 ECL side 15,16 ECL <--> LVDS Converter Signal #8 ECL side 17,18 ECL <--> LVDS Converter Signal #9 ECL side 19,20 ECL <--> LVDS Converter Signal #10 ECL side 21,22 ECL <--> LVDS Converter Signal #11 ECL side 23,24 ECL <--> LVDS Converter Signal #12 ECL side 25,26 ECL <--> LVDS Converter Signal #13 ECL side 27,28 ECL <--> LVDS Converter Signal #14 ECL side 29,30 ECL <--> LVDS Converter Signal #15 ECL side 31,32 ECL <--> LVDS Converter Signal #16 ECL side 33,34 no connection These may be ECL input or output signsl depending on how the ECL <--> LVDS converter has been setup. J10 Pinout 34 pin LVDS side of the ECL <--> LVDS Converter J10 Pin Numbers LVDS Signals In or Out -------- -------------------------------------------------- 1,2 ECL <--> LVDS Converter Signal #1 LVDS side 3,4 ECL <--> LVDS Converter Signal #2 LVDS side 5,6 ECL <--> LVDS Converter Signal #3 LVDS side 7,8 ECL <--> LVDS Converter Signal #4 LVDS side 9,10 ECL <--> LVDS Converter Signal #5 LVDS side 11,12 ECL <--> LVDS Converter Signal #6 LVDS side 13,14 ECL <--> LVDS Converter Signal #7 LVDS side 15,16 ECL <--> LVDS Converter Signal #8 LVDS side 17,18 ECL <--> LVDS Converter Signal #9 LVDS side 19,20 ECL <--> LVDS Converter Signal #10 LVDS side 21,22 ECL <--> LVDS Converter Signal #11 LVDS side 23,24 ECL <--> LVDS Converter Signal #12 LVDS side 25,26 ECL <--> LVDS Converter Signal #13 LVDS side 27,28 ECL <--> LVDS Converter Signal #14 LVDS side 29,30 ECL <--> LVDS Converter Signal #15 LVDS side 31,32 ECL <--> LVDS Converter Signal #16 LVDS side 33,34 no connection These may be LVDS input or output signsl depending on how the ECL <--> LVDS converter has been setup. J11 Pinout 34 pin SBC Control and Status Connector J11 Pin Numbers SBCs_Read_Now and SBC_n_Busy Signals -------- ----------------------------------------- 1 SBCs_Read_Now 3 SBC_1_Busy 5 SBCs_Read_Now 7 SBC_2_Busy 9 SBCs_Read_Now 11 SBC_3_Busy 13 SBCs_Read_Now 15 SBC_4_Busy 17 SBCs_Read_Now 19 SBC_5_Busy 21 SBCs_Read_Now 23 SBC_6_Busy 25 SBCs_Read_Now 27 SBC_7_Busy 29 SBCs_Read_Now 31 SBC_8_Busy 33 no connection All even numbered pins on J11 are grounded. J12 Pinout 10 pin ECL LVDS General Purpose Input Signals 1:4 J12 Pin Numbers ECL or LVDS Level General Purpose Input Signals -------- -------------------------------------------------- 1,2 General Purpose Input Signal #1 3,4 General Purpose Input Signal #2 5,6 General Purpose Input Signal #3 7,8 General Purpose Input Signal #4 9,10 no connection J13 Pinout 10 pin 3.3V General Purpose Input Signals 1:4 J13 Pin Numbers 3.3V Logic Level General Purpose Input Signals -------- -------------------------------------------------- 1 General Purpose Input Signal #1 3 General Purpose Input Signal #2 5 General Purpose Input Signal #3 7 General Purpose Input Signal #4 9 no connection All even numbered pins on J13 are grounded. - There are many options on the CB-Fan card that may be selected. The following section describes the various jumpers that are used to enable or disable these various options. These jumpers are 0603 SMD Zero-Ohm "resistor" packages and thus have "R" series Reference Designators. R101, R102 Install to send Conrol Bus #3 Almost_Full_2 to Control H-Clk R103, R104 Install to send Conrol Bus #4 Almost_Full_2 to Control H-Clk R105, R106 Install to send Conrol Bus #5 Almost_Full_2 to Control H-Clk R107, R108 Install to send Conrol Bus #6 Almost_Full_2 to Control H-Clk R109, R110 Install to send Conrol Bus #7 Almost_Full_2 to Control H-Clk R111, R112 Install to send Conrol Bus #8 Almost_Full_2 to Control H-Clk R113, R114 Install to send Conrol Bus #1 Almost_Full_2 to Control H-Clk R115, R116 Install to send Conrol Bus #2 Almost_Full_2 to Control H-Clk R121 Install to disable sending SBC_1:4_Busy from U53 to Control H-Clk R122 Install to enable sending SBC_1:4_Busy from U53 to Control H-Clk Install only R121 or R122 not both or you will short the Vdd bus R123 Install to disable sending SBC_5:8_Busy from U54 to Control H-Clk R124 Install to enable sending SBC_5:8_Busy from U54 to Control H-Clk Install only R123 or R124 not both or you will short the Vdd bus R125 Install to select the 5th pair on J6, i.e. separate Read_Now as the source of the SBCs Read_Now signal R126 Install to select the 4th pair on J6, i.e. Load_Next_Event / Read_Now as the source of the SBCs Read_Now signal R132 Install to send the CRST signal to Control Bus #9 - Scaler System R133 Install to lock Low the CRST signal to Control Bus #9 - Scaler System R134 Install to send the CRL signal to Control Bus #9 - Scaler System R135 Install to lock Low the CRL signal to Control Bus #9 - Scaler System R136 Install to disable 3.3V General Purpose Input Signals 1 & 2 R137 Install to enable 3.3V General Purpose Input Signals 1 & 2 Install only R136 or R137 not both or you will short the Vdd bus R138 Install to disable 3.3V General Purpose Input Signals 3 & 4 R139 Install to enable 3.3V General Purpose Input Signals 3 & 4 Install only R138 or R139 not both or you will short the Vdd bus - The 16 bit generic Differential ECL <--> LVDS Converter is configured with the following jumpers and resistor packs: J231 Install the jumper between pins 1 and 2 for ECL input LVDS output J231 Install the jumper between pins 2 and 3 for LVDS input ECL output Never jumper J231 pins 1 and 3 together or you will short Vdd bus For ECL input to LVDS output Install 6 pin SIP resistor packs that contain 3 isolated 120 Ohm resistors in the sockets at: R221, R222, R223, R224, R225, R226, R227, R228. Typically these resistor packs will be: CTS Part No. 750-63-R120 Ohm Bourns Part No. 4306R-102-121LF For LVDS input to ECL output Install 6 pin SIP resistor packs that contain 5 bused 56 Ohm resistors in the sockets at: R221, R222, R223, R224, R225, R226, R227, R228. Typically these resistor packs will be: CTS Part No. 750-61-R56 Ohm Bourns Part No. 4606X-101-560 - There are a number of additional jumpers, vias, and other features on the CB-Fan card that may be useful in certain applications of this card. They are: R131 This jumper runs between Vdd and the Output Enable pin, pin #5, of the DS90LV110T control signal fan out chips. The output enable pin of the DS90LV110Ts must be voltage Hi for its outputs to be enabled - thus jumper R231 is normally installed. R231 This jumper runs between Vdd and the Master Enable pin, pin #10, of the DS91M040 LVDS transceiver chips. The master enable pin of the DS91M040 must be voltage Hi for these chips to power up and operate - thus jumper R231 is normally installed. R232 This jumper runs between Gnd and the FSEN 1 & 2 pins, pin #9 & #32, of the DS91M040 LVDS transceiver chips. The FSEN 1 & 2 pins control whether the LVDS receivers have a conventional type 1 symmetric input threshold or a 50 mV offset type 2 failsafe input threshold. With the FSEN 1 & 2 pins held voltage Low the LVDS input have. conventional symmetric thresholds. Jumper R232 is normally installed. R233 This jumper runs between Gnd and the Latch Enable pin, pin #21, of the 100398 Differential ECL transceiver chips. When the Latch 100398 Enable pin is held voltage Low the the latches in this chip are transparent. Thus jumper R233 is normally installed. R234 This jumper runs between Vcc and the Output Enable pin, pin #9, of the 100398 Differential ECL transceiver chips. This Output Enable pin must be pulled voltage Hi for the 100398 outputs to be enabled in either direction. Thus jumper R234 is normally installed. The TRIG and CLK fan out chips, DS90LV110T chips U2 and U4, have vias on their unused outputs to make it easy to access these signals in the future if that is necessary. The Output Enable pin, pin #16, on all of the 100324 Differential ECL driver chips for the Control Buses do not have a jumper or via on them - rather they were all routed through a loop that is external to the chip's foot-print. Thus if one needs to access these Output Enable pins it is straight forward to do so. As built these pins are held voltage Hi to enable the outputs from these chips. These are chips: U27, U28, U37, U38, U43. The unused section of U55, a 65LVDT34D LVDS receiver chip has vias on its input and output pins just in case access to them is necessary in the future. The unused sections of U51, a 74LVC541 Octal Buffer chip, has its inputs pulled Low. Access to the input and output of this SO-20 package chip has been made possible just in case it is needed in the future. The 8 SBC_n_Busy inputs and the 4 General Purpose Inputs may or may not be used or perhaps only a subset of them will be used on a given card. All of these inputs have been equipped with 50k Ohm pull down resistors so these CMOS inputs are safe whether or not they are driven by a signal. Four extra mounting holes for M2.5 screws have been provided on the CB-Fan card. As built nothing will be installed in these holes. They are located at: 137.2, 16.0 137.2, 46.0 135.0, 178.0 135.0, 217.0 Eight extra ground access vias have been provided at locations distributed around the CB-Fan card. These are 1.1mm land 0.7mm hole diameter vias with thermo relief that are tied to both ground planes. They can be used for scope loop grounds or for future modifications to the CB-Fan card. Connection to any of the power buses on the card: Vcc, Vdd, Vtt, Vee are provided at the multi via connected tantalum capacitor locations on the card. U56 the 65LVDS391 quad LVDS driver chip for the 4 single ended General Purpose Input signals is setup so that either or both pairs of its outputs can be enabled. Thus if necessary one can mix and match single ended vs Diff_ECL LVDS General Purpose Inputs signal formats at the pair level. There may be some advantage in grounding the unused Control Bus signal lines that carry the L2_Acpt and L2_Rej signals to the CAEN TDC cards. These 2 control signals are not used by the TDC cards. For all 9 copies of the Control Bus that are sent out from the CB-Fan card, ground vias have been provided near the connector pins for these unused signals so that these lines may easily be grounded if that seems appropriate in the future. The non-isolated DC/DC converters to make the -2.0V and -4.5V Vtt and Vee power buses have been conservatively sized so that power is available for additional ECL receivers, drivers, or logic if that is necessary in the future.