CB-Fan Layout Details --------------------------- Initial Rev. 20-Jan-2012 Current Rev. 3-May-2012 This file is the technical layout and engineering details of the CB-Fanout card for the HAWC Experiment. See the CB-Fan-Design-Points file for a description of this card. Board Size: ----------- Make the CB-Fan card a rationalized 6U VME 160.0mm wide in X by 233.0mm high in Y CB-Fan Stackup and Mentor Layer Usage ------------------------------------- - This card will require at least 3 signal trace routing layers. It can not be done in 2 trace layers because of the large number of traces that must criss-cross. - Power Sections: +3.3V power entry +5.0V power entry Vdd +3.3V power distribution Vcc +5.0V power distribution special Vcc +5V distribution to the negative converters Vee_1 distribution Vee_2 distribution Vtt_1 distribution Vtt_2 distribution On this design only the 2 fuses need to go next to P1, P2. The power entry Varistors and Bulk Caps can go where there is space. - Ground Planes: This card used 2 full coverage ground planes. These ground planes are done as "negative data". There are slits in the ground planes around the negative converters. These slits are lines in the DAM_2 layer. Ground planes are Physical layer #2 and #5 and are exactly the same. - Stackup: Physical Mentor Layer Function Logical Layer Color ------- -------------------------------- --------------- ------- 1 Trace layer top Mentor Signal_1 (Green) 2 Ground Mentor Power_1 (Brown) 3 Vdd & Vee fills, internal traces Mentor Signal_2 (Yellow) 4 Vcc & Vtt fills, internal traces Mentor Signal_3 (Tan) 5 Ground plane Mentor Power_2 (Brown) 6 Trace layer bottom Mentor Signal_4 (Red) - Power Fill Requirements and implementation: The Vcc and Vee planes must be able to occupy the same area. Vcc and Vee_1 are both needed directly under the 100324QC chips. Vcc and Vee_2 need to be almost on top of each other under the 100398QC chips. Vcc and Vdd are both kind of needed under the passive components in the upper left-hand corner. General Implementation Plans: Use a shape to embed the Vee_1 distribution in the Vdd plane. This shape starts at the K2 output filter and has a finger to the left that comes down for U27, U28, U37, U38, C157 and a separate finger to the right that comes down for U43. Use a shape to embed the Vee_2 distribution in the Vdd plane. This shape starts at K4 and runs to the West under U201, U202, U203, U204, and C158. All of the rest of Physical 3 Mentor Signal 2 is the Vdd power fill except for 2 additional power fills for VME power entry for +3.3V and +5.0V which run in small areas right next to P1 and P2 to connect to the power entry fuses. Vtt_1 and Vtt_2 are fills embeded in the Vcc power fill. All of these are on Physical 4 Mentor Signal 3. - Physical #3 Mentor Signal #2 Layer Usage and Contents: Fills: Vdd, Vee_1, Vee_2, VME +3.3V entry, VME +5.0V entry Traces: One short differential pair embeded in Vdd - Physical #4 Mentor Signal #3 Layer Usage and Contents: Fills: Vcc, Vtt_1, Vtt_2 Traces: A major section of the fanout criss-cross Recall General Conservative Routing Guidelines: ----------------------------------------------- - Vias via_0mm7 can be set on 1.2mm center to center. - 0.25mm width traces on 1.5mm center to center to clear a via_0mm7 that is between them. - 0.20mm width single ended logic traces on 0.6mm center to center. - 0.20mm width differential pair on 0.5mm center to center with a unit cell pitch of 1.5mm from one pair to the next. Thus you can fit 8 of these differential pairs in 12mm. - 0.25mm width differential pair on 0.6mm center to center. - 0.30mm width differential pair on 0.6mm center to center. Trace Widths Actually Used In CB-Fan Layout ------------------------------------------- 0603 Ceramic bypass caps 0.60 mm 0.70 via 0.50 or 0.60 to center 0805 Ceramic Capacitors: 1.0 mm power traace in the Power Converters: 1.0 mm Gnd trace with 1mm1 via spaced 1.0mm Tant D pads 2x 1.20 mm 1mm1 via CL on pad edges Al Electrolytic F pads 2x 1.20 mm 1mm1 via edge on pad edges Transient Suppressor pads 1.20 mm 1mm1 via in center Fuse Holder pads 2x 4x 1.20 mm 1mm1 via Power Converter Power Traces: 2.50 mm Power Traces: backplane, fuse 1.50 mm, 2.00 mm, 3.00 mm Very thick "signal" traces 0.50 mm 0.70 via Escape the TSSOP-28 signals 0.20 mm 0.70 via power, ground 0.30 mm 0.70 via Escape the SOIC-8 signals 0.25 mm 0.70 via Alt 0.30 trc power, ground 0.50 mm 0.70 via 0.60mm edge to center Escape the SOIC-16p signals 0.25 mm 0.70 via Alt 0.30 trc power, ground 0.60 mm 0.70 via 0.60mm edge to center Escape the PCC-28 signals 0.25 mm 0.70 via Alt 0.30 trc power, ground 0.50 mm 0.70 via 0.60mm edge to center Escape the SO-20p signals 0.25 mm 0.70 via Alt 0.30 trc power, ground 0.50 mm 0.70 via 0.60mm edge to center Escape the LLP-32 signals 0.20 mm 0.70 via power, ground 0.20 mm 0.70 via The 4 x 9 criss-cross section uses 0.20 mm traces spaced 0.50 mm CC. They step 0.30 mm at the 45 deg bends. In parallel runs the two physically adjacent traces from different pairs are spaced 1.3 mm CC, i.e. a 1.8mm unit cell. In pairs the like traces step 1.0 mm between groups of pairs that make a 45 deg bend. Vias may approach a trace more closely if both sides of the attacking signal have vias at the same distance, i.e. a differential attack. As much trace length as practical was run at 45 deg to minimize the overall trace length. Reference Designators: ---------------------- - Connectors 160 pin VME P1, P2 34 pin Status J5 10 pin Status J7 - Control Fanout: ICs U1:U4 Connector J6 Resistors R1:R4, R131 Bypass Caps C11:C18 - Control Buses 1,2 Connectors J1, J2 Resistors R113:R116 - Control Buses 3,4,5 ICs U21:U28 Connector J3 Resistors R21:R44 R101:R106 Bypass Caps C21:C42 - Control Buses 6,7,8 ICs U31:U38 Connector J4 Resistors R51:R74 R107:R112 Bypass Caps C51:C72 - Scaler Control Bus 9 ICs U41:U43 Connector J8 Resistors R81:R88 R132:R135 Bypass Caps C81:C92 - SBCs Read_Now & Busy ICs U51:U55 Connector J11 Resistors R91:R98 R121:R126 R161:R168 Bypass Caps C101:C110 - General Purpose Input IC U56 4 bit Connectors J12, J13 Resistors R136:R139 R171:R174 Bypass Caps C121, C122 - Generic LVDS<-->ECL ICs U201:U208 16 bit Connectors J9, J10 Resistors R201:R216 R221:R228 Bypass Caps C201:C206 C211:C218 C221:C228 - Generic LVDS<-->ECL Transistors Q231, Q232 Dir Control Connector J231 Resistors R231:R238 - Front-Panel Display ICs U57, LED1, LED2 and Grounds Resistors R141:R148 R151:R153 Capacitors C141, C142 Bypass Caps C143, C144 - Power Entry Vdd +3.3V F301, D301, C301, C302 Vcc +5.0V F302, D302, C303, C304, C305, C306 - Suplemental Tantalums Vdd C151, C152, C153 Vcc C154, C155, C156 Vee_1 C157 Vee_2 C158 Vtt_1 C159 Vtt_2 C160 - Converters Vtt_1 Converter K1 Resistor R311 Inductors L1, L2 Tantalum Caps C311:C313 Ceramic Caps C314:C324 Vee_1 Converter K2 Resistor R331 Inductors L3, L4 Tantalum Caps C331:C333 Ceramic Caps C334:C344 Vtt_2 Converter K3 Resistor R351 Inductors L5, L6 Tantalum Caps C351:C353 Ceramic Caps C354:C364 Vee_2 Converter K4 Resistor R371 Inductors L7, L8 Tantalum Caps C371:C373 Ceramic Caps C374:C384 Components Files: ----------------- In CB-Fan the final Components file to come out of .../Work/Components/ is version 408. Version 409 is exactly the same components data - but as written by Mentor. From 409 on all file are written by Mentor and are silkscreen changes only. Fairchild 100324, 100325, and 100398 ECL parts: ----------------------------------------------- - The Fairchild 1003xy ECL chips in the 28 pin PCC package are about 0.175" tall, i.e. they can not fit on the back side of a VME card. - The pinout of the TTL to ECL and the ECL to TTL parts do not match very well. TTL->ECL ECL->TTL TTL->ECL ECL->TTL Pin 100324 100325 Pin 100324 100325 Num Function Function Num Function Function --- -------- -------- --- -------- -------- 1 Gnd Gnd 15 Vee Vee 2 Gnd Gnd 16 Enable D3 in 3 Gnd Q2 out 17 Vcc D3\ in 4 Q3 out Q1 out 18 D0 in D4 in 5 Q3\ out Q0 out 19 D1 in D4\ in 6 Q4\ out D0\ in 20 D2 in D5 in 7 Q4 out D0 in 21 Q0 out D5\ in 8 Vee Vee 22 Vee Vee 9 Q5\ out D1\ in 23 Q0\ out Q5 out 10 Q5 out D1 in 24 Q1 out Q4 out 11 D5 in D2\ in 25 Q1\ out Q3 out 12 D4 in D2 in 26 Q2\ out Vcc 13 D3 in Vbb out 27 Q2 out Vcc 14 Vee Vee 28 Gnd Gnd The footprints do not match very well. Not all power supply and ground pins are the same. ECL and TTL pins do not match. This forces separate layout patters where conversion in both directions is required. TTL<-->ECL TTL<-->ECL Translator Translator Pin 100398 Pin 100398 Num Function Num Function --- ---------- --- ---------- 1 Gnd 15 Gnd 2 Gnd 16 Gnd 3 Vee 17 Vcc 4 ECL_2 18 TTL_1 5 ECL_2\ 19 TTL_0 6 ECL_3 20 Gnd 7 ECL_3\ 21 LE 8 Gnd 22 Gnd 9 OE 23 ECL_0\ 10 DIR 24 ECL_0 11 Gnd 25 ECL_1\ 12 TTL_3 26 ECL_1 13 TTL_2 27 Vee 14 Vcc 28 Gnd Vcc = +5.0V Gnd = Gnd Vee = -4.5V DIR TTL Low --> ECL Input TTL Output TTL Hi --> TTL Input, ECL Output OE TTL Low --> ECL is cut-off, TTL is 3 stated TTL Hi --> Selected driver is enabled LE TTL Low --> Latch is transparent TTL Hi --> Latches hold Estimate of ECL part power requirements (per full chip) Part Vee Vcc Channels per Chip -------- ----- ----- ----------------- 100324 45 25 mA typ 6 100325 27 45 mA typ 6 100398 159 39 mA max 4 Estimated current draw to -2V per differential pair using 56 Ohm pull-downs: Vout High = -0.955 V --> 18.66 mA across 56 Ohm to -2V Vout Low = -1.705 V --> 5.27 mA across 56 Ohm to -2V Total of 23.93 mA to -2V per differential pair. Estimated of the ECL supply current on each bus based on running: 5x 100324, 4x 100398, 44x Diff ECL Terminator Vee Bus Vcc Bus Vtt Bus ------- ------- ------- 861 281 1053 mA --> 7.39 Watts Total Estimated of the ECL supply current on each bus based on running: 5x 100324, 4x 100398, 44x Diff ECL Terminator and broken up into the individual converters. Control Buses Generic 16 Bit Converter ------------------------- ------------------------- Vee_1 Vcc_1 Vtt_1 Vee_2 Vcc_2 Vtt_2 ----- ----- ----- ----- ----- ----- 225 125 670 636 156 383 mA CB-Fan Drawings: ---------------- - The CB-Fan Drawings will be done in its own .../Work/Drawings/ directory. Seed this with a frozen copy of the H-Clk drawings on 24-Jan-12. Area Fill Generation: --------------------- Note that for the Area Fill generation on the CB_Fan card only I have set the Signal pad diameter for only the VME 5x32 connector in the term_hart_vme geometry to 1.50mm from its normal 1.60mm. This is to optimize the area fill under the VME connectors on just the CB_Fan card for the nets that get +5V and +3V3 power from the VME backplane. Setup the Area Fill clearances from the: Setup Routing --> Setup Net Type Rules menue. For the Default_Net_Type setup: 0.4 mm clearance between Fill and Pin 0.4 mm clearance between Fill and Via 0.8 mm clearance between Fill and Trace 0.5 mm clearance between Fill and Fill Setup the details of the Area Fill for CB-Fan by: Pull Down Setup Routing --> Setup Area Fill Pad Isolation : Polygon Tolerance = 0.025 mm Manufacture Aperature: 0.20 mm <-----<-----< Slot Threshold: try 1.1 mm Solid Fill, NO Keep Islands, YES Allow Merge Do Not ignore area fill to via clearance for the same net Do Not ignore area fill to pin clearance for the same net Thernal: Pins, and Pads use thermal ties Both Pins and Pads are setup the same: Prefer 4 ties, Minimum 3 ties, prefer 45/135 degree Tie_Bar_Width 0.5 mm Select Floading for Via's Traces File Versions to KEEP - Based on 3-May-12 build of the Fills using Comps_426: Note: that traces_94_svd and traces_96 are exactly the same. Traces Version Cmps Nets Conn Fnsh UFin Guid Size Characteristics ------- ---- ---- ---- ---- ---- ---- ---- --------------- 96 430 402 1681 1465 121 95 284k Stable No Fills 97 430 402 1689 1575 69 45 884k With Sig #3 Fills 98 430 402 1695 1695 0 0 1845k Sig #2 & #3 Fills The initial "final" fills were ready on 25-Apr-12 using trace files: 88, 90, 91. These were all dumped on 26-Apr-12 when Jim asked me to add NIM inputs based on Gerd's suggestion. Start the Fill work on Physical #4 Mentor Signal #3 Fill starting with Vtt_1 then Vtt_2 and finally Vcc. To generate the Area Fills: Vtt_1, Vtt_2, Vcc Recall that these nets are on Physical #4 Mentor Signal #3. Pull Down Setup --> Shape Edit Mode ON Select the shape from the Shape Edit layer Right Click --> Change Shape to Fill: Area Fill ? vs Power Fill ? This is an Area Fill because it is on a trace layer and not on a power plane layer. Select Layer = Signal_3 Select Net = Vtt_1 ... Keep all Area Fill defaults NO delete the original shape typical warning: Area Fill is fractured into "N" pieces. After generating the 3 area fills - save traces. If necessary to delete and area fill use FabLink: Select the Area Fill on its Signal_ layer Area Fill Panel Menu --> Delete vertexes Now do the Fill work on Physical #3 Mentor Signal #2 Generate the Area Fills: Vee_1, Vee_2, Vdd, VME_5V, VME_3V3 in that order. Note: Recall some details of making CB-Fan Area Fills These are area fills within an area fills. ---> The trick is just to generate in inner fill first and then generate the surrounding outer fill. The fill-to-fill clearance specification will keep the 2 fills separated. You do not need to explicitly use a KeepOut region. Design Rule Checks ------------------ CB-Fan was routed with the following: Pin Via Trace Fill Pin 0.50 Via 0.06 0.40 Trace 0.22 0.30 0.25 Fill 0.40 0.40 0.80 0.50 DRC runs on: 26-Apr-12 Running at: nets_242 22-Apr-2012 comps_405 22-Apr-2012 Silkscreen is not finished traces_91 25-Apr-2012 Layout says: 426 Comps 402 Nets 1642 Finished Traces 0 UnFin Guid Starting from the "as built" Net based clearances for CB_Fan of: Pin Via Trace Fill Pin 0.50 Via 0.06 0.40 Trace 0.22 0.30 0.25 Fill 0.40 0.40 0.80 0.50 Run the following and crank the clearances up to see if things are rationa: Check --> Traces --> Check_Traces Entire Board Remove Trace Violations NOT Selected Check Net Against Itself NOT Selected Check Trace Widths Less Than Net Rules NOT Selected Check All Thermal Ties on Pins and Vias Selected Check Same Net Pad to Pad Clearances Selected Remove Duplicate Routing NOT Selected Check Pad Connectivity With Fill Hatch NOT Selected Report Off Grid Vias as: Not Checked Report Uncovered Plated Drill Holes as: Warnings This shows: 3 expected problems where the weak grounds are connected to the front-panel and 16 problems with U205:U208 with the vias that tie the DAP pad to thermal ground. The front-panel weak ground trace problems are expected but the DAP Thermal Via to Area Fills are a real clearance problem (caused by just now fixing the pad size on the Thermal Via but not yet re-building the Area Fills). If I set the Pin to Area Fill to 0,3mm clearance then it is OK - but I should re-build the Fills. The current actual clearance is about 0,35mm). 30-April-12 Another round of DRC checks usinging Running at: nets_243 30-Apr-2012 added "emergency" ground vias comps_409 30-Apr-2012 Silkscreen is not finished traces_92 30-Apr-2012 no Fills Trace to Pin is OK at 0.27mm. It blows up at 0.28mm in the llp-32 pad layout. Trace to Via is OK at 0.30mm. It blows up with 4 errors at 0.31mm in the llp-32 section. Trace to Trace is OK at 0.29mm. It blows up with a few errors at 0.30mm in the llp-32 section. Via to Pin is OK at 0.14mm. It blows up with 2 "same net" but actully OK errors at 0.15mm in the C-Bus ECL driver chips. Via to Via is OK at 0.40mm. It blows up with a few errors at 0.41mm in the differential traces vias. Pin to Pin as normal seems to do nothing. Leave it at 0.50mm. Fill to Bla leave it as set for now. So CB-Fan can pass DRC with: Pin Via Trace Fill Pin 0.50 Via 0.14 0.40 Trace 0.27 0.30 0.29 Fill 0.40 0.40 0.80 0.50 3-May-2012 Penultimate run of DRC checks usinging: Running at: nets_243 30-Apr-2012 stable comps_425 2-May-2012 Silkscreen tentatively finished traces_94 2-May-2012 no Fills, stable, with top side ground traces in the Converters Run using DRCs: Pin Via Trace Fill Pin 0.50 Via 0.14 0.40 Trace 0.27 0.30 0.29 Fill 0.40 0.40 0.80 0.50 Run as described above. This shows only the 3 expected warnings where the weak grounds are connected to the front-panel. 3-May-2012 Ultimate run of DRC checks usinging: Running at: nets_243 30-Apr-2012 stable comps_427 2-May-2012 Silkscreen finished traces_98 2-May-2012 has all Fills Note: comps_425, 426, 427 are the same except for small edits to the silkscreen Note: traces_94 and traces_96 are exactly the same. Run DRC using DRCs: Pin Via Trace Fill Pin 0.50 Via 0.14 0.40 Trace 0.27 0.30 0.29 Fill 0.40 0.40 0.80 0.50 Run as described above. This shows only the 3 expected warnings where the weak grounds are connected to the front-panel. Gerber Plot Generation ----------------------------- Assume that the Gerber Format has been setup and saved. Gerber Data is in mm 3.2 format. If necessary use: Right Click --> Artwork --> Change Artwork Format Image Scale: 1 Units: mm Mode: Absolute Plot Offsets: Manual with X=0.0 Y=0.0 G_Code: Allow Zero Suppression: None Interpolation: Linear with 8 Segments Output Format: 3 Significant and 2 decimal Data Record Length: 80 Header String: none Sub-Header String: none Trailer String: none Machine Stop Code: M02 XY-Modal: not checked Open Shutter Modal: not checked View Artwork Format: not checked Command Block End Character: * Verify that you are using the proper version of the Drill_Holes section of the geometry for the H_Clk pcb that has the PADS_2 copper for the front panel mounting screw holes. Aperature Table: Right Click --> Artwork --> Change Aperature Table --> Delete All Apertures Right Click --> Artwork --> Change Aperature Table --> Fill Aperature Table Select the Apertures for ALL Aizes Select NO ReSize and NO ReScale Flash Complex Padstacks: not checked Replace the table Report the Aperture Table (from Report Pull Down Menu) Include the ArtWork Format: yes Save and Display the Report Save Report to .../Work/Text/ Replace the existing Report May/Will need to Edit the Power Apertures: After the Aperture Table is filled it is necessary to edit the 5 Power Apertures (aka thermal reliefs) to get the desired layout. To edit a Power Aperture Right Click --> Artwork --> Change Aperture Table --> Change Power Aperture For each Power Aperture select the Aperture Position and then set the: Tie Width, Air Gap, and Rotation and then click OK. Note that the outer diameter of each Power Aperture is driven by its "power plane relief" diameter in its Geometry. We must set the Air Gap to get the desired pad size and set the Tie Width to get the desired amount of Copper connection. This version of Mentor lets us control the Tie Rotation. Before editing the Power Apertures are the following: Raw Power Apertures from the "Aperture Fill" Wednesday April 25, 2012; 17:02:24 Pos Diameter Dcode This Must Be --- -------- ----- ------------------------ 32 1.20 132 via_0mm7 34 1.65 134 via_1mm1 36 2.20 136 Conn5x32 VME Conn, LEDs 38 2.10 138 term_3m_conn 2x8 2x17 2x25 ... 39 1.19 139 LLP-32 DAP Pad Ground THD pins 41 3.00 141 Power Converter Terminals After editing the Power Apertures are the following: Power Apertures Desired for CB-Fan ------------------------------------ Outer Relief Tie Air Pos Diameter Width Gap Rotate Function --- --------- ----- ----- ------ ---------- 32 1.20 0.30 0.22 45 via_0mm7 34 1.65 0.35 0.25 45 via_1mm1 36 2.20 0.35 0.30 45 term_hart VME Conn, LEDs 38 2.10 0.35 0.30 45 term_3m conn 22x17 2x25 ... 39 1.19 0.35 0.10 45 LLP-32 DAP Pad Ground THD 41 3.00 0.75 0.30 45 Power Converter Terminals In all cases this gives the same or slightly larger Land diameter than in the associated via's Signal layers and it gives generous rational Tie Width. Gerber Data Generation: Right Click --> Artwork --> Creat Artwork Data Gerber Data is Gerber 274X format Stroke the Area Fill, Flash the Polygon ASCII Data, for the BOARD, ALL ArtWork Numbers (1:13) NO Tear Drops, REMOVE Unused Pins, REMOVE Unused Via's NO Output UnPlated Holes NO ReSize, NO ReScale Right Click --> Artwork --> Creat Artwork Data All settings are the same except create Gerber Data for just ArtWork Numbers 1 and 6 i.e. the top and bottom pcb layers, but use the option Output ALL Pins, Output ALL Via's Gerber Data Viewing: Right Click --> Artwork --> Simulate Artwork Data Edit the Final Gerbers: ----------------------- None so far for CB-Fan. Drill File Generation ---------------------------- Assume that the Drill Format has been setup and saved. Drill Data is in mm 3.2 format. Drill Table: Right Click --> Drill --> Change Drill Table --> Delete All Drills Right Click --> Drill --> Change Drill Table --> Fill Drill Table Select Replace the Drill Table Right Click --> Drill --> Creat Drill Data Excellon, Board, ASCII, Drill Hole Type: Both Output Hole Types: ALL, NO Mirror. Report the Drill Table (from Report Pull Down Menu) Include the Drill Format Save and Display the Report Save Report to Design with .../Work/Text/ filename Replace the existing Report Look at the Simulation of the Drill Data and find: Drill Drill Position Size Count Plated Function ---------- ------ ----- ------ -------------------- 1 0.30 656 yes via_0mm7 2 0.60 200 yes via_1mm1 3 0.90 375 yes 3M Conn 2x17 2x25... & SIPs 4 1.00 328 yes VME 5 Column Conn LEDs 5 1.40 20 yes DC-DC Power Converters 6 2.70 11 no Mech Mount VME Conn & F.P. ==================================================================== DRAFTS to be Incorperated or Dumped CB-Fan Power Requirements: -------------------------- - Power Consumption for the LVDS <--> ECL Conversion Hex TTL to ECL Translator Fairchild 100324QC Power: 45 mA of Vee --> 225 mW \/ for the full hex channel chip 25 mA of Vcc --> 125 mW /\ based on +- 5V operation With 50 Ohm Pull-Down Terminators to -2V Vtt Supply High Output -0.955V --> 20.9 mA or 21.84 mW in Term Resistor Low Output -1.705V --> 5.9 mA or 1.74 mW in Term Resistor ------- -------- 26.8 mA or 23.58 mW Total in Term/Ch Each Control Bus needs 4 channels of LVDS --> ECL Conversion so: 30.0 mA of Vee or 150 mW \/ for 4 channels of 16.7 mA of Vcc or 83 mW || TTL to ECL Chip and 107.2 mA of Vtt or 94 mW /\ the 8 Term Resistors 16 Control Busses add up to: 480.0 mA of Vee or 2400 mW \/ for 64 channels of 267.2 mA of Vcc or 1336 mW || TTL to ECL Chip and 1715.2 mA of Vtt or 1504 mW /\ the 128 Term Resistors 4 signals on each of 16 Control Busses is 64 signals total. This will require 32 chips of the SN65LVDT34 type for LVDS to 3.3V cmos conversion. Each of these chips will draw about 8 mA when quiescent and not more than about 15 mA at 40 MHz. Most of the signals are static, e.g. reset signals so call the average 10 mA. This implies 320 mA of Vdd or 1056 mW. - Can the output of a SN65LVDT34 drive multiple 100324 inputs ? The 100324 input requires: Low < 0.8 V pulling 0.9 mA max 0 to 85 deg C range High > 2.0 V pulling 20 uA max The SN65LVDT34 output can: Low will pull 4 mA to < 0.4 V -40 to 85 deg C range High will pull 4 mA to > 2.4 V At 25 deg C the SN65LVDT34 output is more like: Low will pull 10 mA to < 0.5 V High will pull 10 mA to > 2.6 V So having only one SN65LVDT34 LVDS to 3.3V cmos translator per block of 3 ECL drivers servicing a given 50 pin connector for 3 Control Busses looks like it is OK. But that may make it harder to drive the LVDS version of the Control Bus ? But how is the LVDS version of the Control Bus going to be driven anyway ? directly from DS90LV110T Clock FanOut chip or will it be buffered through e.g. a SN65LVDT34D to SN65LVDS9638 (or SN65LVDS31) pair ? Via's and Terminals Used: ------------------------- General Signal Via: via_0mm7 finished hole diameter 0.300 mm land pad 0.700 mm plane relief 1.200 mm --> ring width 0.200 mm --> plane isolation Air Gap 0.250 mm General Power Via: via_1mm1, TERM_0_6_MM finished hole diameter 0.600 mm land pad 1.100 mm plane relief 1.650 mm --> ring width 0.250 mm --> plane isolation Air Gap 0.275 mm term_3m_conn i.e. 3M connectors with 1 track routing 0.1" x 0.1" 25 mil square pin headers finished hole diameter 0.90 mm pad land diameter 1.50 mm plane relief 2.10 mm --> ring width 0.30 mm --> plane isolation air gap 0.30 mm With the 1.50 mm pad land diameter you can route a 0.30 mm trace that has 0.37 mm spaces on each side. term_hart_vme i.e. Hart 5 Column VME Connectors 0.1"x0.1" with 1 track routing finished hole diameter 1.00 mm pad land diameter 1.60 mm plane relief 2.20 mm --> ring width 0.30 mm --> plane isolation air gap 0.30 mm With the 1.60 mm pad land diameter you can route a 0.30 mm trace that has 0.32 mm spaces on each side. "Classic" 0.1" x 0.1" 25 mil square pin headers with 1 track routing finished hole diameter 1.00 mm pad land diameter 1.64 mm plane relief 2.24 mm --> ring width 0.32 mm --> plane isolation air gap 0.30 mm With the 1.64 mm pad land diameter you can route a 0.30 mm trace that has 0.30 mm spaces on each side. ===========================