Description of the H-Firm_2 FPGA Firmware for Initial Testing and Demo of the H-Clk Card ------------------------------------------------ Original Rev. 11-Mar-2012 Current Rev. 11-Mar-2012 Definition of the H_Firm_2 FPGA Firmware ------------------------------------------- - This firmware is (currently) only for Clock type H-Clk cards. - This Firmware does not provide a real test of the H-Clk card. Rather this firmware just makes it safe to power up the H-Clk card and verifies that it is working at a minimal level. Recall that the H-Clk card should not be powered up without a MEZ-456 installed and Configured or else components on the H-Clk card with CMOS inputs will be left floating which is not allowed. - This firmware safely drives or receives ALL signals on the H-Clk card, i.e. no outputs are fighting and no inputs are left floating. - This firmware provides the components that are necessary to allow the 40 MHz PLL on the H-Clk card to operate normally. The 40 MHz Clk signal from the PLL is received by the FPGA and distributed within it on a Global Clock net. - This firmware provides 8 patterns for the 6 LED "user" display on the H-Clk card's front panel. You can switch from one pattern to the next by pressing the lower (non-recessed) S1 push-button on the front panel. The firmware is designed to switch LED patterns as the push button is pressed in. Right after FPGA Configuration the firmware is defined to be in pattern #1. The 8 LED patterns are: 1. The least significant 6 bits of a counter that increments at about 2 Hz. It actually increments at 40 MHz divided by 256 divided by 65536. 2. A counter-clock-wise pattern in the LEDs. The LEDs step at about 2 Hz as above. 3. As above but a CW pattern in the LEDs. 4. A special pattern - all 6 LEDs blink at once. Can you figure it out ?? Think HAWC 5. Top-Rght LED - State of Access Connector EXT Clk signal Bot-Rght LED - 100 msec LED ON triggered by GPS 1 PPS Top-Mid LED - off Bot-Mid LED - Flashes when RS-232 serial data is received from the GPS Top-Left LED - 100 msec pulse when VME DTACK_B is sent Bot-Left LED - off 6. State of of the signals sent out on bits 5:0 of GPIO connector K5. Recall: GPIO K5 is an Output on the Clock type H-Clk. The data sent out on K5 comes from the Control-Status Register at local address 0x1001. This display has the same MSB-LSB LED order as pattern #1 7. State of of the signals sent out on GPIO K5 bits 11:6 8. State of of the signals sent out on GPIO K5 bits 15:12 The 2 MSB LEDs in pattern #8 are defined as OFF by this firmware. - This firmware receives data from GPIO connectors K1 and K2. This firmware sends data to GPIO connectors K3:K10 Thus this firmware is only for Clock type H-Clk cards. Data received on GPIO K1 is sent back out on GPIO K3 and this data may be read by the VME visible Read-Only Status Register at local address 0x1000 Data received on GPIO K2 is sent back out on GPIO K4 The 16 bit data written to the VME visible Read-Write Control/Status Register at local address 0x1002 is send out on GPIO connector K5. The 16 bit data written to the VME visible Read-Write Control/Status Register at local address 0x1004 is send out on GPIO connector K6. The 16 bit data written to the VME visible Read-Write Control/Status Register at local address 0x1006 is send out on GPIO connector K7. GPIO connector K8 - and output - all bits are LOW. GPIO connector K9 - and output - all bits are LOW. GPIO connector K10 - and output - all bits are LOW. - This firmware provides 4 VME visible registers. They are: Local Register Register Address Direction Type Function ------- ---------- --------------- ------------------- 0x1000 Read-Only Status Register reads GPIO K1 input 0x1002 Read-Write Control/Status drives GPIO K5 output 0x1004 Read-Write Control/Status drives GPIO K6 output 0x1006 Read-Write Control/Status drives GPIO K7 output Note that with this firmware, if you do a VME write cycle to the Read-Only Status register a Local Address 0x1000, the VME cycle will complete, i.e. the H-Clk card will DTACK_B, but there will be no other action on the card. - Along with buffer chips on the H-Clk card itself, this firmware provides a simple A24 D16 only interface between the VME Bus and the 4 registers that are instanced in this firmware and are listed above. This simple VME interface: does work OK with a Bit-3 master using programmed I/O, it explicitly does not meet the VME standards, it may not work with other VME crate masters (e.g. CAEN), it explicitly will not work with fast or close together VME cycles. This VME interface was just for a quick test to verify that some of the important signal traces and pin connections on the H-Clk card were made correctly. This VME interface uses Geographic Addressing to set the base address of each card based on which slot a given card is plugged into. See the table below for the map of crate slot number to VME base address. - This firmware makes the following provisions for an interface to the GPS Receiver: It ties LOW to the input to the RS-232 Serial I/O driver that sends data to the GPS Receiver The data that it gets from the RS-232 Serial I/O receiver is sent to a front panel LED when LED pattern #5 is displayed. The GPS 1 PPS signal is received and sent to a front panel LED when LED pattern #5 is displayed. The GPS 10 MHz reference clock is received, it is distributed within the FPGA on a Global Clock net and it is sent to the 40 MHz PLL as a reference signal. - For monitoring, this firmware makes copies of the 10 MHz Reference Clk and the 40 MHz PLL Clk available on the H-Clk's J5 Access connector pins: DEBUG_06 and DEBUG_08. Recall that these are raw FPGA pin signals setup as 3.3V CMOS levels with 4 mA of drive and with Slow edge transitions. - The bit stream for this firmware is setup for Master Serial Mode Configuration as it needs to be. Recall from MEZ-456 documentation on the web that its "DONE" LED goes OFF when the FPGA has finished Configuring. This firmware is setup to Configure into the FPGA and to automatically Start-UP when power is applied to the H-Clk MEZ-456 card pair. - If the proper jumper cable is installed between the H-Clk's "Access" connector and the MEZ-456 "Access" connector then the upper recessed push-button S2 can be used to initiate FPGA Configuration. This jumper cable and jumpers for others functions are described in the H-Clk documentation on the web. - Geographic Address Control of the Card's Base Address The card's base address is slot_number times 0x040000 That is Geo_Adrs_B(4:0) are used to match VME_Adrs(22:18) Three High Order Hex Digits of the VME Address shown in binary VME ---------------- Crate AAAA AAAA AAAA The Card's Slot 2222 1111 1111 Active VME Number 3210 9876 5432 Address Range ------ ---------------- ------------- 1 0000 0100 0001 0 4 1 0 0 x 2 0000 1000 0001 0 8 1 0 0 x 3 0000 1100 0001 0 c 1 0 0 x 4 0001 0000 0001 1 0 1 0 0 x 5 0001 0100 0001 1 4 1 0 0 x 6 0001 1000 0001 1 8 1 0 0 x 7 0001 1100 0001 1 c 1 0 0 x 8 0010 0000 0001 2 0 1 0 0 x 9 0010 0100 0001 2 4 1 0 0 x 10 0010 1000 0001 2 8 1 0 0 x 11 0010 1100 0001 2 c 1 0 0 x 12 0011 0000 0001 3 0 1 0 0 x 13 0011 0100 0001 3 4 1 0 0 x 14 0011 1000 0001 3 8 1 0 0 x 15 0011 1100 0001 3 c 1 0 0 x 16 0100 0000 0001 4 0 1 0 0 x 17 0100 0100 0001 4 4 1 0 0 x 18 0100 1000 0001 4 8 1 0 0 x 19 0100 1100 0001 4 c 1 0 0 x 20 0101 0000 0001 5 0 1 0 0 x 21 0101 0100 0001 5 4 1 0 0 x - I made a sketch of the main blocks of this firmware which are shown in 2 drawings on the web at: http://www.pa.msu.edu/~edmunds/HAWC/H_Clk_Card/Drawings/h_firm_two_1.png http://www.pa.msu.edu/~edmunds/HAWC/H_Clk_Card/Drawings/h_firm_two_2.png Points to keep in mind when working with these cards ---------------------------------------------------- 1. These cards contain many static sensitive components. - Please use either a wrist strap or touch something that you know is grounded before handling the cards. - When you first touch the card, touch something that is part of the ground structure or power supply structure on the card before touching any of the signal pins or traces. That is, the current flow that is necessary to bring you and the card to the same potential should be through the power or ground structure of the card and not through one of its signal lines. - Please understand that there are parts on these cards that I can not replace if you static discharge damage them. 2. Be gentle when installing or removing the 34 pin GPIO connectors. An end-to-end rocking motion will generally reduce the force that is required to remove one of these connectors. When installing one of these connectors use your fingers on the back side of the card to absorb the force and thus keep the card from flexing excessively. 3. Do not allow dirt or metal objects to fall in the top of the crate - they could land on and thus short out the exposed fingers on the FSI connectors or they coul fall between a SMD component and the circuit board and be impossible to remove. 4. The current selection of cable mount connectors that I have to plug into the front-panel GPS receptacle and the "Access" connectors are NOT keyed. You could plug them in backwards. Plugging one of these connectors in backward will blow a fuse and could damage components on the card. Please be careful. All of these connectors are pin #1 labeled with the conventional "dot" or "triangle" mark. Keyed connectors are available - I just don't have any in my stock of spare parts. 5. Please be careful with the WIENER VME crate and the other equipment from my lab. This equipment does not belong to HAWC or to Jim. Specifically please do not make extensive use of slots 8 or 10 in this crate. These slots have already had > 100 insertion extraction cycles and I believe that the connectors on this crate are rated for 200 cycles. The pins on the back side of the P2 connectors are particularly delicate. 6. If you are going to send signals between 2 crates please remember that you need to make a backplane ground connection between the crates to control the level of the common mode voltage between the crates. 7. Please remember that when you plug the JTAG cable into the MEZ-456 card you can not be guaranteed that one of the ground pins in this connector will touch first. Thus the ground of your JTAG computer should be connected to the ground of the crate that holds the H-Clk MEZ-456 card to prevent a JTAG signal pin from being the first thing that connects these two systems. 8. Please don't use unfolded paper clips to push the recessed front panel push-button on the H-Clk card. There is too much chance to touching an electrical connection on the H-Clk card with the paper clip. Absolutely do not use unfolded paper clips to probe connector contacts - doing so will destroy them. 9. The "Clock" type and "Control" type H-Clk cards obviously can not run the same firmware, e.g. because of the difference in the number of input and output GPIO connections to the FPGA. If you want we can use some spare via to FPGA pin connections on the H-Clk card so that the firmware can "discover" at Configure Startup time what type of H-Clk card it is on and thus appropriately set its GPIO inputs and outputs. 10. My web documents for the H-Clk contain a file of "design musts" for the H-Clk FPGA. 11. When you are finished using the GPS receive that you have had for the past months please return it to me and I will try to modify it so that it has the same connections to its circular connector as the version of the GPS receiver that I want to use in all the real HAWC systems.