WARNING:Bitgen:239 - Setting bitgen -g Security:Level2 will minimize the size of the bitstream. System environment during configuration must be carefully managed when using this bitstream. Please contact your FAE for additional information. WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net pat_gen_top/N$4674 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Release 6.3i - Bitgen G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Loading device database for application Bitgen from file "now_this.ncd". "default" is an NCD, version 2.38, device xc2v1000, package fg456, speed -4 Loading device for application Bitgen from file '2v1000.nph' in environment /home/Xilinx/Xilinx_63i. The STEPPING level for this design is 0. Opened constraints file now_this.pcf. Fri Mar 9 16:36:32 2012 bitgen -w -intstyle ise -g CRC:Enable -g ConfigRate:4 -g StartUpClk:CCLK -g CclkPin:PULLUP -g DonePin:PULLNONE -g HswapenPin:PULLUP -g M0Pin:PULLDOWN -g M1Pin:PULLDOWN -g M2Pin:PULLDOWN -g PowerdownPin:PULLUP -g ProgPin:PULLUP -g TckPin:PULLUP -g TdiPin:PULLUP -g TdoPin:PULLNONE -g TmsPin:PULLUP -g UnusedPin:PULLDOWN -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Match_cycle:NoWait -g Persist:No -g DriveDone:No -g DonePipe:No -g Security:LEVEL2 -g ActivateGCLK:No -g Binary:No -g DCMShutdown:Disable -g DisableBandgap:No -g DebugBitstream:No -g Encrypt:No now_this.ncd WARNING:Bitgen:239 - Setting bitgen -g Security:Level2 will minimize the size of the bitstream. System environment during configuration must be carefully managed when using this bitstream. Please contact your FAE for additional information. Summary of Bitgen Options: +----------------------+----------------------+ | Option Name | Current Setting | +----------------------+----------------------+ | Compress | (Not Specified)* | +----------------------+----------------------+ | Readback | (Not Specified)* | +----------------------+----------------------+ | CRC | Enable** | +----------------------+----------------------+ | DebugBitstream | No** | +----------------------+----------------------+ | ConfigRate | 4** | +----------------------+----------------------+ | StartupClk | Cclk** | +----------------------+----------------------+ | DCMShutdown | Disable** | +----------------------+----------------------+ | DisableBandgap | No** | +----------------------+----------------------+ | CclkPin | Pullup** | +----------------------+----------------------+ | DonePin | Pullnone | +----------------------+----------------------+ | HswapenPin | Pullup** | +----------------------+----------------------+ | M0Pin | Pulldown | +----------------------+----------------------+ | M1Pin | Pulldown | +----------------------+----------------------+ | M2Pin | Pulldown | +----------------------+----------------------+ | PowerdownPin | Pullup** | +----------------------+----------------------+ | ProgPin | Pullup** | +----------------------+----------------------+ | TckPin | Pullup** | +----------------------+----------------------+ | TdiPin | Pullup** | +----------------------+----------------------+ | TdoPin | Pullnone | +----------------------+----------------------+ | TmsPin | Pullup** | +----------------------+----------------------+ | UnusedPin | Pulldown** | +----------------------+----------------------+ | GWE_cycle | 6** | +----------------------+----------------------+ | GTS_cycle | 5** | +----------------------+----------------------+ | LCK_cycle | NoWait** | +----------------------+----------------------+ | Match_cycle | NoWait | +----------------------+----------------------+ | DONE_cycle | 4** | +----------------------+----------------------+ | Persist | No** | +----------------------+----------------------+ | DriveDone | No** | +----------------------+----------------------+ | DonePipe | No** | +----------------------+----------------------+ | Security | Level2 | +----------------------+----------------------+ | UserID | 0xFFFFFFFF* | +----------------------+----------------------+ | ActivateGclk | No** | +----------------------+----------------------+ | ActiveReconfig | No* | +----------------------+----------------------+ | PartialMask0 | (Not Specified)* | +----------------------+----------------------+ | PartialMask1 | (Not Specified)* | +----------------------+----------------------+ | PartialMask2 | (Not Specified)* | +----------------------+----------------------+ | PartialGclk | (Not Specified)* | +----------------------+----------------------+ | PartialLeft | (Not Specified)* | +----------------------+----------------------+ | PartialRight | (Not Specified)* | +----------------------+----------------------+ | Encrypt | No** | +----------------------+----------------------+ | Key0 | pick* | +----------------------+----------------------+ | Key1 | pick* | +----------------------+----------------------+ | Key2 | pick* | +----------------------+----------------------+ | Key3 | pick* | +----------------------+----------------------+ | Key4 | pick* | +----------------------+----------------------+ | Key5 | pick* | +----------------------+----------------------+ | Keyseq0 | M* | +----------------------+----------------------+ | Keyseq1 | M* | +----------------------+----------------------+ | Keyseq2 | M* | +----------------------+----------------------+ | Keyseq3 | M* | +----------------------+----------------------+ | Keyseq4 | M* | +----------------------+----------------------+ | Keyseq5 | M* | +----------------------+----------------------+ | KeyFile | (Not Specified)* | +----------------------+----------------------+ | StartKey | 0* | +----------------------+----------------------+ | StartCBC | pick* | +----------------------+----------------------+ | FreezeDCI | No* | +----------------------+----------------------+ | IEEE1532 | No* | +----------------------+----------------------+ | Binary | No** | +----------------------+----------------------+ * Default setting. ** The specified setting matches the default setting. Running DRC. WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net pat_gen_top/N$4674 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. DRC detected 0 errors and 1 warnings. Creating bit map... Saving bit stream in "now_this.bit". Bitstream generation is complete.