Using target part "2v1000fg456-4".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    4
Logic Utilization:
  Number of Slice Flip Flops:         228 out of  10,240    2%
  Number of 4 input LUTs:             210 out of  10,240    2%
Logic Distribution:
  Number of occupied Slices:          192 out of   5,120    3%
  Number of Slices containing only related logic:     192 out of     192  100%
  Number of Slices containing unrelated logic:          0 out of     192    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:            214 out of  10,240    2%
  Number used as logic:               210
  Number used as 16x1 ROMs:             4

  Number of bonded IOBs:              246 out of     324   75%
    IOB Flip Flops:                    70
    IOB Master Pads:                    6
    IOB Slave Pads:                     6
  Number of Tbufs:                     80 out of   2,560    3%
  Number of GCLKs:                      3 out of      16   18%

   Number of RPM macros:            2
Total equivalent gate count for design:  4,132
Additional JTAG gate count for IOBs:  11,808
Peak Memory Usage:  78 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "map.mrp" for details.