Release 6.3i - Par G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.




Constraints file: now_this.pcf

Loading device database for application Par from file "map.ncd".
   "default" is an NCD, version 2.38, device xc2v1000, package fg456, speed -4
Loading device for application Par from file '2v1000.nph' in environment
/home/Xilinx/Xilinx_63i.
The STEPPING level for this design is 0.
Device speed data version:  PRODUCTION 1.118 2004-06-25.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External DIFFMs           6 out of 162     3%
   Number of External DIFFSs           6 out of 162     3%
   Number of External IOBs           234 out of 324    72%
      Number of LOCed External IOBs  234 out of 234   100%

   Number of SLICEs                  192 out of 5120    3%

   Number of BUFGMUXs                  3 out of 16     18%
   Number of TBUFs                    80 out of 2560    3%



Overall effort level (-ol):   Not applicable because -pl and -rl switches are used
Placer effort level (-pl):    High (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    High (set by user)

Starting initial Timing Analysis.  REAL time: 2 secs 
Finished initial Timing Analysis.  REAL time: 10 secs 


Phase 1.1
Phase 1.1 (Checksum:98a74f) REAL time: 11 secs 

Phase 2.2
.
Phase 2.2 (Checksum:1312cfe) REAL time: 11 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 11 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 11 secs 

Phase 5.8
.......
......
.......
......
......
..
Phase 5.8 (Checksum:a4723d) REAL time: 17 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 17 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 18 secs 

Phase 8.24
Phase 8.24 (Checksum:4c4b3f8) REAL time: 18 secs 

Phase 9.27
Phase 9.27 (Checksum:55d4a77) REAL time: 18 secs 

Writing design to file now_this.ncd.

Total REAL time to Placer completion: 19 secs 
Total CPU time to Placer completion: 19 secs 


Phase 1: 1604 unrouted;       REAL time: 19 secs 

Phase 2: 1313 unrouted;       REAL time: 24 secs 

Phase 3: 241 unrouted;       REAL time: 25 secs 

Phase 4: 241 unrouted; (0)      REAL time: 25 secs 

Phase 5: 241 unrouted; (0)      REAL time: 25 secs 

Phase 6: 241 unrouted; (0)      REAL time: 25 secs 

Phase 7: 0 unrouted; (0)      REAL time: 26 secs 

Total REAL time to Router completion: 26 secs 
Total CPU time to Router completion: 26 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|        CLK_40_MHZ       | BUFGMUX0S| No   |  181 |  0.213     |  1.188      |
+-------------------------+----------+------+------+------------+-------------+
|        CLK_10_MHZ       | BUFGMUX6S| No   |    2 |  0.000     |  1.206      |
+-------------------------+----------+------+------+------------+-------------+
|           N$10560       |   Local  |      |    8 |  1.668     |  3.378      |
+-------------------------+----------+------+------+------------+-------------+
|           N$10563       |   Local  |      |    8 |  0.045     |  2.263      |
+-------------------------+----------+------+------+------------+-------------+
|pat_gen_top/N$4674       |   Local  |      |    3 |  0.000     |  2.192      |
+-------------------------+----------+------+------+------------+-------------+
|top_pll_comp/MHZ_40_DIV_ |          |      |      |            |             |
|                       4 |   Local  |      |    2 |  0.000     |  0.789      |
+-------------------------+----------+------+------+------------+-------------+
|           N$10562       |   Local  |      |    8 |  1.843     |  3.330      |
+-------------------------+----------+------+------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  NET "top_pll_comp/MHZ_10_DS_BUFG" MAXDELA | 4.000ns    | 0.182ns    | N/A  
  Y = 4 nS                                  |            |            |      
--------------------------------------------------------------------------------
  NET "top_pll_comp/MHZ_40_DIV_4" MAXDELAY  | 4.000ns    | 0.789ns    | N/A  
  = 4 nS                                    |            |            |      
--------------------------------------------------------------------------------
  NET "top_pll_comp/MHZ_40_DS_BUFG" MAXDELA | 4.000ns    | 0.182ns    | N/A  
  Y = 4 nS                                  |            |            |      
--------------------------------------------------------------------------------
  TS_CLK_40 = PERIOD TIMEGRP "CLK_40"  10 n | 10.000ns   | 7.381ns    | 5    
  S   HIGH 5 nS                             |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 27 secs 
Total CPU time to PAR completion: 27 secs 

Peak Memory Usage:  124 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Writing design to file now_this.ncd.


PAR done.