#             This is a Key In  Net List  file for the
#                 H-CLK card's     ACCESS Connector
#                ----------------====================-
#
#
#                                                 Original Rev. 20-JULY-2011
#                                              Most Recent Rev.   8-NOV-2011


#  This file includes all the nets for the
#  ACCESS Connector  J5.
#
#  This file also includes the some vias for access
#  to various signals.  Via V1 connects to a pin on
#  The J5 Access Connector.  Vias V13:V16 connect to
#  unused FPGA I/O pins on the J1 FSI connector.


#  Ground Pins on the Access Connector
#  Many of the Odd Pins on J5 are tied
#  to Ground.  Othere pins are tied to
#  ground to give good isolation between
#  various sections of this connector.

NET 'GROUND'   J5-1    J5-2     # Grounds

NET 'GROUND'   J5-7    J5-8     # Grounds

NET 'GROUND'   J5-13   J5-14    # Grounds
NET 'GROUND'   J5-15            # Grounds
NET 'GROUND'   J5-17   J5-18    # Grounds
NET 'GROUND'   J5-19            # Grounds
NET 'GROUND'   J5-21            # Grounds

NET 'GROUND'   J5-25            # Grounds

NET 'GROUND'   J5-29            # Grounds

NET 'GROUND'   J5-33            # Grounds

NET 'GROUND'   J5-37            # Grounds
NET 'GROUND'   J5-39            # Grounds



#  Use 2 pins each for VCC and VDD power supplies.

NET 'VDD_LOGIC'   J5-23   J5-31    # Vdd supply to Access

NET 'VCC_LOGIC'   J5-27   J5-35    # Vcc supply to Access



#  Put the PLL Monditor Signal on Pin #16
#  with Grounds on all sides.

NET 'MONITOR_PLL'   J5-16          # PLL Monitor on pin #16



#  Connect the FPGA "Configure" Pushbutton to pin #38 and #40.

NET 'SWTCH_2_NC'    J5-40      # Front Panel S2 Normal Closed Contact pin #40
NET 'SWTCH_2_NO'    J5-38      # Front Panel S2 Normal Open   Contact pin #38



#  The "Open Via" pin is #36

NET 'OPEN_VIA'      J5-36    V1-1    # Open Via to Access Connector



#   DeBug Signals from the Mez-456 FPGA on the DeBug Connector

NET 'DEBUG_01'     J5-20    # DeBug Signal #1
NET 'DEBUG_02'     J5-22    # DeBug Signal #2
NET 'DEBUG_03'     J5-24    # DeBug Signal #3
NET 'DEBUG_04'     J5-26    # DeBug Signal #4
NET 'DEBUG_05'     J5-28    # DeBug Signal #5
NET 'DEBUG_06'     J5-30    # DeBug Signal #6
NET 'DEBUG_07'     J5-32    # DeBug Signal #7
NET 'DEBUG_08'     J5-34    # DeBug Signal #8



#  External Clock to the 40 MHz Distribution Bus  via a Buffer

NET 'EXT_40_MHZ_CLK_IN_DIR'   J5-10   # External LVDS Clock to the
NET 'EXT_40_MHZ_CLK_IN_CMP'   J5-12   # 40 MHz Distribution Bus



#  External Clock to the FPGA  via a Buffer

NET 'EXT_FPGA_CLK_IN_DIR'   J5-5     # External LVDS Signal to a
NET 'EXT_FPGA_CLK_IN_CMP'   J5-3     # FPGA Global Clock Net



#  40 MHz Clock from the Distribution Bus  via a Buffer/Driver

NET 'CLK_40_DIR_FOR_ACCESS_CONN'   J5-4    # From 40 MHz Distribution Bus
NET 'CLK_40_CMP_FOR_ACCESS_CONN'   J5-6    # via a Buffer/Driver



#  LVDS Signal from Normal FPGA I/O Pin  via a Buffer/Driver

NET 'FPGA_BUFD_LVDS_OUT_DIR'    J5-9     # 
NET 'FPGA_BUFD_LVDS_OUT_CMP'    J5-11    # 




#
#  Un-Used FPGA I/O Pins on the J1 FSI Connector
#
#  There are a total of 6 FPGA pins that are not used.
#  All 6 of these pins are on the J1 FSI connector.
#  It is easy to run 4 of the 6 spare FPGA signals to vias.
#  The signal assignments for these 4 spare FPGA
#  signal vias are made here.  These are vias  V13:V16
#

NET 'SPARE_SIG_V13'   V13-1    # Spare FPGA Signal to V13
NET 'SPARE_SIG_V14'   V14-1    # Spare FPGA Signal to V14
NET 'SPARE_SIG_V15'   V15-1    # Spare FPGA Signal to V15
NET 'SPARE_SIG_V16'   V16-1    # Spare FPGA Signal to V16