# This is a Key In Net List file for the # H-CLK card's 40 MHz Clock Fanout # ---------------===================== # # # Original Rev. 9-MAY-2011 # Most Recent Rev. 1-NOV-2011 # This file includes all the nets for the # Fanout of the 40 MHz Clock. # # See the very end of this file for 2 other small # functions that use the same parts and thus are # included in this file. # # CMOS to LVDS Driver of the PLL's 40 MHz Clock U251 # -------------------------------------------------------- # # Isolate, AC Couple, and Clamp the 5V Output of the VCXO NET 'VCXO_WFRM' R251-1 # VCXO Output to Isolation Resistor NET 'ISO_VCXO_WFRM' R251-2 C251-1 # VCXO Output AC Coupling Capacitor NET 'CLAMP_VCXO_WFRM' D251-3 C251-2 # Clamp Diode on the 40 MHz Waveform NET 'GROUND' D251-1 # Ground Clamp Diode Anode NET 'VDD_LOGIC' D251-2 # Vdd_Logic to Clamp Diode Cathode # 40 MHz PLL - CMOS to LVDS Driver chip # This drives the 40 MHz distribution bus NET 'CLAMP_VCXO_WFRM' U251-3 # PLL 40 MHz LVDS Driver Input NET 'PLL_DRV_40_MHZ_BUS_DIR' U251-6 R252-1 # LVDS Direct Ouput NET 'PLL_DRV_40_MHZ_BUS_CMP' U251-5 R253-1 # LVDS Complement Output # # 40 MHz Distribution Bus - Driver Output and Buffer Input and Terminator NET 'DIST_BUS_40_MHZ_DIR' R252-2 # Drive from PLL NET 'DIST_BUS_40_MHZ_DIR' R254-2 # Drive from External Clock NET 'DIST_BUS_40_MHZ_DIR' U254-3 # Input to FPGA Glb_Clk Buffer NET 'DIST_BUS_40_MHZ_DIR' U255-3 # Input to Access Connector Buffer NET 'DIST_BUS_40_MHZ_DIR' U252-7 # Input to 1:10 FanOut to GPIO Connectors NET 'DIST_BUS_40_MHZ_DIR' R257-1 # Terminator on 40 MHz Distribution Bus NET 'DIST_BUS_40_MHZ_CMP' R253-2 # Drive from PLL NET 'DIST_BUS_40_MHZ_CMP' R255-2 # Drive from External Clock NET 'DIST_BUS_40_MHZ_CMP' U254-2 # Input to FPGA Glb_Clk Buffer NET 'DIST_BUS_40_MHZ_CMP' U255-2 # Input to Access Connector Buffer NET 'DIST_BUS_40_MHZ_CMP' U252-8 # Input to 1:10 FanOut to GPIO Connectors NET 'DIST_BUS_40_MHZ_CMP' R257-2 # Terminator on 40 MHz Distribution Bus # # LVDS buffer output to the H-Clk's FPGA Global Clock Net NET 'CLK_40_DIR_FOR_FPGA' U254-6 # 40 MHz Clock to the FPGA NET 'CLK_40_CMP_FOR_FPGA' U254-7 # 40 MHz Clock to the FPGA # # LVDS buffer output to the H-Clk's Access Connector NET 'CLK_40_DIR_FOR_ACCESS_CONN' U255-6 # 40 MHz Clock to Access Connector NET 'CLK_40_CMP_FOR_ACCESS_CONN' U255-7 # 40 MHz Clock to Access Connector # # FanOut of the 40 MHz Clock to the 10 GPIO connectors K1:K10 U253 NET 'CLK_FO_7_DIR' U252-3 # 40 MHz Clock Dir to GPIO K1 NET 'CLK_FO_7_CMP' U252-4 # 40 MHz Clock Cmp to GPIO K1 NET 'CLK_FO_9_DIR' U252-1 # 40 MHz Clock Dir to GPIO K2 NET 'CLK_FO_9_CMP' U252-2 # 40 MHz Clock Cmp to GPIO K2 NET 'CLK_FO_5_DIR' U252-28 # 40 MHz Clock Dir to GPIO K3 NET 'CLK_FO_5_CMP' U252-27 # 40 MHz Clock Cmp to GPIO K3 NET 'CLK_FO_3_DIR' U252-26 # 40 MHz Clock Dir to GPIO K4 NET 'CLK_FO_3_CMP' U252-25 # 40 MHz Clock Cmp to GPIO K4 NET 'CLK_FO_1_DIR' U252-24 # 40 MHz Clock Dir to GPIO K5 NET 'CLK_FO_1_CMP' U252-23 # 40 MHz Clock Cmp to GPIO K5 NET 'CLK_FO_10_DIR' U252-20 # 40 MHz Clock Dir to GPIO K6 NET 'CLK_FO_10_CMP' U252-19 # 40 MHz Clock Cmp to GPIO K6 NET 'CLK_FO_8_DIR' U252-18 # 40 MHz Clock Dir to GPIO K7 NET 'CLK_FO_8_CMP' U252-17 # 40 MHz Clock Cmp to GPIO K7 NET 'CLK_FO_6_DIR' U252-16 # 40 MHz Clock Dir to GPIO K8 NET 'CLK_FO_6_CMP' U252-15 # 40 MHz Clock Cmp to GPIO K8 NET 'CLK_FO_2_DIR' U252-13 # 40 MHz Clock Dir to GPIO K9 NET 'CLK_FO_2_CMP' U252-14 # 40 MHz Clock Cmp to GPIO K9 NET 'CLK_FO_4_DIR' U252-11 # 40 MHz Clock Dir to GPIO K10 NET 'CLK_FO_4_CMP' U252-12 # 40 MHz Clock Cmp to GPIO K10 # # Enable U252 the DS90LV110's outputs. NET 'DS90_OUTPUT_ENB' R259-1 U252-5 # Output Enable Control on DS90LV110 NET 'VDD_LOGIC' R259-2 # Pullup to +3.3 Volt Vdd # # External Clock Driver for the 40 MHz Distribution Bus # The External Clock comes from the Access Connector NET 'EXT_40_MHZ_CLK_IN_DIR' R256-1 U253-3 # Input to External Clk Buffer NET 'EXT_40_MHZ_CLK_IN_CMP' R256-2 U253-2 # Input to External Clk Buffer NET 'EXT_40M_CLK_BUF_OUT_DIR' U253-6 R254-1 # External Clk Buffer Output NET 'EXT_40M_CLK_BUF_OUT_CMP' U253-7 R255-1 # External Clk Buffer Output # # Functions outside of the 40 MHz Distribution # but that use the same parts and thus are logicaly in this nets file # # Buffered External Signal to just an FPGA Global Clock Net # Note that both the input and output differential pins on # LVDS buffer U256 are being used "up-side-down" for routing reasons. NET 'EXT_FPGA_CLK_IN_DIR' R258-1 U256-2 # Input to the Ext FPGA Clk Buffer NET 'EXT_FPGA_CLK_IN_CMP' R258-2 U256-3 # Input to the Ext FPGA Clk Buffer NET 'EXT_FPGA_CLK_BUF_OUT_DIR' U256-7 # External FPGA Clk Buffer Output NET 'EXT_FPGA_CLK_BUF_OUT_CMP' U256-6 # External FPGA Clk Buffer Output # CMOS to LVDS Buffered Output from the FPGA - U251 Buffer. NET 'FPGA_BUFD_LVDS_DRV_IN' U251-2 # Normal FPGA I/O input to LVDS Conv NET 'FPGA_BUFD_LVDS_OUT_DIR' U251-8 # Buffered LVDS Signal NET 'FPGA_BUFD_LVDS_OUT_CMP' U251-7 # from a normal FPGA I/O pin # # Now Enable the Outputs on the 4 DS90LV001 # LVDS Buffer Chips U253, U254, U255, U256 NET 'ENB_BUFF_U253' U253-8 R260-1 # Pullup on U253 Enable Pin NET 'VDD_LOGIC' R260-2 # Vdd to the pullup resistor NET 'ENB_BUFF_U254' U254-8 R261-1 # Pullup on U254 Enable Pin NET 'VDD_LOGIC' R261-2 # Vdd to the pullup resistor NET 'ENB_BUFF_U255' U255-8 R262-1 # Pullup on U255 Enable Pin NET 'VDD_LOGIC' R262-2 # Vdd to the pullup resistor NET 'ENB_BUFF_U256' U256-8 R263-1 # Pullup on U256 Enable Pin NET 'VDD_LOGIC' R263-2 # Vdd to the pullup resistor # # Finally the Power and Ground Connections and some Enable Pins # for all of the ICs in this section, i.e. # U251, U251, U251, U251, U251, # Power and Ground for the Dual CMOS to LVDS Driver chip U251 NET 'VDD_LOGIC' U251-1 # CMOS to LVDS Driver chip +3.3V Vdd pin NET 'GROUND' U251-4 # CMOS to LVDS Driver chip Ground pin NET 'VDD_LOGIC' C252-1 C253-1 C265-1 # Vdd Logic bypass caps NET 'GROUND' C252-2 C253-2 C265-2 # bypass caps grounds # Power, Ground, and ByPass of the DS90LV110 1:10 FanOut chip U252 NET 'VDD_LOGIC' U252-10 U252-22 # FanOut Chip +3.3 Volt Vdd pins NET 'GROUND' U252-6 U252-9 U252-21 # FanOut Chip Ground pins NET 'VDD_LOGIC' C254-1 C255-1 C256-1 # Fanout ByPass Cap Vdd NET 'GROUND' C254-2 C255-2 C256-2 # Fanout ByPass Cap Ground # Power, Ground, and ByPass of the DS90LV001 LVDS Buffer U253 NET 'VDD_LOGIC' U253-5 # LVDS Buffer chip +3.3V Vdd pin NET 'GROUND' U253-1 # LVDS Buffer chip Ground pin NET 'VDD_LOGIC' C257-1 C258-1 # Vdd Logic bypass caps NET 'GROUND' C257-2 C258-2 # bypass caps grounds # Power, Ground, and ByPass of the DS90LV001 LVDS Buffer U254 NET 'VDD_LOGIC' U254-5 # LVDS Buffer chip +3.3V Vdd pin NET 'GROUND' U254-1 # LVDS Buffer chip Ground pin NET 'VDD_LOGIC' C259-1 C260-1 # Vdd Logic bypass caps NET 'GROUND' C259-2 C260-2 # bypass caps grounds # Power, Ground, and ByPass of the DS90LV001 LVDS Buffer U255 NET 'VDD_LOGIC' U255-5 # LVDS Buffer chip +3.3V Vdd pin NET 'GROUND' U255-1 # LVDS Buffer chip Ground pin NET 'VDD_LOGIC' C261-1 C262-1 # Vdd Logic bypass caps NET 'GROUND' C261-2 C262-2 # bypass caps grounds # Power, Ground, and ByPass of the DS90LV001 LVDS Buffer U256 NET 'VDD_LOGIC' U256-5 # LVDS Buffer chip +3.3V Vdd pin NET 'GROUND' U256-1 # LVDS Buffer chip Ground pin NET 'VDD_LOGIC' C263-1 C264-1 # Vdd Logic bypass caps NET 'GROUND' C263-2 C264-2 # bypass caps grounds