# This is a Key In Net List file for # the H-CLK card for HAWC # VME Backplane P1 Connector # --------------====---------- # # Original Rev. 21-Apr-2011 # Most Recent Rev. 7-Nov-2011 # This file includes all the nets from the VME "P1" connector # including the "Z" and "D" columns of this connector. In this # file there is a separate "statement" for each of the 160 # pins in this connector. Only the pins in this connector that # have signals that are used in the H-CLK design have Mentor # Graphics NET statements. # The "Z" Column # -------------- # pin P1-Z1 is VME-64X signal MPR MTM-Bus Pause Request NET 'GROUND' P1-Z2 # VME-64X ground pin # pin P1-Z3 is VME-64X signal MCLK MTM-Bus Clock NET 'GROUND' P1-Z4 # VME-64X ground pin # pin P1-Z5 is VME-64X signal MSD MTM-Bus Slave Data NET 'GROUND' P1-Z6 # VME-64X ground pin # pin P1-Z7 is VME-64X signal MMD MTM-Bus Master Data NET 'GROUND' P1-Z8 # VME-64X ground pin # pin P1-Z9 is VME-64X signal MCTC MTM-Bus Control NET 'GROUND' P1-Z10 # VME-64X ground pin # pin P1-Z11 is VME-64X signal RESP* 2eVME protocol Response NET 'GROUND' P1-Z12 # VME-64X ground pin # pin P1-Z13 is VME-64X Reserved Bus signal 0 NET 'GROUND' P1-Z14 # VME-64X ground pin # pin P1-Z15 is VME-64X Reserved Bus signal 1 NET 'GROUND' P1-Z16 # VME-64X ground pin # pin P1-Z17 # VME-64X Reserved Bus signal 2 NET 'GROUND' P1-Z18 # VME-64X ground pin # pin P1-Z19 # VME-64X Reserved Bus signal 3 NET 'GROUND' P1-Z20 # VME-64X ground pin # pin P1-Z21 # VME-64X Reserved Bus signal 4 NET 'GROUND' P1-Z22 # VME-64X ground pin # pin P1-Z23 # VME-64X Reserved Bus signal 5 NET 'GROUND' P1-Z24 # VME-64X ground pin # pin P1-Z25 # VME-64X Reserved Bus signal 6 NET 'GROUND' P1-Z26 # VME-64X ground pin # pin P1-Z27 # VME-64X Reserved Bus signal 7 NET 'GROUND' P1-Z28 # VME-64X ground pin # pin P1-Z29 # VME-64X Reserved Bus signal 8 NET 'GROUND' P1-Z30 # VME-64X ground pin # pin P1-Z31 # VME-64X Reserved Bus signal 9 NET 'GROUND' P1-Z32 # VME-64X ground pin # The "A" Column # -------------- NET 'VME_DATA(0)' P1-A1 # VME Data Bus D00 NET 'VME_DATA(1)' P1-A2 # VME Data Bus D01 NET 'VME_DATA(2)' P1-A3 # VME Data Bus D02 NET 'VME_DATA(3)' P1-A4 # VME Data Bus D03 NET 'VME_DATA(4)' P1-A5 # VME Data Bus D04 NET 'VME_DATA(5)' P1-A6 # VME Data Bus D05 NET 'VME_DATA(6)' P1-A7 # VME Data Bus D06 NET 'VME_DATA(7)' P1-A8 # VME Data Bus D07 NET 'GROUND' P1-A9 # VME ground pin # pin P1-A10 # VME System_Clock 'VME_SYSCLK' NET 'GROUND' P1-A11 # VME ground pin NET 'VME_DS1_B' P1-A12 # VME Data_Strobe_1_* # pin P1-A13 # VME Data_Strobe_0_* 'VME_DS0_B' NET 'VME_WRITE_B' P1-A14 # VME Write_* NET 'GROUND' P1-A15 # VME ground pin NET 'VME_DTACK_B' P1-A16 # VME Data_Transfer_Acknowledge_* NET 'GROUND' P1-A17 # VME ground pin NET 'VME_AS_B' P1-A18 # VME Address_Strobe_* NET 'GROUND' P1-A19 # VME ground pin NET 'VME_IACK_B' P1-A20 # VME Interrupt_Acknowledge_* NET 'VME_IACK_LOOP' P1-A21 # VME Interrupt_Acknowledge_In_* 'VME_IACKIN_B' NET 'VME_IACK_LOOP' P1-A22 # VME Interrupt_Acknowledge_Out_* 'VME_IACKOUT_B' NET 'VME_AM(4)' P1-A23 # VME Address Modifier 4 NET 'VME_ADDR(7)' P1-A24 # VME Address Bus A07 NET 'VME_ADDR(6)' P1-A25 # VME Address Bus A06 NET 'VME_ADDR(5)' P1-A26 # VME Address Bus A05 NET 'VME_ADDR(4)' P1-A27 # VME Address Bus A04 NET 'VME_ADDR(3)' P1-A28 # VME Address Bus A03 NET 'VME_ADDR(2)' P1-A29 # VME Address Bus A02 NET 'VME_ADDR(1)' P1-A30 # VME Address Bus A01 NET 'VME_N12V' P1-A31 # VME -12 Volt Bus Power NET 'VME_5V' P1-A32 # VME +5 Volt Bus Power # The "B" Column # -------------- # pin P1-B1 VME Bus_Busy_* signal 'VME_BBSY_B' # pin P1-B2 VME Bus_Clear_* signal 'VME_BCLR_B' # pin P1-B3 VME AC_Power_Fail_* signal 'VME_ACFAIL_B' # Note that the Bus Grant In-Out pin pairs # are just tied together. NET 'BUS_GRANT_0' P1-B4 P1-B5 # P1-B4 is VME Bus_Grant_0_In_* signal # P1-B5 is VME Bus_Grant_0_Out_* signal NET 'BUS_GRANT_1' P1-B6 P1-B7 # P1-B6 is VME Bus_Grant_1_In_* signal # P1-B7 is VME Bus_Grant_1_Out_* signal NET 'BUS_GRANT_2' P1-B8 P1-B9 # P1-B8 is VME Bus_Grant_2_In_* signal # P1-B9 is VME Bus_Grant_2_Out_* signal NET 'BUS_GRANT_3' P1-B10 P1-B11 # P1-B10 is VME Bus_Grant_3_In_* signal # P1-B11 is VME Bus_Grant_3_Out_* signal # pin P1-B12 VME Bus_Request_0_* signal 'VME_BR_B(0)' # pin P1-B13 VME Bus_Request_1_* signal 'VME_BR_B(1)' # pin P1-B14 VME Bus_Request_2_* signal 'VME_BR_B(2)' # pin P1-B15 VME Bus_Request_3_* signal 'VME_BR_B(3)' NET 'VME_AM(0)' P1-B16 # VME Address Modifier 0 NET 'VME_AM(1)' P1-B17 # VME Address Modifier 1 NET 'VME_AM(2)' P1-B18 # VME Address Modifier 2 NET 'VME_AM(3)' P1-B19 # VME Address Modifier 3 NET 'GROUND' P1-B20 # VME ground pin # pin P1-B21 VME Serial Clock 'VME_SERCLK' # pin P1-B22 VME Serial Data 'VME_SERDAT' NET 'GROUND' P1-B23 # VME ground pin # pin P1-B24 VME IRQ7* 'VME_IRQ_B(7)' # pin P1-B25 VME IRQ6* 'VME_IRQ_B(6)' # pin P1-B26 VME IRQ5* 'VME_IRQ_B(5)' # pin P1-B27 VME IRQ4* 'VME_IRQ_B(4)' # pin P1-B28 VME IRQ3* 'VME_IRQ_B(3)' # pin P1-B29 VME IRQ2* 'VME_IRQ_B(2)' # pin P1-B30 VME IRQ1* 'VME_IRQ_B(1)' # pin P1-B31 VME +5 Volt Standby NET 'VME_5V' P1-B32 # VME +5 Volt Bus Power # The "C" Column # -------------- NET 'VME_DATA(8)' P1-C1 # VME Data Bus D08 NET 'VME_DATA(9)' P1-C2 # VME Data Bus D09 NET 'VME_DATA(10)' P1-C3 # VME Data Bus D10 NET 'VME_DATA(11)' P1-C4 # VME Data Bus D11 NET 'VME_DATA(12)' P1-C5 # VME Data Bus D12 NET 'VME_DATA(13)' P1-C6 # VME Data Bus D13 NET 'VME_DATA(14)' P1-C7 # VME Data Bus D14 NET 'VME_DATA(15)' P1-C8 # VME Data Bus D15 NET 'GROUND' P1-C9 # VME ground pin # pin P1-C10 # VME System_Fail_* signal 'VME_SYSFAIL_B' # pin P1-C11 # VME Bus_Error_* signal 'VME_BERR_B' NET 'VME_SYSRESET_B' P1-C12 # VME System_Reset_* signal # pin P1-C13 # VME Long_Word signal 'VME_LWORD_B' NET 'VME_AM(5)' P1-C14 # VME Address Modifier 5 NET 'VME_ADDR(23)' P1-C15 # VME Address Bus A23 NET 'VME_ADDR(22)' P1-C16 # VME Address Bus A22 NET 'VME_ADDR(21)' P1-C17 # VME Address Bus A21 NET 'VME_ADDR(20)' P1-C18 # VME Address Bus A20 NET 'VME_ADDR(19)' P1-C19 # VME Address Bus A19 NET 'VME_ADDR(18)' P1-C20 # VME Address Bus A18 NET 'VME_ADDR(17)' P1-C21 # VME Address Bus A17 NET 'VME_ADDR(16)' P1-C22 # VME Address Bus A16 NET 'VME_ADDR(15)' P1-C23 # VME Address Bus A15 NET 'VME_ADDR(14)' P1-C24 # VME Address Bus A14 NET 'VME_ADDR(13)' P1-C25 # VME Address Bus A13 NET 'VME_ADDR(12)' P1-C26 # VME Address Bus A12 NET 'VME_ADDR(11)' P1-C27 # VME Address Bus A11 NET 'VME_ADDR(10)' P1-C28 # VME Address Bus A10 NET 'VME_ADDR(9)' P1-C29 # VME Address Bus A09 NET 'VME_ADDR(8)' P1-C30 # VME Address Bus A08 NET 'VME_P12V' P1-C31 # VME +12 Volt Bus Power NET 'VME_5V' P1-C32 # VME +5 Volt Bus Power # The "D" Column # -------------- # pin P1-D1 is VME-64X signal VPC(1) Voltage PreCharge NET 'GROUND' P1-D2 # VME-64X ground pin Extended Pin # pin P1-D3 is VME-64X +V1 + side of 48 Volt Power # pin P1-D4 is VME-64X +V2 + side of 48 Volt Power # pin P1-D5 is VME-64X Reserved UnBused # pin P1-D6 is VME-64X -V1 - side of 48 Volt Power # pin P1-D7 is VME-64X -V2 - side of 48 Volt Power # pin P1-D8 is VME-64X Reserved UnBused # pin P1-D9 is VME-64X Geographic Address Parity NET 'VME_GEO_B(0)' P1-D10 # VME-64X Geographic Adress (0) bar NET 'VME_GEO_B(1)' P1-D11 # VME-64X Geographic Adress (1) bar NET 'VDD_LOGIC' P1-D12 # VME-64X +3.3 Volt Bus Power NET 'VME_GEO_B(2)' P1-D13 # VME-64X Geographic Adress (2) bar NET 'VDD_LOGIC' P1-D14 # VME-64X +3.3 Volt Bus Power NET 'VME_GEO_B(3)' P1-D15 # VME-64X Geographic Adress (3) bar NET 'VDD_LOGIC' P1-D16 # VME-64X +3.3 Volt Bus Power NET 'VME_GEO_B(4)' P1-D17 # VME-64X Geographic Adress (4) bar NET 'VDD_LOGIC' P1-D18 # VME-64X +3.3 Volt Bus Power # pin P1-D19 # VME-64X Reserved Bus signal 10 NET 'VDD_LOGIC' P1-D20 # VME-64X +3.3 Volt Bus Power # pin P1-D21 # VME-64X Reserved Bus signal 11 NET 'VDD_LOGIC' P1-D22 # VME-64X +3.3 Volt Bus Power # pin P1-D23 # VME-64X Reserved Bus signal 12 NET 'VDD_LOGIC' P1-D24 # VME-64X +3.3 Volt Bus Power # pin P1-D25 # VME-64X Reserved Bus signal 13 NET 'VDD_LOGIC' P1-D26 # VME-64X +3.3 Volt Bus Power # pin P1-D27 is VME-64X signal LI/I* Live Insertion Input NET 'VDD_LOGIC' P1-D28 # VME-64X +3.3 Volt Bus Power # pin P1-D29 is VME-64X signal LI/O* Live Insertion Output NET 'VDD_LOGIC' P1-D30 # VME-64X +3.3 Volt Bus Power NET 'GROUND' P1-D31 # VME-64X ground pin Extended Pin # pin P1-D32 is VME-64X signal VPC(1) Voltage PreCharge # # This is a Key In Net List file for # the H-CLK card for HAWC # Backplane P2 Connector # ------------====------------ # # Original Rev. 21-Apr-2011 # Most Recent Rev. 26-Oct-2011 # This file includes all the nets from the "P2" connector # including the "Z" and "D" columns of this connector. # Only the pins in this connector that have signals that are # used in the H-CLK design have Mentor Graphics NET statements. # The "Z" Column # -------------- NET 'GROUND' P2-Z2 P2-Z4 P2-Z6 P2-Z8 P2-Z10 # VME-64X ground pin NET 'GROUND' P2-Z12 P2-Z14 P2-Z16 P2-Z18 P2-Z20 # VME-64X ground pin NET 'GROUND' P2-Z22 P2-Z24 P2-Z26 P2-Z28 P2-Z30 # VME-64X ground pin NET 'GROUND' P2-Z32 # VME-64X ground pin # The H-CLK makes no P2 connection to "Z" column odd number pins. # The "A" Column # -------------- # # All "A" Column pins are all "User Defined". # H-Clk uses just 2 of these pins to bring the battery backup # power supply for the GPS receiver on-card. This backup supply # is assumed to be something like a 9V or 10V rechargable battery. # It is fused on-card but also needs to be fuse at the battery. NET 'GPS_BAT_POS' P2-A1 # GPS Battery Positive NET 'GROUND' P2-A2 # GPS Battery Negative # The "B" Column # -------------- NET 'GROUND' P2-B2 P2-B12 P2-B22 P2-B31 # VME ground pin ## ## NET 'VME_5V' P2-B1 P2-B13 P2-B32 # VME +5 Volt Bus Power # The H-Clk will get 5V Vcc from the 3 pins on P1 only # The H-CLK makes no P2 connection to "B" column pins 3:11, 14:21, 23:30. # The "C" Column # -------------- # # All "C" Column pins are user defined. # H-Clk does not use any of these pins. # The "D" Column # -------------- NET 'GROUND' P2-D31 # VME-64X ground pin Extended Pin # The H-CLK makes no P2 connection to "D" column pins 1:30, 32. # This is a Key In Net List file for # the H-CLK card for HAWC # VME to OCB Adrs & Ctrl Nets # ---------------------------------- # # Original Rev. 22-Apr-2011 # Most Recent Rev. 7-NOV-2011 # This file includes all the VME P1 backplane Address and Control # type signals. # # Most of these signls are handled by latches U301 and U302. # # One section of U303 used for driving VME_DTACK_B and # the other section of U303 is used for receiving VME_DS1_B, # receiving VME System Reset, receiving the Geographic Address, # and receiving VME_AS_B. # # There are pull up resistors on the VME Geographic Address pins # which are included in this net list file. # # Connection of the nets to the VME P1 connector itself is taken # care of in the P1 net list file. # This file contains the nets for the following components: # # U301, U302 74LVC16374A 16 bit "D" Latch for the # VME "adrs" type information # OR # # U301, U302 74LVC16373A 16 bit Transparent Latches for # VME "adrs" type information # # # U303 74LVT16245B Dual 8 bit Transceiver # Rec. Geo_Adrs, DS1_B, # and VME System Reset, # Drive DTACK_B # # C302:C312 even 0.1 uFd bypass capacitors to Vdd_Logic # # C301:C311 odd 4.7 nFd bypass capacitors to Vdd_Logic # # R301:R305 4.99 k Ohm 0603 1% Pull up on VME Geographic Adrs # # W301 Zero Ohm 0603 jumper controls input to unused # section of U302 a 74LVC16374A latch pin 1D0. # # W303 Zero Ohm 0603 jumper controls input to unused # sections of U303: 2A0, 2A1, 2A2, 2A3, 2A4, 2A5, 2A6 # # V2 : V8 Are via's on the individual inputs of W303. # V10 Is a latch output on U301 # First take care of the 31 VME backplane signals that are received # and latched by U301 and U302. There is one unused section in this # pair of latches. It will be placed at the pin 24-25 end of U301. # Latch for VME "adrs type" information U302 NET 'VME_AM(5)' U302-47 # 1D0 NET 'LTCHD_AM(5)' U302-2 # 1Q0 NET 'VME_WRITE_B' U302-46 # 1D1 NET 'LTCHD_WRITE_B' U302-3 # 1Q1 NET 'VME_ADDR(23)' U302-44 # 1D2 NET 'OCB_ADRS(23)' U302-5 # 1Q2 NET 'VME_ADDR(22)' U302-43 # 1D3 NET 'OCB_ADRS(22)' U302-6 # 1Q3 NET 'VME_AM(0)' U302-41 # 1D4 NET 'LTCHD_AM(0)' U302-8 # 1Q4 NET 'VME_ADDR(21)' U302-40 # 1D5 NET 'OCB_ADRS(21)' U302-9 # 1Q5 NET 'VME_AM(1)' U302-38 # 1D6 NET 'LTCHD_AM(1)' U302-11 # 1Q6 NET 'VME_ADDR(20)' U302-37 # 1D7 NET 'OCB_ADRS(20)' U302-12 # 1Q7 NET 'VME_AM(2)' U302-36 # 2D0 NET 'LTCHD_AM(2)' U302-13 # 2Q0 NET 'VME_ADDR(19)' U302-35 # 2D1 NET 'OCB_ADRS(19)' U302-14 # 2Q1 NET 'VME_AM(3)' U302-33 # 2D2 NET 'LTCHD_AM(3)' U302-16 # 2Q2 NET 'VME_ADDR(18)' U302-32 # 2D3 NET 'OCB_ADRS(18)' U302-17 # 2Q3 NET 'VME_IACK_B' U302-30 # 2D4 NET 'LTCHD_IACK_B' U302-19 # 2Q4 NET 'VME_ADDR(17)' U302-29 # 2D5 NET 'OCB_ADRS(17)' U302-20 # 2Q5 NET 'VME_ADDR(16)' U302-27 # 2D6 NET 'OCB_ADRS(16)' U302-22 # 2Q6 NET 'VME_AM(4)' U302-26 # 2D7 NET 'LTCHD_AM(4)' U302-23 # 2Q7 # Latch for VME "adrs type" information U301 NET 'VME_ADDR(15)' U301-47 # 1D0 NET 'OCB_ADRS(15)' U301-2 # 1Q0 NET 'VME_ADDR(7)' U301-46 # 1D1 NET 'OCB_ADRS(7)' U301-3 # 1Q1 NET 'VME_ADDR(14)' U301-44 # 1D2 NET 'OCB_ADRS(14)' U301-5 # 1Q2 NET 'VME_ADDR(6)' U301-43 # 1D3 NET 'OCB_ADRS(6)' U301-6 # 1Q3 NET 'VME_ADDR(13)' U301-41 # 1D4 NET 'OCB_ADRS(13)' U301-8 # 1Q4 NET 'VME_ADDR(5)' U301-40 # 1D5 NET 'OCB_ADRS(5)' U301-9 # 1Q5 NET 'VME_ADDR(12)' U301-38 # 1D6 NET 'OCB_ADRS(12)' U301-11 # 1Q6 NET 'VME_ADDR(4)' U301-37 # 1D7 NET 'OCB_ADRS(4)' U301-12 # 1Q7 NET 'VME_ADDR(11)' U301-36 # 2D0 NET 'OCB_ADRS(11)' U301-13 # 2Q0 NET 'VME_ADDR(3)' U301-35 # 2D1 NET 'OCB_ADRS(3)' U301-14 # 2Q1 NET 'VME_ADDR(10)' U301-33 # 2D2 NET 'OCB_ADRS(10)' U301-16 # 2Q2 NET 'VME_ADDR(2)' U301-32 # 2D3 NET 'OCB_ADRS(2)' U301-17 # 2Q3 NET 'VME_ADDR(9)' U301-30 # 2D4 NET 'OCB_ADRS(9)' U301-19 # 2Q4 NET 'VME_ADDR(1)' U301-29 # 2D5 NET 'OCB_ADRS(1)' U301-20 # 2Q5 NET 'VME_ADDR(8)' U301-27 # 2D6 NET 'OCB_ADRS(8)' U301-22 # 2Q6 # U301 has one unused section. Tie its input to Gnd # through a zero Ohm jumper W301. The output from # this unused section runs to via, V10. NET 'LFBT_LATCH_IN_1' W301-2 U301-26 # 2D7 Input to unused section NET 'GROUND' W301-1 # of U301 a 16 bit Latch NET 'LFBT_LATCH_OUT_1' U301-23 # 2Q7 Output from the unused NET 'LFBT_LATCH_OUT_1' V10-1 # U301 Latch is connected ### # only to via, V10. # Ground the OE_B pins on the U301 and U302 latches: NET 'GROUND' U301-1 U301-24 U302-1 U302-24 # Connect the clock net to the clock input pins on these latches: NET 'VME_LTCH_CLK' U301-25 U301-48 U302-25 U302-48 # Connect the Vdd power supply pins to the 74LVC16374A latches: NET 'VDD_LOGIC' U301-7 U301-18 U301-31 U301-42 NET 'VDD_LOGIC' U302-7 U302-18 U302-31 U302-42 # Connect the Ground pins to the 74LVC16374A latches: NET 'GROUND' U301-4 U301-10 U301-15 U301-21 NET 'GROUND' U301-28 U301-34 U301-39 U301-45 NET 'GROUND' U302-4 U302-10 U302-15 U302-21 NET 'GROUND' U302-28 U302-34 U302-39 U302-45 # Now include the nets for the bypass capacitors on the latches: # 0.1 uFd Ceramic NET 'VDD_LOGIC' C302-1 C304-2 C306-1 C308-2 NET 'GROUND' C302-2 C304-1 C306-2 C308-1 # 4.7 nFd Ceramic NET 'VDD_LOGIC' C301-2 C303-1 C305-2 C307-1 NET 'GROUND' C301-1 C303-2 C305-1 C307-2 # The following signals are all handled by a single 74LVT16245B. # The "B Side" of this chip is connected to VME-Bus signals. # The "A Side" of this chip is connected to the On Card Bus signals. # # Section "1" of this chip, e.g. pins 1:12, is setup with its Direction # pin LOW (--> B side is an input) and its OE\ pin LOW (--> outputs # are enabled) it receives the: DS1_B, the 5 Geographic Address # lines, VME System Reset, and VME Adrs_Strb_B from the VME-Bus. # # Section "2" of this chip e.g. pins 13:24, is setup with its Direction # pin HI (--> B side is an output) and its OE\ pin is used to assert # the active low DTACK_B signal. All of the inputs to this section # are tied low. # The following net connections are for receiving the VME_DS1_B signal, # the 5 Geographic Address, the VME Reset, and the VME Address Strobe. # These VME signals are received by one section of U303. NET 'VME_DS1_B' U303-12 # Backplane VME_DS1_B signal connects # to receiver input pin 1B7. NET 'RCVD_DS1_B' U303-37 # The received VME_DS1_B signal now # goes to the H-CLK's FPGA. NET 'VME_GEO_B(0)' U303-11 # Backplane VME_GEO_B(0) signal connects # to receiver input pin 1B6. NET 'RCVD_GEO_B(0)' U303-38 # The received GEO_B(0) signal now # goes to the H-CLK's FPGA. NET 'VME_GEO_B(1)' U303-9 # Backplane VME_GEO_B(1) signal connects # to receiver input pin 1B5. NET 'RCVD_GEO_B(1)' U303-40 # The received GEO_B(1) signal now # goes to the H-CLK's FPGA. NET 'VME_GEO_B(2)' U303-8 # Backplane VME_GEO_B(2) signal connects # to receiver input pin 1B4. NET 'RCVD_GEO_B(2)' U303-41 # The received GEO_B(2) signal now # goes to the H-CLK's FPGA. NET 'VME_GEO_B(3)' U303-6 # Backplane VME_GEO_B(3) signal connects # to receiver input pin 1B3. NET 'RCVD_GEO_B(3)' U303-43 # The received GEO_B(3) signal now # goes to the H-CLK's FPGA. NET 'VME_SYSRESET_B' U303-5 # Backplane VME System_Reset_B signal # connects to receiver input pin 1B2 NET 'RCVD_SYSRESET_B' U303-44 # The received SYSRESET_B signal from # pin 1A2 now goes to the H-CLK's FPGA. NET 'VME_GEO_B(4)' U303-3 # Backplane VME_GEO_B(4) signal connects # to receiver input pin 1B1. NET 'RCVD_GEO_B(4)' U303-46 # The received GEO_B(4) signal now # goes to the H-CLK's FPGA. NET 'VME_AS_B' U303-2 # Backplane VME Adrs_Strobe_B signal # connects to receiver input pin 1B0 NET 'RCVD_AS_B' U303-47 # The received Adrs_Strobe_B signal from # pin 1A0 now goes to the H-CLK's FPGA. # The following nets are the pull up resistors on the VME backplane # Geographic Address lines. These 5 Geographic Address signals are # pulled up before being sent to the Board Control PAL VME Interface. # On the backplane the Geographic Address pins are either floating # or tied to Gnd. The pull up resistors are R1001 : R1005. NET 'VME_GEO_B(0)' R301-1 # Pull up VME-64X Geographic Adress (0) bar NET 'VME_GEO_B(1)' R302-1 # Pull up VME-64X Geographic Adress (1) bar NET 'VME_GEO_B(2)' R303-1 # Pull up VME-64X Geographic Adress (2) bar NET 'VME_GEO_B(3)' R304-1 # Pull up VME-64X Geographic Adress (3) bar NET 'VME_GEO_B(4)' R305-1 # Pull up VME-64X Geographic Adress (4) bar # Connect the high side of these pull up resistors to the Vdd_Logic supply. NET 'VDD_LOGIC' R301-2 R302-2 R303-2 R304-2 R305-2 # The following net connections are for driving the VME_DTACK_B signal. # This VME signal is driven by one section of U303. NET 'VME_DTACK_B' U303-23 # The driver output 2B7 connects to the # backplane VME DTACK_B pin. NET 'GROUND' U303-26 # This is the input to this DTACK driver. # It is the 2A7 pin. NET 'DRV_DTACK_B' U303-25 # Connect the DRV_DTACK_B signal that comes # from the H-CLK's FPGA to the Output_Enable_B # pin for section "2" of the 74LVT16245B. # Inputs 2A0, 2A1, 2A2, 2A3, 2A4, 2A5, 2A6 of chip U303 are not # used at this time. These pins are brought out to a Zero-Ohm jumper # W303 and grounded. There are via's in this net to make it possible # to access individual inputs to the U303 chip if that is needed. NET 'RCVR_2A0_2A6_U303' U303-36 U303-35 # 2A0 2A1 Inputs are unused NET 'RCVR_2A0_2A6_U303' U303-33 U303-32 # 2A2 2A3 Inputs are unused NET 'RCVR_2A0_2A6_U303' U303-30 U303-29 # 2A4 2A5 Inputs are unused NET 'RCVR_2A0_2A6_U303' U303-27 # 2A6 Inputs are unused NET 'RCVR_2A0_2A6_U303' V2-1 V3-1 # Via's to access U303 inputs NET 'RCVR_2A0_2A6_U303' V4-1 V5-1 # Via's to access U303 inputs NET 'RCVR_2A0_2A6_U303' V6-1 V7-1 # Via's to access U303 inputs NET 'RCVR_2A0_2A6_U303' V8-1 # Via's to access U303 inputs NET 'RCVR_2A0_2A6_U303' W303-2 # Jumper for this unused NET 'GROUND' W303-1 # inputs - tied to ground ### Outputs 2B0, 2B1, 2B2, 2B3, 2B4, 2B5, 2B6 are not used and ### are not connected. Pins 13, 14, 16, 17, 19, 20, 22 are not connected. # Connect the two Direction pins of the 74LVT16245B Transceiver. NET 'GROUND' U303-1 # Section "1" low -> B input A output NET 'VDD_LOGIC' U303-24 # Section "2" high -> A input B output # Connect the Output Enable bar pin fpr section "1". NET 'GROUND' U303-48 # Section "1" output is enabled. # Connect the Vdd power supply pins to the 74LVT16245B Transceiver. NET 'VDD_LOGIC' U303-7 U303-18 U303-31 U303-42 # Connect the Ground pins to the 74LVT16245B Transceiver. NET 'GROUND' U303-4 U303-10 U303-15 U303-21 NET 'GROUND' U303-28 U303-34 U303-39 U303-45 # Now include the nets for the bypass capacitors on this Transceiver. # 100 nFd Ceramic NET 'VDD_LOGIC' C310-1 C312-2 NET 'GROUND' C310-2 C312-1 # 4.7 nFd Ceramic NET 'VDD_LOGIC' C309-2 C311-1 NET 'GROUND' C309-1 C311-2 # This is a Key In Net List file for # the H-CLK card for HAWC # VME Data Bus to On Card Bus Data Bus Nets # ------------------------------------------------ # # Original Rev. 21-Apr-2011 # Most Recent Rev. 7-July-2011 # This file is the 16 nets that bring the backplane VME data bus # onto the H-CLK card. The backplane VME data bus is received and # driven by U1004 a 74LVT16245B 16 bit Transceiver. # These circuits are shown in the drawing: # # www.pa.msu.edu/~edmunds/ # # # This file contains the nets for the following components: # # U304 74LVT16245B 16 bit Transceiver for VME Data lines # # C314, C316 100 uFd bypass capacitors to Vdd_Logic # # C313, C315 4.7 nFd bypass capacitors to Vdd_Logic # Connect U304 the Transceiver for the data bus VME <-> On_Card_Bus. # VME is connected to the B side of the 74LVT16245B Transceiver. # The On_Card_Bus is connected to the A side. NET 'OCB_DATA(7)' U304-47 # 1A0 NET 'VME_DATA(7)' U304-2 # 1B0 NET 'OCB_DATA(15)' U304-46 # 1A1 NET 'VME_DATA(15)' U304-3 # 1B1 NET 'OCB_DATA(6)' U304-44 # 1A2 NET 'VME_DATA(6)' U304-5 # 1B2 NET 'OCB_DATA(14)' U304-43 # 1A3 NET 'VME_DATA(14)' U304-6 # 1B3 NET 'OCB_DATA(5)' U304-41 # 1A4 NET 'VME_DATA(5)' U304-8 # 1B4 NET 'OCB_DATA(13)' U304-40 # 1A5 NET 'VME_DATA(13)' U304-9 # 1B5 NET 'OCB_DATA(4)' U304-38 # 1A6 NET 'VME_DATA(4)' U304-11 # 1B6 NET 'OCB_DATA(12)' U304-37 # 1A7 NET 'VME_DATA(12)' U304-12 # 1B7 NET 'OCB_DATA(3)' U304-36 # 2A0 NET 'VME_DATA(3)' U304-13 # 2B0 NET 'OCB_DATA(11)' U304-35 # 2A1 NET 'VME_DATA(11)' U304-14 # 2B1 NET 'OCB_DATA(2)' U304-33 # 2A2 NET 'VME_DATA(2)' U304-16 # 2B2 NET 'OCB_DATA(10)' U304-32 # 2A3 NET 'VME_DATA(10)' U304-17 # 2B3 NET 'OCB_DATA(1)' U304-30 # 2A4 NET 'VME_DATA(1)' U304-19 # 2B4 NET 'OCB_DATA(9)' U304-29 # 2A5 NET 'VME_DATA(9)' U304-20 # 2B5 NET 'OCB_DATA(0)' U304-27 # 2A6 NET 'VME_DATA(0)' U304-22 # 2B6 NET 'OCB_DATA(8)' U304-26 # 2A7 NET 'VME_DATA(8)' U304-23 # 2B7 # Connect the two Direction pins of the 74LVT16245B Transceiver. # When low -> B input A output i.e. VME Write # When high -> A input B output i.e. VME Read NET 'DATA_BUF_DIR' U304-1 U304-24 # Connect the two Output Enable bar pins of the 74LVT16245B Transceiver. # When high -> neither buffer output is enabled. NET 'DATA_BUF_ENB_B' U304-25 U304-48 # Connect the Vdd power supply pins to the 74LVT16245B Transceiver. NET 'VDD_LOGIC' U304-7 U304-18 U304-31 U304-42 # Connect the Ground pins to the 74LVT16245B Transceiver. NET 'GROUND' U304-4 U304-10 U304-15 U304-21 NET 'GROUND' U304-28 U304-34 U304-39 U304-45 # Now include the nets for the bypass capacitors on this Transceiver. # 100 nFd Ceramic NET 'VDD_LOGIC' C314-1 C316-2 NET 'GROUND' C314-2 C316-1 # 4.7 nFd Ceramic NET 'VDD_LOGIC' C313-2 C315-1 NET 'GROUND' C313-1 C315-2 # MIGT>---------------------------------------------- # MIGT> V1.0 -- Mon Dec 19 13:22:16 2011 # MIGT> begin substituting from -- instance #1/5 # MIGT>---------------------------------------------- # # This is a Key In NETs Template file for the # H-CLK card for HAWC # # LOWER GPIO NETs Template # ------------==========---====--========---------- # # # Original Rev. 22-Apr-2011 # Most Recent Rev. 19-Dec-2011 # # # This file includes all the Nets for the LOWER GPIO connector # section of the H-CLK card. # # The component reference designators in this section start at 1. # # This file contains nets for the following components for each "unit cell": # # K1 # C1 : C8 # U1 : U8 # # Channel # 1 NET 'GPIO_K_1_PIN_1' K1-1 U1-6 #GPIO K1 Signal 0 Direct NET 'GPIO_K_1_PIN_2' K1-2 U1-5 #GPIO K1 Signal 0 Comp NET 'GPIO_K_1_PIN_3' K1-3 U1-8 #GPIO K1 Signal 1 Direct NET 'GPIO_K_1_PIN_4' K1-4 U1-7 #GPIO K1 Signal 1 Comp NET 'GPIO_K_1_PIN_5' K1-5 U2-8 #GPIO K1 Signal 2 Direct NET 'GPIO_K_1_PIN_6' K1-6 U2-7 #GPIO K1 Signal 2 Comp NET 'GPIO_K_1_PIN_7' K1-7 U2-6 #GPIO K1 Signal 3 Direct NET 'GPIO_K_1_PIN_8' K1-8 U2-5 #GPIO K1 Signal 3 Comp NET 'GPIO_K_1_PIN_9' K1-9 U3-6 #GPIO K1 Signal 4 Direct NET 'GPIO_K_1_PIN_10' K1-10 U3-5 #GPIO K1 Signal 4 Comp NET 'GPIO_K_1_PIN_11' K1-11 U3-8 #GPIO K1 Signal 5 Direct NET 'GPIO_K_1_PIN_12' K1-12 U3-7 #GPIO K1 Signal 5 Comp NET 'GPIO_K_1_PIN_13' K1-13 U4-8 #GPIO K1 Signal 6 Direct NET 'GPIO_K_1_PIN_14' K1-14 U4-7 #GPIO K1 Signal 6 Comp NET 'GPIO_K_1_PIN_15' K1-15 U4-6 #GPIO K1 Signal 7 Direct NET 'GPIO_K_1_PIN_16' K1-16 U4-5 #GPIO K1 Signal 7 Comp NET 'GPIO_K_1_PIN_17' K1-17 U5-6 #GPIO K1 Signal 8 Direct NET 'GPIO_K_1_PIN_18' K1-18 U5-5 #GPIO K1 Signal 8 Comp NET 'GPIO_K_1_PIN_19' K1-19 U5-8 #GPIO K1 Signal 9 Direct NET 'GPIO_K_1_PIN_20' K1-20 U5-7 #GPIO K1 Signal 9 Comp NET 'GPIO_K_1_PIN_21' K1-21 U6-8 #GPIO K1 Signal 10 Direct NET 'GPIO_K_1_PIN_22' K1-22 U6-7 #GPIO K1 Signal 10 Comp NET 'GPIO_K_1_PIN_23' K1-23 U6-6 #GPIO K1 Signal 11 Direct NET 'GPIO_K_1_PIN_24' K1-24 U6-5 #GPIO K1 Signal 11 Comp NET 'GPIO_K_1_PIN_25' K1-25 U7-6 #GPIO K1 Signal 12 Direct NET 'GPIO_K_1_PIN_26' K1-26 U7-5 #GPIO K1 Signal 12 Comp NET 'GPIO_K_1_PIN_27' K1-27 U7-8 #GPIO K1 Signal 13 Direct NET 'GPIO_K_1_PIN_28' K1-28 U7-7 #GPIO K1 Signal 13 Comp NET 'GPIO_K_1_PIN_29' K1-29 U8-8 #GPIO K1 Signal 14 Direct NET 'GPIO_K_1_PIN_30' K1-30 U8-7 #GPIO K1 Signal 14 Comp NET 'GPIO_K_1_PIN_31' K1-31 U8-6 #GPIO K1 Signal 15 Direct NET 'GPIO_K_1_PIN_32' K1-32 U8-5 #GPIO K1 Signal 15 Comp # Pins #33 and #34 are for the 40 MHz Clock signal: NET 'CLK_FO_1_DIR' K1-33 NET 'CLK_FO_1_CMP' K1-34 # Now connect the Power and Ground to each LVDS Driver/Receiver # chip and to its bypass capacitor from Vdd_Logic to Ground NET 'VDD_LOGIC' U1-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U1-4 # Ground connection NET 'VDD_LOGIC' C1-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C1-2 # Ground connection NET 'VDD_LOGIC' U2-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U2-4 # Ground connection NET 'VDD_LOGIC' C2-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C2-2 # Ground connection NET 'VDD_LOGIC' U3-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U3-4 # Ground connection NET 'VDD_LOGIC' C3-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C3-2 # Ground connection NET 'VDD_LOGIC' U4-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U4-4 # Ground connection NET 'VDD_LOGIC' C4-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C4-2 # Ground connection NET 'VDD_LOGIC' U5-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U5-4 # Ground connection NET 'VDD_LOGIC' C5-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C5-2 # Ground connection NET 'VDD_LOGIC' U6-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U6-4 # Ground connection NET 'VDD_LOGIC' C6-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C6-2 # Ground connection NET 'VDD_LOGIC' U7-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U7-4 # Ground connection NET 'VDD_LOGIC' C7-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C7-2 # Ground connection NET 'VDD_LOGIC' U8-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U8-4 # Ground connection NET 'VDD_LOGIC' C8-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C8-2 # Ground connection # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Mon Dec 19 13:22:16 2011 # MIGT> begin substituting from -- instance #1/5 # MIGT>---------------------------------------------- # # This is a Key In NETs Template file for the # H-CLK card for HAWC # # UPPER GPIO NETs Template # ------------==========---====--========---------- # # # Original Rev. 22-Apr-2011 # Most Recent Rev. 19-Dec-2011 # # # This file includes all the Nets for the UPPER GPIO connector # section of the H-CLK card. # # The component reference designators in this section start at 1. # # This file contains nets for the following components for each "unit cell": # # K2 # C9 : C16 # U9 : U16 # # Channel # 2 NET 'GPIO_K_2_PIN_1' K2-1 U9-6 #GPIO K2 Signal 0 Direct NET 'GPIO_K_2_PIN_2' K2-2 U9-5 #GPIO K2 Signal 0 Comp NET 'GPIO_K_2_PIN_3' K2-3 U9-8 #GPIO K2 Signal 1 Direct NET 'GPIO_K_2_PIN_4' K2-4 U9-7 #GPIO K2 Signal 1 Comp NET 'GPIO_K_2_PIN_5' K2-5 U10-8 #GPIO K2 Signal 2 Direct NET 'GPIO_K_2_PIN_6' K2-6 U10-7 #GPIO K2 Signal 2 Comp NET 'GPIO_K_2_PIN_7' K2-7 U10-6 #GPIO K2 Signal 3 Direct NET 'GPIO_K_2_PIN_8' K2-8 U10-5 #GPIO K2 Signal 3 Comp NET 'GPIO_K_2_PIN_9' K2-9 U11-6 #GPIO K2 Signal 4 Direct NET 'GPIO_K_2_PIN_10' K2-10 U11-5 #GPIO K2 Signal 4 Comp NET 'GPIO_K_2_PIN_11' K2-11 U11-8 #GPIO K2 Signal 5 Direct NET 'GPIO_K_2_PIN_12' K2-12 U11-7 #GPIO K2 Signal 5 Comp NET 'GPIO_K_2_PIN_13' K2-13 U12-8 #GPIO K2 Signal 6 Direct NET 'GPIO_K_2_PIN_14' K2-14 U12-7 #GPIO K2 Signal 6 Comp NET 'GPIO_K_2_PIN_15' K2-15 U12-6 #GPIO K2 Signal 7 Direct NET 'GPIO_K_2_PIN_16' K2-16 U12-5 #GPIO K2 Signal 7 Comp NET 'GPIO_K_2_PIN_17' K2-17 U13-6 #GPIO K2 Signal 8 Direct NET 'GPIO_K_2_PIN_18' K2-18 U13-5 #GPIO K2 Signal 8 Comp NET 'GPIO_K_2_PIN_19' K2-19 U13-8 #GPIO K2 Signal 9 Direct NET 'GPIO_K_2_PIN_20' K2-20 U13-7 #GPIO K2 Signal 9 Comp NET 'GPIO_K_2_PIN_21' K2-21 U14-8 #GPIO K2 Signal 10 Direct NET 'GPIO_K_2_PIN_22' K2-22 U14-7 #GPIO K2 Signal 10 Comp NET 'GPIO_K_2_PIN_23' K2-23 U14-6 #GPIO K2 Signal 11 Direct NET 'GPIO_K_2_PIN_24' K2-24 U14-5 #GPIO K2 Signal 11 Comp NET 'GPIO_K_2_PIN_25' K2-25 U15-6 #GPIO K2 Signal 12 Direct NET 'GPIO_K_2_PIN_26' K2-26 U15-5 #GPIO K2 Signal 12 Comp NET 'GPIO_K_2_PIN_27' K2-27 U15-8 #GPIO K2 Signal 13 Direct NET 'GPIO_K_2_PIN_28' K2-28 U15-7 #GPIO K2 Signal 13 Comp NET 'GPIO_K_2_PIN_29' K2-29 U16-8 #GPIO K2 Signal 14 Direct NET 'GPIO_K_2_PIN_30' K2-30 U16-7 #GPIO K2 Signal 14 Comp NET 'GPIO_K_2_PIN_31' K2-31 U16-6 #GPIO K2 Signal 15 Direct NET 'GPIO_K_2_PIN_32' K2-32 U16-5 #GPIO K2 Signal 15 Comp # Pins #33 and #34 are for the 40 MHz Clock signal: NET 'CLK_FO_2_DIR' K2-33 NET 'CLK_FO_2_CMP' K2-34 # Now connect the Power and Ground to each LVDS Driver/Receiver # chip and to its bypass capacitor from Vdd_Logic to Ground NET 'VDD_LOGIC' U9-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U9-4 # Ground connection NET 'VDD_LOGIC' C9-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C9-2 # Ground connection NET 'VDD_LOGIC' U10-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U10-4 # Ground connection NET 'VDD_LOGIC' C10-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C10-2 # Ground connection NET 'VDD_LOGIC' U11-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U11-4 # Ground connection NET 'VDD_LOGIC' C11-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C11-2 # Ground connection NET 'VDD_LOGIC' U12-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U12-4 # Ground connection NET 'VDD_LOGIC' C12-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C12-2 # Ground connection NET 'VDD_LOGIC' U13-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U13-4 # Ground connection NET 'VDD_LOGIC' C13-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C13-2 # Ground connection NET 'VDD_LOGIC' U14-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U14-4 # Ground connection NET 'VDD_LOGIC' C14-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C14-2 # Ground connection NET 'VDD_LOGIC' U15-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U15-4 # Ground connection NET 'VDD_LOGIC' C15-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C15-2 # Ground connection NET 'VDD_LOGIC' U16-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U16-4 # Ground connection NET 'VDD_LOGIC' C16-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C16-2 # Ground connection # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Mon Dec 19 13:22:16 2011 # MIGT> begin substituting from -- instance #2/5 # MIGT>---------------------------------------------- # # This is a Key In NETs Template file for the # H-CLK card for HAWC # # LOWER GPIO NETs Template # ------------==========---====--========---------- # # # Original Rev. 22-Apr-2011 # Most Recent Rev. 19-Dec-2011 # # # This file includes all the Nets for the LOWER GPIO connector # section of the H-CLK card. # # The component reference designators in this section start at 1. # # This file contains nets for the following components for each "unit cell": # # K1 # C1 : C8 # U1 : U8 # # Channel # 3 NET 'GPIO_K_3_PIN_1' K3-1 U17-6 #GPIO K3 Signal 0 Direct NET 'GPIO_K_3_PIN_2' K3-2 U17-5 #GPIO K3 Signal 0 Comp NET 'GPIO_K_3_PIN_3' K3-3 U17-8 #GPIO K3 Signal 1 Direct NET 'GPIO_K_3_PIN_4' K3-4 U17-7 #GPIO K3 Signal 1 Comp NET 'GPIO_K_3_PIN_5' K3-5 U18-8 #GPIO K3 Signal 2 Direct NET 'GPIO_K_3_PIN_6' K3-6 U18-7 #GPIO K3 Signal 2 Comp NET 'GPIO_K_3_PIN_7' K3-7 U18-6 #GPIO K3 Signal 3 Direct NET 'GPIO_K_3_PIN_8' K3-8 U18-5 #GPIO K3 Signal 3 Comp NET 'GPIO_K_3_PIN_9' K3-9 U19-6 #GPIO K3 Signal 4 Direct NET 'GPIO_K_3_PIN_10' K3-10 U19-5 #GPIO K3 Signal 4 Comp NET 'GPIO_K_3_PIN_11' K3-11 U19-8 #GPIO K3 Signal 5 Direct NET 'GPIO_K_3_PIN_12' K3-12 U19-7 #GPIO K3 Signal 5 Comp NET 'GPIO_K_3_PIN_13' K3-13 U20-8 #GPIO K3 Signal 6 Direct NET 'GPIO_K_3_PIN_14' K3-14 U20-7 #GPIO K3 Signal 6 Comp NET 'GPIO_K_3_PIN_15' K3-15 U20-6 #GPIO K3 Signal 7 Direct NET 'GPIO_K_3_PIN_16' K3-16 U20-5 #GPIO K3 Signal 7 Comp NET 'GPIO_K_3_PIN_17' K3-17 U21-6 #GPIO K3 Signal 8 Direct NET 'GPIO_K_3_PIN_18' K3-18 U21-5 #GPIO K3 Signal 8 Comp NET 'GPIO_K_3_PIN_19' K3-19 U21-8 #GPIO K3 Signal 9 Direct NET 'GPIO_K_3_PIN_20' K3-20 U21-7 #GPIO K3 Signal 9 Comp NET 'GPIO_K_3_PIN_21' K3-21 U22-8 #GPIO K3 Signal 10 Direct NET 'GPIO_K_3_PIN_22' K3-22 U22-7 #GPIO K3 Signal 10 Comp NET 'GPIO_K_3_PIN_23' K3-23 U22-6 #GPIO K3 Signal 11 Direct NET 'GPIO_K_3_PIN_24' K3-24 U22-5 #GPIO K3 Signal 11 Comp NET 'GPIO_K_3_PIN_25' K3-25 U23-6 #GPIO K3 Signal 12 Direct NET 'GPIO_K_3_PIN_26' K3-26 U23-5 #GPIO K3 Signal 12 Comp NET 'GPIO_K_3_PIN_27' K3-27 U23-8 #GPIO K3 Signal 13 Direct NET 'GPIO_K_3_PIN_28' K3-28 U23-7 #GPIO K3 Signal 13 Comp NET 'GPIO_K_3_PIN_29' K3-29 U24-8 #GPIO K3 Signal 14 Direct NET 'GPIO_K_3_PIN_30' K3-30 U24-7 #GPIO K3 Signal 14 Comp NET 'GPIO_K_3_PIN_31' K3-31 U24-6 #GPIO K3 Signal 15 Direct NET 'GPIO_K_3_PIN_32' K3-32 U24-5 #GPIO K3 Signal 15 Comp # Pins #33 and #34 are for the 40 MHz Clock signal: NET 'CLK_FO_3_DIR' K3-33 NET 'CLK_FO_3_CMP' K3-34 # Now connect the Power and Ground to each LVDS Driver/Receiver # chip and to its bypass capacitor from Vdd_Logic to Ground NET 'VDD_LOGIC' U17-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U17-4 # Ground connection NET 'VDD_LOGIC' C17-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C17-2 # Ground connection NET 'VDD_LOGIC' U18-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U18-4 # Ground connection NET 'VDD_LOGIC' C18-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C18-2 # Ground connection NET 'VDD_LOGIC' U19-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U19-4 # Ground connection NET 'VDD_LOGIC' C19-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C19-2 # Ground connection NET 'VDD_LOGIC' U20-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U20-4 # Ground connection NET 'VDD_LOGIC' C20-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C20-2 # Ground connection NET 'VDD_LOGIC' U21-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U21-4 # Ground connection NET 'VDD_LOGIC' C21-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C21-2 # Ground connection NET 'VDD_LOGIC' U22-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U22-4 # Ground connection NET 'VDD_LOGIC' C22-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C22-2 # Ground connection NET 'VDD_LOGIC' U23-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U23-4 # Ground connection NET 'VDD_LOGIC' C23-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C23-2 # Ground connection NET 'VDD_LOGIC' U24-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U24-4 # Ground connection NET 'VDD_LOGIC' C24-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C24-2 # Ground connection # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Mon Dec 19 13:22:16 2011 # MIGT> begin substituting from -- instance #2/5 # MIGT>---------------------------------------------- # # This is a Key In NETs Template file for the # H-CLK card for HAWC # # UPPER GPIO NETs Template # ------------==========---====--========---------- # # # Original Rev. 22-Apr-2011 # Most Recent Rev. 19-Dec-2011 # # # This file includes all the Nets for the UPPER GPIO connector # section of the H-CLK card. # # The component reference designators in this section start at 1. # # This file contains nets for the following components for each "unit cell": # # K2 # C9 : C16 # U9 : U16 # # Channel # 4 NET 'GPIO_K_4_PIN_1' K4-1 U25-6 #GPIO K4 Signal 0 Direct NET 'GPIO_K_4_PIN_2' K4-2 U25-5 #GPIO K4 Signal 0 Comp NET 'GPIO_K_4_PIN_3' K4-3 U25-8 #GPIO K4 Signal 1 Direct NET 'GPIO_K_4_PIN_4' K4-4 U25-7 #GPIO K4 Signal 1 Comp NET 'GPIO_K_4_PIN_5' K4-5 U26-8 #GPIO K4 Signal 2 Direct NET 'GPIO_K_4_PIN_6' K4-6 U26-7 #GPIO K4 Signal 2 Comp NET 'GPIO_K_4_PIN_7' K4-7 U26-6 #GPIO K4 Signal 3 Direct NET 'GPIO_K_4_PIN_8' K4-8 U26-5 #GPIO K4 Signal 3 Comp NET 'GPIO_K_4_PIN_9' K4-9 U27-6 #GPIO K4 Signal 4 Direct NET 'GPIO_K_4_PIN_10' K4-10 U27-5 #GPIO K4 Signal 4 Comp NET 'GPIO_K_4_PIN_11' K4-11 U27-8 #GPIO K4 Signal 5 Direct NET 'GPIO_K_4_PIN_12' K4-12 U27-7 #GPIO K4 Signal 5 Comp NET 'GPIO_K_4_PIN_13' K4-13 U28-8 #GPIO K4 Signal 6 Direct NET 'GPIO_K_4_PIN_14' K4-14 U28-7 #GPIO K4 Signal 6 Comp NET 'GPIO_K_4_PIN_15' K4-15 U28-6 #GPIO K4 Signal 7 Direct NET 'GPIO_K_4_PIN_16' K4-16 U28-5 #GPIO K4 Signal 7 Comp NET 'GPIO_K_4_PIN_17' K4-17 U29-6 #GPIO K4 Signal 8 Direct NET 'GPIO_K_4_PIN_18' K4-18 U29-5 #GPIO K4 Signal 8 Comp NET 'GPIO_K_4_PIN_19' K4-19 U29-8 #GPIO K4 Signal 9 Direct NET 'GPIO_K_4_PIN_20' K4-20 U29-7 #GPIO K4 Signal 9 Comp NET 'GPIO_K_4_PIN_21' K4-21 U30-8 #GPIO K4 Signal 10 Direct NET 'GPIO_K_4_PIN_22' K4-22 U30-7 #GPIO K4 Signal 10 Comp NET 'GPIO_K_4_PIN_23' K4-23 U30-6 #GPIO K4 Signal 11 Direct NET 'GPIO_K_4_PIN_24' K4-24 U30-5 #GPIO K4 Signal 11 Comp NET 'GPIO_K_4_PIN_25' K4-25 U31-6 #GPIO K4 Signal 12 Direct NET 'GPIO_K_4_PIN_26' K4-26 U31-5 #GPIO K4 Signal 12 Comp NET 'GPIO_K_4_PIN_27' K4-27 U31-8 #GPIO K4 Signal 13 Direct NET 'GPIO_K_4_PIN_28' K4-28 U31-7 #GPIO K4 Signal 13 Comp NET 'GPIO_K_4_PIN_29' K4-29 U32-8 #GPIO K4 Signal 14 Direct NET 'GPIO_K_4_PIN_30' K4-30 U32-7 #GPIO K4 Signal 14 Comp NET 'GPIO_K_4_PIN_31' K4-31 U32-6 #GPIO K4 Signal 15 Direct NET 'GPIO_K_4_PIN_32' K4-32 U32-5 #GPIO K4 Signal 15 Comp # Pins #33 and #34 are for the 40 MHz Clock signal: NET 'CLK_FO_4_DIR' K4-33 NET 'CLK_FO_4_CMP' K4-34 # Now connect the Power and Ground to each LVDS Driver/Receiver # chip and to its bypass capacitor from Vdd_Logic to Ground NET 'VDD_LOGIC' U25-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U25-4 # Ground connection NET 'VDD_LOGIC' C25-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C25-2 # Ground connection NET 'VDD_LOGIC' U26-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U26-4 # Ground connection NET 'VDD_LOGIC' C26-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C26-2 # Ground connection NET 'VDD_LOGIC' U27-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U27-4 # Ground connection NET 'VDD_LOGIC' C27-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C27-2 # Ground connection NET 'VDD_LOGIC' U28-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U28-4 # Ground connection NET 'VDD_LOGIC' C28-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C28-2 # Ground connection NET 'VDD_LOGIC' U29-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U29-4 # Ground connection NET 'VDD_LOGIC' C29-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C29-2 # Ground connection NET 'VDD_LOGIC' U30-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U30-4 # Ground connection NET 'VDD_LOGIC' C30-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C30-2 # Ground connection NET 'VDD_LOGIC' U31-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U31-4 # Ground connection NET 'VDD_LOGIC' C31-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C31-2 # Ground connection NET 'VDD_LOGIC' U32-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U32-4 # Ground connection NET 'VDD_LOGIC' C32-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C32-2 # Ground connection # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Mon Dec 19 13:22:16 2011 # MIGT> begin substituting from -- instance #3/5 # MIGT>---------------------------------------------- # # This is a Key In NETs Template file for the # H-CLK card for HAWC # # LOWER GPIO NETs Template # ------------==========---====--========---------- # # # Original Rev. 22-Apr-2011 # Most Recent Rev. 19-Dec-2011 # # # This file includes all the Nets for the LOWER GPIO connector # section of the H-CLK card. # # The component reference designators in this section start at 1. # # This file contains nets for the following components for each "unit cell": # # K1 # C1 : C8 # U1 : U8 # # Channel # 5 NET 'GPIO_K_5_PIN_1' K5-1 U33-6 #GPIO K5 Signal 0 Direct NET 'GPIO_K_5_PIN_2' K5-2 U33-5 #GPIO K5 Signal 0 Comp NET 'GPIO_K_5_PIN_3' K5-3 U33-8 #GPIO K5 Signal 1 Direct NET 'GPIO_K_5_PIN_4' K5-4 U33-7 #GPIO K5 Signal 1 Comp NET 'GPIO_K_5_PIN_5' K5-5 U34-8 #GPIO K5 Signal 2 Direct NET 'GPIO_K_5_PIN_6' K5-6 U34-7 #GPIO K5 Signal 2 Comp NET 'GPIO_K_5_PIN_7' K5-7 U34-6 #GPIO K5 Signal 3 Direct NET 'GPIO_K_5_PIN_8' K5-8 U34-5 #GPIO K5 Signal 3 Comp NET 'GPIO_K_5_PIN_9' K5-9 U35-6 #GPIO K5 Signal 4 Direct NET 'GPIO_K_5_PIN_10' K5-10 U35-5 #GPIO K5 Signal 4 Comp NET 'GPIO_K_5_PIN_11' K5-11 U35-8 #GPIO K5 Signal 5 Direct NET 'GPIO_K_5_PIN_12' K5-12 U35-7 #GPIO K5 Signal 5 Comp NET 'GPIO_K_5_PIN_13' K5-13 U36-8 #GPIO K5 Signal 6 Direct NET 'GPIO_K_5_PIN_14' K5-14 U36-7 #GPIO K5 Signal 6 Comp NET 'GPIO_K_5_PIN_15' K5-15 U36-6 #GPIO K5 Signal 7 Direct NET 'GPIO_K_5_PIN_16' K5-16 U36-5 #GPIO K5 Signal 7 Comp NET 'GPIO_K_5_PIN_17' K5-17 U37-6 #GPIO K5 Signal 8 Direct NET 'GPIO_K_5_PIN_18' K5-18 U37-5 #GPIO K5 Signal 8 Comp NET 'GPIO_K_5_PIN_19' K5-19 U37-8 #GPIO K5 Signal 9 Direct NET 'GPIO_K_5_PIN_20' K5-20 U37-7 #GPIO K5 Signal 9 Comp NET 'GPIO_K_5_PIN_21' K5-21 U38-8 #GPIO K5 Signal 10 Direct NET 'GPIO_K_5_PIN_22' K5-22 U38-7 #GPIO K5 Signal 10 Comp NET 'GPIO_K_5_PIN_23' K5-23 U38-6 #GPIO K5 Signal 11 Direct NET 'GPIO_K_5_PIN_24' K5-24 U38-5 #GPIO K5 Signal 11 Comp NET 'GPIO_K_5_PIN_25' K5-25 U39-6 #GPIO K5 Signal 12 Direct NET 'GPIO_K_5_PIN_26' K5-26 U39-5 #GPIO K5 Signal 12 Comp NET 'GPIO_K_5_PIN_27' K5-27 U39-8 #GPIO K5 Signal 13 Direct NET 'GPIO_K_5_PIN_28' K5-28 U39-7 #GPIO K5 Signal 13 Comp NET 'GPIO_K_5_PIN_29' K5-29 U40-8 #GPIO K5 Signal 14 Direct NET 'GPIO_K_5_PIN_30' K5-30 U40-7 #GPIO K5 Signal 14 Comp NET 'GPIO_K_5_PIN_31' K5-31 U40-6 #GPIO K5 Signal 15 Direct NET 'GPIO_K_5_PIN_32' K5-32 U40-5 #GPIO K5 Signal 15 Comp # Pins #33 and #34 are for the 40 MHz Clock signal: NET 'CLK_FO_5_DIR' K5-33 NET 'CLK_FO_5_CMP' K5-34 # Now connect the Power and Ground to each LVDS Driver/Receiver # chip and to its bypass capacitor from Vdd_Logic to Ground NET 'VDD_LOGIC' U33-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U33-4 # Ground connection NET 'VDD_LOGIC' C33-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C33-2 # Ground connection NET 'VDD_LOGIC' U34-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U34-4 # Ground connection NET 'VDD_LOGIC' C34-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C34-2 # Ground connection NET 'VDD_LOGIC' U35-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U35-4 # Ground connection NET 'VDD_LOGIC' C35-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C35-2 # Ground connection NET 'VDD_LOGIC' U36-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U36-4 # Ground connection NET 'VDD_LOGIC' C36-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C36-2 # Ground connection NET 'VDD_LOGIC' U37-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U37-4 # Ground connection NET 'VDD_LOGIC' C37-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C37-2 # Ground connection NET 'VDD_LOGIC' U38-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U38-4 # Ground connection NET 'VDD_LOGIC' C38-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C38-2 # Ground connection NET 'VDD_LOGIC' U39-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U39-4 # Ground connection NET 'VDD_LOGIC' C39-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C39-2 # Ground connection NET 'VDD_LOGIC' U40-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U40-4 # Ground connection NET 'VDD_LOGIC' C40-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C40-2 # Ground connection # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Mon Dec 19 13:22:16 2011 # MIGT> begin substituting from -- instance #3/5 # MIGT>---------------------------------------------- # # This is a Key In NETs Template file for the # H-CLK card for HAWC # # UPPER GPIO NETs Template # ------------==========---====--========---------- # # # Original Rev. 22-Apr-2011 # Most Recent Rev. 19-Dec-2011 # # # This file includes all the Nets for the UPPER GPIO connector # section of the H-CLK card. # # The component reference designators in this section start at 1. # # This file contains nets for the following components for each "unit cell": # # K2 # C9 : C16 # U9 : U16 # # Channel # 6 NET 'GPIO_K_6_PIN_1' K6-1 U41-6 #GPIO K6 Signal 0 Direct NET 'GPIO_K_6_PIN_2' K6-2 U41-5 #GPIO K6 Signal 0 Comp NET 'GPIO_K_6_PIN_3' K6-3 U41-8 #GPIO K6 Signal 1 Direct NET 'GPIO_K_6_PIN_4' K6-4 U41-7 #GPIO K6 Signal 1 Comp NET 'GPIO_K_6_PIN_5' K6-5 U42-8 #GPIO K6 Signal 2 Direct NET 'GPIO_K_6_PIN_6' K6-6 U42-7 #GPIO K6 Signal 2 Comp NET 'GPIO_K_6_PIN_7' K6-7 U42-6 #GPIO K6 Signal 3 Direct NET 'GPIO_K_6_PIN_8' K6-8 U42-5 #GPIO K6 Signal 3 Comp NET 'GPIO_K_6_PIN_9' K6-9 U43-6 #GPIO K6 Signal 4 Direct NET 'GPIO_K_6_PIN_10' K6-10 U43-5 #GPIO K6 Signal 4 Comp NET 'GPIO_K_6_PIN_11' K6-11 U43-8 #GPIO K6 Signal 5 Direct NET 'GPIO_K_6_PIN_12' K6-12 U43-7 #GPIO K6 Signal 5 Comp NET 'GPIO_K_6_PIN_13' K6-13 U44-8 #GPIO K6 Signal 6 Direct NET 'GPIO_K_6_PIN_14' K6-14 U44-7 #GPIO K6 Signal 6 Comp NET 'GPIO_K_6_PIN_15' K6-15 U44-6 #GPIO K6 Signal 7 Direct NET 'GPIO_K_6_PIN_16' K6-16 U44-5 #GPIO K6 Signal 7 Comp NET 'GPIO_K_6_PIN_17' K6-17 U45-6 #GPIO K6 Signal 8 Direct NET 'GPIO_K_6_PIN_18' K6-18 U45-5 #GPIO K6 Signal 8 Comp NET 'GPIO_K_6_PIN_19' K6-19 U45-8 #GPIO K6 Signal 9 Direct NET 'GPIO_K_6_PIN_20' K6-20 U45-7 #GPIO K6 Signal 9 Comp NET 'GPIO_K_6_PIN_21' K6-21 U46-8 #GPIO K6 Signal 10 Direct NET 'GPIO_K_6_PIN_22' K6-22 U46-7 #GPIO K6 Signal 10 Comp NET 'GPIO_K_6_PIN_23' K6-23 U46-6 #GPIO K6 Signal 11 Direct NET 'GPIO_K_6_PIN_24' K6-24 U46-5 #GPIO K6 Signal 11 Comp NET 'GPIO_K_6_PIN_25' K6-25 U47-6 #GPIO K6 Signal 12 Direct NET 'GPIO_K_6_PIN_26' K6-26 U47-5 #GPIO K6 Signal 12 Comp NET 'GPIO_K_6_PIN_27' K6-27 U47-8 #GPIO K6 Signal 13 Direct NET 'GPIO_K_6_PIN_28' K6-28 U47-7 #GPIO K6 Signal 13 Comp NET 'GPIO_K_6_PIN_29' K6-29 U48-8 #GPIO K6 Signal 14 Direct NET 'GPIO_K_6_PIN_30' K6-30 U48-7 #GPIO K6 Signal 14 Comp NET 'GPIO_K_6_PIN_31' K6-31 U48-6 #GPIO K6 Signal 15 Direct NET 'GPIO_K_6_PIN_32' K6-32 U48-5 #GPIO K6 Signal 15 Comp # Pins #33 and #34 are for the 40 MHz Clock signal: NET 'CLK_FO_6_DIR' K6-33 NET 'CLK_FO_6_CMP' K6-34 # Now connect the Power and Ground to each LVDS Driver/Receiver # chip and to its bypass capacitor from Vdd_Logic to Ground NET 'VDD_LOGIC' U41-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U41-4 # Ground connection NET 'VDD_LOGIC' C41-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C41-2 # Ground connection NET 'VDD_LOGIC' U42-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U42-4 # Ground connection NET 'VDD_LOGIC' C42-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C42-2 # Ground connection NET 'VDD_LOGIC' U43-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U43-4 # Ground connection NET 'VDD_LOGIC' C43-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C43-2 # Ground connection NET 'VDD_LOGIC' U44-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U44-4 # Ground connection NET 'VDD_LOGIC' C44-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C44-2 # Ground connection NET 'VDD_LOGIC' U45-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U45-4 # Ground connection NET 'VDD_LOGIC' C45-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C45-2 # Ground connection NET 'VDD_LOGIC' U46-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U46-4 # Ground connection NET 'VDD_LOGIC' C46-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C46-2 # Ground connection NET 'VDD_LOGIC' U47-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U47-4 # Ground connection NET 'VDD_LOGIC' C47-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C47-2 # Ground connection NET 'VDD_LOGIC' U48-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U48-4 # Ground connection NET 'VDD_LOGIC' C48-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C48-2 # Ground connection # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Mon Dec 19 13:22:16 2011 # MIGT> begin substituting from -- instance #4/5 # MIGT>---------------------------------------------- # # This is a Key In NETs Template file for the # H-CLK card for HAWC # # LOWER GPIO NETs Template # ------------==========---====--========---------- # # # Original Rev. 22-Apr-2011 # Most Recent Rev. 19-Dec-2011 # # # This file includes all the Nets for the LOWER GPIO connector # section of the H-CLK card. # # The component reference designators in this section start at 1. # # This file contains nets for the following components for each "unit cell": # # K1 # C1 : C8 # U1 : U8 # # Channel # 7 NET 'GPIO_K_7_PIN_1' K7-1 U49-6 #GPIO K7 Signal 0 Direct NET 'GPIO_K_7_PIN_2' K7-2 U49-5 #GPIO K7 Signal 0 Comp NET 'GPIO_K_7_PIN_3' K7-3 U49-8 #GPIO K7 Signal 1 Direct NET 'GPIO_K_7_PIN_4' K7-4 U49-7 #GPIO K7 Signal 1 Comp NET 'GPIO_K_7_PIN_5' K7-5 U50-8 #GPIO K7 Signal 2 Direct NET 'GPIO_K_7_PIN_6' K7-6 U50-7 #GPIO K7 Signal 2 Comp NET 'GPIO_K_7_PIN_7' K7-7 U50-6 #GPIO K7 Signal 3 Direct NET 'GPIO_K_7_PIN_8' K7-8 U50-5 #GPIO K7 Signal 3 Comp NET 'GPIO_K_7_PIN_9' K7-9 U51-6 #GPIO K7 Signal 4 Direct NET 'GPIO_K_7_PIN_10' K7-10 U51-5 #GPIO K7 Signal 4 Comp NET 'GPIO_K_7_PIN_11' K7-11 U51-8 #GPIO K7 Signal 5 Direct NET 'GPIO_K_7_PIN_12' K7-12 U51-7 #GPIO K7 Signal 5 Comp NET 'GPIO_K_7_PIN_13' K7-13 U52-8 #GPIO K7 Signal 6 Direct NET 'GPIO_K_7_PIN_14' K7-14 U52-7 #GPIO K7 Signal 6 Comp NET 'GPIO_K_7_PIN_15' K7-15 U52-6 #GPIO K7 Signal 7 Direct NET 'GPIO_K_7_PIN_16' K7-16 U52-5 #GPIO K7 Signal 7 Comp NET 'GPIO_K_7_PIN_17' K7-17 U53-6 #GPIO K7 Signal 8 Direct NET 'GPIO_K_7_PIN_18' K7-18 U53-5 #GPIO K7 Signal 8 Comp NET 'GPIO_K_7_PIN_19' K7-19 U53-8 #GPIO K7 Signal 9 Direct NET 'GPIO_K_7_PIN_20' K7-20 U53-7 #GPIO K7 Signal 9 Comp NET 'GPIO_K_7_PIN_21' K7-21 U54-8 #GPIO K7 Signal 10 Direct NET 'GPIO_K_7_PIN_22' K7-22 U54-7 #GPIO K7 Signal 10 Comp NET 'GPIO_K_7_PIN_23' K7-23 U54-6 #GPIO K7 Signal 11 Direct NET 'GPIO_K_7_PIN_24' K7-24 U54-5 #GPIO K7 Signal 11 Comp NET 'GPIO_K_7_PIN_25' K7-25 U55-6 #GPIO K7 Signal 12 Direct NET 'GPIO_K_7_PIN_26' K7-26 U55-5 #GPIO K7 Signal 12 Comp NET 'GPIO_K_7_PIN_27' K7-27 U55-8 #GPIO K7 Signal 13 Direct NET 'GPIO_K_7_PIN_28' K7-28 U55-7 #GPIO K7 Signal 13 Comp NET 'GPIO_K_7_PIN_29' K7-29 U56-8 #GPIO K7 Signal 14 Direct NET 'GPIO_K_7_PIN_30' K7-30 U56-7 #GPIO K7 Signal 14 Comp NET 'GPIO_K_7_PIN_31' K7-31 U56-6 #GPIO K7 Signal 15 Direct NET 'GPIO_K_7_PIN_32' K7-32 U56-5 #GPIO K7 Signal 15 Comp # Pins #33 and #34 are for the 40 MHz Clock signal: NET 'CLK_FO_7_DIR' K7-33 NET 'CLK_FO_7_CMP' K7-34 # Now connect the Power and Ground to each LVDS Driver/Receiver # chip and to its bypass capacitor from Vdd_Logic to Ground NET 'VDD_LOGIC' U49-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U49-4 # Ground connection NET 'VDD_LOGIC' C49-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C49-2 # Ground connection NET 'VDD_LOGIC' U50-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U50-4 # Ground connection NET 'VDD_LOGIC' C50-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C50-2 # Ground connection NET 'VDD_LOGIC' U51-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U51-4 # Ground connection NET 'VDD_LOGIC' C51-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C51-2 # Ground connection NET 'VDD_LOGIC' U52-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U52-4 # Ground connection NET 'VDD_LOGIC' C52-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C52-2 # Ground connection NET 'VDD_LOGIC' U53-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U53-4 # Ground connection NET 'VDD_LOGIC' C53-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C53-2 # Ground connection NET 'VDD_LOGIC' U54-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U54-4 # Ground connection NET 'VDD_LOGIC' C54-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C54-2 # Ground connection NET 'VDD_LOGIC' U55-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U55-4 # Ground connection NET 'VDD_LOGIC' C55-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C55-2 # Ground connection NET 'VDD_LOGIC' U56-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U56-4 # Ground connection NET 'VDD_LOGIC' C56-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C56-2 # Ground connection # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Mon Dec 19 13:22:16 2011 # MIGT> begin substituting from -- instance #4/5 # MIGT>---------------------------------------------- # # This is a Key In NETs Template file for the # H-CLK card for HAWC # # UPPER GPIO NETs Template # ------------==========---====--========---------- # # # Original Rev. 22-Apr-2011 # Most Recent Rev. 19-Dec-2011 # # # This file includes all the Nets for the UPPER GPIO connector # section of the H-CLK card. # # The component reference designators in this section start at 1. # # This file contains nets for the following components for each "unit cell": # # K2 # C9 : C16 # U9 : U16 # # Channel # 8 NET 'GPIO_K_8_PIN_1' K8-1 U57-6 #GPIO K8 Signal 0 Direct NET 'GPIO_K_8_PIN_2' K8-2 U57-5 #GPIO K8 Signal 0 Comp NET 'GPIO_K_8_PIN_3' K8-3 U57-8 #GPIO K8 Signal 1 Direct NET 'GPIO_K_8_PIN_4' K8-4 U57-7 #GPIO K8 Signal 1 Comp NET 'GPIO_K_8_PIN_5' K8-5 U58-8 #GPIO K8 Signal 2 Direct NET 'GPIO_K_8_PIN_6' K8-6 U58-7 #GPIO K8 Signal 2 Comp NET 'GPIO_K_8_PIN_7' K8-7 U58-6 #GPIO K8 Signal 3 Direct NET 'GPIO_K_8_PIN_8' K8-8 U58-5 #GPIO K8 Signal 3 Comp NET 'GPIO_K_8_PIN_9' K8-9 U59-6 #GPIO K8 Signal 4 Direct NET 'GPIO_K_8_PIN_10' K8-10 U59-5 #GPIO K8 Signal 4 Comp NET 'GPIO_K_8_PIN_11' K8-11 U59-8 #GPIO K8 Signal 5 Direct NET 'GPIO_K_8_PIN_12' K8-12 U59-7 #GPIO K8 Signal 5 Comp NET 'GPIO_K_8_PIN_13' K8-13 U60-8 #GPIO K8 Signal 6 Direct NET 'GPIO_K_8_PIN_14' K8-14 U60-7 #GPIO K8 Signal 6 Comp NET 'GPIO_K_8_PIN_15' K8-15 U60-6 #GPIO K8 Signal 7 Direct NET 'GPIO_K_8_PIN_16' K8-16 U60-5 #GPIO K8 Signal 7 Comp NET 'GPIO_K_8_PIN_17' K8-17 U61-6 #GPIO K8 Signal 8 Direct NET 'GPIO_K_8_PIN_18' K8-18 U61-5 #GPIO K8 Signal 8 Comp NET 'GPIO_K_8_PIN_19' K8-19 U61-8 #GPIO K8 Signal 9 Direct NET 'GPIO_K_8_PIN_20' K8-20 U61-7 #GPIO K8 Signal 9 Comp NET 'GPIO_K_8_PIN_21' K8-21 U62-8 #GPIO K8 Signal 10 Direct NET 'GPIO_K_8_PIN_22' K8-22 U62-7 #GPIO K8 Signal 10 Comp NET 'GPIO_K_8_PIN_23' K8-23 U62-6 #GPIO K8 Signal 11 Direct NET 'GPIO_K_8_PIN_24' K8-24 U62-5 #GPIO K8 Signal 11 Comp NET 'GPIO_K_8_PIN_25' K8-25 U63-6 #GPIO K8 Signal 12 Direct NET 'GPIO_K_8_PIN_26' K8-26 U63-5 #GPIO K8 Signal 12 Comp NET 'GPIO_K_8_PIN_27' K8-27 U63-8 #GPIO K8 Signal 13 Direct NET 'GPIO_K_8_PIN_28' K8-28 U63-7 #GPIO K8 Signal 13 Comp NET 'GPIO_K_8_PIN_29' K8-29 U64-8 #GPIO K8 Signal 14 Direct NET 'GPIO_K_8_PIN_30' K8-30 U64-7 #GPIO K8 Signal 14 Comp NET 'GPIO_K_8_PIN_31' K8-31 U64-6 #GPIO K8 Signal 15 Direct NET 'GPIO_K_8_PIN_32' K8-32 U64-5 #GPIO K8 Signal 15 Comp # Pins #33 and #34 are for the 40 MHz Clock signal: NET 'CLK_FO_8_DIR' K8-33 NET 'CLK_FO_8_CMP' K8-34 # Now connect the Power and Ground to each LVDS Driver/Receiver # chip and to its bypass capacitor from Vdd_Logic to Ground NET 'VDD_LOGIC' U57-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U57-4 # Ground connection NET 'VDD_LOGIC' C57-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C57-2 # Ground connection NET 'VDD_LOGIC' U58-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U58-4 # Ground connection NET 'VDD_LOGIC' C58-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C58-2 # Ground connection NET 'VDD_LOGIC' U59-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U59-4 # Ground connection NET 'VDD_LOGIC' C59-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C59-2 # Ground connection NET 'VDD_LOGIC' U60-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U60-4 # Ground connection NET 'VDD_LOGIC' C60-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C60-2 # Ground connection NET 'VDD_LOGIC' U61-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U61-4 # Ground connection NET 'VDD_LOGIC' C61-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C61-2 # Ground connection NET 'VDD_LOGIC' U62-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U62-4 # Ground connection NET 'VDD_LOGIC' C62-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C62-2 # Ground connection NET 'VDD_LOGIC' U63-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U63-4 # Ground connection NET 'VDD_LOGIC' C63-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C63-2 # Ground connection NET 'VDD_LOGIC' U64-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U64-4 # Ground connection NET 'VDD_LOGIC' C64-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C64-2 # Ground connection # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Mon Dec 19 13:22:16 2011 # MIGT> begin substituting from -- instance #5/5 # MIGT>---------------------------------------------- # # This is a Key In NETs Template file for the # H-CLK card for HAWC # # LOWER GPIO NETs Template # ------------==========---====--========---------- # # # Original Rev. 22-Apr-2011 # Most Recent Rev. 19-Dec-2011 # # # This file includes all the Nets for the LOWER GPIO connector # section of the H-CLK card. # # The component reference designators in this section start at 1. # # This file contains nets for the following components for each "unit cell": # # K1 # C1 : C8 # U1 : U8 # # Channel # 9 NET 'GPIO_K_9_PIN_1' K9-1 U65-6 #GPIO K9 Signal 0 Direct NET 'GPIO_K_9_PIN_2' K9-2 U65-5 #GPIO K9 Signal 0 Comp NET 'GPIO_K_9_PIN_3' K9-3 U65-8 #GPIO K9 Signal 1 Direct NET 'GPIO_K_9_PIN_4' K9-4 U65-7 #GPIO K9 Signal 1 Comp NET 'GPIO_K_9_PIN_5' K9-5 U66-8 #GPIO K9 Signal 2 Direct NET 'GPIO_K_9_PIN_6' K9-6 U66-7 #GPIO K9 Signal 2 Comp NET 'GPIO_K_9_PIN_7' K9-7 U66-6 #GPIO K9 Signal 3 Direct NET 'GPIO_K_9_PIN_8' K9-8 U66-5 #GPIO K9 Signal 3 Comp NET 'GPIO_K_9_PIN_9' K9-9 U67-6 #GPIO K9 Signal 4 Direct NET 'GPIO_K_9_PIN_10' K9-10 U67-5 #GPIO K9 Signal 4 Comp NET 'GPIO_K_9_PIN_11' K9-11 U67-8 #GPIO K9 Signal 5 Direct NET 'GPIO_K_9_PIN_12' K9-12 U67-7 #GPIO K9 Signal 5 Comp NET 'GPIO_K_9_PIN_13' K9-13 U68-8 #GPIO K9 Signal 6 Direct NET 'GPIO_K_9_PIN_14' K9-14 U68-7 #GPIO K9 Signal 6 Comp NET 'GPIO_K_9_PIN_15' K9-15 U68-6 #GPIO K9 Signal 7 Direct NET 'GPIO_K_9_PIN_16' K9-16 U68-5 #GPIO K9 Signal 7 Comp NET 'GPIO_K_9_PIN_17' K9-17 U69-6 #GPIO K9 Signal 8 Direct NET 'GPIO_K_9_PIN_18' K9-18 U69-5 #GPIO K9 Signal 8 Comp NET 'GPIO_K_9_PIN_19' K9-19 U69-8 #GPIO K9 Signal 9 Direct NET 'GPIO_K_9_PIN_20' K9-20 U69-7 #GPIO K9 Signal 9 Comp NET 'GPIO_K_9_PIN_21' K9-21 U70-8 #GPIO K9 Signal 10 Direct NET 'GPIO_K_9_PIN_22' K9-22 U70-7 #GPIO K9 Signal 10 Comp NET 'GPIO_K_9_PIN_23' K9-23 U70-6 #GPIO K9 Signal 11 Direct NET 'GPIO_K_9_PIN_24' K9-24 U70-5 #GPIO K9 Signal 11 Comp NET 'GPIO_K_9_PIN_25' K9-25 U71-6 #GPIO K9 Signal 12 Direct NET 'GPIO_K_9_PIN_26' K9-26 U71-5 #GPIO K9 Signal 12 Comp NET 'GPIO_K_9_PIN_27' K9-27 U71-8 #GPIO K9 Signal 13 Direct NET 'GPIO_K_9_PIN_28' K9-28 U71-7 #GPIO K9 Signal 13 Comp NET 'GPIO_K_9_PIN_29' K9-29 U72-8 #GPIO K9 Signal 14 Direct NET 'GPIO_K_9_PIN_30' K9-30 U72-7 #GPIO K9 Signal 14 Comp NET 'GPIO_K_9_PIN_31' K9-31 U72-6 #GPIO K9 Signal 15 Direct NET 'GPIO_K_9_PIN_32' K9-32 U72-5 #GPIO K9 Signal 15 Comp # Pins #33 and #34 are for the 40 MHz Clock signal: NET 'CLK_FO_9_DIR' K9-33 NET 'CLK_FO_9_CMP' K9-34 # Now connect the Power and Ground to each LVDS Driver/Receiver # chip and to its bypass capacitor from Vdd_Logic to Ground NET 'VDD_LOGIC' U65-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U65-4 # Ground connection NET 'VDD_LOGIC' C65-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C65-2 # Ground connection NET 'VDD_LOGIC' U66-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U66-4 # Ground connection NET 'VDD_LOGIC' C66-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C66-2 # Ground connection NET 'VDD_LOGIC' U67-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U67-4 # Ground connection NET 'VDD_LOGIC' C67-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C67-2 # Ground connection NET 'VDD_LOGIC' U68-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U68-4 # Ground connection NET 'VDD_LOGIC' C68-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C68-2 # Ground connection NET 'VDD_LOGIC' U69-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U69-4 # Ground connection NET 'VDD_LOGIC' C69-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C69-2 # Ground connection NET 'VDD_LOGIC' U70-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U70-4 # Ground connection NET 'VDD_LOGIC' C70-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C70-2 # Ground connection NET 'VDD_LOGIC' U71-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U71-4 # Ground connection NET 'VDD_LOGIC' C71-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C71-2 # Ground connection NET 'VDD_LOGIC' U72-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U72-4 # Ground connection NET 'VDD_LOGIC' C72-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C72-2 # Ground connection # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Mon Dec 19 13:22:16 2011 # MIGT> begin substituting from -- instance #5/5 # MIGT>---------------------------------------------- # # This is a Key In NETs Template file for the # H-CLK card for HAWC # # UPPER GPIO NETs Template # ------------==========---====--========---------- # # # Original Rev. 22-Apr-2011 # Most Recent Rev. 19-Dec-2011 # # # This file includes all the Nets for the UPPER GPIO connector # section of the H-CLK card. # # The component reference designators in this section start at 1. # # This file contains nets for the following components for each "unit cell": # # K2 # C9 : C16 # U9 : U16 # # Channel # 10 NET 'GPIO_K_10_PIN_1' K10-1 U73-6 #GPIO K10 Signal 0 Direct NET 'GPIO_K_10_PIN_2' K10-2 U73-5 #GPIO K10 Signal 0 Comp NET 'GPIO_K_10_PIN_3' K10-3 U73-8 #GPIO K10 Signal 1 Direct NET 'GPIO_K_10_PIN_4' K10-4 U73-7 #GPIO K10 Signal 1 Comp NET 'GPIO_K_10_PIN_5' K10-5 U74-8 #GPIO K10 Signal 2 Direct NET 'GPIO_K_10_PIN_6' K10-6 U74-7 #GPIO K10 Signal 2 Comp NET 'GPIO_K_10_PIN_7' K10-7 U74-6 #GPIO K10 Signal 3 Direct NET 'GPIO_K_10_PIN_8' K10-8 U74-5 #GPIO K10 Signal 3 Comp NET 'GPIO_K_10_PIN_9' K10-9 U75-6 #GPIO K10 Signal 4 Direct NET 'GPIO_K_10_PIN_10' K10-10 U75-5 #GPIO K10 Signal 4 Comp NET 'GPIO_K_10_PIN_11' K10-11 U75-8 #GPIO K10 Signal 5 Direct NET 'GPIO_K_10_PIN_12' K10-12 U75-7 #GPIO K10 Signal 5 Comp NET 'GPIO_K_10_PIN_13' K10-13 U76-8 #GPIO K10 Signal 6 Direct NET 'GPIO_K_10_PIN_14' K10-14 U76-7 #GPIO K10 Signal 6 Comp NET 'GPIO_K_10_PIN_15' K10-15 U76-6 #GPIO K10 Signal 7 Direct NET 'GPIO_K_10_PIN_16' K10-16 U76-5 #GPIO K10 Signal 7 Comp NET 'GPIO_K_10_PIN_17' K10-17 U77-6 #GPIO K10 Signal 8 Direct NET 'GPIO_K_10_PIN_18' K10-18 U77-5 #GPIO K10 Signal 8 Comp NET 'GPIO_K_10_PIN_19' K10-19 U77-8 #GPIO K10 Signal 9 Direct NET 'GPIO_K_10_PIN_20' K10-20 U77-7 #GPIO K10 Signal 9 Comp NET 'GPIO_K_10_PIN_21' K10-21 U78-8 #GPIO K10 Signal 10 Direct NET 'GPIO_K_10_PIN_22' K10-22 U78-7 #GPIO K10 Signal 10 Comp NET 'GPIO_K_10_PIN_23' K10-23 U78-6 #GPIO K10 Signal 11 Direct NET 'GPIO_K_10_PIN_24' K10-24 U78-5 #GPIO K10 Signal 11 Comp NET 'GPIO_K_10_PIN_25' K10-25 U79-6 #GPIO K10 Signal 12 Direct NET 'GPIO_K_10_PIN_26' K10-26 U79-5 #GPIO K10 Signal 12 Comp NET 'GPIO_K_10_PIN_27' K10-27 U79-8 #GPIO K10 Signal 13 Direct NET 'GPIO_K_10_PIN_28' K10-28 U79-7 #GPIO K10 Signal 13 Comp NET 'GPIO_K_10_PIN_29' K10-29 U80-8 #GPIO K10 Signal 14 Direct NET 'GPIO_K_10_PIN_30' K10-30 U80-7 #GPIO K10 Signal 14 Comp NET 'GPIO_K_10_PIN_31' K10-31 U80-6 #GPIO K10 Signal 15 Direct NET 'GPIO_K_10_PIN_32' K10-32 U80-5 #GPIO K10 Signal 15 Comp # Pins #33 and #34 are for the 40 MHz Clock signal: NET 'CLK_FO_10_DIR' K10-33 NET 'CLK_FO_10_CMP' K10-34 # Now connect the Power and Ground to each LVDS Driver/Receiver # chip and to its bypass capacitor from Vdd_Logic to Ground NET 'VDD_LOGIC' U73-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U73-4 # Ground connection NET 'VDD_LOGIC' C73-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C73-2 # Ground connection NET 'VDD_LOGIC' U74-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U74-4 # Ground connection NET 'VDD_LOGIC' C74-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C74-2 # Ground connection NET 'VDD_LOGIC' U75-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U75-4 # Ground connection NET 'VDD_LOGIC' C75-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C75-2 # Ground connection NET 'VDD_LOGIC' U76-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U76-4 # Ground connection NET 'VDD_LOGIC' C76-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C76-2 # Ground connection NET 'VDD_LOGIC' U77-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U77-4 # Ground connection NET 'VDD_LOGIC' C77-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C77-2 # Ground connection NET 'VDD_LOGIC' U78-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U78-4 # Ground connection NET 'VDD_LOGIC' C78-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C78-2 # Ground connection NET 'VDD_LOGIC' U79-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U79-4 # Ground connection NET 'VDD_LOGIC' C79-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C79-2 # Ground connection NET 'VDD_LOGIC' U80-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U80-4 # Ground connection NET 'VDD_LOGIC' C80-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C80-2 # Ground connection # MIGT>---------------------------------------------- # MIGT> done substituting from # This is a Key In Net List file for the # H-CLK card's Power Entry and GPS Power # # # Original Rev. 5-MAY-2011 # Most Recent Rev. 1-DEC-2011 # This file includes all the nets for the Power Entry # and GPS Power. It also includes the nets to ground # ground the front panel of the card through isolation # resistors. # VCC +5V Power Entry # ------------------- NET 'VME_5V' F400-2 # VME +5 Volt Bus Power Fuse NET 'VCC_LOGIC' F400-1 # on board Vcc +5 Volts NET 'VCC_LOGIC' D400-1 # VCC_Logic Varistor NET 'GROUND' D400-2 NET 'VCC_LOGIC' C400-1 # VCC_Logic Aluminum NET 'GROUND' C400-2 NET 'VCC_LOGIC' C401-1 C430-1 C431-1 C432-1 # VCC_Logic Tantalum NET 'GROUND' C401-2 C430-2 C431-2 C432-2 NET 'VCC_LOGIC' C402-1 C403-2 C404-1 C405-2 # VCC_Logic Ceramic NET 'GROUND' C402-2 C403-1 C404-2 C405-1 NET 'VCC_LOGIC' C406-1 C407-2 C408-1 C409-2 # VCC_Logic Ceramic NET 'GROUND' C406-2 C407-1 C408-2 C409-1 # Additional Vcc Ceramic Capacitors to clamp the whole Vcc Plane NET 'VCC_LOGIC' C433-1 C434-2 C435-1 C436-2 # VCC_Logic Ceramic NET 'GROUND' C433-2 C434-1 C435-2 C436-1 NET 'VCC_LOGIC' C437-1 C438-2 C439-1 C440-2 # VCC_Logic Ceramic NET 'GROUND' C437-2 C438-1 C439-2 C440-1 NET 'VCC_LOGIC' C441-1 C442-2 C443-1 C444-2 # VCC_Logic Ceramic NET 'GROUND' C441-2 C442-1 C443-2 C444-1 # VDD +3.3V Power Entry # --------------------- NET 'VDD_LOGIC' F420-2 # VME +3.3 Volt Bus Power Fuse NET 'VDD_LOGIC' F420-1 # on board Vdd +3.3 Volts # power plane slit to isolate Fues NET 'VDD_LOGIC' D420-1 # VDD_Logic Varistor NET 'GROUND' D420-2 NET 'VDD_LOGIC' C420-1 # VDD_Logic Aluminum NET 'GROUND' C420-2 NET 'VDD_LOGIC' C421-1 C422-1 C423-1 # VDD_Logic Tantalum NET 'GROUND' C421-2 C422-2 C423-2 # Additional Vdd Ceramic Capacitors NET 'VDD_LOGIC' C445-2 C446-1 C447-2 C448-1 # VDD_Logic Ceramic NET 'GROUND' C445-1 C446-2 C447-1 C448-2 NET 'VDD_LOGIC' C449-1 C450-1 C451-1 C452-1 # VDD_Logic Ceramic NET 'GROUND' C449-2 C450-2 C451-2 C452-2 NET 'VDD_LOGIC' C453-1 C454-1 # VDD_Logic Ceramic NET 'GROUND' C453-2 C454-2 # VME +12V Power Entry and GPS Power # ------------------------------------- NET 'VME_P12V' F410-2 # VME +12 Volt Bus Power Fuse NET 'P12V_ON_BRD' F410-1 # on board +12 Volts NET 'P12V_ON_BRD' D410-1 D410-2 # VME Isolation Diode Anode NET 'GPS_POWER' D410-3 # VME Isolation Diode Cathode NET 'GPS_BAT_POS' F411-2 # Battery power comes on-card # via P2 pin A1. Fuse at the # battery and on-card. NET 'FUSED_BAT_POW' F411-1 # Battery Fuse NET 'FUSED_BAT_POW' V12-1 # Wire Via to Front of Card NET 'FRONT_BAT_POW' V11-1 # Wire Via at Front of Card NET 'FRONT_BAT_POW' D411-1 D411-2 # Battery Isolation Diode Anode NET 'FRONT_BAT_POW' R410-2 # Battery Charging Resistor - shunt D411 NET 'GPS_POWER' D411-3 # Battery Isolation Diode Cathode NET 'GPS_POWER' R410-1 # Battery Charging Resistor - shunt D411 NET 'GPS_POWER' D412-1 # +12 Volt Varistor NET 'GROUND' D412-2 NET 'GPS_POWER' C410-1 C411-1 # GPS Power Aluminum and Tantalum NET 'GROUND' C410-2 C411-2 NET 'GPS_POWER' C412-1 C413-1 # GPS Power Ceramic Caps NET 'GROUND' C412-2 C413-2 # Ground the Front Panel of the card through isolation # resistors R420 and R421. The isolated ground connections # to the front panel mounting screws at the top and bottom # are made through "components" ground_anchor 1 and 2. NET 'GROUND' R420-1 R421-1 # Ground end of the isolation resistors NET 'GA_TIE_1' R420-2 GA1-1 # Tie the isolation resistors to the NET 'GA_TIE_2' R421-2 GA2-1 # front panel mounting screw pads. # This is a Key In Net List file for the # GPS Receiver Connector # # Original Rev. 6-MAY-2011 # Most Recent Rev. 6-MAY-2011 # This file includes all the NETS for the # GPS Receiver Connector. # GPS Receiver Connector # ---------------------- NET 'H_CLK_SERIAL_TRANS' K11-1 # RS-232 output from the H-Clk Card NET 'GROUND' K11-2 # Ground NET 'GPS_POWER' K11-3 K11-4 # GPS Power NET 'GROUND' K11-5 K11-6 # Ground NET 'PPS_1_POS_IN' K11-7 # 1 PPS + from the GPS Receiver NET 'PPS_1_NEG_IN' K11-8 # 1 PPS - from the GPS Receiver NET 'GROUND' K11-9 K11-10 # Ground NET 'MHZ_10_IN' K11-11 # 10 MHz sine wave from the GPS Receiver NET 'GROUND' K11-12 # Ground NET 'GROUND' K11-13 K11-14 # Ground NET 'H_CLK_SERIAL_RECVR' K11-15 # RS-232 input to the H-Clk Card NET 'GROUND' K11-16 # Ground # This is a Key In Net List file for the # RS-232 Tranceiver Nets # -------------------====- # # Original Rev. 6-MAY-2011 # Most Recent Rev. 26-OCT-2011 # This file includes all the NETS for the # RS-232 Transceiver # # MAX3232 RS-232 Receiver # NET 'H_CLK_SERIAL_RECVR' R273-2 # RS-232 from the GPS to iso resistor NET 'H_CLK_SERIAL_RECVR' D271-1 # TVS Protection on data from GPS NET 'GROUND' D271-2 # Ground TVS Protection Diode NET 'H_CLK_SER_ISO_RECV' R273-1 U271-13 # Isolated GPS Data into Receiver NET 'MAX_REC_1_OUT' U271-12 R271-1 # Rec #1 output to isolation resistor NET 'SERIAL_TO_FPGA' R271-2 # Received GPS Serial to FPGA NET 'GROUND' U271-8 # Reveiver #2 Input Grounded # # MAX3232 RS-232 Transmitter # NET 'SERIAL_FROM_FPGA' U271-11 # Serial from FPGA into transmitter NET 'MAX_TRANS_1_OUT' U271-14 R272-1 # Trans #1 out to isolation resistor NET 'H_CLK_SERIAL_TRANS' R272-2 # RS-232 from H-Clk to GPS NET 'H_CLK_SERIAL_TRANS' D272-1 # TVS Protection on data to GPS NET 'GROUND' D272-2 # Ground TVS Protection Diode NET 'GROUND' U271-10 # Transmitter #2 Input Grounded # # MAX3232 Internal Power Supply Capacitors # NET 'MAX_PS_C1_POS' C272-1 U271-1 # Internal Power Supply C1 NET 'MAX_PS_C1_NEG' C272-2 U271-3 # NET 'MAX_PS_C2_POS' C273-1 U271-4 # Internal Power Supply C2 NET 'MAX_PS_C2_NEG' C273-2 U271-5 # NET 'MAX_PS_C3_POS' C274-1 U271-2 # Internal Power Supply C3 NET 'GROUND' C274-2 # NET 'MAX_PS_C4_POS' C275-1 U271-6 # Internal Power Supply C4 NET 'GROUND' C275-2 # # # Power and Ground to the MAX3232 chip # NET 'VDD_LOGIC' U271-16 # +3.3V Power to the MAX3232 NET 'GROUND' U271-15 # Ground to the MAX3232 NET 'VDD_LOGIC' C271-1 C276-2 # Power ByPass Capacitor NET 'GROUND' C271-2 C276-1 # # # Un-Connected pins on the H-Clk's usage of the MAX3232 # # transmitter #2 output pin #7 is not used # receiver #2 output pin #9 is not used # # This is a Key In Net List file for the # H-CLK card's MEZ-456 FPGA FSI Connector Power and Ground # # Original Rev. 9-MAY-2011 # Most Recent Rev. 9-MAY-2011 # This file includes all the nets for the Power and Ground # to the H-Clk's FPGA on the MEZ-456 via the FSI connectors. # VCC +5V Power to MEZ-456 FPGA # ----------------------------- NET 'VCC_LOGIC' J1-49 J1-50 J1-51 J1-52 # +5V power to J1 FSI NET 'VCC_LOGIC' J2-49 J2-50 J2-51 J2-52 # +5V power to J2 FSI NET 'VCC_LOGIC' J3-49 J3-50 J3-51 J3-52 # +5V power to J3 FSI NET 'VCC_LOGIC' J4-49 J4-50 J4-51 J4-52 # +5V power to J3 FSI # Ground to the MEZ-456 FPGA # -------------------------- NET 'GROUND' J1-1 J1-2 J1-7 J1-8 # Ground to J1 FSI NET 'GROUND' J1-13 J1-14 J1-19 J1-20 NET 'GROUND' J1-29 J1-30 J1-35 J1-36 NET 'GROUND' J1-41 J1-42 J1-47 J1-48 NET 'GROUND' J1-53 J1-54 J1-59 J1-60 NET 'GROUND' J1-65 J1-66 J1-71 J1-72 NET 'GROUND' J1-81 J1-82 J1-87 J1-88 NET 'GROUND' J1-93 J1-94 J1-99 J1-100 NET 'GROUND' J2-1 J2-2 J2-7 J2-8 # Ground to J2 FSI NET 'GROUND' J2-13 J2-14 J2-19 J2-20 NET 'GROUND' J2-29 J2-30 J2-35 J2-36 NET 'GROUND' J2-41 J2-42 J2-47 J2-48 NET 'GROUND' J2-53 J2-54 J2-59 J2-60 NET 'GROUND' J2-65 J2-66 J2-71 J2-72 NET 'GROUND' J2-81 J2-82 J2-87 J2-88 NET 'GROUND' J2-93 J2-94 J2-99 J2-100 NET 'GROUND' J3-1 J3-2 J3-7 J3-8 # Ground to J3 FSI NET 'GROUND' J3-13 J3-14 J3-19 J3-20 NET 'GROUND' J3-29 J3-30 J3-35 J3-36 NET 'GROUND' J3-41 J3-42 J3-47 J3-48 NET 'GROUND' J3-53 J3-54 J3-59 J3-60 NET 'GROUND' J3-65 J3-66 J3-71 J3-72 NET 'GROUND' J3-81 J3-82 J3-87 J3-88 NET 'GROUND' J3-93 J3-94 J3-99 J3-100 NET 'GROUND' J4-1 J4-2 J4-7 J4-8 # Ground to J4 FSI NET 'GROUND' J4-13 J4-14 J4-19 J4-20 NET 'GROUND' J4-29 J4-30 J4-35 J4-36 NET 'GROUND' J4-41 J4-42 J4-47 J4-48 NET 'GROUND' J4-53 J4-54 J4-59 J4-60 NET 'GROUND' J4-65 J4-66 J4-71 J4-72 NET 'GROUND' J4-81 J4-82 J4-87 J4-88 NET 'GROUND' J4-93 J4-94 J4-99 J4-100 # This is a Key In Net List file for the # H-CLK card's Receiver GPS 10 MHz and GPS 1 PPS # -----------------=================================== # # Original Rev. 14-JULY-2011 # Most Recent Rev. 9-NOV-2011 # This file includes all the nets for the # Receivers for the GPS 10 MHz and 1 PPS ######################################################## # # # Receiver for the GPS 10 MHz # # # ######################################################## NET 'MHZ_10_IN' R201-1 C201-1 # 10 MHz sine wave from the GPS NET 'GROUND' R201-2 # Ground the Term Resistor NET 'MHZ_10_IN' D201-1 # TVS Protection on 10 MHz from GPS NET 'GROUND' D201-2 # Ground TVS Protection Diode NET 'MHZ_10_RC' C201-2 R202-1 # Series Cap to Resistor connection NET 'MHZ_10_POS_IN' R202-2 R203-1 # Input to + term of receiver NET 'MHZ_10_POS_IN' C202-1 U201-6 # NET 'MHZ_10_NEG_IN' R203-2 # Input to - term of receiver NET 'MHZ_10_NEG_IN' C202-2 U201-5 # This is the +1.2V Reference. NET 'MHZ_10_NEG_IN' R204-1 R205-1 # NET 'MHZ_10_NEG_IN' C203-1 C204-1 # NET 'MHZ_10_NEG_IN' C205-1 C206-1 # NET 'MHZ_10_NEG_IN' C211-1 C212-1 # NET 'GROUND' R204-2 # Ground the ByPass Caps for NET 'GROUND' C203-2 C204-2 # the +1.2V Ref Supply and NET 'GROUND' C205-2 C206-2 # Ground the voltage divider. NET 'GROUND' C211-2 C212-2 # Ground the voltage divider. NET 'VCC_PLL' R205-2 # Quiet Vcc for the +1.2V resistor divider NET 'RECVD_10_MHZ' U201-3 U202-2 # Receiver Out to Driver In NET 'DRVN_10_MHZ_DIR' U202-8 # Received 10 MHz Driver Direct Out NET 'DRVN_10_MHZ_CMP' U202-7 # Received 10 MHz Driver Comp Out ######################################################## # # # Receiver for the GPS 1 PPS # # # ######################################################## NET 'PPS_1_POS_IN' R206-1 R207-1 # 1 PPS + from the GPS Receiver NET 'PPS_1_POS_IN' D203-1 # TVS Protection on +1 PPS from GPS NET 'GROUND' D203-2 # Ground TVS Protection Diode NET 'PPS_1_NEG_IN' R206-2 R208-1 # 1 PPS - from the GPS Receiver NET 'PPS_1_NEG_IN' D202-2 # TVS Protection on -1 PPS from GPS NET 'GROUND' D202-1 # Ground TVS Protection Diode NET 'PPS_1_POS_ATTN' R207-2 R209-1 # Input to + term of receiver NET 'PPS_1_POS_ATTN' U201-8 R211-2 # and the R211 attenuator NET 'PPS_1_NEG_ATTN' R208-2 R210-1 # Input to - term of receiver NET 'PPS_1_NEG_ATTN' U201-7 R211-1 # and the R211 attenuator NET 'GROUND' R209-2 R210-2 # Ground the voltage dividers NET 'RECVD_1_PPS' U201-2 U202-3 # Receiver Out to Driver In NET 'DRVN_1_PPS_DIR' U202-6 # Received 10 MHz Driver Direct Out NET 'DRVN_1_PPS_CMP' U202-5 # Received 10 MHz Driver Comp Out ######################################################## # # # Power and Gnd and Vdd ByPass for U201 and U202 # # # ######################################################## NET 'VDD_LOGIC' U201-1 U202-1 # Vdd for receiver and driver NET 'GROUND' U201-4 U202-4 # Gnd for receiver and driver NET 'VDD_LOGIC' C207-1 C208-1 # ByPass Caps for U201 NET 'GROUND' C207-2 C208-2 # NET 'VDD_LOGIC' C209-1 C210-1 # ByPass Caps for U202 NET 'GROUND' C209-2 C210-2 # # This is a Key In Net List file for the # H-CLK card's 40 MHz Clock Fanout # ---------------===================== # # # Original Rev. 9-MAY-2011 # Most Recent Rev. 1-NOV-2011 # This file includes all the nets for the # Fanout of the 40 MHz Clock. # # See the very end of this file for 2 other small # functions that use the same parts and thus are # included in this file. # # CMOS to LVDS Driver of the PLL's 40 MHz Clock U251 # -------------------------------------------------------- # # Isolate, AC Couple, and Clamp the 5V Output of the VCXO NET 'VCXO_WFRM' R251-1 # VCXO Output to Isolation Resistor NET 'ISO_VCXO_WFRM' R251-2 C251-1 # VCXO Output AC Coupling Capacitor NET 'CLAMP_VCXO_WFRM' D251-3 C251-2 # Clamp Diode on the 40 MHz Waveform NET 'GROUND' D251-1 # Ground Clamp Diode Anode NET 'VDD_LOGIC' D251-2 # Vdd_Logic to Clamp Diode Cathode # 40 MHz PLL - CMOS to LVDS Driver chip # This drives the 40 MHz distribution bus NET 'CLAMP_VCXO_WFRM' U251-3 # PLL 40 MHz LVDS Driver Input NET 'PLL_DRV_40_MHZ_BUS_DIR' U251-6 R252-1 # LVDS Direct Ouput NET 'PLL_DRV_40_MHZ_BUS_CMP' U251-5 R253-1 # LVDS Complement Output # # 40 MHz Distribution Bus - Driver Output and Buffer Input and Terminator NET 'DIST_BUS_40_MHZ_DIR' R252-2 # Drive from PLL NET 'DIST_BUS_40_MHZ_DIR' R254-2 # Drive from External Clock NET 'DIST_BUS_40_MHZ_DIR' U254-3 # Input to FPGA Glb_Clk Buffer NET 'DIST_BUS_40_MHZ_DIR' U255-3 # Input to Access Connector Buffer NET 'DIST_BUS_40_MHZ_DIR' U252-7 # Input to 1:10 FanOut to GPIO Connectors NET 'DIST_BUS_40_MHZ_DIR' R257-1 # Terminator on 40 MHz Distribution Bus NET 'DIST_BUS_40_MHZ_CMP' R253-2 # Drive from PLL NET 'DIST_BUS_40_MHZ_CMP' R255-2 # Drive from External Clock NET 'DIST_BUS_40_MHZ_CMP' U254-2 # Input to FPGA Glb_Clk Buffer NET 'DIST_BUS_40_MHZ_CMP' U255-2 # Input to Access Connector Buffer NET 'DIST_BUS_40_MHZ_CMP' U252-8 # Input to 1:10 FanOut to GPIO Connectors NET 'DIST_BUS_40_MHZ_CMP' R257-2 # Terminator on 40 MHz Distribution Bus # # LVDS buffer output to the H-Clk's FPGA Global Clock Net NET 'CLK_40_DIR_FOR_FPGA' U254-6 # 40 MHz Clock to the FPGA NET 'CLK_40_CMP_FOR_FPGA' U254-7 # 40 MHz Clock to the FPGA # # LVDS buffer output to the H-Clk's Access Connector NET 'CLK_40_DIR_FOR_ACCESS_CONN' U255-6 # 40 MHz Clock to Access Connector NET 'CLK_40_CMP_FOR_ACCESS_CONN' U255-7 # 40 MHz Clock to Access Connector # # FanOut of the 40 MHz Clock to the 10 GPIO connectors K1:K10 U253 NET 'CLK_FO_7_DIR' U252-3 # 40 MHz Clock Dir to GPIO K1 NET 'CLK_FO_7_CMP' U252-4 # 40 MHz Clock Cmp to GPIO K1 NET 'CLK_FO_9_DIR' U252-1 # 40 MHz Clock Dir to GPIO K2 NET 'CLK_FO_9_CMP' U252-2 # 40 MHz Clock Cmp to GPIO K2 NET 'CLK_FO_5_DIR' U252-28 # 40 MHz Clock Dir to GPIO K3 NET 'CLK_FO_5_CMP' U252-27 # 40 MHz Clock Cmp to GPIO K3 NET 'CLK_FO_3_DIR' U252-26 # 40 MHz Clock Dir to GPIO K4 NET 'CLK_FO_3_CMP' U252-25 # 40 MHz Clock Cmp to GPIO K4 NET 'CLK_FO_1_DIR' U252-24 # 40 MHz Clock Dir to GPIO K5 NET 'CLK_FO_1_CMP' U252-23 # 40 MHz Clock Cmp to GPIO K5 NET 'CLK_FO_10_DIR' U252-20 # 40 MHz Clock Dir to GPIO K6 NET 'CLK_FO_10_CMP' U252-19 # 40 MHz Clock Cmp to GPIO K6 NET 'CLK_FO_8_DIR' U252-18 # 40 MHz Clock Dir to GPIO K7 NET 'CLK_FO_8_CMP' U252-17 # 40 MHz Clock Cmp to GPIO K7 NET 'CLK_FO_6_DIR' U252-16 # 40 MHz Clock Dir to GPIO K8 NET 'CLK_FO_6_CMP' U252-15 # 40 MHz Clock Cmp to GPIO K8 NET 'CLK_FO_2_DIR' U252-13 # 40 MHz Clock Dir to GPIO K9 NET 'CLK_FO_2_CMP' U252-14 # 40 MHz Clock Cmp to GPIO K9 NET 'CLK_FO_4_DIR' U252-11 # 40 MHz Clock Dir to GPIO K10 NET 'CLK_FO_4_CMP' U252-12 # 40 MHz Clock Cmp to GPIO K10 # # Enable U252 the DS90LV110's outputs. NET 'DS90_OUTPUT_ENB' R259-1 U252-5 # Output Enable Control on DS90LV110 NET 'VDD_LOGIC' R259-2 # Pullup to +3.3 Volt Vdd # # External Clock Driver for the 40 MHz Distribution Bus # The External Clock comes from the Access Connector NET 'EXT_40_MHZ_CLK_IN_DIR' R256-1 U253-3 # Input to External Clk Buffer NET 'EXT_40_MHZ_CLK_IN_CMP' R256-2 U253-2 # Input to External Clk Buffer NET 'EXT_40M_CLK_BUF_OUT_DIR' U253-6 R254-1 # External Clk Buffer Output NET 'EXT_40M_CLK_BUF_OUT_CMP' U253-7 R255-1 # External Clk Buffer Output # # Functions outside of the 40 MHz Distribution # but that use the same parts and thus are logicaly in this nets file # # Buffered External Signal to just an FPGA Global Clock Net # Note that both the input and output differential pins on # LVDS buffer U256 are being used "up-side-down" for routing reasons. NET 'EXT_FPGA_CLK_IN_DIR' R258-1 U256-2 # Input to the Ext FPGA Clk Buffer NET 'EXT_FPGA_CLK_IN_CMP' R258-2 U256-3 # Input to the Ext FPGA Clk Buffer NET 'EXT_FPGA_CLK_BUF_OUT_DIR' U256-7 # External FPGA Clk Buffer Output NET 'EXT_FPGA_CLK_BUF_OUT_CMP' U256-6 # External FPGA Clk Buffer Output # CMOS to LVDS Buffered Output from the FPGA - U251 Buffer. NET 'FPGA_BUFD_LVDS_DRV_IN' U251-2 # Normal FPGA I/O input to LVDS Conv NET 'FPGA_BUFD_LVDS_OUT_DIR' U251-8 # Buffered LVDS Signal NET 'FPGA_BUFD_LVDS_OUT_CMP' U251-7 # from a normal FPGA I/O pin # # Now Enable the Outputs on the 4 DS90LV001 # LVDS Buffer Chips U253, U254, U255, U256 NET 'ENB_BUFF_U253' U253-8 R260-1 # Pullup on U253 Enable Pin NET 'VDD_LOGIC' R260-2 # Vdd to the pullup resistor NET 'ENB_BUFF_U254' U254-8 R261-1 # Pullup on U254 Enable Pin NET 'VDD_LOGIC' R261-2 # Vdd to the pullup resistor NET 'ENB_BUFF_U255' U255-8 R262-1 # Pullup on U255 Enable Pin NET 'VDD_LOGIC' R262-2 # Vdd to the pullup resistor NET 'ENB_BUFF_U256' U256-8 R263-1 # Pullup on U256 Enable Pin NET 'VDD_LOGIC' R263-2 # Vdd to the pullup resistor # # Finally the Power and Ground Connections and some Enable Pins # for all of the ICs in this section, i.e. # U251, U251, U251, U251, U251, # Power and Ground for the Dual CMOS to LVDS Driver chip U251 NET 'VDD_LOGIC' U251-1 # CMOS to LVDS Driver chip +3.3V Vdd pin NET 'GROUND' U251-4 # CMOS to LVDS Driver chip Ground pin NET 'VDD_LOGIC' C252-1 C253-1 C265-1 # Vdd Logic bypass caps NET 'GROUND' C252-2 C253-2 C265-2 # bypass caps grounds # Power, Ground, and ByPass of the DS90LV110 1:10 FanOut chip U252 NET 'VDD_LOGIC' U252-10 U252-22 # FanOut Chip +3.3 Volt Vdd pins NET 'GROUND' U252-6 U252-9 U252-21 # FanOut Chip Ground pins NET 'VDD_LOGIC' C254-1 C255-1 C256-1 # Fanout ByPass Cap Vdd NET 'GROUND' C254-2 C255-2 C256-2 # Fanout ByPass Cap Ground # Power, Ground, and ByPass of the DS90LV001 LVDS Buffer U253 NET 'VDD_LOGIC' U253-5 # LVDS Buffer chip +3.3V Vdd pin NET 'GROUND' U253-1 # LVDS Buffer chip Ground pin NET 'VDD_LOGIC' C257-1 C258-1 # Vdd Logic bypass caps NET 'GROUND' C257-2 C258-2 # bypass caps grounds # Power, Ground, and ByPass of the DS90LV001 LVDS Buffer U254 NET 'VDD_LOGIC' U254-5 # LVDS Buffer chip +3.3V Vdd pin NET 'GROUND' U254-1 # LVDS Buffer chip Ground pin NET 'VDD_LOGIC' C259-1 C260-1 # Vdd Logic bypass caps NET 'GROUND' C259-2 C260-2 # bypass caps grounds # Power, Ground, and ByPass of the DS90LV001 LVDS Buffer U255 NET 'VDD_LOGIC' U255-5 # LVDS Buffer chip +3.3V Vdd pin NET 'GROUND' U255-1 # LVDS Buffer chip Ground pin NET 'VDD_LOGIC' C261-1 C262-1 # Vdd Logic bypass caps NET 'GROUND' C261-2 C262-2 # bypass caps grounds # Power, Ground, and ByPass of the DS90LV001 LVDS Buffer U256 NET 'VDD_LOGIC' U256-5 # LVDS Buffer chip +3.3V Vdd pin NET 'GROUND' U256-1 # LVDS Buffer chip Ground pin NET 'VDD_LOGIC' C263-1 C264-1 # Vdd Logic bypass caps NET 'GROUND' C263-2 C264-2 # bypass caps grounds # This is a Key In Net List file for the # H-CLK card's 40 MHz Phase Locked Loop # ----------------========================- # # Original Rev. 10-MAY-2011 # Most Recent Rev. 28-NOV-2011 # This file includes all the nets for the # 40 MHz PLL Clock Generator ######################################################## # # # Receive the PLL Reference and Feedback signals # # that are coming from the H-Clk's FPGA as # # LVDS signals on differential trace pairs. # # # ######################################################## NET 'PLL_REF_DIR' U221-8 R229-1 # PLL Phase Comparator Reference DIR NET 'PLL_REF_CMP' U221-7 R229-2 # PLL Phase Comparator Reference CMP NET 'PLL_REF_RCVD' U221-2 # Received PLL Reference Signal NET 'PLL_FBK_DIR' U221-6 R230-1 # PLL Phase Comparator Reference DIR NET 'PLL_FBK_CMP' U221-5 R230-2 # PLL Phase Comparator Reference CMP NET 'PLL_FBK_RCVD' U221-3 # Received PLL Feedback Signal NET 'VDD_LOGIC' U221-1 # Vdd for LVDS Receiver NET 'GROUND' U221-4 # Gnd for LVDS Receiver NET 'VDD_LOGIC' C227-1 C228-1 # ByPass Caps for U221 NET 'GROUND' C227-2 C228-2 # ######################################################## # # # PLL Phase Detector U222 XOR # # # ######################################################## NET 'PLL_REF_RCVD' U222-4 # Phase Comparator Reference Signal NET 'PLL_FBK_RCVD' U222-5 U222-10 # Phase Comparator Feedback Signal NET 'GROUND' U222-9 # Ground other Volt Ref XOR input NET 'PHASE_DET_OUT' U222-6 # Phase-Detector output NET 'LOOP_FILTER_REF' U222-8 # Reference Voltage output NET 'GROUND' U222-1 U222-2 # Ground some unused XOR inputs NET 'VCC_PLL' U222-12 U222-13 # VCC_PLL some unused XOR inputs NET 'VCC_PLL' U222-14 # Vcc for Phase Detector NET 'GROUND' U222-7 # Gnd for Phase Detector NET 'VCC_PLL' C229-1 C230-1 C231-1 # ByPass Caps for U222 NET 'GROUND' C229-2 C230-2 C231-2 # ######################################################## # # # PLL Loop Filter U223 # # # ######################################################## # Non-Inverting side of the Loop Filter Op-Amp NET 'LOOP_FILTER_REF' R222-1 # Reference to input resistor NET 'LF_FLT_PLS' R222-2 C222-1 R224-1 # Filter on + side input NET 'GROUND' C222-2 # Ground the filter capacitor NET 'LF_OPAMP_PLUS_IN' C224-1 U223-3 R224-2 # Op-Amp non-invert input NET 'GROUND' C224-2 # Ground the filter capacitor # Input to the Inverting side of the Loop Filter Op-Amp NET 'PHASE_DET_OUT' R221-1 # Phase Det to input resistor NET 'LF_FLT_NEG' R221-2 C221-1 R223-1 # Filter on - side input NET 'GROUND' C221-2 # Ground the filter capacitor NET 'LF_OPAMP_NEG_IN' U223-4 R223-2 # Op-Amp invert input # Loop Filter Op-Amp Feadback Network NET 'LF_OPAMP_NEG_IN' C223-2 R225-2 # Op-Amp invert input NET 'LF_OPAMP_OUT' U223-1 C223-1 C225-2 # Op-Amp Output NET 'LF_FB_RC_TIE' R225-1 C225-1 # Connect feedback R and C # Connect the Loop Filter output to the VCXO Control Input NET 'LF_OPAMP_OUT' R226-1 # Loop Filter output to VCXO Input Filter # Connect the Loop Filter output to the PLL Monitoring NET 'LF_OPAMP_OUT' R227-1 # Loop Filter output isolation resistor NET 'MONITOR_ISO' R227-2 # Jump to the 2nd Monitor Isolation resistor NET 'MONITOR_ISO' R231-2 # 2nd PLL Monitor Isolation resistor NET 'MONITOR_PLL' R231-1 # Connections for PLL Monitor # Connect the Loop Filter power and ground and bypass capacitors NET 'VCC_PLL' U223-6 # Vcc for the Loop Filter Op-Amp NET 'GROUND' U223-2 # Gnd for the Loop Filter Op-Amp NET 'VCC_PLL' C232-1 C233-1 C234-1 # ByPass Caps for U223 NET 'GROUND' C232-2 C233-2 C234-2 # ######################################################## # # # PLL Voltage Controlled Crystal Oscillator U224 # # # ######################################################## # Pin #2 is the Enable/Disable pin. High --> Enable Output. # Pin #5 has no internal connection and it will be left floating. # Pin #1 Control Input, Pin #3 Ground, Pin #4 Output, Pin #6 Vcc NET 'VCXO_CTRL_IN' R226-2 C226-1 # Signal to the VCXO Control Input NET 'GROUND' C226-2 # Ground the filter capacitor NET 'VCXO_CTRL_IN' U224-1 # VCXO Control Input pin NET 'VCXO_ENBL' U224-2 R228-1 # VCXO Enable pin NET 'VCXO_WFRM' U224-4 # VCXO Output signal NET 'VCC_PLL' U224-6 R228-2 # Vcc for the VCXO NET 'GROUND' U224-3 # Gnd for the VCXO NET 'VCC_PLL' C235-1 C236-1 C237-1 # ByPass Caps for U224 NET 'GROUND' C235-2 C236-2 C237-2 # ################################################### # # # PLL Isolated +5 Volt PLL Vcc # # # ################################################### # The Phase Detector, Loop Filter Op-Amp, and the VCX0 # are powered from an isolated +5 Volt PLL Vcc supply. # # This PLL Vcc supply is just a section "moated" out of the # VCC_PLL plane. In the net list these PLL Vcc connections # appear as connected to the standard VCC_PLL supply. # # There is an inductor that connects the PLL VCC plane to the # standard VCC_PLL plane, i.e. it crosses the moat. NET 'VCC_LOGIC' I221-2 # Power source from VCC_LOGIC plane fill NET 'VCC_PLL' I221-1 # Power to the PLL VCC_PLL plane fill NET 'VCC_PLL' C238-1 # PLL Vcc Tantalum cap NET 'GROUND' C238-2 # bypass caps grounds NET 'VCC_PLL' C239-1 C240-1 # PLL Vcc Ceramic caps NET 'GROUND' C239-2 C240-2 # bypass caps grounds NET 'VCC_PLL' C241-1 C242-1 # PLL Vcc Ceramic caps NET 'GROUND' C241-2 C242-2 # bypass caps grounds NET 'VCC_PLL' C243-1 C244-1 # PLL Vcc Ceramic caps NET 'GROUND' C243-2 C244-2 # bypass caps grounds NET 'VCC_PLL' C245-1 # PLL Vcc Ceramic caps NET 'GROUND' C245-2 # bypass caps grounds # This is a Key In Net List file for the # H-CLK card's ACCESS Connector # ----------------====================- # # # Original Rev. 20-JULY-2011 # Most Recent Rev. 8-NOV-2011 # This file includes all the nets for the # ACCESS Connector J5. # # This file also includes the some vias for access # to various signals. Via V1 connects to a pin on # The J5 Access Connector. Vias V13:V16 connect to # unused FPGA I/O pins on the J1 FSI connector. # Ground Pins on the Access Connector # Many of the Odd Pins on J5 are tied # to Ground. Othere pins are tied to # ground to give good isolation between # various sections of this connector. NET 'GROUND' J5-1 J5-2 # Grounds NET 'GROUND' J5-7 J5-8 # Grounds NET 'GROUND' J5-13 J5-14 # Grounds NET 'GROUND' J5-15 # Grounds NET 'GROUND' J5-17 J5-18 # Grounds NET 'GROUND' J5-19 # Grounds NET 'GROUND' J5-21 # Grounds NET 'GROUND' J5-25 # Grounds NET 'GROUND' J5-29 # Grounds NET 'GROUND' J5-33 # Grounds NET 'GROUND' J5-37 # Grounds NET 'GROUND' J5-39 # Grounds # Use 2 pins each for VCC and VDD power supplies. NET 'VDD_LOGIC' J5-23 J5-31 # Vdd supply to Access NET 'VCC_LOGIC' J5-27 J5-35 # Vcc supply to Access # Put the PLL Monditor Signal on Pin #16 # with Grounds on all sides. NET 'MONITOR_PLL' J5-16 # PLL Monitor on pin #16 # Connect the FPGA "Configure" Pushbutton to pin #38 and #40. NET 'SWTCH_2_NC' J5-40 # Front Panel S2 Normal Closed Contact pin #40 NET 'SWTCH_2_NO' J5-38 # Front Panel S2 Normal Open Contact pin #38 # The "Open Via" pin is #36 NET 'OPEN_VIA' J5-36 V1-1 # Open Via to Access Connector # DeBug Signals from the Mez-456 FPGA on the DeBug Connector NET 'DEBUG_01' J5-20 # DeBug Signal #1 NET 'DEBUG_02' J5-22 # DeBug Signal #2 NET 'DEBUG_03' J5-24 # DeBug Signal #3 NET 'DEBUG_04' J5-26 # DeBug Signal #4 NET 'DEBUG_05' J5-28 # DeBug Signal #5 NET 'DEBUG_06' J5-30 # DeBug Signal #6 NET 'DEBUG_07' J5-32 # DeBug Signal #7 NET 'DEBUG_08' J5-34 # DeBug Signal #8 # External Clock to the 40 MHz Distribution Bus via a Buffer NET 'EXT_40_MHZ_CLK_IN_DIR' J5-10 # External LVDS Clock to the NET 'EXT_40_MHZ_CLK_IN_CMP' J5-12 # 40 MHz Distribution Bus # External Clock to the FPGA via a Buffer NET 'EXT_FPGA_CLK_IN_DIR' J5-5 # External LVDS Signal to a NET 'EXT_FPGA_CLK_IN_CMP' J5-3 # FPGA Global Clock Net # 40 MHz Clock from the Distribution Bus via a Buffer/Driver NET 'CLK_40_DIR_FOR_ACCESS_CONN' J5-4 # From 40 MHz Distribution Bus NET 'CLK_40_CMP_FOR_ACCESS_CONN' J5-6 # via a Buffer/Driver # LVDS Signal from Normal FPGA I/O Pin via a Buffer/Driver NET 'FPGA_BUFD_LVDS_OUT_DIR' J5-9 # NET 'FPGA_BUFD_LVDS_OUT_CMP' J5-11 # # # Un-Used FPGA I/O Pins on the J1 FSI Connector # # There are a total of 6 FPGA pins that are not used. # All 6 of these pins are on the J1 FSI connector. # It is easy to run 4 of the 6 spare FPGA signals to vias. # The signal assignments for these 4 spare FPGA # signal vias are made here. These are vias V13:V16 # NET 'SPARE_SIG_V13' V13-1 # Spare FPGA Signal to V13 NET 'SPARE_SIG_V14' V14-1 # Spare FPGA Signal to V14 NET 'SPARE_SIG_V15' V15-1 # Spare FPGA Signal to V15 NET 'SPARE_SIG_V16' V16-1 # Spare FPGA Signal to V16 # This is a Key In Net List file for the # H-CLK card's Front Panel LEDs and Switches # ----------------=============================- # # # Original Rev. 20-JULY-2011 # Most Recent Rev. 26-SEPT-2011 # This file includes all the nets for the # Front Panel LEDs and Pushbutton Switches. # # Vdd_Logic Power LED LED_3 Left # NET 'GROUND' LED3-1 # Ground LED Cathode NET 'LED_VDD_POW' LED3-2 R289-2 # LED Anode to Resistor NET 'VDD_LOGIC' R289-1 # Vdd to Resistor # # Vcc_Logic Power LED LED_3 Center # NET 'GROUND' LED3-3 # Ground LED Cathode NET 'LED_VCC_POW' LED3-4 R288-2 # LED Anode to Resistor NET 'VCC_LOGIC' R288-1 # Vcc to Resistor # # GPS Receiver Power LED LED_3 Right # NET 'GROUND' LED3-5 # Ground LED Cathode NET 'LED_GPS_POW' LED3-6 R287-2 # LED Anode to Resistor NET 'GPS_POWER' R287-1 # GPS Power to Resistor # # FPGA Indicator LED_2 Left # NET 'VDD_LOGIC' LED2-2 # LED Anode to Vdd NET 'LED_2L_RSTR' LED2-1 R286-1 # LED Cathode to Resistor NET 'LED_2L_ON_B' R286-2 # LED 2 Left - pull low for ON # # FPGA Indicator LED_2 Center # NET 'VDD_LOGIC' LED2-4 # LED Anode to Vdd NET 'LED_2C_RSTR' LED2-3 R285-1 # LED Cathode to Resistor NET 'LED_2C_ON_B' R285-2 # LED 2 Center - pull low for ON # # FPGA Indicator LED_2 Right # NET 'VDD_LOGIC' LED2-6 # LED Anode to Vdd NET 'LED_2R_RSTR' LED2-5 R284-1 # LED Cathode to Resistor NET 'LED_2R_ON_B' R284-2 # LED 2 Right - pull low for ON # # FPGA Indicator LED_1 Left # NET 'VDD_LOGIC' LED1-2 # LED Anode to Vdd NET 'LED_1L_RSTR' LED1-1 R283-1 # LED Cathode to Resistor NET 'LED_1L_ON_B' R283-2 # LED 1 Left - pull low for ON # # FPGA Indicator LED_1 Center # NET 'VDD_LOGIC' LED1-4 # LED Anode to Vdd NET 'LED_1C_RSTR' LED1-3 R282-1 # LED Cathode to Resistor NET 'LED_1C_ON_B' R282-2 # LED 1 Center - pull low for ON # # FPGA Indicator LED_1 Right # NET 'VDD_LOGIC' LED1-6 # LED Anode to Vdd NET 'LED_1R_RSTR' LED1-5 R281-1 # LED Cathode to Resistor NET 'LED_1R_ON_B' R281-2 # LED 1 Right - pull low for ON # # Pushbutton Switch S1 General Purpose FPGA Input # NET 'GROUND' S1-1 S1-3 # Ground switch center contact & housing NET 'SWTCH_1_NC' S1-2 R290-1 # S1 Normal Closed Contact and PU Resistor NET 'SWTCH_1_NO' S1-4 R291-1 # S1 Normal Open Contact and PU Resistor NET 'VDD_LOGIC' R290-2 R291-2 # PU Resistors to Vdd # # Pushbutton Switch S2 FPGA Configuration to DeBug Connector # NET 'GROUND' S2-1 S2-3 # Ground switch center contact & housing NET 'SWTCH_2_NC' S2-2 # S2 Normal Closed Contact NET 'SWTCH_2_NO' S2-4 # S2 Normal Open Contact # # File created by Match_Resource_to_Pin V0.1 at Mon Dec 19 13:22:17 2011 # derived from input Netlist file # and Resource to Pin dictionary # # # This is the Net 2 Resource file for the # # K1 to J2 FSI Connections # ---==------------------------- # # # Original Rev. 8-Sept-2011 # Current Rev. 19-Dec-2011 # This file specifies what J2 FSI Resource is # connected to each K1 GPIO driver or receiver. # -- NET 'GPIO_K_1_SIGNAL_0' U1-3 J2-45 # IO_L96P_7 NET 'GPIO_K_1_SIGNAL_1' U1-2 J2-46 # IO_L96N_7 NET 'GPIO_K_1_SIGNAL_2' U2-2 J2-43 # IO_L94P_7 NET 'GPIO_K_1_SIGNAL_3' U2-3 J2-44 # IO_L94N_7 NET 'GPIO_K_1_SIGNAL_4' U3-3 J2-39 # IO_L93P_7_VREF_7 NET 'GPIO_K_1_SIGNAL_5' U3-2 J2-40 # IO_L93N_7 NET 'GPIO_K_1_SIGNAL_6' U4-2 J2-37 # IO_L91P_7 NET 'GPIO_K_1_SIGNAL_7' U4-3 J2-38 # IO_L91N_7 NET 'GPIO_K_1_SIGNAL_8' U5-3 J2-33 # IO_L51P_7_VREF_7 NET 'GPIO_K_1_SIGNAL_9' U5-2 J2-34 # IO_L51N_7 NET 'GPIO_K_1_SIGNAL_10' U6-2 J2-31 # IO_L49P_7 NET 'GPIO_K_1_SIGNAL_11' U6-3 J2-32 # IO_L49N_7 NET 'GPIO_K_1_SIGNAL_12' U7-3 J2-27 # IO_L48P_7 NET 'GPIO_K_1_SIGNAL_13' U7-2 J2-28 # IO_L48N_7 NET 'GPIO_K_1_SIGNAL_14' U8-2 J2-25 # IO_L46P_7 NET 'GPIO_K_1_SIGNAL_15' U8-3 J2-26 # IO_L46N_7 # # This is the Net 2 Resource file for the # # K2 to J2 FSI Connections # ---==------------------------- # # # Original Rev. 8-Sept-2011 # Current Rev. 19-Dec-2011 # This file specifies what J2 FSI Resource is # connected to each K2 GPIO driver or receiver. # -- NET 'GPIO_K_2_SIGNAL_0' U9-3 J2-23 # IO_L43P_7 NET 'GPIO_K_2_SIGNAL_1' U9-2 J2-24 # IO_L43N_7 NET 'GPIO_K_2_SIGNAL_2' U10-2 J2-21 # IO_L24P_7 NET 'GPIO_K_2_SIGNAL_3' U10-3 J2-22 # IO_L24N_7 NET 'GPIO_K_2_SIGNAL_4' U11-3 J2-17 # IO_L22P_7 NET 'GPIO_K_2_SIGNAL_5' U11-2 J2-18 # IO_L22N_7 NET 'GPIO_K_2_SIGNAL_6' U12-2 J2-15 # IO_L21P_7_VREF_7 NET 'GPIO_K_2_SIGNAL_7' U12-3 J2-16 # IO_L21N_7 NET 'GPIO_K_2_SIGNAL_8' U13-3 J2-11 # IO_L06P_7 NET 'GPIO_K_2_SIGNAL_9' U13-2 J2-12 # IO_L06N_7 NET 'GPIO_K_2_SIGNAL_10' U14-2 J2-9 # IO_L04P_7 NET 'GPIO_K_2_SIGNAL_11' U14-3 J2-10 # IO_L04N_7 NET 'GPIO_K_2_SIGNAL_12' U15-3 J2-5 # IO_L03P_7_VREF_7 NET 'GPIO_K_2_SIGNAL_13' U15-2 J2-6 # IO_L03N_7 NET 'GPIO_K_2_SIGNAL_14' U16-2 J2-3 # IO_L02P_7_VRN_7 NET 'GPIO_K_2_SIGNAL_15' U16-3 J2-4 # IO_L02N_7_VRP_7 # # This is the Net 2 Resource file for the # # K3 to J2 FSI Connections # ---==------------------------- # # # Original Rev. 9-Sept-2011 # Current Rev. 19-Dec-2011 # This file specifies what J2 FSI Resource is # connected to each K3 GPIO driver or receiver. # -- NET 'GPIO_K_3_SIGNAL_0' U17-3 J2-97 # IO_L02P_6_VRN_6 NET 'GPIO_K_3_SIGNAL_1' U17-2 J2-68 # IO_L51N_6_VREF_6 NET 'GPIO_K_3_SIGNAL_2' U18-2 J2-95 # IO_L04P_6 NET 'GPIO_K_3_SIGNAL_3' U18-3 J2-70 # IO_L49N_6 NET 'GPIO_K_3_SIGNAL_4' U19-3 J2-91 # IO_L03P_6 NET 'GPIO_K_3_SIGNAL_5' U19-2 J2-74 # IO_L46N_6 NET 'GPIO_K_3_SIGNAL_6' U20-2 J2-89 # IO_L19P_6 NET 'GPIO_K_3_SIGNAL_7' U20-3 J2-76 # IO_L45N_6_VREF_6 NET 'GPIO_K_3_SIGNAL_8' U21-3 J2-85 # IO_L06P_6 NET 'GPIO_K_3_SIGNAL_9' U21-2 J2-78 # IO_L43N_6 NET 'GPIO_K_3_SIGNAL_10' U22-2 J2-83 # IO_L21P_6 NET 'GPIO_K_3_SIGNAL_11' U22-3 J2-80 # IO_L24N_6 NET 'GPIO_K_3_SIGNAL_12' U23-3 J2-79 # IO_L24P_6 NET 'GPIO_K_3_SIGNAL_13' U23-2 J2-84 # IO_L21N_6_VREF_6 NET 'GPIO_K_3_SIGNAL_14' U24-2 J2-77 # IO_L43P_6 NET 'GPIO_K_3_SIGNAL_15' U24-3 J2-86 # IO_L06N_6 # # This is the Net 2 Resource file for the # # K4 to J2 FSI Connections # ---==------------------------- # # # Original Rev. 9-Sept-2011 # Current Rev. 19-Dec-2011 # This file specifies what J2 FSI Resource is # connected to each K4 GPIO driver or receiver. # -- NET 'GPIO_K_4_SIGNAL_0' U25-3 J2-75 # IO_L45P_6 NET 'GPIO_K_4_SIGNAL_1' U25-2 J2-90 # IO_L19N_6 NET 'GPIO_K_4_SIGNAL_2' U26-2 J2-73 # IO_L46P_6 NET 'GPIO_K_4_SIGNAL_3' U26-3 J2-92 # IO_L03N_6_VREF_6 NET 'GPIO_K_4_SIGNAL_4' U27-3 J2-69 # IO_L49P_6 NET 'GPIO_K_4_SIGNAL_5' U27-2 J2-96 # IO_L04N_6 NET 'GPIO_K_4_SIGNAL_6' U28-2 J2-67 # IO_L51P_6 NET 'GPIO_K_4_SIGNAL_7' U28-3 J2-98 # IO_L02N_6_VRP_6 NET 'GPIO_K_4_SIGNAL_8' U29-3 J2-63 # IO_L54P_6 NET 'GPIO_K_4_SIGNAL_9' U29-2 J2-64 # IO_L54N_6 NET 'GPIO_K_4_SIGNAL_10' U30-2 J2-61 # IO_L91P_6 NET 'GPIO_K_4_SIGNAL_11' U30-3 J2-62 # IO_L91N_6 NET 'GPIO_K_4_SIGNAL_12' U31-3 J2-57 # IO_L94P_6 NET 'GPIO_K_4_SIGNAL_13' U31-2 J2-58 # IO_L94N_6 NET 'GPIO_K_4_SIGNAL_14' U32-2 J2-55 # IO_L96P_6 NET 'GPIO_K_4_SIGNAL_15' U32-3 J2-56 # IO_L96N_6 # # This is the Net 2 Resource file for the # # K5 to J3 FSI Connections # ---==------------------------- # # # Original Rev. 9-Sept-2011 # Current Rev. 19-Dec-2011 # This file specifies what J3 FSI Resource is # connected to each K5 GPIO driver or receiver. # -- NET 'GPIO_K_5_SIGNAL_0' U33-3 J3-45 # IO_L96N_5_GCLK7S NET 'GPIO_K_5_SIGNAL_1' U33-2 J3-46 # IO_L95N_5_GCLK5S NET 'GPIO_K_5_SIGNAL_2' U34-2 J3-43 # IO_L96P_5_GCLK6P NET 'GPIO_K_5_SIGNAL_3' U34-3 J3-44 # IO_L95P_5_GCLK4P NET 'GPIO_K_5_SIGNAL_4' U35-3 J3-39 # IO_L93P_5 NET 'GPIO_K_5_SIGNAL_5' U35-2 J3-40 # IO_L93N_5 NET 'GPIO_K_5_SIGNAL_6' U36-2 J3-37 # IO_L54P_5 NET 'GPIO_K_5_SIGNAL_7' U36-3 J3-38 # IO_L54N_5 NET 'GPIO_K_5_SIGNAL_8' U37-3 J3-33 # IO_L92P_5 NET 'GPIO_K_5_SIGNAL_9' U37-2 J3-34 # IO_L92N_5 NET 'GPIO_K_5_SIGNAL_10' U38-2 J3-31 # IO_L51P_5 NET 'GPIO_K_5_SIGNAL_11' U38-3 J3-32 # IO_L51N_5_VREF_5 NET 'GPIO_K_5_SIGNAL_12' U39-3 J3-27 # IO_L52P_5 NET 'GPIO_K_5_SIGNAL_13' U39-2 J3-28 # IO_L52N_5 NET 'GPIO_K_5_SIGNAL_14' U40-2 J3-25 # IO_L22P_5 NET 'GPIO_K_5_SIGNAL_15' U40-3 J3-26 # IO_L22N_5 # # This is the Net 2 Resource file for the # # K6 to J3 FSI Connections # ---==------------------------- # # # Original Rev. 9-Sept-2011 # Current Rev. 19-Dec-2011 # This file specifies what J3 FSI Resource is # connected to each K6 GPIO driver or receiver. # -- NET 'GPIO_K_6_SIGNAL_0' U41-3 J3-23 # IO_L49P_5 NET 'GPIO_K_6_SIGNAL_1' U41-2 J3-24 # IO_L49N_5 NET 'GPIO_K_6_SIGNAL_2' U42-2 J3-21 # IO_L19P_5 NET 'GPIO_K_6_SIGNAL_3' U42-3 J3-22 # IO_L19N_5 NET 'GPIO_K_6_SIGNAL_4' U43-3 J3-17 # IO_L21P_5 NET 'GPIO_K_6_SIGNAL_5' U43-2 J3-18 # IO_L21N_5_VREF_5 NET 'GPIO_K_6_SIGNAL_6' U44-2 J3-15 # IO_L04P_5_VREF_5 NET 'GPIO_K_6_SIGNAL_7' U44-3 J3-16 # IO_L04N_5 NET 'GPIO_K_6_SIGNAL_8' U45-3 J3-11 # IO_L06P_5 NET 'GPIO_K_6_SIGNAL_9' U45-2 J3-12 # IO_L06N_5 NET 'GPIO_K_6_SIGNAL_10' U46-2 J3-9 # IO_L02P_5_D7 NET 'GPIO_K_6_SIGNAL_11' U46-3 J3-10 # IO_L02N_5_D6 NET 'GPIO_K_6_SIGNAL_12' U47-3 J3-5 # IO_L03P_5_D5_ALT_VRN_5 NET 'GPIO_K_6_SIGNAL_13' U47-2 J3-6 # IO_L03N_5_D4_ALT_VRP_5 NET 'GPIO_K_6_SIGNAL_14' U48-2 J3-3 # IO_L01P_5_CS_B NET 'GPIO_K_6_SIGNAL_15' U48-3 J3-4 # IO_L01N_5_RDWR_B # # This is the Net 2 Resource file for the # # K7 to J3 FSI Connections # ---==------------------------- # # # Original Rev. 9-Sept-2011 # Current Rev. 19-Dec-2011 # This file specifies what J3 FSI Resource is # connected to each K7 GPIO driver or receiver. # -- NET 'GPIO_K_7_SIGNAL_0' U49-3 J3-97 # IO_L01P_3 NET 'GPIO_K_7_SIGNAL_1' U49-2 J3-98 # IO_L01N_4_BUSY_DOUT NET 'GPIO_K_7_SIGNAL_2' U50-2 J3-95 # IO_L03P_4_D3_ALT_VRN_4 NET 'GPIO_K_7_SIGNAL_3' U50-3 J3-96 # IO_L03N_4_D2_ALT_VRP_4 NET 'GPIO_K_7_SIGNAL_4' U51-3 J3-91 # IO_L04P_4 NET 'GPIO_K_7_SIGNAL_5' U51-2 J3-92 # IO_L04N_4_VREF_4 NET 'GPIO_K_7_SIGNAL_6' U52-2 J3-89 # IO_L05P_4_VRN_4 NET 'GPIO_K_7_SIGNAL_7' U52-3 J3-90 # IO_L05N_4_VRP_4 NET 'GPIO_K_7_SIGNAL_8' U53-3 J3-85 # IO_L06P_4 NET 'GPIO_K_7_SIGNAL_9' U53-2 J3-86 # IO_L06N_4 NET 'GPIO_K_7_SIGNAL_10' U54-2 J3-83 # IO_L21P_4_VREF_4 NET 'GPIO_K_7_SIGNAL_11' U54-3 J3-84 # IO_L21N_4 NET 'GPIO_K_7_SIGNAL_12' U55-3 J3-79 # IO_L22P_4 NET 'GPIO_K_7_SIGNAL_13' U55-2 J3-80 # IO_L22N_4 NET 'GPIO_K_7_SIGNAL_14' U56-2 J3-77 # IO_L24P_4 NET 'GPIO_K_7_SIGNAL_15' U56-3 J3-78 # IO_L24N_4 # # This is the Net 2 Resource file for the # # K8 to J3 FSI Connections # ---==------------------------- # # # Original Rev. 9-Sept-2011 # Current Rev. 19-Dec-2011 # This file specifies what J3 FSI Resource is # connected to each K8 GPIO driver or receiver. # -- NET 'GPIO_K_8_SIGNAL_0' U57-3 J3-75 # IO_L49P_4 NET 'GPIO_K_8_SIGNAL_1' U57-2 J3-76 # IO_L49N_4 NET 'GPIO_K_8_SIGNAL_2' U58-2 J3-73 # IO_L52P_4 NET 'GPIO_K_8_SIGNAL_3' U58-3 J3-74 # IO_L52N_4 NET 'GPIO_K_8_SIGNAL_4' U59-3 J3-69 # IO_L54P_4 NET 'GPIO_K_8_SIGNAL_5' U59-2 J3-70 # IO_L54N_4 NET 'GPIO_K_8_SIGNAL_6' U60-2 J3-67 # IO_L92P_4 NET 'GPIO_K_8_SIGNAL_7' U60-3 J3-68 # IO_L92N_4 NET 'GPIO_K_8_SIGNAL_8' U61-3 J3-63 # IO_L93P_4 NET 'GPIO_K_8_SIGNAL_9' U61-2 J3-64 # IO_L93N_4 NET 'GPIO_K_8_SIGNAL_10' U62-2 J3-61 # IO_L91P_4 NET 'GPIO_K_8_SIGNAL_11' U62-3 J3-62 # IO_L91N_4_VREF_4 NET 'GPIO_K_8_SIGNAL_12' U63-3 J3-57 # IO_L96P_4_GCLK0P NET 'GPIO_K_8_SIGNAL_13' U63-2 J3-58 # IO_L95P_4_GCLK2P NET 'GPIO_K_8_SIGNAL_14' U64-2 J3-55 # IO_L96N_4_GCLK1S NET 'GPIO_K_8_SIGNAL_15' U64-3 J3-56 # IO_L95N_4_GCLK3S # # This is the Net 2 Resource file for the # # K9 to J4 FSI Connections # ---==------------------------- # # # Original Rev. 14-Sept-2011 # Current Rev. 19-Dec-2011 # This file specifies what J4 FSI Resource is # connected to each K9 GPIO driver or receiver. # -- NET 'GPIO_K_9_SIGNAL_0' U65-3 J4-45 # IO_L96P_3 NET 'GPIO_K_9_SIGNAL_1' U65-2 J4-46 # IO_L96N_3 NET 'GPIO_K_9_SIGNAL_2' U66-2 J4-43 # IO_L94P_3 NET 'GPIO_K_9_SIGNAL_3' U66-3 J4-44 # IO_L94N_3 NET 'GPIO_K_9_SIGNAL_4' U67-3 J4-39 # IO_L91P_3 NET 'GPIO_K_9_SIGNAL_5' U67-2 J4-40 # IO_L91N_3 NET 'GPIO_K_9_SIGNAL_6' U68-2 J4-37 # IO_L54P_3 NET 'GPIO_K_9_SIGNAL_7' U68-3 J4-38 # IO_L54N_3 NET 'GPIO_K_9_SIGNAL_8' U69-3 J4-33 # IO_L51P_3 NET 'GPIO_K_9_SIGNAL_9' U69-2 J4-34 # IO_L51N_3_VREF_3 NET 'GPIO_K_9_SIGNAL_10' U70-2 J4-31 # IO_L49P_3 NET 'GPIO_K_9_SIGNAL_11' U70-3 J4-32 # IO_L49N_3 NET 'GPIO_K_9_SIGNAL_12' U71-3 J4-27 # IO_L48P_3 NET 'GPIO_K_9_SIGNAL_13' U71-2 J4-28 # IO_L48N_3 NET 'GPIO_K_9_SIGNAL_14' U72-2 J4-25 # IO_L46P_3 NET 'GPIO_K_9_SIGNAL_15' U72-3 J4-26 # IO_L46N_3 # # This is the Net 2 Resource file for the # # K10 to J4 FSI Connections # ---===------------------------- # # # Original Rev. 14-Sept-2011 # Current Rev. 19-Dec-2011 # This file specifies what J4 FSI Resource is # connected to each K10 GPIO driver or receiver. # --- NET 'GPIO_K_10_SIGNAL_0' U73-3 J4-23 # IO_L43P_3 NET 'GPIO_K_10_SIGNAL_1' U73-2 J4-24 # IO_L43N_3 NET 'GPIO_K_10_SIGNAL_2' U74-2 J4-21 # IO_L24P_3 NET 'GPIO_K_10_SIGNAL_3' U74-3 J4-22 # IO_L24N_3 NET 'GPIO_K_10_SIGNAL_4' U75-3 J4-17 # IO_L22P_3 NET 'GPIO_K_10_SIGNAL_5' U75-2 J4-18 # IO_L22N_3 NET 'GPIO_K_10_SIGNAL_6' U76-2 J4-15 # IO_L21P_3 NET 'GPIO_K_10_SIGNAL_7' U76-3 J4-16 # IO_L21N_3_VREF_3 NET 'GPIO_K_10_SIGNAL_8' U77-3 J4-11 # IO_L06P_3 NET 'GPIO_K_10_SIGNAL_9' U77-2 J4-12 # IO_L06N_3 NET 'GPIO_K_10_SIGNAL_10' U78-2 J4-9 # IO_L04P_3 NET 'GPIO_K_10_SIGNAL_11' U78-3 J4-10 # IO_L04N_3 NET 'GPIO_K_10_SIGNAL_12' U79-3 J4-5 # IO_L03P_3 NET 'GPIO_K_10_SIGNAL_13' U79-2 J4-6 # IO_L03N_3_VREF_3 NET 'GPIO_K_10_SIGNAL_14' U80-2 J4-3 # IO_L02P_3_VRN_3 NET 'GPIO_K_10_SIGNAL_15' U80-3 J4-4 # IO_L02N_3_VRP_3 # # This is the Net 2 Resource file for the # # Miscellaneous J1 FSI Connections # ---------------------------------- # # # Original Rev. 15-Sept-2011 # Current Rev. 8-NOV-2011 # This file specifies what J1 FSI Resource is # connected to the Miscellaneous J1 nets. # # This file includes all the miscellaneous connections # to the J1 FSI connector to the MEZ-456, these include: # # Clock Signals, RS-232, LEDs, Pushbuttons, DeBug # 40 MHz Global Clock from the PLL to the FPGA # -------------------------------------------- NET 'CLK_40_DIR_FOR_FPGA' J1-43 # IO_L95P_1_GCLK0S NET 'CLK_40_CMP_FOR_FPGA' J1-45 # IO_L95N_1_GCLK1P # 10 MHz Global Clock from the GPS Receiver to the FPGA # ----------------------------------------------------- NET 'DRVN_10_MHZ_DIR' J1-58 # IO_L95P_0_GCLK6S NET 'DRVN_10_MHZ_CMP' J1-56 # IO_L95N_0_GCLK7P # 1 PPS from the GPS Receiver to the FPGA # ----------------------------------------- NET 'DRVN_1_PPS_DIR' J1-57 # IO_L96P_0_GCLK4S NET 'DRVN_1_PPS_CMP' J1-55 # IO_L96N_0_GCLK5P # External Signal from the Access Conn to Global Clock Net # --------------------------------------------------------- NET 'EXT_FPGA_CLK_BUF_OUT_DIR' J1-44 # IO_L96P_1_GCLK2S NET 'EXT_FPGA_CLK_BUF_OUT_CMP' J1-46 # IO_L96N_1_GCLK3P # Normal FPGA I/O Pin to the CMOS to LVDS Converter/Driver # and then to the Access Connector # ---------------------------------------------------------- NET 'FPGA_BUFD_LVDS_DRV_IN' J1-39 # IO_L94P_1_VREF_1 # PLL Reference and PLL Feedback from the FPGA # to the PLL's LVDS Inputs NET 'PLL_REF_DIR' J1-67 # IO_L92P_0 NET 'PLL_REF_CMP' J1-68 # IO_L92N_0 NET 'PLL_FBK_DIR' J1-63 # IO_L93P_0 NET 'PLL_FBK_CMP' J1-64 # IO_L93N_0 # Connect the RS-232 Signals to/from GPS Receiver # ------------------------------------------------- NET 'SERIAL_TO_FPGA' J1-83 # IO_L21P_0_VREF_0 NET 'SERIAL_FROM_FPGA' J1-85 # IO_L05P_0 # Connect the 6 Front Panel LEDs # -------------------------------- # FPGA Indicator LED_2 Left NET 'LED_2L_ON_B' J1-92 # IO_L03N_0_VRP_0 # FPGA Indicator LED_2 Center NET 'LED_2C_ON_B' J1-98 # IO_L01N_0 # FPGA Indicator LED_2 Right NET 'LED_2R_ON_B' J1-96 # IO_L02P_0 # FPGA Indicator LED_1 Left NET 'LED_1L_ON_B' J1-91 # IO_L03P_0_VRN_0 # FPGA Indicator LED_1 Center NET 'LED_1C_ON_B' J1-90 # IO_L04N_0_VREF_0 # FPGA Indicator LED_1 Right NET 'LED_1R_ON_B' J1-89 # IO_L04P_0 # Connect the Front Panel Pushbutton Switch # ------------------------------------------- # NET 'SWTCH_1_NC' J1-95 # IO_L02N_0 NET 'SWTCH_1_NO' J1-97 # IO_L01P_0 # # DeBug Connections from MEZ-456 J1 Connector # to the DeBug Connector J5 # NET 'DEBUG_01' J1-73 # IO_L52P_0 NET 'DEBUG_02' J1-74 # IO_L52N_0 NET 'DEBUG_03' J1-75 # IO_L49P_0 NET 'DEBUG_04' J1-76 # IO_L49N_0 NET 'DEBUG_05' J1-77 # IO_L24P_0 NET 'DEBUG_06' J1-78 # IO_L24N_0 NET 'DEBUG_07' J1-79 # IO_L22P_0 NET 'DEBUG_08' J1-80 # IO_L22N_0 # # Un-Used FPGA I/O Pins on the J1 FSI Connector # # There are a total of 6 FPGA pins that are not used. # All 6 of these pins are on the J1 FSI connector. # It is easy to run 4 of the 6 spare FPGA signals to vias. # The signal assignments for these 4 spare FPGA # signal vias are made here. These are vias V13:V16 # NET 'SPARE_SIG_V13' J1-86 # IO_L05N_0 NET 'SPARE_SIG_V14' J1-84 # IO_L21N_0 NET 'SPARE_SIG_V15' J1-70 # IO_L54N_0 NET 'SPARE_SIG_V16' J1-62 # IO_L91N_0_VREF_0 # # This is the Net 2 Resource file for the # # On Card Data Bus to J1 FSI Connections # ------------------------------------------ # # # Original Rev. 16-Sept-2011 # Current Rev. 7-Nov-2011 # This file specifies what J1 FSI Resource is # connected to which VME Data Bus receiver/driver. # This file includes the connections for all the VME P1 backplane # Data Bus signals from their buffer, i.e. U304, over to the J1 # connector for the MEZ-456. # The routing of these signals into the FPGA on the MEZ-456 is # picked to make the trace layout as easy as possible on the # H-Clk pcb. # Connect the 16 data lines from the "A" side of the U304 # 74LVT16245B Transceiver to J1 pins on the MEZ-456. NET 'OCB_DATA(7)' J1-27 # IO_L52P_1 NET 'OCB_DATA(15)' J1-37 # IO_L93P_1 NET 'OCB_DATA(6)' J1-33 # IO_L92P_1 NET 'OCB_DATA(14)' J1-40 # IO_L94N_1 NET 'OCB_DATA(5)' J1-38 # IO_L93N_1 NET 'OCB_DATA(13)' J1-34 # IO_L92N_1 NET 'OCB_DATA(4)' J1-32 # IO_L54N_1 NET 'OCB_DATA(12)' J1-28 # IO_L52N_1 NET 'OCB_DATA(3)' J1-26 # IO_L51P_1 NET 'OCB_DATA(11)' J1-24 # IO_L49N_1 NET 'OCB_DATA(2)' J1-22 # IO_L22N_1 NET 'OCB_DATA(10)' J1-18 # IO_L21N_1_VREF_1 NET 'OCB_DATA(1)' J1-16 # IO_L05N_1 NET 'OCB_DATA(9)' J1-12 # IO_L04N_1 NET 'OCB_DATA(0)' J1-10 # IO_L03N_1_VRP_1 NET 'OCB_DATA(8)' J1-6 # IO_L02N_1 # Connection from the MEZ-456 FPGA to the two Direction # pins of the 74LVT16245B VME Data Bus Transceiver. # When Low -> B input A output i.e. VME Write # When High -> A input B output i.e. VME Read NET 'DATA_BUF_DIR' J1-4 # IO_L01N_1 # Connection from the MEZ-456 FPGA to the two Output Enable bar # pins of the 74LVT16245B VME Data Bus Transceiver. # When high -> neither buffer output is enabled. NET 'DATA_BUF_ENB_B' J1-25 # IO_L51N_1_VREF_1 # # This is the Net 2 Resource file for the # # On Card Address and Control Bus # to # J1 and J4 FSI Connections # ----------------------------------------- # # # Original Rev. 16-Sept-2011 # Current Rev. 7-NOV-2011 # This file specifies what J1 or J4 FSI Resource is # connected to which On Card Address and Control Bus line. # This file includes the connections for all the VME P1 backplane # Address and Control type signals from their buffers/latches, i.e. # U301, U302, and U303 over to the J1 and J4 connectors for # the MEZ-456. # The routing of these signals into the FPGA on the MEZ-456 is # picked to make the trace layout as easy as possible on the # H-Clk pcb. # First take care of the 31 VME backplane signals that are received # and latched by U301 and U302. # Latch for VME "adrs type" information U302 NET 'LTCHD_AM(5)' J4-97 # IO_L01P_2 NET 'LTCHD_WRITE_B' J4-98 # IO_L01N_2 NET 'OCB_ADRS(23)' J4-95 # IO_L03P_2_VREF_2 NET 'OCB_ADRS(22)' J4-96 # IO_L03N_2 NET 'LTCHD_AM(0)' J4-91 # IO_L04P_2 NET 'OCB_ADRS(21)' J4-92 # IO_L04N_2 NET 'LTCHD_AM(1)' J4-89 # IO_L06P_2 NET 'OCB_ADRS(20)' J4-90 # IO_L06N_2 NET 'LTCHD_AM(2)' J4-86 # IO_L19N_2 NET 'OCB_ADRS(19)' J4-85 # IO_L19P_2 NET 'LTCHD_AM(3)' J4-84 # IO_L21N_2 NET 'OCB_ADRS(18)' J4-83 # IO_L21P_2_VREF_2 NET 'LTCHD_IACK_B' J4-80 # IO_L24N_2 NET 'OCB_ADRS(17)' J4-79 # IO_L24P_2 NET 'OCB_ADRS(16)' J4-78 # IO_L43N_2 NET 'LTCHD_AM(4)' J4-77 # IO_L43P_2 # Connect the clock line from the FPGA to the clock input # pins on these VME latches: NET 'VME_LTCH_CLK' J4-76 # IO_L45N_2 # Latch for VME "adrs type" information U301 NET 'OCB_ADRS(15)' J4-75 # IO_L45P_2_VREF_2 NET 'OCB_ADRS(7)' J4-56 # IO_L96N_2 NET 'OCB_ADRS(14)' J4-73 # IO_L46P_2 NET 'OCB_ADRS(6)' J4-58 # IO_L94N_2 NET 'OCB_ADRS(13)' J4-69 # IO_L49P_2 NET 'OCB_ADRS(5)' J4-62 # IO_L91N_2 NET 'OCB_ADRS(12)' J4-67 # IO_L51P_2_VREF_2 NET 'OCB_ADRS(4)' J4-64 # IO_L54N_2 NET 'OCB_ADRS(11)' J4-68 # IO_L51N_2 NET 'OCB_ADRS(3)' J4-63 # IO_L54P_2 NET 'OCB_ADRS(10)' J4-70 # IO_L49N_2 NET 'OCB_ADRS(2)' J4-61 # IO_L91P_2 NET 'OCB_ADRS(9)' J4-74 # IO_L46N_2 NET 'OCB_ADRS(1)' J4-57 # IO_L94P_2 NET 'OCB_ADRS(8)' J4-55 # IO_L96P_2 # VME Control & Address Signsl To & From U303 NET 'RCVD_GEO_B(0)' J1-9 # IO_L03P_1_VRN_1 NET 'RCVD_GEO_B(1)' J1-11 # IO_L04P_1_VREF_1 NET 'RCVD_GEO_B(2)' J1-15 # IO_L05P_1 NET 'RCVD_GEO_B(3)' J1-17 # IO_L21P_1 NET 'RCVD_GEO_B(4)' J1-23 # IO_L49P_1 NET 'DRV_DTACK_B' J1-3 # IO_L01P_1 NET 'RCVD_DS1_B' J1-5 # IO_L02P_1 NET 'RCVD_SYSRESET_B' J1-21 # IO_L22P_1 NET 'RCVD_AS_B' J1-31 # IO_L54P_1