# # This is a Key In NETs Template file for the # H-CLK card for HAWC # # LOWER GPIO NETs Template # ------------==========---====--========---------- # # # Original Rev. 22-Apr-2011 # Most Recent Rev. 19-Dec-2011 # # # This file includes all the Nets for the LOWER GPIO connector # section of the H-CLK card. # # The component reference designators in this section start at 1. # # This file contains nets for the following components for each "unit cell": # # K1 # C1 : C8 # U1 : U8 # # Channel # NET 'GPIO_K__PIN_1' K-1 U-6 #GPIO K Signal 0 Direct NET 'GPIO_K__PIN_2' K-2 U-5 #GPIO K Signal 0 Comp NET 'GPIO_K__PIN_3' K-3 U-8 #GPIO K Signal 1 Direct NET 'GPIO_K__PIN_4' K-4 U-7 #GPIO K Signal 1 Comp NET 'GPIO_K__PIN_5' K-5 U-8 #GPIO K Signal 2 Direct NET 'GPIO_K__PIN_6' K-6 U-7 #GPIO K Signal 2 Comp NET 'GPIO_K__PIN_7' K-7 U-6 #GPIO K Signal 3 Direct NET 'GPIO_K__PIN_8' K-8 U-5 #GPIO K Signal 3 Comp NET 'GPIO_K__PIN_9' K-9 U-6 #GPIO K Signal 4 Direct NET 'GPIO_K__PIN_10' K-10 U-5 #GPIO K Signal 4 Comp NET 'GPIO_K__PIN_11' K-11 U-8 #GPIO K Signal 5 Direct NET 'GPIO_K__PIN_12' K-12 U-7 #GPIO K Signal 5 Comp NET 'GPIO_K__PIN_13' K-13 U-8 #GPIO K Signal 6 Direct NET 'GPIO_K__PIN_14' K-14 U-7 #GPIO K Signal 6 Comp NET 'GPIO_K__PIN_15' K-15 U-6 #GPIO K Signal 7 Direct NET 'GPIO_K__PIN_16' K-16 U-5 #GPIO K Signal 7 Comp NET 'GPIO_K__PIN_17' K-17 U-6 #GPIO K Signal 8 Direct NET 'GPIO_K__PIN_18' K-18 U-5 #GPIO K Signal 8 Comp NET 'GPIO_K__PIN_19' K-19 U-8 #GPIO K Signal 9 Direct NET 'GPIO_K__PIN_20' K-20 U-7 #GPIO K Signal 9 Comp NET 'GPIO_K__PIN_21' K-21 U-8 #GPIO K Signal 10 Direct NET 'GPIO_K__PIN_22' K-22 U-7 #GPIO K Signal 10 Comp NET 'GPIO_K__PIN_23' K-23 U-6 #GPIO K Signal 11 Direct NET 'GPIO_K__PIN_24' K-24 U-5 #GPIO K Signal 11 Comp NET 'GPIO_K__PIN_25' K-25 U-6 #GPIO K Signal 12 Direct NET 'GPIO_K__PIN_26' K-26 U-5 #GPIO K Signal 12 Comp NET 'GPIO_K__PIN_27' K-27 U-8 #GPIO K Signal 13 Direct NET 'GPIO_K__PIN_28' K-28 U-7 #GPIO K Signal 13 Comp NET 'GPIO_K__PIN_29' K-29 U-8 #GPIO K Signal 14 Direct NET 'GPIO_K__PIN_30' K-30 U-7 #GPIO K Signal 14 Comp NET 'GPIO_K__PIN_31' K-31 U-6 #GPIO K Signal 15 Direct NET 'GPIO_K__PIN_32' K-32 U-5 #GPIO K Signal 15 Comp # Pins #33 and #34 are for the 40 MHz Clock signal: NET 'CLK_FO__DIR' K-33 NET 'CLK_FO__CMP' K-34 # Now connect the Power and Ground to each LVDS Driver/Receiver # chip and to its bypass capacitor from Vdd_Logic to Ground NET 'VDD_LOGIC' U-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U-4 # Ground connection NET 'VDD_LOGIC' C-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C-2 # Ground connection NET 'VDD_LOGIC' U-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U-4 # Ground connection NET 'VDD_LOGIC' C-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C-2 # Ground connection NET 'VDD_LOGIC' U-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U-4 # Ground connection NET 'VDD_LOGIC' C-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C-2 # Ground connection NET 'VDD_LOGIC' U-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U-4 # Ground connection NET 'VDD_LOGIC' C-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C-2 # Ground connection NET 'VDD_LOGIC' U-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U-4 # Ground connection NET 'VDD_LOGIC' C-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C-2 # Ground connection NET 'VDD_LOGIC' U-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U-4 # Ground connection NET 'VDD_LOGIC' C-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C-2 # Ground connection NET 'VDD_LOGIC' U-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U-4 # Ground connection NET 'VDD_LOGIC' C-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C-2 # Ground connection NET 'VDD_LOGIC' U-1 # Vdd power connection LVDS Driver/Receiver NET 'GROUND' U-4 # Ground connection NET 'VDD_LOGIC' C-1 # Vdd power connection ByPass Capacitor NET 'GROUND' C-2 # Ground connection