# # This is the Net 2 Resource file for the # # Miscellaneous J1 FSI Connections # ---------------------------------- # # # Original Rev. 15-Sept-2011 # Current Rev. 8-NOV-2011 # This file specifies what J1 FSI Resource is # connected to the Miscellaneous J1 nets. # # This file includes all the miscellaneous connections # to the J1 FSI connector to the MEZ-456, these include: # # Clock Signals, RS-232, LEDs, Pushbuttons, DeBug # 40 MHz Global Clock from the PLL to the FPGA # -------------------------------------------- NET 'CLK_40_DIR_FOR_FPGA' J1- # 40 MHz Clock to the FPGA DIR NET 'CLK_40_CMP_FOR_FPGA' J1- # 40 MHz Clock to the FPGA CMP # 10 MHz Global Clock from the GPS Receiver to the FPGA # ----------------------------------------------------- NET 'DRVN_10_MHZ_DIR' J1- # Recvd 10 MHz Driver Direct Out NET 'DRVN_10_MHZ_CMP' J1- # Recvd 10 MHz Driver Comp Out # 1 PPS from the GPS Receiver to the FPGA # ----------------------------------------- NET 'DRVN_1_PPS_DIR' J1- # Recvd 1 PPS Driver Direct Out NET 'DRVN_1_PPS_CMP' J1- # Recvd 1 PPS Driver Comp Out # External Signal from the Access Conn to Global Clock Net # --------------------------------------------------------- NET 'EXT_FPGA_CLK_BUF_OUT_DIR' J1- # BUFD Ext Signal DIR NET 'EXT_FPGA_CLK_BUF_OUT_CMP' J1- # BUFD Ext Signal CMP # Normal FPGA I/O Pin to the CMOS to LVDS Converter/Driver # and then to the Access Connector # ---------------------------------------------------------- NET 'FPGA_BUFD_LVDS_DRV_IN' J1- # FPGA I/O input to LVDS Converter # PLL Reference and PLL Feedback from the FPGA # to the PLL's LVDS Inputs NET 'PLL_REF_DIR' J1- # PLL Phase Comparator Reference DIR NET 'PLL_REF_CMP' J1- # PLL Phase Comparator Reference CMP NET 'PLL_FBK_DIR' J1- # PLL Phase Comparator Feedback DIR NET 'PLL_FBK_CMP' J1- # PLL Phase Comparator Feedback CMP # Connect the RS-232 Signals to/from GPS Receiver # ------------------------------------------------- NET 'SERIAL_TO_FPGA' J1- # Received GPS Serial to FPGA NET 'SERIAL_FROM_FPGA' J1- # Serial from H-Clk's FPGA to GPS # Connect the 6 Front Panel LEDs # -------------------------------- # FPGA Indicator LED_2 Left NET 'LED_2L_ON_B' J1- # LED 2 Left - pull low for ON # FPGA Indicator LED_2 Center NET 'LED_2C_ON_B' J1- # LED 2 Center - pull low for ON # FPGA Indicator LED_2 Right NET 'LED_2R_ON_B' J1- # LED 2 Right - pull low for ON # FPGA Indicator LED_1 Left NET 'LED_1L_ON_B' J1- # LED 1 Left - pull low for ON # FPGA Indicator LED_1 Center NET 'LED_1C_ON_B' J1- # LED 1 Center - pull low for ON # FPGA Indicator LED_1 Right NET 'LED_1R_ON_B' J1- # LED 1 Right - pull low for ON # Connect the Front Panel Pushbutton Switch # ------------------------------------------- # NET 'SWTCH_1_NC' J1- # S1 Normal Closed Contact NET 'SWTCH_1_NO' J1- # S1 Normal Open Contact # # DeBug Connections from MEZ-456 J1 Connector # to the DeBug Connector J5 # NET 'DEBUG_01' J1- # FPGA DeBug Signal 01 NET 'DEBUG_02' J1- # FPGA DeBug Signal 02 NET 'DEBUG_03' J1- # FPGA DeBug Signal 03 NET 'DEBUG_04' J1- # FPGA DeBug Signal 04 NET 'DEBUG_05' J1- # FPGA DeBug Signal 05 NET 'DEBUG_06' J1- # FPGA DeBug Signal 06 NET 'DEBUG_07' J1- # FPGA DeBug Signal 07 NET 'DEBUG_08' J1- # FPGA DeBug Signal 08 # # Un-Used FPGA I/O Pins on the J1 FSI Connector # # There are a total of 6 FPGA pins that are not used. # All 6 of these pins are on the J1 FSI connector. # It is easy to run 4 of the 6 spare FPGA signals to vias. # The signal assignments for these 4 spare FPGA # signal vias are made here. These are vias V13:V16 # NET 'SPARE_SIG_V13' J1- # Spare FPGA Signal to V13 NET 'SPARE_SIG_V14' J1- # Spare FPGA Signal to V14 NET 'SPARE_SIG_V15' J1- # Spare FPGA Signal to V15 NET 'SPARE_SIG_V16' J1- # Spare FPGA Signal to V16