#
#           This is the Net 2 Resource file for the
#
#               On Card Address and Control Bus
#                                to
#                  J1 and J4 FSI Connections
#          -----------------------------------------
#
#
#                                                Original Rev. 16-Sept-2011
#                                                 Current Rev.   7-NOV-2011


#  This file specifies what  J1 or J4 FSI Resource  is
#  connected to which On Card Address and Control Bus line.

#  This file includes the connections for all the VME P1 backplane
#  Address and Control type signals from their buffers/latches, i.e.
#  U301, U302, and U303  over to the J1 and J4 connectors for
#  the MEZ-456.

#  The routing of these signals into the FPGA on the MEZ-456 is
#  picked to make the trace layout as easy as possible on the
#  H-Clk pcb.

#  First take care of the 31 VME backplane signals that are received
#  and latched by U301 and U302.


#  Latch for VME "adrs type" information  U302

NET 'LTCHD_AM(5)'      J4-<IO_L01P_2>          # U302-2    1Q0
NET 'LTCHD_WRITE_B'    J4-<IO_L01N_2>          # U302-3    1Q1
NET 'OCB_ADRS(23)'     J4-<IO_L03P_2_VREF_2>   # U302-5    1Q2
NET 'OCB_ADRS(22)'     J4-<IO_L03N_2>          # U302-6    1Q3

NET 'LTCHD_AM(0)'      J4-<IO_L04P_2>          # U302-8    1Q4
NET 'OCB_ADRS(21)'     J4-<IO_L04N_2>          # U302-9    1Q5
NET 'LTCHD_AM(1)'      J4-<IO_L06P_2>          # U302-11   1Q6
NET 'OCB_ADRS(20)'     J4-<IO_L06N_2>          # U302-12   1Q7

NET 'LTCHD_AM(2)'      J4-<IO_L19N_2>          # U302-13   2Q0
NET 'OCB_ADRS(19)'     J4-<IO_L19P_2>          # U302-14   2Q1
NET 'LTCHD_AM(3)'      J4-<IO_L21N_2>          # U302-16   2Q2
NET 'OCB_ADRS(18)'     J4-<IO_L21P_2_VREF_2>   # U302-17   2Q3

NET 'LTCHD_IACK_B'     J4-<IO_L24N_2>          # U302-19   2Q4
NET 'OCB_ADRS(17)'     J4-<IO_L24P_2>          # U302-20   2Q5
NET 'OCB_ADRS(16)'     J4-<IO_L43N_2>          # U302-22   2Q6
NET 'LTCHD_AM(4)'      J4-<IO_L43P_2>          # U302-23   2Q7



#  Connect the clock line from the FPGA to the clock input
#  pins on these VME latches:

NET 'VME_LTCH_CLK'     J4-<IO_L45N_2>    # U301-25, U301-48, U302-25, U302-48



#  Latch for VME "adrs type" information  U301

NET 'OCB_ADRS(15)'     J4-<IO_L45P_2_VREF_2>   # U301-2   1Q0
NET 'OCB_ADRS(7)'      J4-<IO_L96N_2>          # U301-3   1Q1
NET 'OCB_ADRS(14)'     J4-<IO_L46P_2>          # U301-5   1Q2
NET 'OCB_ADRS(6)'      J4-<IO_L94N_2>          # U301-6   1Q3

NET 'OCB_ADRS(13)'     J4-<IO_L49P_2>          # U301-8   1Q4
NET 'OCB_ADRS(5)'      J4-<IO_L91N_2>          # U301-9   1Q5
NET 'OCB_ADRS(12)'     J4-<IO_L51P_2_VREF_2>   # U301-11  1Q6
NET 'OCB_ADRS(4)'      J4-<IO_L54N_2>          # U301-12  1Q7

NET 'OCB_ADRS(11)'     J4-<IO_L51N_2>          # U301-13  2Q0
NET 'OCB_ADRS(3)'      J4-<IO_L54P_2>          # U301-14  2Q1
NET 'OCB_ADRS(10)'     J4-<IO_L49N_2>          # U301-16  2Q2
NET 'OCB_ADRS(2)'      J4-<IO_L91P_2>          # U301-17  2Q3

NET 'OCB_ADRS(9)'      J4-<IO_L46N_2>          # U301-19  2Q4
NET 'OCB_ADRS(1)'      J4-<IO_L94P_2>          # U301-20  2Q5
NET 'OCB_ADRS(8)'      J4-<IO_L96P_2>          # U301-22  2Q6



#  VME Control & Address Signsl  To & From U303

NET 'RCVD_GEO_B(0)'  J1-<IO_L03P_1_VRN_1>   # U303-38  The received GEO_B(0) signal
NET 'RCVD_GEO_B(1)'  J1-<IO_L04P_1_VREF_1>  # U303-40  The received GEO_B(1) signal
NET 'RCVD_GEO_B(2)'  J1-<IO_L05P_1>         # U303-41  The received GEO_B(2) signal
NET 'RCVD_GEO_B(3)'  J1-<IO_L21P_1>         # U303-43  The received GEO_B(3) signal
NET 'RCVD_GEO_B(4)'  J1-<IO_L49P_1>         # U303-46  The received GEO_B(4) signal

NET 'DRV_DTACK_B'      J1-<IO_L01P_1>   # U303-25  Connect the DRV_DTACK_B signal

NET 'RCVD_DS1_B'       J1-<IO_L02P_1>   # U303-37  The received VME_DS1_B signal

NET 'RCVD_SYSRESET_B'  J1-<IO_L22P_1>   # U103-44  The received SYSRESET_B signal

NET 'RCVD_AS_B'        J1-<IO_L54P_1>   # U103-47  The received Adrs_Strb_B signal