# # This is the Net 2 Resource file for the # # On Card Data Bus to J1 FSI Connections # ------------------------------------------ # # # Original Rev. 16-Sept-2011 # Current Rev. 7-Nov-2011 # This file specifies what J1 FSI Resource is # connected to which VME Data Bus receiver/driver. # This file includes the connections for all the VME P1 backplane # Data Bus signals from their buffer, i.e. U304, over to the J1 # connector for the MEZ-456. # The routing of these signals into the FPGA on the MEZ-456 is # picked to make the trace layout as easy as possible on the # H-Clk pcb. # Connect the 16 data lines from the "A" side of the U304 # 74LVT16245B Transceiver to J1 pins on the MEZ-456. NET 'OCB_DATA(7)' J1- # U304-47 1A0 NET 'OCB_DATA(15)' J1- # U304-46 1A1 NET 'OCB_DATA(6)' J1- # U304-44 1A2 NET 'OCB_DATA(14)' J1- # U304-43 1A3 NET 'OCB_DATA(5)' J1- # U304-41 1A4 NET 'OCB_DATA(13)' J1- # U304-40 1A5 NET 'OCB_DATA(4)' J1- # U304-38 1A6 NET 'OCB_DATA(12)' J1- # U304-37 1A7 NET 'OCB_DATA(3)' J1- # U304-36 2A0 NET 'OCB_DATA(11)' J1- # U304-35 2A1 NET 'OCB_DATA(2)' J1- # U304-33 2A2 NET 'OCB_DATA(10)' J1- # U304-32 2A3 NET 'OCB_DATA(1)' J1- # U304-30 2A4 NET 'OCB_DATA(9)' J1- # U304-29 2A5 NET 'OCB_DATA(0)' J1- # U304-27 2A6 NET 'OCB_DATA(8)' J1- # U304-26 2A7 # Connection from the MEZ-456 FPGA to the two Direction # pins of the 74LVT16245B VME Data Bus Transceiver. # When Low -> B input A output i.e. VME Write # When High -> A input B output i.e. VME Read NET 'DATA_BUF_DIR' J1- # U304-1 U304-24 # Connection from the MEZ-456 FPGA to the two Output Enable bar # pins of the 74LVT16245B VME Data Bus Transceiver. # When high -> neither buffer output is enabled. NET 'DATA_BUF_ENB_B' J1- # U304-25 U304-48