# # This is the Net 2 Resource file for the # # K1 to J2 FSI Connections # ---==------------------------- # # # Original Rev. 8-Sept-2011 # Current Rev. 19-Dec-2011 # This file specifies what J2 FSI Resource is # connected to each K1 GPIO driver or receiver. # -- NET 'GPIO_K_1_SIGNAL_0' U1-3 J2- #GPIO K1 Signal 0 NET 'GPIO_K_1_SIGNAL_1' U1-2 J2- #GPIO K1 Signal 1 NET 'GPIO_K_1_SIGNAL_2' U2-2 J2- #GPIO K1 Signal 2 NET 'GPIO_K_1_SIGNAL_3' U2-3 J2- #GPIO K1 Signal 3 NET 'GPIO_K_1_SIGNAL_4' U3-3 J2- #GPIO K1 Signal 4 NET 'GPIO_K_1_SIGNAL_5' U3-2 J2- #GPIO K1 Signal 5 NET 'GPIO_K_1_SIGNAL_6' U4-2 J2- #GPIO K1 Signal 6 NET 'GPIO_K_1_SIGNAL_7' U4-3 J2- #GPIO K1 Signal 7 NET 'GPIO_K_1_SIGNAL_8' U5-3 J2- #GPIO K1 Signal 8 NET 'GPIO_K_1_SIGNAL_9' U5-2 J2- #GPIO K1 Signal 9 NET 'GPIO_K_1_SIGNAL_10' U6-2 J2- #GPIO K1 Signal 10 NET 'GPIO_K_1_SIGNAL_11' U6-3 J2- #GPIO K1 Signal 11 NET 'GPIO_K_1_SIGNAL_12' U7-3 J2- #GPIO K1 Signal 12 NET 'GPIO_K_1_SIGNAL_13' U7-2 J2- #GPIO K1 Signal 13 NET 'GPIO_K_1_SIGNAL_14' U8-2 J2- #GPIO K1 Signal 14 NET 'GPIO_K_1_SIGNAL_15' U8-3 J2- #GPIO K1 Signal 15 # # This is the Net 2 Resource file for the # # K2 to J2 FSI Connections # ---==------------------------- # # # Original Rev. 8-Sept-2011 # Current Rev. 19-Dec-2011 # This file specifies what J2 FSI Resource is # connected to each K2 GPIO driver or receiver. # -- NET 'GPIO_K_2_SIGNAL_0' U9-3 J2- #GPIO K2 Signal 0 NET 'GPIO_K_2_SIGNAL_1' U9-2 J2- #GPIO K2 Signal 1 NET 'GPIO_K_2_SIGNAL_2' U10-2 J2- #GPIO K2 Signal 2 NET 'GPIO_K_2_SIGNAL_3' U10-3 J2- #GPIO K2 Signal 3 NET 'GPIO_K_2_SIGNAL_4' U11-3 J2- #GPIO K2 Signal 4 NET 'GPIO_K_2_SIGNAL_5' U11-2 J2- #GPIO K2 Signal 5 NET 'GPIO_K_2_SIGNAL_6' U12-2 J2- #GPIO K2 Signal 6 NET 'GPIO_K_2_SIGNAL_7' U12-3 J2- #GPIO K2 Signal 7 NET 'GPIO_K_2_SIGNAL_8' U13-3 J2- #GPIO K2 Signal 8 NET 'GPIO_K_2_SIGNAL_9' U13-2 J2- #GPIO K2 Signal 9 NET 'GPIO_K_2_SIGNAL_10' U14-2 J2- #GPIO K2 Signal 10 NET 'GPIO_K_2_SIGNAL_11' U14-3 J2- #GPIO K2 Signal 11 NET 'GPIO_K_2_SIGNAL_12' U15-3 J2- #GPIO K2 Signal 12 NET 'GPIO_K_2_SIGNAL_13' U15-2 J2- #GPIO K2 Signal 13 NET 'GPIO_K_2_SIGNAL_14' U16-2 J2- #GPIO K2 Signal 14 NET 'GPIO_K_2_SIGNAL_15' U16-3 J2- #GPIO K2 Signal 15 # # This is the Net 2 Resource file for the # # K3 to J2 FSI Connections # ---==------------------------- # # # Original Rev. 9-Sept-2011 # Current Rev. 19-Dec-2011 # This file specifies what J2 FSI Resource is # connected to each K3 GPIO driver or receiver. # -- NET 'GPIO_K_3_SIGNAL_0' U17-3 J2- #GPIO K3 Signal 0 NET 'GPIO_K_3_SIGNAL_1' U17-2 J2- #GPIO K3 Signal 1 NET 'GPIO_K_3_SIGNAL_2' U18-2 J2- #GPIO K3 Signal 2 NET 'GPIO_K_3_SIGNAL_3' U18-3 J2- #GPIO K3 Signal 3 NET 'GPIO_K_3_SIGNAL_4' U19-3 J2- #GPIO K3 Signal 4 NET 'GPIO_K_3_SIGNAL_5' U19-2 J2- #GPIO K3 Signal 5 NET 'GPIO_K_3_SIGNAL_6' U20-2 J2- #GPIO K3 Signal 6 NET 'GPIO_K_3_SIGNAL_7' U20-3 J2- #GPIO K3 Signal 7 NET 'GPIO_K_3_SIGNAL_8' U21-3 J2- #GPIO K3 Signal 8 NET 'GPIO_K_3_SIGNAL_9' U21-2 J2- #GPIO K3 Signal 9 NET 'GPIO_K_3_SIGNAL_10' U22-2 J2- #GPIO K3 Signal 10 NET 'GPIO_K_3_SIGNAL_11' U22-3 J2- #GPIO K3 Signal 11 NET 'GPIO_K_3_SIGNAL_12' U23-3 J2- #GPIO K3 Signal 12 NET 'GPIO_K_3_SIGNAL_13' U23-2 J2- #GPIO K3 Signal 13 NET 'GPIO_K_3_SIGNAL_14' U24-2 J2- #GPIO K3 Signal 14 NET 'GPIO_K_3_SIGNAL_15' U24-3 J2- #GPIO K3 Signal 15 # # This is the Net 2 Resource file for the # # K4 to J2 FSI Connections # ---==------------------------- # # # Original Rev. 9-Sept-2011 # Current Rev. 19-Dec-2011 # This file specifies what J2 FSI Resource is # connected to each K4 GPIO driver or receiver. # -- NET 'GPIO_K_4_SIGNAL_0' U25-3 J2- #GPIO K4 Signal 0 NET 'GPIO_K_4_SIGNAL_1' U25-2 J2- #GPIO K4 Signal 1 NET 'GPIO_K_4_SIGNAL_2' U26-2 J2- #GPIO K4 Signal 2 NET 'GPIO_K_4_SIGNAL_3' U26-3 J2- #GPIO K4 Signal 3 NET 'GPIO_K_4_SIGNAL_4' U27-3 J2- #GPIO K4 Signal 4 NET 'GPIO_K_4_SIGNAL_5' U27-2 J2- #GPIO K4 Signal 5 NET 'GPIO_K_4_SIGNAL_6' U28-2 J2- #GPIO K4 Signal 6 NET 'GPIO_K_4_SIGNAL_7' U28-3 J2- #GPIO K4 Signal 7 NET 'GPIO_K_4_SIGNAL_8' U29-3 J2- #GPIO K4 Signal 8 NET 'GPIO_K_4_SIGNAL_9' U29-2 J2- #GPIO K4 Signal 9 NET 'GPIO_K_4_SIGNAL_10' U30-2 J2- #GPIO K4 Signal 10 NET 'GPIO_K_4_SIGNAL_11' U30-3 J2- #GPIO K4 Signal 11 NET 'GPIO_K_4_SIGNAL_12' U31-3 J2- #GPIO K4 Signal 12 NET 'GPIO_K_4_SIGNAL_13' U31-2 J2- #GPIO K4 Signal 13 NET 'GPIO_K_4_SIGNAL_14' U32-2 J2- #GPIO K4 Signal 14 NET 'GPIO_K_4_SIGNAL_15' U32-3 J2- #GPIO K4 Signal 15 # # This is the Net 2 Resource file for the # # K5 to J3 FSI Connections # ---==------------------------- # # # Original Rev. 9-Sept-2011 # Current Rev. 19-Dec-2011 # This file specifies what J3 FSI Resource is # connected to each K5 GPIO driver or receiver. # -- NET 'GPIO_K_5_SIGNAL_0' U33-3 J3- #GPIO K5 Signal 0 NET 'GPIO_K_5_SIGNAL_1' U33-2 J3- #GPIO K5 Signal 1 NET 'GPIO_K_5_SIGNAL_2' U34-2 J3- #GPIO K5 Signal 2 NET 'GPIO_K_5_SIGNAL_3' U34-3 J3- #GPIO K5 Signal 3 NET 'GPIO_K_5_SIGNAL_4' U35-3 J3- #GPIO K5 Signal 4 NET 'GPIO_K_5_SIGNAL_5' U35-2 J3- #GPIO K5 Signal 5 NET 'GPIO_K_5_SIGNAL_6' U36-2 J3- #GPIO K5 Signal 6 NET 'GPIO_K_5_SIGNAL_7' U36-3 J3- #GPIO K5 Signal 7 NET 'GPIO_K_5_SIGNAL_8' U37-3 J3- #GPIO K5 Signal 8 NET 'GPIO_K_5_SIGNAL_9' U37-2 J3- #GPIO K5 Signal 9 NET 'GPIO_K_5_SIGNAL_10' U38-2 J3- #GPIO K5 Signal 10 NET 'GPIO_K_5_SIGNAL_11' U38-3 J3- #GPIO K5 Signal 11 NET 'GPIO_K_5_SIGNAL_12' U39-3 J3- #GPIO K5 Signal 12 NET 'GPIO_K_5_SIGNAL_13' U39-2 J3- #GPIO K5 Signal 13 NET 'GPIO_K_5_SIGNAL_14' U40-2 J3- #GPIO K5 Signal 14 NET 'GPIO_K_5_SIGNAL_15' U40-3 J3- #GPIO K5 Signal 15 # # This is the Net 2 Resource file for the # # K6 to J3 FSI Connections # ---==------------------------- # # # Original Rev. 9-Sept-2011 # Current Rev. 19-Dec-2011 # This file specifies what J3 FSI Resource is # connected to each K6 GPIO driver or receiver. # -- NET 'GPIO_K_6_SIGNAL_0' U41-3 J3- #GPIO K6 Signal 0 NET 'GPIO_K_6_SIGNAL_1' U41-2 J3- #GPIO K6 Signal 1 NET 'GPIO_K_6_SIGNAL_2' U42-2 J3- #GPIO K6 Signal 2 NET 'GPIO_K_6_SIGNAL_3' U42-3 J3- #GPIO K6 Signal 3 NET 'GPIO_K_6_SIGNAL_4' U43-3 J3- #GPIO K6 Signal 4 NET 'GPIO_K_6_SIGNAL_5' U43-2 J3- #GPIO K6 Signal 5 NET 'GPIO_K_6_SIGNAL_6' U44-2 J3- #GPIO K6 Signal 6 NET 'GPIO_K_6_SIGNAL_7' U44-3 J3- #GPIO K6 Signal 7 NET 'GPIO_K_6_SIGNAL_8' U45-3 J3- #GPIO K6 Signal 8 NET 'GPIO_K_6_SIGNAL_9' U45-2 J3- #GPIO K6 Signal 9 NET 'GPIO_K_6_SIGNAL_10' U46-2 J3- #GPIO K6 Signal 10 NET 'GPIO_K_6_SIGNAL_11' U46-3 J3- #GPIO K6 Signal 11 NET 'GPIO_K_6_SIGNAL_12' U47-3 J3- #GPIO K6 Signal 12 NET 'GPIO_K_6_SIGNAL_13' U47-2 J3- #GPIO K6 Signal 13 NET 'GPIO_K_6_SIGNAL_14' U48-2 J3- #GPIO K6 Signal 14 NET 'GPIO_K_6_SIGNAL_15' U48-3 J3- #GPIO K6 Signal 15 # # This is the Net 2 Resource file for the # # K7 to J3 FSI Connections # ---==------------------------- # # # Original Rev. 9-Sept-2011 # Current Rev. 19-Dec-2011 # This file specifies what J3 FSI Resource is # connected to each K7 GPIO driver or receiver. # -- NET 'GPIO_K_7_SIGNAL_0' U49-3 J3- #GPIO K7 Signal 0 NET 'GPIO_K_7_SIGNAL_1' U49-2 J3- #GPIO K7 Signal 1 NET 'GPIO_K_7_SIGNAL_2' U50-2 J3- #GPIO K7 Signal 2 NET 'GPIO_K_7_SIGNAL_3' U50-3 J3- #GPIO K7 Signal 3 NET 'GPIO_K_7_SIGNAL_4' U51-3 J3- #GPIO K7 Signal 4 NET 'GPIO_K_7_SIGNAL_5' U51-2 J3- #GPIO K7 Signal 5 NET 'GPIO_K_7_SIGNAL_6' U52-2 J3- #GPIO K7 Signal 6 NET 'GPIO_K_7_SIGNAL_7' U52-3 J3- #GPIO K7 Signal 7 NET 'GPIO_K_7_SIGNAL_8' U53-3 J3- #GPIO K7 Signal 8 NET 'GPIO_K_7_SIGNAL_9' U53-2 J3- #GPIO K7 Signal 9 NET 'GPIO_K_7_SIGNAL_10' U54-2 J3- #GPIO K7 Signal 10 NET 'GPIO_K_7_SIGNAL_11' U54-3 J3- #GPIO K7 Signal 11 NET 'GPIO_K_7_SIGNAL_12' U55-3 J3- #GPIO K7 Signal 12 NET 'GPIO_K_7_SIGNAL_13' U55-2 J3- #GPIO K7 Signal 13 NET 'GPIO_K_7_SIGNAL_14' U56-2 J3- #GPIO K7 Signal 14 NET 'GPIO_K_7_SIGNAL_15' U56-3 J3- #GPIO K7 Signal 15 # # This is the Net 2 Resource file for the # # K8 to J3 FSI Connections # ---==------------------------- # # # Original Rev. 9-Sept-2011 # Current Rev. 19-Dec-2011 # This file specifies what J3 FSI Resource is # connected to each K8 GPIO driver or receiver. # -- NET 'GPIO_K_8_SIGNAL_0' U57-3 J3- #GPIO K8 Signal 0 NET 'GPIO_K_8_SIGNAL_1' U57-2 J3- #GPIO K8 Signal 1 NET 'GPIO_K_8_SIGNAL_2' U58-2 J3- #GPIO K8 Signal 2 NET 'GPIO_K_8_SIGNAL_3' U58-3 J3- #GPIO K8 Signal 3 NET 'GPIO_K_8_SIGNAL_4' U59-3 J3- #GPIO K8 Signal 4 NET 'GPIO_K_8_SIGNAL_5' U59-2 J3- #GPIO K8 Signal 5 NET 'GPIO_K_8_SIGNAL_6' U60-2 J3- #GPIO K8 Signal 6 NET 'GPIO_K_8_SIGNAL_7' U60-3 J3- #GPIO K8 Signal 7 NET 'GPIO_K_8_SIGNAL_8' U61-3 J3- #GPIO K8 Signal 8 NET 'GPIO_K_8_SIGNAL_9' U61-2 J3- #GPIO K8 Signal 9 NET 'GPIO_K_8_SIGNAL_10' U62-2 J3- #GPIO K8 Signal 10 NET 'GPIO_K_8_SIGNAL_11' U62-3 J3- #GPIO K8 Signal 11 NET 'GPIO_K_8_SIGNAL_12' U63-3 J3- #GPIO K8 Signal 12 NET 'GPIO_K_8_SIGNAL_13' U63-2 J3- #GPIO K8 Signal 13 NET 'GPIO_K_8_SIGNAL_14' U64-2 J3- #GPIO K8 Signal 14 NET 'GPIO_K_8_SIGNAL_15' U64-3 J3- #GPIO K8 Signal 15 # # This is the Net 2 Resource file for the # # K9 to J4 FSI Connections # ---==------------------------- # # # Original Rev. 14-Sept-2011 # Current Rev. 19-Dec-2011 # This file specifies what J4 FSI Resource is # connected to each K9 GPIO driver or receiver. # -- NET 'GPIO_K_9_SIGNAL_0' U65-3 J4- #GPIO K9 Signal 0 NET 'GPIO_K_9_SIGNAL_1' U65-2 J4- #GPIO K9 Signal 1 NET 'GPIO_K_9_SIGNAL_2' U66-2 J4- #GPIO K9 Signal 2 NET 'GPIO_K_9_SIGNAL_3' U66-3 J4- #GPIO K9 Signal 3 NET 'GPIO_K_9_SIGNAL_4' U67-3 J4- #GPIO K9 Signal 4 NET 'GPIO_K_9_SIGNAL_5' U67-2 J4- #GPIO K9 Signal 5 NET 'GPIO_K_9_SIGNAL_6' U68-2 J4- #GPIO K9 Signal 6 NET 'GPIO_K_9_SIGNAL_7' U68-3 J4- #GPIO K9 Signal 7 NET 'GPIO_K_9_SIGNAL_8' U69-3 J4- #GPIO K9 Signal 8 NET 'GPIO_K_9_SIGNAL_9' U69-2 J4- #GPIO K9 Signal 9 NET 'GPIO_K_9_SIGNAL_10' U70-2 J4- #GPIO K9 Signal 10 NET 'GPIO_K_9_SIGNAL_11' U70-3 J4- #GPIO K9 Signal 11 NET 'GPIO_K_9_SIGNAL_12' U71-3 J4- #GPIO K9 Signal 12 NET 'GPIO_K_9_SIGNAL_13' U71-2 J4- #GPIO K9 Signal 13 NET 'GPIO_K_9_SIGNAL_14' U72-2 J4- #GPIO K9 Signal 14 NET 'GPIO_K_9_SIGNAL_15' U72-3 J4- #GPIO K9 Signal 15 # # This is the Net 2 Resource file for the # # K10 to J4 FSI Connections # ---===------------------------- # # # Original Rev. 14-Sept-2011 # Current Rev. 19-Dec-2011 # This file specifies what J4 FSI Resource is # connected to each K10 GPIO driver or receiver. # --- NET 'GPIO_K_10_SIGNAL_0' U73-3 J4- #GPIO K9 Signal 0 NET 'GPIO_K_10_SIGNAL_1' U73-2 J4- #GPIO K9 Signal 1 NET 'GPIO_K_10_SIGNAL_2' U74-2 J4- #GPIO K9 Signal 2 NET 'GPIO_K_10_SIGNAL_3' U74-3 J4- #GPIO K9 Signal 3 NET 'GPIO_K_10_SIGNAL_4' U75-3 J4- #GPIO K9 Signal 4 NET 'GPIO_K_10_SIGNAL_5' U75-2 J4- #GPIO K9 Signal 5 NET 'GPIO_K_10_SIGNAL_6' U76-2 J4- #GPIO K9 Signal 6 NET 'GPIO_K_10_SIGNAL_7' U76-3 J4- #GPIO K9 Signal 7 NET 'GPIO_K_10_SIGNAL_8' U77-3 J4- #GPIO K9 Signal 8 NET 'GPIO_K_10_SIGNAL_9' U77-2 J4- #GPIO K9 Signal 9 NET 'GPIO_K_10_SIGNAL_10' U78-2 J4- #GPIO K9 Signal 10 NET 'GPIO_K_10_SIGNAL_11' U78-3 J4- #GPIO K9 Signal 11 NET 'GPIO_K_10_SIGNAL_12' U79-3 J4- #GPIO K9 Signal 12 NET 'GPIO_K_10_SIGNAL_13' U79-2 J4- #GPIO K9 Signal 13 NET 'GPIO_K_10_SIGNAL_14' U80-2 J4- #GPIO K9 Signal 14 NET 'GPIO_K_10_SIGNAL_15' U80-3 J4- #GPIO K9 Signal 15 # # This is the Net 2 Resource file for the # # Miscellaneous J1 FSI Connections # ---------------------------------- # # # Original Rev. 15-Sept-2011 # Current Rev. 8-NOV-2011 # This file specifies what J1 FSI Resource is # connected to the Miscellaneous J1 nets. # # This file includes all the miscellaneous connections # to the J1 FSI connector to the MEZ-456, these include: # # Clock Signals, RS-232, LEDs, Pushbuttons, DeBug # 40 MHz Global Clock from the PLL to the FPGA # -------------------------------------------- NET 'CLK_40_DIR_FOR_FPGA' J1- # 40 MHz Clock to the FPGA DIR NET 'CLK_40_CMP_FOR_FPGA' J1- # 40 MHz Clock to the FPGA CMP # 10 MHz Global Clock from the GPS Receiver to the FPGA # ----------------------------------------------------- NET 'DRVN_10_MHZ_DIR' J1- # Recvd 10 MHz Driver Direct Out NET 'DRVN_10_MHZ_CMP' J1- # Recvd 10 MHz Driver Comp Out # 1 PPS from the GPS Receiver to the FPGA # ----------------------------------------- NET 'DRVN_1_PPS_DIR' J1- # Recvd 1 PPS Driver Direct Out NET 'DRVN_1_PPS_CMP' J1- # Recvd 1 PPS Driver Comp Out # External Signal from the Access Conn to Global Clock Net # --------------------------------------------------------- NET 'EXT_FPGA_CLK_BUF_OUT_DIR' J1- # BUFD Ext Signal DIR NET 'EXT_FPGA_CLK_BUF_OUT_CMP' J1- # BUFD Ext Signal CMP # Normal FPGA I/O Pin to the CMOS to LVDS Converter/Driver # and then to the Access Connector # ---------------------------------------------------------- NET 'FPGA_BUFD_LVDS_DRV_IN' J1- # FPGA I/O input to LVDS Converter # PLL Reference and PLL Feedback from the FPGA # to the PLL's LVDS Inputs NET 'PLL_REF_DIR' J1- # PLL Phase Comparator Reference DIR NET 'PLL_REF_CMP' J1- # PLL Phase Comparator Reference CMP NET 'PLL_FBK_DIR' J1- # PLL Phase Comparator Feedback DIR NET 'PLL_FBK_CMP' J1- # PLL Phase Comparator Feedback CMP # Connect the RS-232 Signals to/from GPS Receiver # ------------------------------------------------- NET 'SERIAL_TO_FPGA' J1- # Received GPS Serial to FPGA NET 'SERIAL_FROM_FPGA' J1- # Serial from H-Clk's FPGA to GPS # Connect the 6 Front Panel LEDs # -------------------------------- # FPGA Indicator LED_2 Left NET 'LED_2L_ON_B' J1- # LED 2 Left - pull low for ON # FPGA Indicator LED_2 Center NET 'LED_2C_ON_B' J1- # LED 2 Center - pull low for ON # FPGA Indicator LED_2 Right NET 'LED_2R_ON_B' J1- # LED 2 Right - pull low for ON # FPGA Indicator LED_1 Left NET 'LED_1L_ON_B' J1- # LED 1 Left - pull low for ON # FPGA Indicator LED_1 Center NET 'LED_1C_ON_B' J1- # LED 1 Center - pull low for ON # FPGA Indicator LED_1 Right NET 'LED_1R_ON_B' J1- # LED 1 Right - pull low for ON # Connect the Front Panel Pushbutton Switch # ------------------------------------------- # NET 'SWTCH_1_NC' J1- # S1 Normal Closed Contact NET 'SWTCH_1_NO' J1- # S1 Normal Open Contact # # DeBug Connections from MEZ-456 J1 Connector # to the DeBug Connector J5 # NET 'DEBUG_01' J1- # FPGA DeBug Signal 01 NET 'DEBUG_02' J1- # FPGA DeBug Signal 02 NET 'DEBUG_03' J1- # FPGA DeBug Signal 03 NET 'DEBUG_04' J1- # FPGA DeBug Signal 04 NET 'DEBUG_05' J1- # FPGA DeBug Signal 05 NET 'DEBUG_06' J1- # FPGA DeBug Signal 06 NET 'DEBUG_07' J1- # FPGA DeBug Signal 07 NET 'DEBUG_08' J1- # FPGA DeBug Signal 08 # # Un-Used FPGA I/O Pins on the J1 FSI Connector # # There are a total of 6 FPGA pins that are not used. # All 6 of these pins are on the J1 FSI connector. # It is easy to run 4 of the 6 spare FPGA signals to vias. # The signal assignments for these 4 spare FPGA # signal vias are made here. These are vias V13:V16 # NET 'SPARE_SIG_V13' J1- # Spare FPGA Signal to V13 NET 'SPARE_SIG_V14' J1- # Spare FPGA Signal to V14 NET 'SPARE_SIG_V15' J1- # Spare FPGA Signal to V15 NET 'SPARE_SIG_V16' J1- # Spare FPGA Signal to V16 # # This is the Net 2 Resource file for the # # On Card Data Bus to J1 FSI Connections # ------------------------------------------ # # # Original Rev. 16-Sept-2011 # Current Rev. 7-Nov-2011 # This file specifies what J1 FSI Resource is # connected to which VME Data Bus receiver/driver. # This file includes the connections for all the VME P1 backplane # Data Bus signals from their buffer, i.e. U304, over to the J1 # connector for the MEZ-456. # The routing of these signals into the FPGA on the MEZ-456 is # picked to make the trace layout as easy as possible on the # H-Clk pcb. # Connect the 16 data lines from the "A" side of the U304 # 74LVT16245B Transceiver to J1 pins on the MEZ-456. NET 'OCB_DATA(7)' J1- # U304-47 1A0 NET 'OCB_DATA(15)' J1- # U304-46 1A1 NET 'OCB_DATA(6)' J1- # U304-44 1A2 NET 'OCB_DATA(14)' J1- # U304-43 1A3 NET 'OCB_DATA(5)' J1- # U304-41 1A4 NET 'OCB_DATA(13)' J1- # U304-40 1A5 NET 'OCB_DATA(4)' J1- # U304-38 1A6 NET 'OCB_DATA(12)' J1- # U304-37 1A7 NET 'OCB_DATA(3)' J1- # U304-36 2A0 NET 'OCB_DATA(11)' J1- # U304-35 2A1 NET 'OCB_DATA(2)' J1- # U304-33 2A2 NET 'OCB_DATA(10)' J1- # U304-32 2A3 NET 'OCB_DATA(1)' J1- # U304-30 2A4 NET 'OCB_DATA(9)' J1- # U304-29 2A5 NET 'OCB_DATA(0)' J1- # U304-27 2A6 NET 'OCB_DATA(8)' J1- # U304-26 2A7 # Connection from the MEZ-456 FPGA to the two Direction # pins of the 74LVT16245B VME Data Bus Transceiver. # When Low -> B input A output i.e. VME Write # When High -> A input B output i.e. VME Read NET 'DATA_BUF_DIR' J1- # U304-1 U304-24 # Connection from the MEZ-456 FPGA to the two Output Enable bar # pins of the 74LVT16245B VME Data Bus Transceiver. # When high -> neither buffer output is enabled. NET 'DATA_BUF_ENB_B' J1- # U304-25 U304-48 # # This is the Net 2 Resource file for the # # On Card Address and Control Bus # to # J1 and J4 FSI Connections # ----------------------------------------- # # # Original Rev. 16-Sept-2011 # Current Rev. 7-NOV-2011 # This file specifies what J1 or J4 FSI Resource is # connected to which On Card Address and Control Bus line. # This file includes the connections for all the VME P1 backplane # Address and Control type signals from their buffers/latches, i.e. # U301, U302, and U303 over to the J1 and J4 connectors for # the MEZ-456. # The routing of these signals into the FPGA on the MEZ-456 is # picked to make the trace layout as easy as possible on the # H-Clk pcb. # First take care of the 31 VME backplane signals that are received # and latched by U301 and U302. # Latch for VME "adrs type" information U302 NET 'LTCHD_AM(5)' J4- # U302-2 1Q0 NET 'LTCHD_WRITE_B' J4- # U302-3 1Q1 NET 'OCB_ADRS(23)' J4- # U302-5 1Q2 NET 'OCB_ADRS(22)' J4- # U302-6 1Q3 NET 'LTCHD_AM(0)' J4- # U302-8 1Q4 NET 'OCB_ADRS(21)' J4- # U302-9 1Q5 NET 'LTCHD_AM(1)' J4- # U302-11 1Q6 NET 'OCB_ADRS(20)' J4- # U302-12 1Q7 NET 'LTCHD_AM(2)' J4- # U302-13 2Q0 NET 'OCB_ADRS(19)' J4- # U302-14 2Q1 NET 'LTCHD_AM(3)' J4- # U302-16 2Q2 NET 'OCB_ADRS(18)' J4- # U302-17 2Q3 NET 'LTCHD_IACK_B' J4- # U302-19 2Q4 NET 'OCB_ADRS(17)' J4- # U302-20 2Q5 NET 'OCB_ADRS(16)' J4- # U302-22 2Q6 NET 'LTCHD_AM(4)' J4- # U302-23 2Q7 # Connect the clock line from the FPGA to the clock input # pins on these VME latches: NET 'VME_LTCH_CLK' J4- # U301-25, U301-48, U302-25, U302-48 # Latch for VME "adrs type" information U301 NET 'OCB_ADRS(15)' J4- # U301-2 1Q0 NET 'OCB_ADRS(7)' J4- # U301-3 1Q1 NET 'OCB_ADRS(14)' J4- # U301-5 1Q2 NET 'OCB_ADRS(6)' J4- # U301-6 1Q3 NET 'OCB_ADRS(13)' J4- # U301-8 1Q4 NET 'OCB_ADRS(5)' J4- # U301-9 1Q5 NET 'OCB_ADRS(12)' J4- # U301-11 1Q6 NET 'OCB_ADRS(4)' J4- # U301-12 1Q7 NET 'OCB_ADRS(11)' J4- # U301-13 2Q0 NET 'OCB_ADRS(3)' J4- # U301-14 2Q1 NET 'OCB_ADRS(10)' J4- # U301-16 2Q2 NET 'OCB_ADRS(2)' J4- # U301-17 2Q3 NET 'OCB_ADRS(9)' J4- # U301-19 2Q4 NET 'OCB_ADRS(1)' J4- # U301-20 2Q5 NET 'OCB_ADRS(8)' J4- # U301-22 2Q6 # VME Control & Address Signsl To & From U303 NET 'RCVD_GEO_B(0)' J1- # U303-38 The received GEO_B(0) signal NET 'RCVD_GEO_B(1)' J1- # U303-40 The received GEO_B(1) signal NET 'RCVD_GEO_B(2)' J1- # U303-41 The received GEO_B(2) signal NET 'RCVD_GEO_B(3)' J1- # U303-43 The received GEO_B(3) signal NET 'RCVD_GEO_B(4)' J1- # U303-46 The received GEO_B(4) signal NET 'DRV_DTACK_B' J1- # U303-25 Connect the DRV_DTACK_B signal NET 'RCVD_DS1_B' J1- # U303-37 The received VME_DS1_B signal NET 'RCVD_SYSRESET_B' J1- # U103-44 The received SYSRESET_B signal NET 'RCVD_AS_B' J1- # U103-47 The received Adrs_Strb_B signal