# # File created by Match_Resource_to_Pin V0.1 at Mon Dec 19 13:22:17 2011 # derived from input Netlist file # and Resource to Pin dictionary # # # This is the Net 2 Resource file for the # # K1 to J2 FSI Connections # ---==------------------------- # # # Original Rev. 8-Sept-2011 # Current Rev. 19-Dec-2011 # This file specifies what J2 FSI Resource is # connected to each K1 GPIO driver or receiver. # -- NET 'GPIO_K_1_SIGNAL_0' U1-3 J2-45 # IO_L96P_7 NET 'GPIO_K_1_SIGNAL_1' U1-2 J2-46 # IO_L96N_7 NET 'GPIO_K_1_SIGNAL_2' U2-2 J2-43 # IO_L94P_7 NET 'GPIO_K_1_SIGNAL_3' U2-3 J2-44 # IO_L94N_7 NET 'GPIO_K_1_SIGNAL_4' U3-3 J2-39 # IO_L93P_7_VREF_7 NET 'GPIO_K_1_SIGNAL_5' U3-2 J2-40 # IO_L93N_7 NET 'GPIO_K_1_SIGNAL_6' U4-2 J2-37 # IO_L91P_7 NET 'GPIO_K_1_SIGNAL_7' U4-3 J2-38 # IO_L91N_7 NET 'GPIO_K_1_SIGNAL_8' U5-3 J2-33 # IO_L51P_7_VREF_7 NET 'GPIO_K_1_SIGNAL_9' U5-2 J2-34 # IO_L51N_7 NET 'GPIO_K_1_SIGNAL_10' U6-2 J2-31 # IO_L49P_7 NET 'GPIO_K_1_SIGNAL_11' U6-3 J2-32 # IO_L49N_7 NET 'GPIO_K_1_SIGNAL_12' U7-3 J2-27 # IO_L48P_7 NET 'GPIO_K_1_SIGNAL_13' U7-2 J2-28 # IO_L48N_7 NET 'GPIO_K_1_SIGNAL_14' U8-2 J2-25 # IO_L46P_7 NET 'GPIO_K_1_SIGNAL_15' U8-3 J2-26 # IO_L46N_7 # # This is the Net 2 Resource file for the # # K2 to J2 FSI Connections # ---==------------------------- # # # Original Rev. 8-Sept-2011 # Current Rev. 19-Dec-2011 # This file specifies what J2 FSI Resource is # connected to each K2 GPIO driver or receiver. # -- NET 'GPIO_K_2_SIGNAL_0' U9-3 J2-23 # IO_L43P_7 NET 'GPIO_K_2_SIGNAL_1' U9-2 J2-24 # IO_L43N_7 NET 'GPIO_K_2_SIGNAL_2' U10-2 J2-21 # IO_L24P_7 NET 'GPIO_K_2_SIGNAL_3' U10-3 J2-22 # IO_L24N_7 NET 'GPIO_K_2_SIGNAL_4' U11-3 J2-17 # IO_L22P_7 NET 'GPIO_K_2_SIGNAL_5' U11-2 J2-18 # IO_L22N_7 NET 'GPIO_K_2_SIGNAL_6' U12-2 J2-15 # IO_L21P_7_VREF_7 NET 'GPIO_K_2_SIGNAL_7' U12-3 J2-16 # IO_L21N_7 NET 'GPIO_K_2_SIGNAL_8' U13-3 J2-11 # IO_L06P_7 NET 'GPIO_K_2_SIGNAL_9' U13-2 J2-12 # IO_L06N_7 NET 'GPIO_K_2_SIGNAL_10' U14-2 J2-9 # IO_L04P_7 NET 'GPIO_K_2_SIGNAL_11' U14-3 J2-10 # IO_L04N_7 NET 'GPIO_K_2_SIGNAL_12' U15-3 J2-5 # IO_L03P_7_VREF_7 NET 'GPIO_K_2_SIGNAL_13' U15-2 J2-6 # IO_L03N_7 NET 'GPIO_K_2_SIGNAL_14' U16-2 J2-3 # IO_L02P_7_VRN_7 NET 'GPIO_K_2_SIGNAL_15' U16-3 J2-4 # IO_L02N_7_VRP_7 # # This is the Net 2 Resource file for the # # K3 to J2 FSI Connections # ---==------------------------- # # # Original Rev. 9-Sept-2011 # Current Rev. 19-Dec-2011 # This file specifies what J2 FSI Resource is # connected to each K3 GPIO driver or receiver. # -- NET 'GPIO_K_3_SIGNAL_0' U17-3 J2-97 # IO_L02P_6_VRN_6 NET 'GPIO_K_3_SIGNAL_1' U17-2 J2-68 # IO_L51N_6_VREF_6 NET 'GPIO_K_3_SIGNAL_2' U18-2 J2-95 # IO_L04P_6 NET 'GPIO_K_3_SIGNAL_3' U18-3 J2-70 # IO_L49N_6 NET 'GPIO_K_3_SIGNAL_4' U19-3 J2-91 # IO_L03P_6 NET 'GPIO_K_3_SIGNAL_5' U19-2 J2-74 # IO_L46N_6 NET 'GPIO_K_3_SIGNAL_6' U20-2 J2-89 # IO_L19P_6 NET 'GPIO_K_3_SIGNAL_7' U20-3 J2-76 # IO_L45N_6_VREF_6 NET 'GPIO_K_3_SIGNAL_8' U21-3 J2-85 # IO_L06P_6 NET 'GPIO_K_3_SIGNAL_9' U21-2 J2-78 # IO_L43N_6 NET 'GPIO_K_3_SIGNAL_10' U22-2 J2-83 # IO_L21P_6 NET 'GPIO_K_3_SIGNAL_11' U22-3 J2-80 # IO_L24N_6 NET 'GPIO_K_3_SIGNAL_12' U23-3 J2-79 # IO_L24P_6 NET 'GPIO_K_3_SIGNAL_13' U23-2 J2-84 # IO_L21N_6_VREF_6 NET 'GPIO_K_3_SIGNAL_14' U24-2 J2-77 # IO_L43P_6 NET 'GPIO_K_3_SIGNAL_15' U24-3 J2-86 # IO_L06N_6 # # This is the Net 2 Resource file for the # # K4 to J2 FSI Connections # ---==------------------------- # # # Original Rev. 9-Sept-2011 # Current Rev. 19-Dec-2011 # This file specifies what J2 FSI Resource is # connected to each K4 GPIO driver or receiver. # -- NET 'GPIO_K_4_SIGNAL_0' U25-3 J2-75 # IO_L45P_6 NET 'GPIO_K_4_SIGNAL_1' U25-2 J2-90 # IO_L19N_6 NET 'GPIO_K_4_SIGNAL_2' U26-2 J2-73 # IO_L46P_6 NET 'GPIO_K_4_SIGNAL_3' U26-3 J2-92 # IO_L03N_6_VREF_6 NET 'GPIO_K_4_SIGNAL_4' U27-3 J2-69 # IO_L49P_6 NET 'GPIO_K_4_SIGNAL_5' U27-2 J2-96 # IO_L04N_6 NET 'GPIO_K_4_SIGNAL_6' U28-2 J2-67 # IO_L51P_6 NET 'GPIO_K_4_SIGNAL_7' U28-3 J2-98 # IO_L02N_6_VRP_6 NET 'GPIO_K_4_SIGNAL_8' U29-3 J2-63 # IO_L54P_6 NET 'GPIO_K_4_SIGNAL_9' U29-2 J2-64 # IO_L54N_6 NET 'GPIO_K_4_SIGNAL_10' U30-2 J2-61 # IO_L91P_6 NET 'GPIO_K_4_SIGNAL_11' U30-3 J2-62 # IO_L91N_6 NET 'GPIO_K_4_SIGNAL_12' U31-3 J2-57 # IO_L94P_6 NET 'GPIO_K_4_SIGNAL_13' U31-2 J2-58 # IO_L94N_6 NET 'GPIO_K_4_SIGNAL_14' U32-2 J2-55 # IO_L96P_6 NET 'GPIO_K_4_SIGNAL_15' U32-3 J2-56 # IO_L96N_6 # # This is the Net 2 Resource file for the # # K5 to J3 FSI Connections # ---==------------------------- # # # Original Rev. 9-Sept-2011 # Current Rev. 19-Dec-2011 # This file specifies what J3 FSI Resource is # connected to each K5 GPIO driver or receiver. # -- NET 'GPIO_K_5_SIGNAL_0' U33-3 J3-45 # IO_L96N_5_GCLK7S NET 'GPIO_K_5_SIGNAL_1' U33-2 J3-46 # IO_L95N_5_GCLK5S NET 'GPIO_K_5_SIGNAL_2' U34-2 J3-43 # IO_L96P_5_GCLK6P NET 'GPIO_K_5_SIGNAL_3' U34-3 J3-44 # IO_L95P_5_GCLK4P NET 'GPIO_K_5_SIGNAL_4' U35-3 J3-39 # IO_L93P_5 NET 'GPIO_K_5_SIGNAL_5' U35-2 J3-40 # IO_L93N_5 NET 'GPIO_K_5_SIGNAL_6' U36-2 J3-37 # IO_L54P_5 NET 'GPIO_K_5_SIGNAL_7' U36-3 J3-38 # IO_L54N_5 NET 'GPIO_K_5_SIGNAL_8' U37-3 J3-33 # IO_L92P_5 NET 'GPIO_K_5_SIGNAL_9' U37-2 J3-34 # IO_L92N_5 NET 'GPIO_K_5_SIGNAL_10' U38-2 J3-31 # IO_L51P_5 NET 'GPIO_K_5_SIGNAL_11' U38-3 J3-32 # IO_L51N_5_VREF_5 NET 'GPIO_K_5_SIGNAL_12' U39-3 J3-27 # IO_L52P_5 NET 'GPIO_K_5_SIGNAL_13' U39-2 J3-28 # IO_L52N_5 NET 'GPIO_K_5_SIGNAL_14' U40-2 J3-25 # IO_L22P_5 NET 'GPIO_K_5_SIGNAL_15' U40-3 J3-26 # IO_L22N_5 # # This is the Net 2 Resource file for the # # K6 to J3 FSI Connections # ---==------------------------- # # # Original Rev. 9-Sept-2011 # Current Rev. 19-Dec-2011 # This file specifies what J3 FSI Resource is # connected to each K6 GPIO driver or receiver. # -- NET 'GPIO_K_6_SIGNAL_0' U41-3 J3-23 # IO_L49P_5 NET 'GPIO_K_6_SIGNAL_1' U41-2 J3-24 # IO_L49N_5 NET 'GPIO_K_6_SIGNAL_2' U42-2 J3-21 # IO_L19P_5 NET 'GPIO_K_6_SIGNAL_3' U42-3 J3-22 # IO_L19N_5 NET 'GPIO_K_6_SIGNAL_4' U43-3 J3-17 # IO_L21P_5 NET 'GPIO_K_6_SIGNAL_5' U43-2 J3-18 # IO_L21N_5_VREF_5 NET 'GPIO_K_6_SIGNAL_6' U44-2 J3-15 # IO_L04P_5_VREF_5 NET 'GPIO_K_6_SIGNAL_7' U44-3 J3-16 # IO_L04N_5 NET 'GPIO_K_6_SIGNAL_8' U45-3 J3-11 # IO_L06P_5 NET 'GPIO_K_6_SIGNAL_9' U45-2 J3-12 # IO_L06N_5 NET 'GPIO_K_6_SIGNAL_10' U46-2 J3-9 # IO_L02P_5_D7 NET 'GPIO_K_6_SIGNAL_11' U46-3 J3-10 # IO_L02N_5_D6 NET 'GPIO_K_6_SIGNAL_12' U47-3 J3-5 # IO_L03P_5_D5_ALT_VRN_5 NET 'GPIO_K_6_SIGNAL_13' U47-2 J3-6 # IO_L03N_5_D4_ALT_VRP_5 NET 'GPIO_K_6_SIGNAL_14' U48-2 J3-3 # IO_L01P_5_CS_B NET 'GPIO_K_6_SIGNAL_15' U48-3 J3-4 # IO_L01N_5_RDWR_B # # This is the Net 2 Resource file for the # # K7 to J3 FSI Connections # ---==------------------------- # # # Original Rev. 9-Sept-2011 # Current Rev. 19-Dec-2011 # This file specifies what J3 FSI Resource is # connected to each K7 GPIO driver or receiver. # -- NET 'GPIO_K_7_SIGNAL_0' U49-3 J3-97 # IO_L01P_3 NET 'GPIO_K_7_SIGNAL_1' U49-2 J3-98 # IO_L01N_4_BUSY_DOUT NET 'GPIO_K_7_SIGNAL_2' U50-2 J3-95 # IO_L03P_4_D3_ALT_VRN_4 NET 'GPIO_K_7_SIGNAL_3' U50-3 J3-96 # IO_L03N_4_D2_ALT_VRP_4 NET 'GPIO_K_7_SIGNAL_4' U51-3 J3-91 # IO_L04P_4 NET 'GPIO_K_7_SIGNAL_5' U51-2 J3-92 # IO_L04N_4_VREF_4 NET 'GPIO_K_7_SIGNAL_6' U52-2 J3-89 # IO_L05P_4_VRN_4 NET 'GPIO_K_7_SIGNAL_7' U52-3 J3-90 # IO_L05N_4_VRP_4 NET 'GPIO_K_7_SIGNAL_8' U53-3 J3-85 # IO_L06P_4 NET 'GPIO_K_7_SIGNAL_9' U53-2 J3-86 # IO_L06N_4 NET 'GPIO_K_7_SIGNAL_10' U54-2 J3-83 # IO_L21P_4_VREF_4 NET 'GPIO_K_7_SIGNAL_11' U54-3 J3-84 # IO_L21N_4 NET 'GPIO_K_7_SIGNAL_12' U55-3 J3-79 # IO_L22P_4 NET 'GPIO_K_7_SIGNAL_13' U55-2 J3-80 # IO_L22N_4 NET 'GPIO_K_7_SIGNAL_14' U56-2 J3-77 # IO_L24P_4 NET 'GPIO_K_7_SIGNAL_15' U56-3 J3-78 # IO_L24N_4 # # This is the Net 2 Resource file for the # # K8 to J3 FSI Connections # ---==------------------------- # # # Original Rev. 9-Sept-2011 # Current Rev. 19-Dec-2011 # This file specifies what J3 FSI Resource is # connected to each K8 GPIO driver or receiver. # -- NET 'GPIO_K_8_SIGNAL_0' U57-3 J3-75 # IO_L49P_4 NET 'GPIO_K_8_SIGNAL_1' U57-2 J3-76 # IO_L49N_4 NET 'GPIO_K_8_SIGNAL_2' U58-2 J3-73 # IO_L52P_4 NET 'GPIO_K_8_SIGNAL_3' U58-3 J3-74 # IO_L52N_4 NET 'GPIO_K_8_SIGNAL_4' U59-3 J3-69 # IO_L54P_4 NET 'GPIO_K_8_SIGNAL_5' U59-2 J3-70 # IO_L54N_4 NET 'GPIO_K_8_SIGNAL_6' U60-2 J3-67 # IO_L92P_4 NET 'GPIO_K_8_SIGNAL_7' U60-3 J3-68 # IO_L92N_4 NET 'GPIO_K_8_SIGNAL_8' U61-3 J3-63 # IO_L93P_4 NET 'GPIO_K_8_SIGNAL_9' U61-2 J3-64 # IO_L93N_4 NET 'GPIO_K_8_SIGNAL_10' U62-2 J3-61 # IO_L91P_4 NET 'GPIO_K_8_SIGNAL_11' U62-3 J3-62 # IO_L91N_4_VREF_4 NET 'GPIO_K_8_SIGNAL_12' U63-3 J3-57 # IO_L96P_4_GCLK0P NET 'GPIO_K_8_SIGNAL_13' U63-2 J3-58 # IO_L95P_4_GCLK2P NET 'GPIO_K_8_SIGNAL_14' U64-2 J3-55 # IO_L96N_4_GCLK1S NET 'GPIO_K_8_SIGNAL_15' U64-3 J3-56 # IO_L95N_4_GCLK3S # # This is the Net 2 Resource file for the # # K9 to J4 FSI Connections # ---==------------------------- # # # Original Rev. 14-Sept-2011 # Current Rev. 19-Dec-2011 # This file specifies what J4 FSI Resource is # connected to each K9 GPIO driver or receiver. # -- NET 'GPIO_K_9_SIGNAL_0' U65-3 J4-45 # IO_L96P_3 NET 'GPIO_K_9_SIGNAL_1' U65-2 J4-46 # IO_L96N_3 NET 'GPIO_K_9_SIGNAL_2' U66-2 J4-43 # IO_L94P_3 NET 'GPIO_K_9_SIGNAL_3' U66-3 J4-44 # IO_L94N_3 NET 'GPIO_K_9_SIGNAL_4' U67-3 J4-39 # IO_L91P_3 NET 'GPIO_K_9_SIGNAL_5' U67-2 J4-40 # IO_L91N_3 NET 'GPIO_K_9_SIGNAL_6' U68-2 J4-37 # IO_L54P_3 NET 'GPIO_K_9_SIGNAL_7' U68-3 J4-38 # IO_L54N_3 NET 'GPIO_K_9_SIGNAL_8' U69-3 J4-33 # IO_L51P_3 NET 'GPIO_K_9_SIGNAL_9' U69-2 J4-34 # IO_L51N_3_VREF_3 NET 'GPIO_K_9_SIGNAL_10' U70-2 J4-31 # IO_L49P_3 NET 'GPIO_K_9_SIGNAL_11' U70-3 J4-32 # IO_L49N_3 NET 'GPIO_K_9_SIGNAL_12' U71-3 J4-27 # IO_L48P_3 NET 'GPIO_K_9_SIGNAL_13' U71-2 J4-28 # IO_L48N_3 NET 'GPIO_K_9_SIGNAL_14' U72-2 J4-25 # IO_L46P_3 NET 'GPIO_K_9_SIGNAL_15' U72-3 J4-26 # IO_L46N_3 # # This is the Net 2 Resource file for the # # K10 to J4 FSI Connections # ---===------------------------- # # # Original Rev. 14-Sept-2011 # Current Rev. 19-Dec-2011 # This file specifies what J4 FSI Resource is # connected to each K10 GPIO driver or receiver. # --- NET 'GPIO_K_10_SIGNAL_0' U73-3 J4-23 # IO_L43P_3 NET 'GPIO_K_10_SIGNAL_1' U73-2 J4-24 # IO_L43N_3 NET 'GPIO_K_10_SIGNAL_2' U74-2 J4-21 # IO_L24P_3 NET 'GPIO_K_10_SIGNAL_3' U74-3 J4-22 # IO_L24N_3 NET 'GPIO_K_10_SIGNAL_4' U75-3 J4-17 # IO_L22P_3 NET 'GPIO_K_10_SIGNAL_5' U75-2 J4-18 # IO_L22N_3 NET 'GPIO_K_10_SIGNAL_6' U76-2 J4-15 # IO_L21P_3 NET 'GPIO_K_10_SIGNAL_7' U76-3 J4-16 # IO_L21N_3_VREF_3 NET 'GPIO_K_10_SIGNAL_8' U77-3 J4-11 # IO_L06P_3 NET 'GPIO_K_10_SIGNAL_9' U77-2 J4-12 # IO_L06N_3 NET 'GPIO_K_10_SIGNAL_10' U78-2 J4-9 # IO_L04P_3 NET 'GPIO_K_10_SIGNAL_11' U78-3 J4-10 # IO_L04N_3 NET 'GPIO_K_10_SIGNAL_12' U79-3 J4-5 # IO_L03P_3 NET 'GPIO_K_10_SIGNAL_13' U79-2 J4-6 # IO_L03N_3_VREF_3 NET 'GPIO_K_10_SIGNAL_14' U80-2 J4-3 # IO_L02P_3_VRN_3 NET 'GPIO_K_10_SIGNAL_15' U80-3 J4-4 # IO_L02N_3_VRP_3 # # This is the Net 2 Resource file for the # # Miscellaneous J1 FSI Connections # ---------------------------------- # # # Original Rev. 15-Sept-2011 # Current Rev. 8-NOV-2011 # This file specifies what J1 FSI Resource is # connected to the Miscellaneous J1 nets. # # This file includes all the miscellaneous connections # to the J1 FSI connector to the MEZ-456, these include: # # Clock Signals, RS-232, LEDs, Pushbuttons, DeBug # 40 MHz Global Clock from the PLL to the FPGA # -------------------------------------------- NET 'CLK_40_DIR_FOR_FPGA' J1-43 # IO_L95P_1_GCLK0S NET 'CLK_40_CMP_FOR_FPGA' J1-45 # IO_L95N_1_GCLK1P # 10 MHz Global Clock from the GPS Receiver to the FPGA # ----------------------------------------------------- NET 'DRVN_10_MHZ_DIR' J1-58 # IO_L95P_0_GCLK6S NET 'DRVN_10_MHZ_CMP' J1-56 # IO_L95N_0_GCLK7P # 1 PPS from the GPS Receiver to the FPGA # ----------------------------------------- NET 'DRVN_1_PPS_DIR' J1-57 # IO_L96P_0_GCLK4S NET 'DRVN_1_PPS_CMP' J1-55 # IO_L96N_0_GCLK5P # External Signal from the Access Conn to Global Clock Net # --------------------------------------------------------- NET 'EXT_FPGA_CLK_BUF_OUT_DIR' J1-44 # IO_L96P_1_GCLK2S NET 'EXT_FPGA_CLK_BUF_OUT_CMP' J1-46 # IO_L96N_1_GCLK3P # Normal FPGA I/O Pin to the CMOS to LVDS Converter/Driver # and then to the Access Connector # ---------------------------------------------------------- NET 'FPGA_BUFD_LVDS_DRV_IN' J1-39 # IO_L94P_1_VREF_1 # PLL Reference and PLL Feedback from the FPGA # to the PLL's LVDS Inputs NET 'PLL_REF_DIR' J1-67 # IO_L92P_0 NET 'PLL_REF_CMP' J1-68 # IO_L92N_0 NET 'PLL_FBK_DIR' J1-63 # IO_L93P_0 NET 'PLL_FBK_CMP' J1-64 # IO_L93N_0 # Connect the RS-232 Signals to/from GPS Receiver # ------------------------------------------------- NET 'SERIAL_TO_FPGA' J1-83 # IO_L21P_0_VREF_0 NET 'SERIAL_FROM_FPGA' J1-85 # IO_L05P_0 # Connect the 6 Front Panel LEDs # -------------------------------- # FPGA Indicator LED_2 Left NET 'LED_2L_ON_B' J1-92 # IO_L03N_0_VRP_0 # FPGA Indicator LED_2 Center NET 'LED_2C_ON_B' J1-98 # IO_L01N_0 # FPGA Indicator LED_2 Right NET 'LED_2R_ON_B' J1-96 # IO_L02P_0 # FPGA Indicator LED_1 Left NET 'LED_1L_ON_B' J1-91 # IO_L03P_0_VRN_0 # FPGA Indicator LED_1 Center NET 'LED_1C_ON_B' J1-90 # IO_L04N_0_VREF_0 # FPGA Indicator LED_1 Right NET 'LED_1R_ON_B' J1-89 # IO_L04P_0 # Connect the Front Panel Pushbutton Switch # ------------------------------------------- # NET 'SWTCH_1_NC' J1-95 # IO_L02N_0 NET 'SWTCH_1_NO' J1-97 # IO_L01P_0 # # DeBug Connections from MEZ-456 J1 Connector # to the DeBug Connector J5 # NET 'DEBUG_01' J1-73 # IO_L52P_0 NET 'DEBUG_02' J1-74 # IO_L52N_0 NET 'DEBUG_03' J1-75 # IO_L49P_0 NET 'DEBUG_04' J1-76 # IO_L49N_0 NET 'DEBUG_05' J1-77 # IO_L24P_0 NET 'DEBUG_06' J1-78 # IO_L24N_0 NET 'DEBUG_07' J1-79 # IO_L22P_0 NET 'DEBUG_08' J1-80 # IO_L22N_0 # # Un-Used FPGA I/O Pins on the J1 FSI Connector # # There are a total of 6 FPGA pins that are not used. # All 6 of these pins are on the J1 FSI connector. # It is easy to run 4 of the 6 spare FPGA signals to vias. # The signal assignments for these 4 spare FPGA # signal vias are made here. These are vias V13:V16 # NET 'SPARE_SIG_V13' J1-86 # IO_L05N_0 NET 'SPARE_SIG_V14' J1-84 # IO_L21N_0 NET 'SPARE_SIG_V15' J1-70 # IO_L54N_0 NET 'SPARE_SIG_V16' J1-62 # IO_L91N_0_VREF_0 # # This is the Net 2 Resource file for the # # On Card Data Bus to J1 FSI Connections # ------------------------------------------ # # # Original Rev. 16-Sept-2011 # Current Rev. 7-Nov-2011 # This file specifies what J1 FSI Resource is # connected to which VME Data Bus receiver/driver. # This file includes the connections for all the VME P1 backplane # Data Bus signals from their buffer, i.e. U304, over to the J1 # connector for the MEZ-456. # The routing of these signals into the FPGA on the MEZ-456 is # picked to make the trace layout as easy as possible on the # H-Clk pcb. # Connect the 16 data lines from the "A" side of the U304 # 74LVT16245B Transceiver to J1 pins on the MEZ-456. NET 'OCB_DATA(7)' J1-27 # IO_L52P_1 NET 'OCB_DATA(15)' J1-37 # IO_L93P_1 NET 'OCB_DATA(6)' J1-33 # IO_L92P_1 NET 'OCB_DATA(14)' J1-40 # IO_L94N_1 NET 'OCB_DATA(5)' J1-38 # IO_L93N_1 NET 'OCB_DATA(13)' J1-34 # IO_L92N_1 NET 'OCB_DATA(4)' J1-32 # IO_L54N_1 NET 'OCB_DATA(12)' J1-28 # IO_L52N_1 NET 'OCB_DATA(3)' J1-26 # IO_L51P_1 NET 'OCB_DATA(11)' J1-24 # IO_L49N_1 NET 'OCB_DATA(2)' J1-22 # IO_L22N_1 NET 'OCB_DATA(10)' J1-18 # IO_L21N_1_VREF_1 NET 'OCB_DATA(1)' J1-16 # IO_L05N_1 NET 'OCB_DATA(9)' J1-12 # IO_L04N_1 NET 'OCB_DATA(0)' J1-10 # IO_L03N_1_VRP_1 NET 'OCB_DATA(8)' J1-6 # IO_L02N_1 # Connection from the MEZ-456 FPGA to the two Direction # pins of the 74LVT16245B VME Data Bus Transceiver. # When Low -> B input A output i.e. VME Write # When High -> A input B output i.e. VME Read NET 'DATA_BUF_DIR' J1-4 # IO_L01N_1 # Connection from the MEZ-456 FPGA to the two Output Enable bar # pins of the 74LVT16245B VME Data Bus Transceiver. # When high -> neither buffer output is enabled. NET 'DATA_BUF_ENB_B' J1-25 # IO_L51N_1_VREF_1 # # This is the Net 2 Resource file for the # # On Card Address and Control Bus # to # J1 and J4 FSI Connections # ----------------------------------------- # # # Original Rev. 16-Sept-2011 # Current Rev. 7-NOV-2011 # This file specifies what J1 or J4 FSI Resource is # connected to which On Card Address and Control Bus line. # This file includes the connections for all the VME P1 backplane # Address and Control type signals from their buffers/latches, i.e. # U301, U302, and U303 over to the J1 and J4 connectors for # the MEZ-456. # The routing of these signals into the FPGA on the MEZ-456 is # picked to make the trace layout as easy as possible on the # H-Clk pcb. # First take care of the 31 VME backplane signals that are received # and latched by U301 and U302. # Latch for VME "adrs type" information U302 NET 'LTCHD_AM(5)' J4-97 # IO_L01P_2 NET 'LTCHD_WRITE_B' J4-98 # IO_L01N_2 NET 'OCB_ADRS(23)' J4-95 # IO_L03P_2_VREF_2 NET 'OCB_ADRS(22)' J4-96 # IO_L03N_2 NET 'LTCHD_AM(0)' J4-91 # IO_L04P_2 NET 'OCB_ADRS(21)' J4-92 # IO_L04N_2 NET 'LTCHD_AM(1)' J4-89 # IO_L06P_2 NET 'OCB_ADRS(20)' J4-90 # IO_L06N_2 NET 'LTCHD_AM(2)' J4-86 # IO_L19N_2 NET 'OCB_ADRS(19)' J4-85 # IO_L19P_2 NET 'LTCHD_AM(3)' J4-84 # IO_L21N_2 NET 'OCB_ADRS(18)' J4-83 # IO_L21P_2_VREF_2 NET 'LTCHD_IACK_B' J4-80 # IO_L24N_2 NET 'OCB_ADRS(17)' J4-79 # IO_L24P_2 NET 'OCB_ADRS(16)' J4-78 # IO_L43N_2 NET 'LTCHD_AM(4)' J4-77 # IO_L43P_2 # Connect the clock line from the FPGA to the clock input # pins on these VME latches: NET 'VME_LTCH_CLK' J4-76 # IO_L45N_2 # Latch for VME "adrs type" information U301 NET 'OCB_ADRS(15)' J4-75 # IO_L45P_2_VREF_2 NET 'OCB_ADRS(7)' J4-56 # IO_L96N_2 NET 'OCB_ADRS(14)' J4-73 # IO_L46P_2 NET 'OCB_ADRS(6)' J4-58 # IO_L94N_2 NET 'OCB_ADRS(13)' J4-69 # IO_L49P_2 NET 'OCB_ADRS(5)' J4-62 # IO_L91N_2 NET 'OCB_ADRS(12)' J4-67 # IO_L51P_2_VREF_2 NET 'OCB_ADRS(4)' J4-64 # IO_L54N_2 NET 'OCB_ADRS(11)' J4-68 # IO_L51N_2 NET 'OCB_ADRS(3)' J4-63 # IO_L54P_2 NET 'OCB_ADRS(10)' J4-70 # IO_L49N_2 NET 'OCB_ADRS(2)' J4-61 # IO_L91P_2 NET 'OCB_ADRS(9)' J4-74 # IO_L46N_2 NET 'OCB_ADRS(1)' J4-57 # IO_L94P_2 NET 'OCB_ADRS(8)' J4-55 # IO_L96P_2 # VME Control & Address Signsl To & From U303 NET 'RCVD_GEO_B(0)' J1-9 # IO_L03P_1_VRN_1 NET 'RCVD_GEO_B(1)' J1-11 # IO_L04P_1_VREF_1 NET 'RCVD_GEO_B(2)' J1-15 # IO_L05P_1 NET 'RCVD_GEO_B(3)' J1-17 # IO_L21P_1 NET 'RCVD_GEO_B(4)' J1-23 # IO_L49P_1 NET 'DRV_DTACK_B' J1-3 # IO_L01P_1 NET 'RCVD_DS1_B' J1-5 # IO_L02P_1 NET 'RCVD_SYSRESET_B' J1-21 # IO_L22P_1 NET 'RCVD_AS_B' J1-31 # IO_L54P_1