# This is a Key In Net List file for # the H-CLK card for HAWC # VME to OCB Adrs & Ctrl Nets # ---------------------------------- # # Original Rev. 22-Apr-2011 # Most Recent Rev. 7-NOV-2011 # This file includes all the VME P1 backplane Address and Control # type signals. # # Most of these signls are handled by latches U301 and U302. # # One section of U303 used for driving VME_DTACK_B and # the other section of U303 is used for receiving VME_DS1_B, # receiving VME System Reset, receiving the Geographic Address, # and receiving VME_AS_B. # # There are pull up resistors on the VME Geographic Address pins # which are included in this net list file. # # Connection of the nets to the VME P1 connector itself is taken # care of in the P1 net list file. # This file contains the nets for the following components: # # U301, U302 74LVC16374A 16 bit "D" Latch for the # VME "adrs" type information # OR # # U301, U302 74LVC16373A 16 bit Transparent Latches for # VME "adrs" type information # # # U303 74LVT16245B Dual 8 bit Transceiver # Rec. Geo_Adrs, DS1_B, # and VME System Reset, # Drive DTACK_B # # C302:C312 even 0.1 uFd bypass capacitors to Vdd_Logic # # C301:C311 odd 4.7 nFd bypass capacitors to Vdd_Logic # # R301:R305 4.99 k Ohm 0603 1% Pull up on VME Geographic Adrs # # W301 Zero Ohm 0603 jumper controls input to unused # section of U302 a 74LVC16374A latch pin 1D0. # # W303 Zero Ohm 0603 jumper controls input to unused # sections of U303: 2A0, 2A1, 2A2, 2A3, 2A4, 2A5, 2A6 # # V2 : V8 Are via's on the individual inputs of W303. # V10 Is a latch output on U301 # First take care of the 31 VME backplane signals that are received # and latched by U301 and U302. There is one unused section in this # pair of latches. It will be placed at the pin 24-25 end of U301. # Latch for VME "adrs type" information U302 NET 'VME_AM(5)' U302-47 # 1D0 NET 'LTCHD_AM(5)' U302-2 # 1Q0 NET 'VME_WRITE_B' U302-46 # 1D1 NET 'LTCHD_WRITE_B' U302-3 # 1Q1 NET 'VME_ADDR(23)' U302-44 # 1D2 NET 'OCB_ADRS(23)' U302-5 # 1Q2 NET 'VME_ADDR(22)' U302-43 # 1D3 NET 'OCB_ADRS(22)' U302-6 # 1Q3 NET 'VME_AM(0)' U302-41 # 1D4 NET 'LTCHD_AM(0)' U302-8 # 1Q4 NET 'VME_ADDR(21)' U302-40 # 1D5 NET 'OCB_ADRS(21)' U302-9 # 1Q5 NET 'VME_AM(1)' U302-38 # 1D6 NET 'LTCHD_AM(1)' U302-11 # 1Q6 NET 'VME_ADDR(20)' U302-37 # 1D7 NET 'OCB_ADRS(20)' U302-12 # 1Q7 NET 'VME_AM(2)' U302-36 # 2D0 NET 'LTCHD_AM(2)' U302-13 # 2Q0 NET 'VME_ADDR(19)' U302-35 # 2D1 NET 'OCB_ADRS(19)' U302-14 # 2Q1 NET 'VME_AM(3)' U302-33 # 2D2 NET 'LTCHD_AM(3)' U302-16 # 2Q2 NET 'VME_ADDR(18)' U302-32 # 2D3 NET 'OCB_ADRS(18)' U302-17 # 2Q3 NET 'VME_IACK_B' U302-30 # 2D4 NET 'LTCHD_IACK_B' U302-19 # 2Q4 NET 'VME_ADDR(17)' U302-29 # 2D5 NET 'OCB_ADRS(17)' U302-20 # 2Q5 NET 'VME_ADDR(16)' U302-27 # 2D6 NET 'OCB_ADRS(16)' U302-22 # 2Q6 NET 'VME_AM(4)' U302-26 # 2D7 NET 'LTCHD_AM(4)' U302-23 # 2Q7 # Latch for VME "adrs type" information U301 NET 'VME_ADDR(15)' U301-47 # 1D0 NET 'OCB_ADRS(15)' U301-2 # 1Q0 NET 'VME_ADDR(7)' U301-46 # 1D1 NET 'OCB_ADRS(7)' U301-3 # 1Q1 NET 'VME_ADDR(14)' U301-44 # 1D2 NET 'OCB_ADRS(14)' U301-5 # 1Q2 NET 'VME_ADDR(6)' U301-43 # 1D3 NET 'OCB_ADRS(6)' U301-6 # 1Q3 NET 'VME_ADDR(13)' U301-41 # 1D4 NET 'OCB_ADRS(13)' U301-8 # 1Q4 NET 'VME_ADDR(5)' U301-40 # 1D5 NET 'OCB_ADRS(5)' U301-9 # 1Q5 NET 'VME_ADDR(12)' U301-38 # 1D6 NET 'OCB_ADRS(12)' U301-11 # 1Q6 NET 'VME_ADDR(4)' U301-37 # 1D7 NET 'OCB_ADRS(4)' U301-12 # 1Q7 NET 'VME_ADDR(11)' U301-36 # 2D0 NET 'OCB_ADRS(11)' U301-13 # 2Q0 NET 'VME_ADDR(3)' U301-35 # 2D1 NET 'OCB_ADRS(3)' U301-14 # 2Q1 NET 'VME_ADDR(10)' U301-33 # 2D2 NET 'OCB_ADRS(10)' U301-16 # 2Q2 NET 'VME_ADDR(2)' U301-32 # 2D3 NET 'OCB_ADRS(2)' U301-17 # 2Q3 NET 'VME_ADDR(9)' U301-30 # 2D4 NET 'OCB_ADRS(9)' U301-19 # 2Q4 NET 'VME_ADDR(1)' U301-29 # 2D5 NET 'OCB_ADRS(1)' U301-20 # 2Q5 NET 'VME_ADDR(8)' U301-27 # 2D6 NET 'OCB_ADRS(8)' U301-22 # 2Q6 # U301 has one unused section. Tie its input to Gnd # through a zero Ohm jumper W301. The output from # this unused section runs to via, V10. NET 'LFBT_LATCH_IN_1' W301-2 U301-26 # 2D7 Input to unused section NET 'GROUND' W301-1 # of U301 a 16 bit Latch NET 'LFBT_LATCH_OUT_1' U301-23 # 2Q7 Output from the unused NET 'LFBT_LATCH_OUT_1' V10-1 # U301 Latch is connected ### # only to via, V10. # Ground the OE_B pins on the U301 and U302 latches: NET 'GROUND' U301-1 U301-24 U302-1 U302-24 # Connect the clock net to the clock input pins on these latches: NET 'VME_LTCH_CLK' U301-25 U301-48 U302-25 U302-48 # Connect the Vdd power supply pins to the 74LVC16374A latches: NET 'VDD_LOGIC' U301-7 U301-18 U301-31 U301-42 NET 'VDD_LOGIC' U302-7 U302-18 U302-31 U302-42 # Connect the Ground pins to the 74LVC16374A latches: NET 'GROUND' U301-4 U301-10 U301-15 U301-21 NET 'GROUND' U301-28 U301-34 U301-39 U301-45 NET 'GROUND' U302-4 U302-10 U302-15 U302-21 NET 'GROUND' U302-28 U302-34 U302-39 U302-45 # Now include the nets for the bypass capacitors on the latches: # 0.1 uFd Ceramic NET 'VDD_LOGIC' C302-1 C304-2 C306-1 C308-2 NET 'GROUND' C302-2 C304-1 C306-2 C308-1 # 4.7 nFd Ceramic NET 'VDD_LOGIC' C301-2 C303-1 C305-2 C307-1 NET 'GROUND' C301-1 C303-2 C305-1 C307-2 # The following signals are all handled by a single 74LVT16245B. # The "B Side" of this chip is connected to VME-Bus signals. # The "A Side" of this chip is connected to the On Card Bus signals. # # Section "1" of this chip, e.g. pins 1:12, is setup with its Direction # pin LOW (--> B side is an input) and its OE\ pin LOW (--> outputs # are enabled) it receives the: DS1_B, the 5 Geographic Address # lines, VME System Reset, and VME Adrs_Strb_B from the VME-Bus. # # Section "2" of this chip e.g. pins 13:24, is setup with its Direction # pin HI (--> B side is an output) and its OE\ pin is used to assert # the active low DTACK_B signal. All of the inputs to this section # are tied low. # The following net connections are for receiving the VME_DS1_B signal, # the 5 Geographic Address, the VME Reset, and the VME Address Strobe. # These VME signals are received by one section of U303. NET 'VME_DS1_B' U303-12 # Backplane VME_DS1_B signal connects # to receiver input pin 1B7. NET 'RCVD_DS1_B' U303-37 # The received VME_DS1_B signal now # goes to the H-CLK's FPGA. NET 'VME_GEO_B(0)' U303-11 # Backplane VME_GEO_B(0) signal connects # to receiver input pin 1B6. NET 'RCVD_GEO_B(0)' U303-38 # The received GEO_B(0) signal now # goes to the H-CLK's FPGA. NET 'VME_GEO_B(1)' U303-9 # Backplane VME_GEO_B(1) signal connects # to receiver input pin 1B5. NET 'RCVD_GEO_B(1)' U303-40 # The received GEO_B(1) signal now # goes to the H-CLK's FPGA. NET 'VME_GEO_B(2)' U303-8 # Backplane VME_GEO_B(2) signal connects # to receiver input pin 1B4. NET 'RCVD_GEO_B(2)' U303-41 # The received GEO_B(2) signal now # goes to the H-CLK's FPGA. NET 'VME_GEO_B(3)' U303-6 # Backplane VME_GEO_B(3) signal connects # to receiver input pin 1B3. NET 'RCVD_GEO_B(3)' U303-43 # The received GEO_B(3) signal now # goes to the H-CLK's FPGA. NET 'VME_SYSRESET_B' U303-5 # Backplane VME System_Reset_B signal # connects to receiver input pin 1B2 NET 'RCVD_SYSRESET_B' U303-44 # The received SYSRESET_B signal from # pin 1A2 now goes to the H-CLK's FPGA. NET 'VME_GEO_B(4)' U303-3 # Backplane VME_GEO_B(4) signal connects # to receiver input pin 1B1. NET 'RCVD_GEO_B(4)' U303-46 # The received GEO_B(4) signal now # goes to the H-CLK's FPGA. NET 'VME_AS_B' U303-2 # Backplane VME Adrs_Strobe_B signal # connects to receiver input pin 1B0 NET 'RCVD_AS_B' U303-47 # The received Adrs_Strobe_B signal from # pin 1A0 now goes to the H-CLK's FPGA. # The following nets are the pull up resistors on the VME backplane # Geographic Address lines. These 5 Geographic Address signals are # pulled up before being sent to the Board Control PAL VME Interface. # On the backplane the Geographic Address pins are either floating # or tied to Gnd. The pull up resistors are R1001 : R1005. NET 'VME_GEO_B(0)' R301-1 # Pull up VME-64X Geographic Adress (0) bar NET 'VME_GEO_B(1)' R302-1 # Pull up VME-64X Geographic Adress (1) bar NET 'VME_GEO_B(2)' R303-1 # Pull up VME-64X Geographic Adress (2) bar NET 'VME_GEO_B(3)' R304-1 # Pull up VME-64X Geographic Adress (3) bar NET 'VME_GEO_B(4)' R305-1 # Pull up VME-64X Geographic Adress (4) bar # Connect the high side of these pull up resistors to the Vdd_Logic supply. NET 'VDD_LOGIC' R301-2 R302-2 R303-2 R304-2 R305-2 # The following net connections are for driving the VME_DTACK_B signal. # This VME signal is driven by one section of U303. NET 'VME_DTACK_B' U303-23 # The driver output 2B7 connects to the # backplane VME DTACK_B pin. NET 'GROUND' U303-26 # This is the input to this DTACK driver. # It is the 2A7 pin. NET 'DRV_DTACK_B' U303-25 # Connect the DRV_DTACK_B signal that comes # from the H-CLK's FPGA to the Output_Enable_B # pin for section "2" of the 74LVT16245B. # Inputs 2A0, 2A1, 2A2, 2A3, 2A4, 2A5, 2A6 of chip U303 are not # used at this time. These pins are brought out to a Zero-Ohm jumper # W303 and grounded. There are via's in this net to make it possible # to access individual inputs to the U303 chip if that is needed. NET 'RCVR_2A0_2A6_U303' U303-36 U303-35 # 2A0 2A1 Inputs are unused NET 'RCVR_2A0_2A6_U303' U303-33 U303-32 # 2A2 2A3 Inputs are unused NET 'RCVR_2A0_2A6_U303' U303-30 U303-29 # 2A4 2A5 Inputs are unused NET 'RCVR_2A0_2A6_U303' U303-27 # 2A6 Inputs are unused NET 'RCVR_2A0_2A6_U303' V2-1 V3-1 # Via's to access U303 inputs NET 'RCVR_2A0_2A6_U303' V4-1 V5-1 # Via's to access U303 inputs NET 'RCVR_2A0_2A6_U303' V6-1 V7-1 # Via's to access U303 inputs NET 'RCVR_2A0_2A6_U303' V8-1 # Via's to access U303 inputs NET 'RCVR_2A0_2A6_U303' W303-2 # Jumper for this unused NET 'GROUND' W303-1 # inputs - tied to ground ### Outputs 2B0, 2B1, 2B2, 2B3, 2B4, 2B5, 2B6 are not used and ### are not connected. Pins 13, 14, 16, 17, 19, 20, 22 are not connected. # Connect the two Direction pins of the 74LVT16245B Transceiver. NET 'GROUND' U303-1 # Section "1" low -> B input A output NET 'VDD_LOGIC' U303-24 # Section "2" high -> A input B output # Connect the Output Enable bar pin fpr section "1". NET 'GROUND' U303-48 # Section "1" output is enabled. # Connect the Vdd power supply pins to the 74LVT16245B Transceiver. NET 'VDD_LOGIC' U303-7 U303-18 U303-31 U303-42 # Connect the Ground pins to the 74LVT16245B Transceiver. NET 'GROUND' U303-4 U303-10 U303-15 U303-21 NET 'GROUND' U303-28 U303-34 U303-39 U303-45 # Now include the nets for the bypass capacitors on this Transceiver. # 100 nFd Ceramic NET 'VDD_LOGIC' C310-1 C312-2 NET 'GROUND' C310-2 C312-1 # 4.7 nFd Ceramic NET 'VDD_LOGIC' C309-2 C311-1 NET 'GROUND' C309-1 C311-2