H-Clk  FPGA  Minimal Design Requirements
        ------------------------------------------


                                         Initial Rev.  15-Aug-2011
                                         Current Rev.  13-Oct-2011


Any FPGA design that is used on the H-Clk card must contain a
certain minimal set of function for the card to operate at all
and for it to be safely powered up.  This note lists some of
these minimum requirements:

1. The direction and signal level of ALL of the FPGA's I/O pins
   that run to either the card's  65LVDS9638  Dual LVDS Line
   Drivers  or the card's  65LVDS9637 Dual LVDS Line Receivers
   must match the type of chip that they are tied to.  No output
   to output battles can be allowed.  If a given H-Clk card
   application does not use all 160 of the card's GPIOs - you
   must still include all of them in the FPGA design for that
   application.

2. Control of enabling the high current outputs on the 16 bit
   VME Bus Data Transceiver,  either to place the H-Clk card's
   data onto the VME Bus  or  to send VME Bus data to the H-Clk's
   FPGA must  always  be controlled.  No possibility of
   initializing in the wrong state or "hanging" in the wrong
   state can be allowed.

3. The "Direction" of the 16 bit VME Bus Data Transceiver must
   always be controlled.  This direction must never conflict with
   the direction of the IO pins on the H-Clk's FPGA that either
   receive data from or send data to the VME Bus Data Transceiver.
   No possibility of initializing in the wrong state or "hanging"
   in the wrong state can be allowed.  Think carefully about
   what default direction you want, i.e. when there is no VME
   cycle taking place to the VME card.  Recall that CMOS inputs
   can not be left floating.

4. Even if a given application of the H-Clk card is not going to
   use RS-232 communication with the GPS Receiver - you still
   must correctly define the FPGA's IO pins that connect to the
   H-Clk card's RS-232 Transceiver.

5. All H-Clk FPGA designs must include the small section of
   logic (pre-scaler) that is part of the H-Clk card's 40 MHz
   Phase Locked Loop - even if a given H-Clk card application
   is not going to use the 10 MHz to 40 MHz PLL.  The FPGA's
   IO pins to the PLL must be correctly defined.

6. For most applications the 40 MHz LVDS Global Clock input
   on the FPGA should be the one (and only) clock that is used
   in the design of the synchronous logic in the FPGA.  All
   logic in the FPGA should be synchronous and driven from
   this single Global Clock source.  If a second clock domain
   is used  (e.g. a 10 MHz clock domain)  then all control and
   data lines that cross domains must be formally handled.
   I.E. your FPGA logic should be designed to work even if
   the 40 MHz and 10 MHz have lost their expected frequency
   and/or phase relationship.

7. For all user I/O pins on the FPGA one must specify for the
   pins that will be used as receivers the input signal voltage
   level and  for all pins that will be used as drivers one
   must specify the output voltage level and the drive current
   to be used.

8. You must check and verify what has been optimized out of
   your design.   E.G.  You must understand what happens went
   an FPGA pin that runs to an unused  H_Clk GPIO driver or receiver
   has been optimized out of the design  (e.g. because it is not
   used in that design).

9. Have you defined the desired initial state that you want all
   of the state persistent logic structures to be in as the system
   "wakes up" immediately after you configure logic into the
   FPGA and start it running ?

10. How do you "reset" your circuit ?  e.g. VME_RESET_B,  front
    push button,  setting a bit in a control register ?
    Are absolutely all parts of your circuit reset to a known
    specified default state when you tell it to reset ?

11. What Xilinx FPGA configuration process are you using ?
    How does your circuit behave during all the different
    stages of Xilinx configuration ?   What is your card
    telling other parts of the HAWC Trig/DAQ system to do
    while it is configuring ?