Definition of the H_Clk Card ------------------------------ Initial Rev. 7-MAR-2011 Current Rev. 13-FEB-2012 The following points define the structure of and the components used on the H-Clk card. - The H-Clk card will be designed as a 6U x 160mm VME-64X card. .It will use 5 column 160 pin connectors. .It will requires a VME-64X crate with a 3.3V supply .Additional VME details are below .To have space for all the cables and connectors H-Clk is a "double wide" card, i.e. 8 HP unites. - General Purpose I/O .There are 10 GPIO connectors. .Each connector is a standard 34 pin header 0.1" x 0.1" with pins numbered in the standard way and pin #1 marked. .The GPIO connectors are labeled K1 through K10 on the pcb. .Each connector will have 16 LVDS GPIO signals to or from the FPGA and a high quality 40 MHz LVDS clock signal output on its 17th pair, i.e. pins 33 and 34. .All of the GPIO LVDS pin pairs that go to receivers will have built in LVDS termination resistors.. .In pairs the LVDS pin pairs may be setup as inputs or as outputs by installing either 65LVDT34D receivers or 65LVDS9638D drivers, e.g. pin pairs 1_&_2 and 2_&_3 may be setup as either 2 inputs or as 2 outputs. .In the Jan 2012 build of 20 H-Clk cards: 11 will be made as "Clock" type H-Clk cards with GPIO connectors K1, K2 inputs and K3:K10 outputs, 9 will be made as "Control" type H-Clk cards with GPIO connectors K1:K6 inputs and K7:K10 outputs. - LVDS Receivers and Drivers for the GPIO .Use the 2 channel LVDS parts in the SOIC package. .This package does not have a thermo pad - i.e. we can re-work. .Driver: 65LVDS9638D Receiver: 65LVDT34D .The driver and receiver have the same pinout. .Decide the I/O ratio at build time. .The thermo load in this package is fine. .To have enough space for the SOIC package it is necessary to put these parts on both the front and back sides of the card. .The H-Clk will use single ended connections from the Receivers and Drivers for the General Purpose I/O lines to the FPGA on the Mez-456. .There are enough grounds to support single ended connection, about 32 Gnd pins in each of the 4 connectors that tie the H-Clk and the Mez-456 together. I.E. about 128 Gnd pins total. - The H-Clk connects to the Mez-456 via 4 Samtec "FSI" connectors. .FSI connectors have 2 rows of pins with a 1mm pitch. .The FSI solder pads will be on the H-Clk. .The FSI wipe pads will be on the Mez-456. .The Mez-456 will have its FPGA and other ICs on top with the wipe contact FSI on the bottom. .The FSI connectors are 10mm stack height. .The wipe contact pattern is the same for all 3 stack heights. .The 3mm stack height has a different solder contact pattern than the common pattern used by the 6mm and 10mm stack height. .Tentative FSI connector Samtec Number FSI-150-10-L-D-E-AD which is 50 pins per row, 10mm height, Gold on wipe contact, screw threads. .The H-Clk layout has these connectors 83mm apart, i.e. one pair is shifted 83mm in Y and the other pair 83mm in X. .The H-Clk layout of the pins on each FSI connector gives 64 signals, 32 grounds, and 4 power pins per side. The 4 FSI connectors will have only FPGA user I/O pins and the 128 grounds pins and 16 power pins. Things like the FPGA Configuration pins are handled separately. .The Mez-456 should be oriented so that the bulk of the VME connections are from the North and East sides, the West and South sides are runs to the GPIO connectors. - PLL Design and Components .Use the same general multiplier scheme as on the ADF-2. .VCXO is a Vectron VX-7031-DAT-KKKA-40M000000 D=+5V Vcc, A=CMOS output, T=0_to_70 deg C, K=+-50ppm APR, K=standard temperature stability, K=standard initial accuracy, A=pin #2 EN=H standard .Use filtered +5V power supply on private power fill .Use MAX4476AUT-T opamp and normal analog comps. .Fanout: from VCXO through a limiter resistor and AC coupled and 2 limiter diodes to a single sections of a 65LVDS9638 dual 3.3V CMOS to LVDS driver. (one load only) The output of this 65LVDS9638 sends PLL 40 MHz to a distribution section. The distribution section sends either the PLL 40 MHz, or else an externally supplied 40 MHz, to: the H-Clk's FPGA, its Access Connector, and to the GPIO 40 MHz Fanout. The GPIO connector 40 MHz fanout is done with a National DS90LV110T 1:10 LVDS Fanout chip using a separate run to each of the 10 GPIO connectors. .The PLL's Phase Comparator is a 5.0V XOR is Onsemi MC74VHCT86ADTR2G in a TSSOP-14 .The digital part of the PLL, i.e. the divide by 4 prescaler and the two D FFs are all implemented in the FPGA. .Sending 10 MHz, 40 MHz, and 1 PPS to the Mez-456 FPGA are done via LVDS. Sending the Reference and the Feedback signals to the PLL Phase Comparator are also done via LVDS. .There are features on the H_Clk card to install a shield over the PLL, i.e. between the PLL components and the MEZ-456 card if needed (but the whole back side of the MEZ-456 is a ground plane. - NavSync CW46S-RS232 Electrical Interface and Components .Use the RS232 version of the CW46S receiver. .Use a MAX3232E RS-232 transceiver on the H-Clk card to talk with the CW46. .Receive the 10 MHz and the 1pps using a SN65LVDS9637DGK LVDS receiver. .The 10 MHz is expected to be single ended about a 3.1 Vpp sine wave into a 100 Ohm term. Could be AC coupled, terminated, attenuated, and LVDS received. .The 1 pps signal is RS422 levels. Terminate, attenuate, and receive as LVDS. .Will supply the +6.5V to +30V DC 100 mA power from fused and filtered VME +12V supply. Use a double diode to allow a backup supply. Diode polarity protection on the outgoing line. .The battery backup GPS power can come on-card through user defined P2 connector "A" column pins. All "A" column pins are all "User Defined". H-Clk uses just 2 of these pins to bring the battery backup power supply for the GPS receiver on-card. This backup supply is assumed to be something like a 9V or 10V rechargeable battery. It is fused on-card but also needs to be fuse at the battery. Pin P2 A1 goes to the positive terminal of the battery and P2 A2 is the negative battery terminal. Note that the H-Clk card can provide float charge current to the battery via resistor R410. .The connector on the H-Clk for the cable running to the CW46 will be a normal 0.1"x0.1" 16 pin header on the front panel. .Varistor "lightning protection" is provided on the H-Clk card for all lines running to the CW46. .MAX3232 looks like it is setup so that its logic input levels High/Low are basically independent of powering it from 3.3V or 5V - but its logic output voltage is Vcc - 0.6V minimum - so we must run it from 3.3V to have it send signals directly to the FPGA's 3V inputs. .Pinout of the 16 pin connector on the H-Clk card to GPS Pin Function --- ---------- 1 H-Clk RS-232 Transmit data to the CW46S receiver 2 Gnd 3 GPS Power 4 GPS Power 5 Gnd 6 Gnd 7 1 PPS + 8 1 PPS - 9 Gnd 10 Gnd 11 10 MHz Sine Wave 12 Gnd 13 Gnd 14 Gnd 15 H-Clk RS-232 Received data from the CW46S receiver 16 Gnd - VME Interface Design and Components .The VME I/F will be simple slave only A24 D16. .Folks were asked and did not want anything wider/faster. .Make Geographic Addressing available. .The pin count will be about: Address 23 Adrs Modif 6 Geo Adrs 5 Data 16 DS1 1 AS 1 DTACK 1 Write 1 IACK 1 VME Reset + 1 -------- 56 I/Os for A24/D16 16 Data I/Os 39 Control Inputs 1 Control Output .These signals will go into the North-East cornet of the MEZ-456 layout for the H-CLK's FPGA. .Base address is set in Firmware (with assistance of the Geographic Adrs pins if desired). .Receivers for Adrs type signals are: U1001 U1002 Phillips 74lvc16373a 16 bit transparent latch. .Transceiver for Data type signals is: U1011 Phillips 74LVT16245B 16 bit Transceiver .Use one section of another 74LVT16245 ti receiver DS1_B and the 5 Geo_Adrs lines. Use the other section of this chips as the OC Driver for DTACK_B. - LEDs and Other Front Panel Items .LEDs for card and CW46 power 3x .GP-LEDs under control of the MEZ-456 FPGA 6x for example: use one to show VME activity use one to show "clock locked" use one to show 1 pps to of the second use one to show that the FPGA is configured use two to show RS-232 activity to/from GPS sensor .GP-LEDs are driven by 3.3V FPGA outputs through 866 Ohm resistors. The FPGA outputs are setup for: "LVTTL SLOW 4". .Will use 3 triple LED arrays: top array 3x Green, rest red .Recessed pushbutton to cause FPGA Configuration - S2 .Non-recessed pushbutton tied to FPGA pin for general purpose - S1 - VME Connectors and Power .Use the 5 column type P1 and P2 connectors. .No P0 connector is used. .All power received with fuse, varistor, aluminum electrolytic, and large tantalum bypass capacitors .Use VME +5V for powering the Mez-456. .Use VME +5V with extra filtering to power the 40 MHz PLL. .Use VME +3.3V for the H-Clk card's logic and drivers and receivers. .Use VME +12V power to operate the CW46 gps sensor. .No connection to the VME Bus -12V. .Bring on the battery backup power for the GPS via P2 User Defined pins. - Access Connector .Provide a 40 pin 2mm Access Connector for auxiliary connections to the H-Clk card .The Access Connector can be used for: some unknown auxiliary function, for debugging an FPGA application, or for running 2 H-Clk cards with synchronous 40 MHz and 1 pps signals .Provide the following connections: External 40 MHz LVDS input (for making a "slave" H-Clk card) Buffered output of this H-Clk card's 40 MHz PLL clock Buffered LVDS input and output to the H-Clk's FPGA (e.g. 1 pps) Switch S2 N.O. and N.C. contacts. An open terminal via Two pins each of +3.3V and +5V Eight direct runs to the H-Clk's FPGA (debug or chain cards) Monitor pin for the PLL loop control signal Ground pins 16 H-Clk Access Connector J5 39 ___ 1 +--------+ +--------+ | | +---------------------+ 40 2 Looking down onto the pcb connector Pin Function Pin Function --- ------------------------ --- ------------------------ 1 Gnd 2 Gnd 3 EXT_FPGA_CLK_IN_CMP 4 this card's 40_MHZ_OUT_DIR 5 EXT_FPGA_CLK_IN_DIR 6 this card's 40_MHZ_OUT_CMP 7 Gnd 8 Gnd 9 FPGA_BUFD_LVDS_OUT_DIR 10 EXT_40_MHZ_CLK_IN_DIR 11 FPGA_BUFD_LVDS_OUT_CMP 12 EXT_40_MHZ_CLK_IN_CMP 13 Gnd 14 Gnd 15 Gnd 16 Monitor PLL VXCO Ctrl 17 GnD 18 Gnd 19 Gnd 20 FPGA DeBug Signal #1 21 Gnd 22 FPGA DeBug Signal #2 23 Vdd +3.3V 24 FPGA DeBug Signal #3 25 Gnd 26 FPGA DeBug Signal #4 27 Vcc +5.0V 28 FPGA DeBug Signal #5 29 Gnd 30 FPGA DeBug Signal #6 31 Vdd +3.3V 32 FPGA DeBug Signal #7 33 Gnd 34 FPGA DeBug Signal #8 35 Vcc +5.0V 36 to open via V1-1 37 Gnd 38 S2 Normal Open Contact 39 Gnd 40 S2 Normal Closed Contact