H_Clk_2 Layout Details ------------------------------- Initial Rev. 7-MAR-2011 Current Rev. 21-DEC-2011 This file contains the details about the actual layout of the the H-Clk card for the HAWC Experiment. Board Size: ----------- Make the H-Clk card a rationalized 6U VME 160.0mm wide in X by 233.0mm high in Y In the K1:K10 GPIO connector section all of the components are in arrays that step by: delta X = 24.6 mm delta Y = 53.5 mm Geometries: ----------- For the H_Clk_2 all Mentor geometries are coming out of /home2/designs/boards/H_Clk_2/Work/Geometries/ Reference Designators: ---------------------- - The 17 connectors on the card use normal low numeric value reference designators that are not controlled in the blocks described next. - The bulk of the components on the H-Clk card have reference designators that are organized into blocks. 1:199 the GPIO components: term resistor, rec/drv IC, bypass cap 201:219 Receivers for 10 MHz and 1 PPS from GPS 221:249 40 MHz PLL - Phase Comparator, Loop Filter, and VCXO 251:269 40 MHz Clock FanOut 271:279 RS-232 tranceiver to/from GPS 281:295 Front Panel LED and Switch Resistors 301:319 VME Bus I/F: drivers, receivers, bypass cap 321:349 Front panel and miscellaneous components 401:499 Power: power entry and GPS power: fuses, bulk caps, varistors 400:409 VCC +5 410:419: VCC +12 420:499 VDD +3.3 Board Layers: ------------- - This card will require at least 3 signal trace routing layers. It can not be done in 2 trace layers because of the need to carefully distribute the 40 MHz clock and 3 layers may be necessary in the area of the connection to the P1 connector. - Power layers 3 Power Entry 3.3V VDD in the GPIO area and in the 40 MHz Clock FanOut area. 5.0V VCC in the PLL area, the RS-232 Serial I/O, and MEZ conn area 12V in the area for the GPS power On this design only the 3 fuses need to go next to P1, P2. The Varistors and Bulk Caps can go where there is space. - Stackup - these are the Physical Stackup Layers: ------- 1. trace layer top Mentor Signal_1 (Green) 2. ground Mentor Power_1 (Brown) 3. 3.3V power plane Mentor Power_2 (Green) 4. internal trace layer and Vcc fills Mentor Signal_2 (Yellow) 5. ground plane Mentor Power_3 (Brown) 6. trace layer bottom Mentor Signal_3 (Red) - Ground Planes: Solid except for a "U" moat around the PLL. The moat slice is on layer DAM_2. May also remove the ground plane under the PLL filter summing node. Plotted as negative data. Physical layer #2 and #5 are exactly the same. - +3.3V Vdd plane This Vdd power plane is solid except: .For a slice through it to isolate the input section along the backplane before the Vdd power input fuse. This isolation slice is on the DAM_1 layer. .For removal of this plane under the PLL. This removed section is also on the DAM_1 layer. Plotted as negative data. - Physical #4 layer is a combination of traces and power fills: The VCC_Logic power fill is on layer #4. This power fill includes: the VCC_Logic supply backplane connections, its fuse and input capacitors, and the distribution to the FSI connector array. The VCC_PLL power fill is also on layer #4. It is just under the PLL area. It connects to the main Vcc supply via the filter inductor L221. The traces to get from the GPS receiver connector K11 to the inside of the FSI connector rectaangle are on this layer. The traces to run from the 40 MHz distribution components that are inside the FSI rectangle to the 10x Fanout are on this layer. All of the traces for the 40 MHz Fanout to the GPIO connectors are on this layer. The VME +12V backplane input with its fuse and filter capacitors, the backup supply for the GPS with its fuse and input capacitors, and the filter capacitors for the supply to the GPS receiver are all on layer #4. What to Route First: -------------------- - GPIO "cells" and connection traces only as high as the upper connectors verify no need to spread out connectors (blocking P2) - VME Bus driver receiver area verify no need to move the MEZ West. Clocks Global Clocks -------------------- - All of the Global Clock lines into the MEZ-456 are routed to its connectors J1 and J3 - there are no Global Clocks routed to J2 and J4. - On the H-Clk card we will use all 64 I/Os on J3 to connect to the General Purpose I/O lines - thus giving up the Global Clocks on J3. - We will use the remaining 4 Global Clocks on J1 which are: List of Where the Mez-456 Global Clock Nets Are Located On J1: NET 'IO_L95P_1_GCLK0S' J1-43 # U1-D12 - clock NET 'IO_L95N_1_GCLK1P' J1-45 # U1-E12 - order pair NET 'IO_L96P_1_GCLK2S' J1-44 # U1-F13 - clock NET 'IO_L96N_1_GCLK3P' J1-46 # U1-F12 - order pair NET 'IO_L96N_0_GCLK5P' J1-55 # U1-B11 - clock NET 'IO_L96P_0_GCLK4S' J1-57 # U1-A11 - order pair NET 'IO_L95N_0_GCLK7P' J1-56 # U1-D11 - clock NET 'IO_L95P_0_GCLK6S' J1-58 # U1-C11 - order pair On J3: NET 'IO_L96P_5_GCLK6P' J3-43 # U1-Y11 - clock NET 'IO_L96N_5_GCLK7S' J3-45 # U1-AA11 - order pair NET 'IO_L95P_5_GCLK4P' J3-44 # U1-V11 - clock NET 'IO_L95N_5_GCLK5S' J3-46 # U1-W11 - order pair NET 'IO_L96N_4_GCLK1S' J3-55 # U1-AA12 - clock NET 'IO_L96P_4_GCLK0P' J3-57 # U1-AB12 - order pair NET 'IO_L95N_4_GCLK3S' J3-56 # U1-W12 - clock NET 'IO_L95P_4_GCLK2P' J3-58 # U1-Y12 - order pair Via's and Terminals Used: ------------------------- General Signal Via: via_0mm7 finished hole diameter 0.300 mm land pad 0.700 mm plane relief 1.200 mm --> ring width 0.200 mm --> plane isolation Air Gap 0.250 mm General Power Via: via_1mm1, TERM_0_6_MM finished hole diameter 0.600 mm land pad 1.100 mm plane relief 1.650 mm --> ring width 0.250 mm --> plane isolation Air Gap 0.275 mm term_3m_conn i.e. 3M connectors with 1 track routing 0.1" x 0.1" 25 mil square pin headers finished hole diameter 0.90 mm pad land diameter 1.50 mm plane relief 2.10 mm --> ring width 0.30 mm --> plane isolation air gap 0.30 mm With the 1.50 mm pad land diameter you can route a 0.30 mm trace that has 0.37 mm spaces on each side. term_hart_vme i.e. Hart 5 Column VME Connectors 0.1"x0.1" with 1 track routing finished hole diameter 1.00 mm pad land diameter 1.60 mm plane relief 2.20 mm --> ring width 0.30 mm --> plane isolation air gap 0.30 mm With the 1.60 mm pad land diameter you can route a 0.30 mm trace that has 0.32 mm spaces on each side. "Classic" 0.1" x 0.1" 25 mil square pin headers with 1 track routing finished hole diameter 1.00 mm pad land diameter 1.64 mm plane relief 2.24 mm --> ring width 0.32 mm --> plane isolation air gap 0.30 mm With the 1.64 mm pad land diameter you can route a 0.30 mm trace that has 0.30 mm spaces on each side. Trace Widths Used: ------------------ LVDS Receivers/Drivers: - From the LVDS Driver/Receiver pins to the Terminator resistor and then to the 34 pin header pins use 0.30 mm traces. - Power/Ground traces to the LVDS Driver/Receiver pads use 0.38 mm traces, use via_0mm7 to reach the planes. - Use 0.75 mm traces on the bypass capacitors for the LVDS Receiver/Driver chips. - Signal runs from the LVDS Receiver/Drivers to the MEZ-456 FSI connectors: use 0.20 mm traces on 0.6 mm centers, i.e. 0.4 mm of open space between traces. To break out by 45 degrees they stager by 0.3 mm on the 0.6 mm center to center run. VME Bus Buffers: - From the buffer chips to the backplane connectors: use a 0.25 mm trace if it just receives a signal, e.g. Address Lines, use a 0.20 mm trace if it just receives a signal and you need to be this narrow to escape the TSSOP-48 use a 0.30 mm trace if it is a driven line, e.g. Data Lines. Power and Ground connections to the FSI connectors for Mez-456: - All FSI connector ground pins are routed with 0.5 mm traces. - All FSI connector Vcc power pins are routed with 0.60 mm traces. Clock Fanout to GPIO Connectors: We want 100 Ohm differential signaling on these traces. This is a 6 layer card so it will have a nominal 12 mil laminate, i.e. 0.30 mm. This is an FR-4 card with a dielectric constant of about 4.3 With 0.2 mm wide striplines this is about 52 Ohm Zo. h = 0.063 cm w = 0.02 cm t = 0.0036 cm (1 oz cu) dielectric constant = 4.3 "factor" = +56 For two lines spaced 0.30 mm this gives a differential line impedance of about 96 Ohms. h = 0.063 cm s = 0.03 cm "factor" = 0.905 96 Ohm differential line impedance is not bad but should look into bumping up the dielectric cores on both sides of Physical layer #4. E.G. 3x 10 mil cores and 16 mil cores on both sides of Physical layer #4. General Signals: 0.20 mm 0mm7 via tightest TSOP layouts General Signals: 0.25 mm 0mm7 via General Signals: 0.30 mm 0mm7 via 1 track 0.1"x0.1" General Signals: 0.35 mm 0mm7 via to the 10x VLDS fanout power and ground 0.30 mm to ceramic bypass cap pads 0.60 mm 0.70 via To pads on Tant D 2x 1.20 mm 1mm1 via CL on pad edges To pands on Electrolytic F 2x 1.20 mm 1mm1 via edge on pad edges To Transient Suppressor 1x 1.20 mm 1mm1 via in center To pads on Fuse Holders 2x 1.20 mm 1mm1 via Power Traces: backplane, fuse 1.50 mm, 2.00 mm, 3.00 mm Design Rules: ------------- Net Type Design Rules - Class Default Pin Via Trace Fill Pin 0.50 Via 0.01 0.35 Trace 0.22 0.30 0.25 Fill 0.40 0.40 0.50 0.50 Trace to Pin A 0.26 mm Trace to Pin is required by the power and ground connections to the ti_dgk_8 package for the LVDS Receiver/drivers and the 0.38mm traces that connect power and ground to these packages. A 0.22 mm Trace to Pin is required by the 0.25 mm breakout traces from the TSSOP-48 packages for the VME Bus interface chips. From the note above - the next tightest Trace to Pin clearance is 0.26 mm. Trace to Via A 0.30 mm Trace to Via is required was achieved only by putting the inner ring of external breakout vias around the TSSOP-48 package on 0.05 mm grid points. This allowed t the 0.20 mm breakout traces from the TSSOP-48 packages for the VME Bus interface chips to run between vias with a 0.30 mm clearance. In all other locations something like a 0.35 mm Trace to Via clearance would work out OK. Old version of Trace to Via ( 0.1 mm grid vias ) A 0.25 mm Trace to Via is required by the 0.20 mm breakout traces from the TSSOP-48 packages for the VME Bus interface chips. In all other locations something like a 0.35 mm Trace to Via clearance would work out OK. Comps Files: ------------ - During design the normal Comps process used was: > /home2/designs/boards/H_Clk/Work/Components > cp ../../H_Clk_pcb/pcb/comps.comps_ijk ./input_comps_file.txt > aaa_build_h_clk_comps_from_extracted.sh > aaa_hclk_comps_data_path.sh ---> On 11-Oct-2011 turn the Comps completely over to mentor. If more work in needed in the .../Work/Components/ area then things like the R281 : R291 will need to be extracted back out of mentor ---> The file .../Components/input_comps_file.txt is the final version of the comps file that was used in the mentor branch right before the Silkscreen Reference Designator layout was done. Area Fill Generation --------------------------- Setup the Area Fill clearances from the: Setup Routing --> Setup Net Type Rules menue. For the Default_Net_Type setup: 0.4 mm clearance between Fill and Pin 0.4 mm clearance between Fill and Via 0.5 mm clearance between Fill and Trace 0.5 mm clearance between Fill and Fill Pull Down Setup Routing --> Setup Area Fill Pad Isolation : Polygon Tolerance = 0.025 mm Manufacture Aperature: 0.50 mm Slot Threshold: try 1.1 mm Solid Fill, NO Keep Islands, YES Allow Merge Do Not ignore area fill to via clearance for the same net Do Not ignore area fill to pin clearance for the same net Thernal: Pins, and Pads use thermal ties Bothe Pins and Pads are setup the same: Prefer 4 ties, Minimum 3 ties, prefer 45/135 degree Tie_Bar_Width 0.5 mm Select Floading for Via's Then to generate the Area Fills: Vcc_LOGIC & VCC_PLL Recall that H_Clk has a separate Vcc_PLL area fill inside of the Vcc_LOGIC area fill. These are both on the SIGNAL_2 layer which is Physical Layer #4. Pull Down Setup --> Shape Edit Mode ON Select the shape from the Shape Edit layer Right Click --> Change Shape to Fill: Area Fill ? vs Power Fill ? This is an Area Fill because it is on a trace layer and not on a power plane layer. Select Layer = Signal_2 Select Net = Vcc_bla Keep all Area Fill defaults NO delete the original shape typical warning: Area Fill is fractured into "N" pieces. After generating the 3 area fills, setup the view as you like and then make a save all. If necessary to delete and area fill use FabLink: Select the Area Fill on its Signal_ layer Area Fill Panel Menu --> Delete vertexes This is an area fill within an area fill. ---> The trick is just to generate in inner fill first and then generate the surrounding outer fill. The fill-to-fill clearance specification will keep the 2 fills separated. You do not need to explicitly use a KeepOut region. But if a keepout were needed - Area Fill Keep Out ------------------ FIL '$NONE' 'SIGNAL_2' CUTOUT 8 0 0 0 0 0 110000 0 0 T 5 5 F VER 6490000 14580000 VER 8510000 14580000 VER 8620000 14690000 VER 8620000 18610000 VER 8510000 18720000 VER 6490000 18720000 VER 6380000 18610000 VER 6380000 14690000 ST 0 1774 88 313 0 0 0 1 Design Rule Checks ------------------ Final DRC runs on 23-Nov-2011 Running at: nets_167 23-Nov-2011 (just changed J3-97 FPGA I/O) comps_308 9-Nov-2011 traces_85 11-Nov-2011 Layout says: 557 Comps 739 Nets 2420 Finished Traces 557(0) 2420(0) Starting from the "typical" Net based clearances for H-Cls of: Pin Via Trace Fill Pin 0.50 Via 0.01 0.35 Trace 0.22 0.30 0.25 Fill 0.40 0.40 0.50 0.50 Run the following and crank the clearances up to see if things are rationa: Check --> Traces --> Check_Traces Entire Board Remove Trace Violations NOT Selected Check Net Against Itself NOT Selected Check Trace Widths Less Than Net Rules NOT Selected Check All Thermal Ties on Pins and Vias Selected Check Same Net Pad to Pad Clearances Selected Remove Duplicate Routing NOT Selected Check Pad Connectivity With Fill Hatch NOT Selected Report Off Grid Vias as: Not Checked Report Uncovered Plated Drill Holes as: Warnings - It found 76 Coincident Trace Vertices, so I made a pass and let it Remove Duplicate Routing. It said that it pulled out 75 traces. In a quick check of a few things I can still see the things duplicated that I want duplicated so I save Traces_86. Now with the starting DRC rules DRC runs with zero errors. - Crank up Via to Pin. via-pin of 0.06 is still OK. via-pin of 0.07 is 160 errors all in the bypass capacitors for the GPIO drivers/receivers. 2x8x10=160. This was expected. Leave the via-pin set at 0.06 - Crank up via-via at via-via of 0.40 still zero errors. at 0.41 there are 3 errors. 2 of these are in the small vias placed exactly 1.1mm apart in the clock distribution. The 3rd one is in the GPS +12V power supply cross card connection. at 0.45 there are 5 errors. This is a slow turn on curve. For now leave this set at 0.40 The 1.1mm via to via center to center spacing is OK. - Crank up trace-pin at trace-pin of 0.23 pick up 214 errors. I think that these are all in the 0.25mm wide traces escaping the TSSOP-48 layouts for the VME IF. At trace-pin of 0.25 you pickup 2 more errors in a top side trace going to the front panel LEDs. At trace-pin of 0.26 go to 350 erros as you now pickup all the TSSOP-48 pins (both 0.20 and 0.25mm trace pins). At trace-pin of 0.27 to a total of 520 errors as now all of the ti_dgk_8 layout patterns for the LVDS parts have errors on their power pins. So the only thing that can be fixed is the LED trace and none of the other things up to 0.27mm are really problems. Set trace-pin back to 0.22mm - Crank up trace-via At trace-via of 0.30 there are 0 errors. At a trace-via of 0.31 you get 88 errors from the TSSOP-48 section from 0.25mm traces between escape vias. Going up to trace-via of 0.35 and you have only 89 errors still all in the TSSOP-48 VME arrea. This is OK - it's a clearance of 0.30mm. Set trace-via to 0.30mm. - Crank up trace-trace At trace-trace of 0.25mm there are zero errors. At trace-trace of 0.26mm pick up 49 errors all in the TSSOP-48 VME arrea. At 0.28 move up to 212 errors still all in the TSSOP-48 VME area. At 0.30mm you move up to 321 errors with errors now also in the clock distribution traces. So a trace-trace clearance of 0.25mm is OK so set the rules to 0.25mm. - So after the crank up study we are left at: Pin Via Trace Fill Pin 0.50 Via 0.06 0.40 Trace 0.22 0.30 0.25 We were only able to crank up the via-pin and via-via. There is still one warning about 2 coincident virtices. This is in the +12V line coming out of the fuse. I think that it is just from the double via and is OK. Restart Layout and do a full save with the new clearances set as above. Record the versions: Running at: nets_167 23-Nov-2011 (just changed J3-97 FPGA I/O) comps_308 9-Nov-2011 traces_86 23-Nov-2011 Layout says: 557 Comps 739 Nets 2271 Finished Traces 557(0) 2271(0) There are no obvious DRC errors on 23-Nov-2011 28-NOV-2011 Add more bypass capacitors: on Vdd add C450, C451, C452, C453, C454, C455 on Vcc PLL add C243, C244, C245, add components for the isolated front panel ground connection R420, R421, GA1, GA2. After these componets have been added and routed we are at: nets_169 comps_308 traces_87 all from today Layout says: 569 Comps 741 Nets 2291 Finished Traces 569(0) 2291(0) DRC still passes with zero errors using the rules Pin Via Trace Fill Pin 0.50 Via 0.06 0.40 Trace 0.22 0.30 0.25 There is still just the one expected warning about coincident virtices in the +12V line coming out of the fuse. DRC still looks OK. 1-DEC-2011 Final pass of DRC. Note that R410 has been moved. We are at: nets_180 comps_318 traces_90 all from today Nets_180 is from Work i.e. not from mentor Layout says: 569 Comps 741 Nets 2292 Finished Traces 569 (0) 2292 (0) DRC still passes with zero errors using the rules Pin Via Trace Fill Pin 0.50 Via 0.06 0.40 Trace 0.22 0.30 0.25 20-DEC-2011 Final pass of DRC. Now on H_Clk_2. We are at: nets_203 comps_334 traces_113 Traces and Comps are from today. Nets_203 is from Work i.e. not from mentor Layout says: 409 Comps 741 Nets 1812 Finished Traces 409 (2 = F.P,Grounds) 1812 (0) DRC still passes with zero errors using the rules Pin Via Trace Fill Pin 0.50 Via 0.06 0.40 Trace 0.22 0.30 0.25 DRC, Gerber, & Drill for H-Clk-2: Completed on 20-Dec-2011 -------------------------------------------------------------- Gerber Plot Generation ----------------------------- Assume that the Gerber Format has been setup and saved. Gerber Data is in mm 3.2 format. If necessary use: Right Click --> Artwork --> Change Artwork Format Image Scale: 1 Units: mm Mode: Absolute Plot Offsets: Manual with X=0.0 Y=0.0 G_Code: Allow Zero Suppression: None Interpolation: Linear with 8 Segments Output Format: 3 Significant and 2 decimal Data Record Length: 80 Header String: none Sub-Header String: none Trailer String: none Machine Stop Code: M02 XY-Modal: not checked Open Shutter Modal: not checked View Artwork Format: not checked Command Block End Character: * Verify that you are using the proper version of the Drill_Holes section of the geometry for the H_Clk pcb that has the PADS_2 copper for the front panel mounting screw holes. Aperature Table: Right Click --> Artwork --> Change Aperature Table --> Delete All Apertures Right Click --> Artwork --> Change Aperature Table --> Fill Aperature Table Select the Apertures for ALL Aizes Select NO ReSize and NO ReScale Flash Complex Padstacks: not checked Replace the table Report the Aperture Table (from Report Pull Down Menu) Include the ArtWork Format: yes Save and Display the Report Save Report to .../Work/Text/ Replace the existing Report May/Will need to Edit the Power Apertures: After the Aperture Table is filled it is necessary to edit the 5 Power Apertures (aka thermal reliefs) to get the desired layout. To edit a Power Aperture Right Click --> Artwork --> Change Aperture Table --> Change Power Aperture For each Power Aperture select the Aperture Position and then set the: Tie Width, Air Gap, and Rotation and then click OK. Note that the outer diameter of each Power Aperture is driven by its "power plane relief" diameter in its Geometry. We must set the Air Gap to get the desired pad size and set the Tie Width to get the desired amount of Copper connection. This version of Mentor lets us control the Tie Rotation. Before editing the Power Apertures are the following: Raw Power Apertures from the "Fill" Wednesday November 9, 2011; 13:49:14 Position Diameter Power Dcode This Must Be -------- -------- ----- ----- ------------------------ 41 1.20 true 141 via_0mm7 43 1.65 true 143 via_1mm1 & TERM_0_6_MM 45 2.10 true 145 term_3m_conn 2x8 2x17 46 2.2352 true 146 ck_term 49 2.20 true 149 term_hart_vme After editing the Power Apertures are the following: Desired for H-Clk ---------------------- Outer Relief Tie Air Position Diameter Width Gap Rotate Function -------- --------- ----- ----- ------ ---------- 41 1.20 0.30 0.22 45 via_0mm7 43 1.65 0.35 0.25 45 via_1mm1 & TERM_0_6_MM 45 2.10 0.35 0.30 45 term_3m_conn 2x8 2x17 46 2.2352 0.35 0.30 45 ck_term 49 2.20 0.35 0.30 45 term_hart_vme In all cases this gives the same or slightly larger Land diameter than in the associated via's Signal layers and it gives generous rational Tie Width. Gerber Data Generation: Right Click --> Artwork --> Creat Artwork Data Gerber Data is Gerber 274X format Stroke the Area Fill, Flash the Polygon ASCII Data, for the BOARD, ALL ArtWork Numbers (1:13) NO Tear Drops, REMOVE Unused Pins, REMOVE Unused Via's NO Output UnPlated Holes NO ReSize, NO ReScale Right Click --> Artwork --> Creat Artwork Data All settings are the same except create Gerber Data for just ArtWork Numbers 1 and 6 i.e. the top and bottom pcb layers, but use the option Output ALL Pins, Output ALL Via's Gerber Data Viewing: Right Click --> Artwork --> Simulate Artwork Data Edit the Final Gerbers: ----------------------- In the Gerber file, Artwork_3, i.e. Layer #3 the Vdd Power Plane, from the fully moated isolated area of this power plane under the PLL, remove two of the Ground Via Relief flashes so that this fully isolated section of the Vdd plane is tied to the PLL Ground. Remove the flash for the vias at: 66.2 155.7 and 83.8 178.0 mm. Remove: X06620Y15570D03* and X08380Y17800D03* from artwork_3 Drill File Generation ---------------------------- Assume that the Drill Format has been setup and saved. Drill Data is in mm 3.2 format. Drill Table: Right Click --> Drill --> Change Drill Table --> Delete All Drills Right Click --> Drill --> Change Drill Table --> Fill Drill Table Select Replace the Drill Table Right Click --> Drill --> Creat Drill Data Excellon, Board, ASCII, Drill Hole Type: Both Output Hole Types: ALL, NO Mirror. Report the Drill Table (from Report Pull Down Menu) Include the Drill Format Save and Display the Report Save Report to Design with .../Work/Text/ filename Replace the existing Report Look at the Simulation of the Drill Data and find: Drill Drill Position Size Count Plated Function ---------- ------ ----- ------ -------------------- 1 0.30 901 yes via_0mm7 2 0.60 88 yes via_1mm1 & TERM_0_6_MM 3 0.90 356 yes 3M Conn 10x34 + 1x16 4 1.00 320 yes VME 5 Column Conn 5 1.00 2 no J5 Access Conn Mount 6 1.0160 26 yes LED and Switch THD Pins 7 1.190 8 no FSI Conn Mount 8 2.6924 2 no 3M 16 pin conn mount 9 2.70 6 no VME Conn & Front Panel Now hand edit the final plated_unplated_drill_file to make things more uniform: - Drills #4 and #6 will be combined all into drill #4 - Drills #8 and #9 will be combined all into drill #9 - Pull out the now empty drills #6 and #8 and pack their numbers - We now have drills #1 through #7 as follows Drill Drill Position Size Count Plated Function ---------- ------ ----- ------ -------------------- 1 0.30 901 yes via_0mm7 2 0.60 88 yes via_1mm1 & TERM_0_6_MM 3 0.90 356 yes 3M Conn 10x34 + 1x16 4 1.00 346 yes VME 5 Column Conn and LED and Switch THD Pins 5 1.00 2 no J5 Access Conn Mount 6 1.190 8 no FSI Conn Mount 7 2.70 8 no VME Conn & Front Panel & 3M 16 pin conn mount Two Assembly Types: ------------------- "Clock Type": 2 Input Connectors, 8 Output Connectors, Build 11 cards 32 Receiver Ch. 128 Driver Ch. K1,K2 are Inputs K3:K10 are Outputs K1,K2 --> U1:U16 K3:K10 --> U17:U80 "Control Type": 6 Input Connectors, 4 Output Connectors, Build 9 cards 96 Receiver Ch. 64 Driver Ch. K1:K6 are Inputs K7:K10 are Outputs K1,K6 --> U1:U48 K7:K10 --> U49:U80 ======================================================================= Old Reference Junk