// H-Clk to MEZ-456 to XC2V1000 // Pin Constraint File // ---------------------------------- // // // Original Rev: 30-DEC-2011 // Current Rev: 13-FEB-2012 // First list the H-Clk's 160 GPIO signals. These GPIO signals are // organized in 10 connectors (K1 through K10) of 16 signals each. // // On the Clock type H-Clk K1,K2 are inputs K3:K10 are outputs // On the Control type H-Clk K1:K6 are inputs K7:K10 are outputs // // GPIO Connector K1 All H-Clk to MEZ-456 nets for K1 are on FSI J2 // // MEZ-456 FSI FPGA // FPGA J2 Pin Signal // GPIO K1 Signal U1 PIN No. Number Name NET "GPIO_K_1_SIGNAL_0" LOC = "L2"; // 45 IO_L96P_7 NET "GPIO_K_1_SIGNAL_1" LOC = "L3"; // 46 IO_L96N_7 NET "GPIO_K_1_SIGNAL_2" LOC = "L4"; // 43 IO_L94P_7 NET "GPIO_K_1_SIGNAL_3" LOC = "L5"; // 44 IO_L94N_7 NET "GPIO_K_1_SIGNAL_4" LOC = "K1"; // 39 IO_L93P_7_VREF_7 NET "GPIO_K_1_SIGNAL_5" LOC = "K2"; // 40 IO_L93N_7 NET "GPIO_K_1_SIGNAL_6" LOC = "K3"; // 37 IO_L91P_7 NET "GPIO_K_1_SIGNAL_7" LOC = "K4"; // 38 IO_L91N_7 NET "GPIO_K_1_SIGNAL_8" LOC = "J1"; // 33 IO_L51P_7_VREF_7 NET "GPIO_K_1_SIGNAL_9" LOC = "J2"; // 34 IO_L51N_7 NET "GPIO_K_1_SIGNAL_10" LOC = "J3"; // 31 IO_L49P_7 NET "GPIO_K_1_SIGNAL_11" LOC = "J4"; // 32 IO_L49N_7 NET "GPIO_K_1_SIGNAL_12" LOC = "H1"; // 27 IO_L48P_7 NET "GPIO_K_1_SIGNAL_13" LOC = "H2"; // 28 IO_L48N_7 NET "GPIO_K_1_SIGNAL_14" LOC = "H3"; // 25 IO_L46P_7 NET "GPIO_K_1_SIGNAL_15" LOC = "H4"; // 26 IO_L46N_7 // // GPIO Connector K2 All H-Clk to MEZ-456 nets for K2 are on FSI J2 // // MEZ-456 FSI FPGA // FPGA J2 Pin Signal // GPIO K2 Signal U1 PIN No. Number Name NET "GPIO_K_2_SIGNAL_0" LOC = "G1"; // 23 IO_L43P_7 NET "GPIO_K_2_SIGNAL_1" LOC = "G2"; // 24 IO_L43N_7 NET "GPIO_K_2_SIGNAL_2" LOC = "G3"; // 21 IO_L24P_7 NET "GPIO_K_2_SIGNAL_3" LOC = "G4"; // 22 IO_L24N_7 NET "GPIO_K_2_SIGNAL_4" LOC = "F1"; // 17 IO_L22P_7 NET "GPIO_K_2_SIGNAL_5" LOC = "F2"; // 18 IO_L22N_7 NET "GPIO_K_2_SIGNAL_6" LOC = "F3"; // 15 IO_L21P_7_VREF_7 NET "GPIO_K_2_SIGNAL_7" LOC = "F4"; // 16 IO_L21N_7 NET "GPIO_K_2_SIGNAL_8" LOC = "E1"; // 11 IO_L06P_7 NET "GPIO_K_2_SIGNAL_9" LOC = "E2"; // 12 IO_L06N_7 NET "GPIO_K_2_SIGNAL_10" LOC = "E3"; // 9 IO_L04P_7 NET "GPIO_K_2_SIGNAL_11" LOC = "E4"; // 10 IO_L04N_7 NET "GPIO_K_2_SIGNAL_12" LOC = "D1"; // 5 IO_L03P_7_VREF_7 NET "GPIO_K_2_SIGNAL_13" LOC = "D2"; // 6 IO_L03N_7 NET "GPIO_K_2_SIGNAL_14" LOC = "C1"; // 3 IO_L02P_7_VRN_7 NET "GPIO_K_2_SIGNAL_15" LOC = "C2"; // 4 IO_L02N_7_VRP_7 // // GPIO Connector K3 All H-Clk to MEZ-456 nets for K3 are on FSI J2 // // MEZ-456 FSI FPGA // FPGA J2 Pin Signal // GPIO K3 Signal U1 PIN No. Number Name NET "GPIO_K_3_SIGNAL_0" LOC = "Y2"; // 97 IO_L02P_6_VRN_6 NET "GPIO_K_3_SIGNAL_1" LOC = "P1"; // 68 IO_L51N_6_VREF_6 NET "GPIO_K_3_SIGNAL_2" LOC = "W2"; // 95 IO_L04P_6 NET "GPIO_K_3_SIGNAL_3" LOC = "P3"; // 70 IO_L49N_6 NET "GPIO_K_3_SIGNAL_4" LOC = "V4"; // 91 IO_L03P_6 NET "GPIO_K_3_SIGNAL_5" LOC = "R1"; // 74 IO_L46N_6 NET "GPIO_K_3_SIGNAL_6" LOC = "V2"; // 89 IO_L19P_6 NET "GPIO_K_3_SIGNAL_7" LOC = "R3"; // 76 IO_L45N_6_VREF_6 NET "GPIO_K_3_SIGNAL_8" LOC = "U4"; // 85 IO_L06P_6 NET "GPIO_K_3_SIGNAL_9" LOC = "T1"; // 78 IO_L43N_6 NET "GPIO_K_3_SIGNAL_10" LOC = "U2"; // 83 IO_L21P_6 NET "GPIO_K_3_SIGNAL_11" LOC = "T3"; // 80 IO_L24N_6 NET "GPIO_K_3_SIGNAL_12" LOC = "T4"; // 79 IO_L24P_6 NET "GPIO_K_3_SIGNAL_13" LOC = "U1"; // 84 IO_L21N_6_VREF_6 NET "GPIO_K_3_SIGNAL_14" LOC = "T2"; // 77 IO_L43P_6 NET "GPIO_K_3_SIGNAL_15" LOC = "U3"; // 86 IO_L06N_6 // // GPIO Connector K4 All H-Clk to MEZ-456 nets for K4 are on FSI J2 // // MEZ-456 FSI FPGA // FPGA J2 Pin Signal // GPIO K4 Signal U1 PIN No. Number Name NET "GPIO_K_4_SIGNAL_0" LOC = "R4"; // 75 IO_L45P_6 NET "GPIO_K_4_SIGNAL_1" LOC = "V1"; // 90 IO_L19N_6 NET "GPIO_K_4_SIGNAL_2" LOC = "R2"; // 73 IO_L46P_6 NET "GPIO_K_4_SIGNAL_3" LOC = "V3"; // 92 IO_L03N_6_VREF_6 NET "GPIO_K_4_SIGNAL_4" LOC = "P4"; // 69 IO_L49P_6 NET "GPIO_K_4_SIGNAL_5" LOC = "W1"; // 96 IO_L04N_6 NET "GPIO_K_4_SIGNAL_6" LOC = "P2"; // 67 IO_L51P_6 NET "GPIO_K_4_SIGNAL_7" LOC = "Y1"; // 98 IO_L02N_6_VRP_6 NET "GPIO_K_4_SIGNAL_8" LOC = "N4"; // 63 IO_L54P_6 NET "GPIO_K_4_SIGNAL_9" LOC = "N3"; // 64 IO_L54N_6 NET "GPIO_K_4_SIGNAL_10" LOC = "N2"; // 61 IO_L91P_6 NET "GPIO_K_4_SIGNAL_11" LOC = "N1"; // 62 IO_L91N_6 NET "GPIO_K_4_SIGNAL_12" LOC = "M4"; // 57 IO_L94P_6 NET "GPIO_K_4_SIGNAL_13" LOC = "M3"; // 58 IO_L94N_6 NET "GPIO_K_4_SIGNAL_14" LOC = "M2"; // 55 IO_L96P_6 NET "GPIO_K_4_SIGNAL_15" LOC = "M1"; // 56 IO_L96N_6 // // GPIO Connector K5 All H-Clk to MEZ-456 nets for K5 are on FSI J3 // // MEZ-456 FSI FPGA // FPGA J3 Pin Signal // GPIO K5 Signal U1 PIN No. Number Name NET "GPIO_K_5_SIGNAL_0" LOC = "AA11"; // 45 IO_L96N_5_GCLK7S NET "GPIO_K_5_SIGNAL_1" LOC = "W11"; // 46 IO_L95N_5_GCLK5S NET "GPIO_K_5_SIGNAL_2" LOC = "Y11"; // 43 IO_L96P_5_GCLK6P NET "GPIO_K_5_SIGNAL_3" LOC = "V11"; // 44 IO_L95P_5_GCLK4P NET "GPIO_K_5_SIGNAL_4" LOC = "AA10"; // 39 IO_L93P_5 NET "GPIO_K_5_SIGNAL_5" LOC = "AB10"; // 40 IO_L93N_5 NET "GPIO_K_5_SIGNAL_6" LOC = "AA9"; // 37 IO_L54P_5 NET "GPIO_K_5_SIGNAL_7" LOC = "AB9"; // 38 IO_L54N_5 NET "GPIO_K_5_SIGNAL_8" LOC = "W10"; // 33 IO_L92P_5 NET "GPIO_K_5_SIGNAL_9" LOC = "Y10"; // 34 IO_L92N_5 NET "GPIO_K_5_SIGNAL_10" LOC = "AA8"; // 31 IO_L51P_5 NET "GPIO_K_5_SIGNAL_11" LOC = "AB8"; // 32 IO_L51N_5_VREF_5 NET "GPIO_K_5_SIGNAL_12" LOC = "W9"; // 27 IO_L52P_5 NET "GPIO_K_5_SIGNAL_13" LOC = "Y9"; // 28 IO_L52N_5 NET "GPIO_K_5_SIGNAL_14" LOC = "AA7"; // 25 IO_L22P_5 NET "GPIO_K_5_SIGNAL_15" LOC = "AB7"; // 26 IO_L22N_5 // // GPIO Connector K6 All H-Clk to MEZ-456 nets for K6 are on FSI J3 // // MEZ-456 FSI FPGA // FPGA J3 Pin Signal // GPIO K6 Signal U1 PIN No. Number Name NET "GPIO_K_6_SIGNAL_0" LOC = "W8"; // 23 IO_L49P_5 NET "GPIO_K_6_SIGNAL_1" LOC = "Y8"; // 24 IO_L49N_5 NET "GPIO_K_6_SIGNAL_2" LOC = "AA6"; // 21 IO_L19P_5 NET "GPIO_K_6_SIGNAL_3" LOC = "AB6"; // 22 IO_L19N_5 NET "GPIO_K_6_SIGNAL_4" LOC = "W7"; // 17 IO_L21P_5 NET "GPIO_K_6_SIGNAL_5" LOC = "Y7"; // 18 IO_L21N_5_VREF_5 NET "GPIO_K_6_SIGNAL_6" LOC = "AA5"; // 15 IO_L04P_5_VREF_5 NET "GPIO_K_6_SIGNAL_7" LOC = "AB5"; // 16 IO_L04N_5 NET "GPIO_K_6_SIGNAL_8" LOC = "W6"; // 11 IO_L06P_5 NET "GPIO_K_6_SIGNAL_9" LOC = "Y6"; // 12 IO_L06N_5 NET "GPIO_K_6_SIGNAL_10" LOC = "AA4"; // 9 IO_L02P_5_D7 NET "GPIO_K_6_SIGNAL_11" LOC = "AB4"; // 10 IO_L02N_5_D6 NET "GPIO_K_6_SIGNAL_12" LOC = "W5"; // 5 IO_L03P_5_D5_ALT_VRN_5 NET "GPIO_K_6_SIGNAL_13" LOC = "Y5"; // 6 IO_L03N_5_D4_ALT_VRP_5 NET "GPIO_K_6_SIGNAL_14" LOC = "AA3"; // 3 IO_L01P_5_CS_B NET "GPIO_K_6_SIGNAL_15" LOC = "Y4"; // 4 IO_L01N_5_RDWR_B // // GPIO Connector K7 All H-Clk to MEZ-456 nets for K7 are on FSI J3 // // MEZ-456 FSI FPGA // FPGA J3 Pin Signal // GPIO K7 Signal U1 PIN No. Number Name NET "GPIO_K_7_SIGNAL_0" LOC = "AA20"; // 97 IO_L01P_3 NET "GPIO_K_7_SIGNAL_1" LOC = "AB19"; // 98 IO_L01N_4_BUSY_DOUT NET "GPIO_K_7_SIGNAL_2" LOC = "Y18"; // 95 IO_L03P_4_D3_ALT_VRN_4 NET "GPIO_K_7_SIGNAL_3" LOC = "W18"; // 96 IO_L03N_4_D2_ALT_VRP_4 NET "GPIO_K_7_SIGNAL_4" LOC = "AB18"; // 91 IO_L04P_4 NET "GPIO_K_7_SIGNAL_5" LOC = "AA18"; // 92 IO_L04N_4_VREF_4 NET "GPIO_K_7_SIGNAL_6" LOC = "Y17"; // 89 IO_L05P_4_VRN_4 NET "GPIO_K_7_SIGNAL_7" LOC = "W17"; // 90 IO_L05N_4_VRP_4 NET "GPIO_K_7_SIGNAL_8" LOC = "AB17"; // 85 IO_L06P_4 NET "GPIO_K_7_SIGNAL_9" LOC = "AA17"; // 86 IO_L06N_4 NET "GPIO_K_7_SIGNAL_10" LOC = "Y16"; // 83 IO_L21P_4_VREF_4 NET "GPIO_K_7_SIGNAL_11" LOC = "W16"; // 84 IO_L21N_4 NET "GPIO_K_7_SIGNAL_12" LOC = "AB16"; // 79 IO_L22P_4 NET "GPIO_K_7_SIGNAL_13" LOC = "AA16"; // 80 IO_L22N_4 NET "GPIO_K_7_SIGNAL_14" LOC = "Y15"; // 77 IO_L24P_4 NET "GPIO_K_7_SIGNAL_15" LOC = "W15"; // 78 IO_L24N_4 // // GPIO Connector K8 All H-Clk to MEZ-456 nets for K8 are on FSI J3 // // MEZ-456 FSI FPGA // FPGA J3 Pin Signal // GPIO K8 Signal U1 PIN No. Number Name NET "GPIO_K_8_SIGNAL_0" LOC = "AB15"; // 75 IO_L49P_4 NET "GPIO_K_8_SIGNAL_1" LOC = "AA15"; // 76 IO_L49N_4 NET "GPIO_K_8_SIGNAL_2" LOC = "Y14"; // 73 IO_L52P_4 NET "GPIO_K_8_SIGNAL_3" LOC = "W14"; // 74 IO_L52N_4 NET "GPIO_K_8_SIGNAL_4" LOC = "AB14"; // 69 IO_L54P_4 NET "GPIO_K_8_SIGNAL_5" LOC = "AA14"; // 70 IO_L54N_4 NET "GPIO_K_8_SIGNAL_6" LOC = "Y13"; // 67 IO_L92P_4 NET "GPIO_K_8_SIGNAL_7" LOC = "W13"; // 68 IO_L92N_4 NET "GPIO_K_8_SIGNAL_8" LOC = "AB13"; // 63 IO_L93P_4 NET "GPIO_K_8_SIGNAL_9" LOC = "AA13"; // 64 IO_L93N_4 NET "GPIO_K_8_SIGNAL_10" LOC = "V13"; // 61 IO_L91P_4 NET "GPIO_K_8_SIGNAL_11" LOC = "U13"; // 62 IO_L91N_4_VREF_4 NET "GPIO_K_8_SIGNAL_12" LOC = "AB12"; // 57 IO_L96P_4_GCLK0P NET "GPIO_K_8_SIGNAL_13" LOC = "Y12"; // 58 IO_L95P_4_GCLK2P NET "GPIO_K_8_SIGNAL_14" LOC = "AA12"; // 55 IO_L96N_4_GCLK1S NET "GPIO_K_8_SIGNAL_15" LOC = "W12"; // 56 IO_L95N_4_GCLK3S // // GPIO Connector K9 All H-Clk to MEZ-456 nets for K9 are on FSI J4 // // MEZ-456 FSI FPGA // FPGA J4 Pin Signal // GPIO K9 Signal U1 PIN No. Number Name NET "GPIO_K_9_SIGNAL_0" LOC = "M20"; // 45 IO_L96P_3 NET "GPIO_K_9_SIGNAL_1" LOC = "M21"; // 46 IO_L96N_3 NET "GPIO_K_9_SIGNAL_2" LOC = "M18"; // 43 IO_L94P_3 NET "GPIO_K_9_SIGNAL_3" LOC = "M19"; // 44 IO_L94N_3 NET "GPIO_K_9_SIGNAL_4" LOC = "N21"; // 39 IO_L91P_3 NET "GPIO_K_9_SIGNAL_5" LOC = "N22"; // 40 IO_L91N_3 NET "GPIO_K_9_SIGNAL_6" LOC = "N19"; // 37 IO_L54P_3 NET "GPIO_K_9_SIGNAL_7" LOC = "N20"; // 38 IO_L54N_3 NET "GPIO_K_9_SIGNAL_8" LOC = "P21"; // 33 IO_L51P_3 NET "GPIO_K_9_SIGNAL_9" LOC = "P22"; // 34 IO_L51N_3_VREF_3 NET "GPIO_K_9_SIGNAL_10" LOC = "P19"; // 31 IO_L49P_3 NET "GPIO_K_9_SIGNAL_11" LOC = "P20"; // 32 IO_L49N_3 NET "GPIO_K_9_SIGNAL_12" LOC = "R21"; // 27 IO_L48P_3 NET "GPIO_K_9_SIGNAL_13" LOC = "R22"; // 28 IO_L48N_3 NET "GPIO_K_9_SIGNAL_14" LOC = "R19"; // 25 IO_L46P_3 NET "GPIO_K_9_SIGNAL_15" LOC = "R20"; // 26 IO_L46N_3 // // GPIO Connector K10 All H-Clk to MEZ-456 nets for K10 are on FSI J4 // // MEZ-456 FSI FPGA // FPGA J4 Pin Signal // GPIO K10 Signal U1 PIN No. Number Name NET "GPIO_K_10_SIGNAL_0" LOC = "T21"; // 23 IO_L43P_3 NET "GPIO_K_10_SIGNAL_1" LOC = "T22"; // 24 IO_L43N_3 NET "GPIO_K_10_SIGNAL_2" LOC = "T19"; // 21 IO_L24P_3 NET "GPIO_K_10_SIGNAL_3" LOC = "T20"; // 22 IO_L24N_3 NET "GPIO_K_10_SIGNAL_4" LOC = "U21"; // 17 IO_L22P_3 NET "GPIO_K_10_SIGNAL_5" LOC = "U22"; // 18 IO_L22N_3 NET "GPIO_K_10_SIGNAL_6" LOC = "U19"; // 15 IO_L21P_3 NET "GPIO_K_10_SIGNAL_7" LOC = "U20"; // 16 IO_L21N_3_VREF_3 NET "GPIO_K_10_SIGNAL_8" LOC = "V21"; // 11 IO_L06P_3 NET "GPIO_K_10_SIGNAL_9" LOC = "V22"; // 12 IO_L06N_3 NET "GPIO_K_10_SIGNAL_10" LOC = "V19"; // 9 IO_L04P_3 NET "GPIO_K_10_SIGNAL_11" LOC = "V20"; // 10 IO_L04N_3 NET "GPIO_K_10_SIGNAL_12" LOC = "W21"; // 5 IO_L03P_3 NET "GPIO_K_10_SIGNAL_13" LOC = "W22"; // 6 IO_L03N_3_VREF_3 NET "GPIO_K_10_SIGNAL_14" LOC = "Y21"; // 3 IO_L02P_3_VRN_3 NET "GPIO_K_10_SIGNAL_15" LOC = "Y22"; // 4 IO_L02N_3_VRP_3 // // Now list the VME interface signals that are routed to the // H-Clk card via FSI connector J4. // // - To help understand these signals please refer // to the drawing of the H-Clk card's VME Interface. // // - Note that none of the VME Bus interface chips are // inverting, thus signals that are low-acive on the // bus appear low-active to the H-Clk's FPGA. // // // MEZ-456 FSI FPGA // FPGA J4 Pin Signal // VME Signal U1 PIN No. Number Name NET "OCB_ADRS(1)" LOC = "L20"; // 57 IO_L94P_2 NET "OCB_ADRS(2)" LOC = "K22"; // 61 IO_L91P_2 NET "OCB_ADRS(3)" LOC = "K20"; // 63 IO_L54P_2 NET "OCB_ADRS(4)" LOC = "K19"; // 64 IO_L54N_2 NET "OCB_ADRS(5)" LOC = "K21"; // 62 IO_L91N_2 NET "OCB_ADRS(6)" LOC = "L19"; // 58 IO_L94N_2 NET "OCB_ADRS(7)" LOC = "L21"; // 56 IO_L96N_2 NET "OCB_ADRS(8)" LOC = "L22"; // 55 IO_L96P_2 NET "OCB_ADRS(9)" LOC = "H21"; // 74 IO_L46N_2 NET "OCB_ADRS(10)" LOC = "J19"; // 70 IO_L49N_2 NET "OCB_ADRS(11)" LOC = "J21"; // 68 IO_L51N_2 NET "OCB_ADRS(12)" LOC = "J22"; // 67 IO_L51P_2_VREF_2 NET "OCB_ADRS(13)" LOC = "J20"; // 69 IO_L49P_2 NET "OCB_ADRS(14)" LOC = "H22"; // 73 IO_L46P_2 NET "OCB_ADRS(15)" LOC = "H20"; // 75 IO_L45P_2_VREF_2 NET "OCB_ADRS(16)" LOC = "G21"; // 78 IO_L43N_2 NET "OCB_ADRS(17)" LOC = "G20"; // 79 IO_L24P_2 NET "OCB_ADRS(18)" LOC = "F22"; // 83 IO_L21P_2_VREF_2 NET "OCB_ADRS(19)" LOC = "F20"; // 85 IO_L19P_2 NET "OCB_ADRS(20)" LOC = "E21"; // 90 IO_L06N_2 NET "OCB_ADRS(21)" LOC = "E19"; // 92 IO_L04N_2 NET "OCB_ADRS(22)" LOC = "D21"; // 96 IO_L03N_2 NET "OCB_ADRS(23)" LOC = "D22"; // 95 IO_L03P_2_VREF_2 NET "LTCHD_AM(0)" LOC = "E20"; // 91 IO_L04P_2 NET "LTCHD_AM(1)" LOC = "E22"; // 89 IO_L06P_2 NET "LTCHD_AM(2)" LOC = "F19"; // 86 IO_L19N_2 NET "LTCHD_AM(3)" LOC = "F21"; // 84 IO_L21N_2 NET "LTCHD_AM(4)" LOC = "G22"; // 77 IO_L43P_2 NET "LTCHD_AM(5)" LOC = "C22"; // 97 IO_L01P_2 NET "LTCHD_WRITE_B" LOC = "C21"; // 98 IO_L01N_2 NET "LTCHD_IACK_B" LOC = "G19"; // 80 IO_L24N_2 // // Now list the VME interface signals that are routed to the // H-Clk card via FSI connector J1: // // - To help understand these signals please refer // to the drawing of the H-Clk card's VME Interface. // // - Note that none of the VME Bus interface chips are // inverting, thus signals that are low-acive on the // bus appear low-active to the H-Clk's FPGA. // // // MEZ-456 FSI FPGA // FPGA J1 Pin Signal // VME Signal U1 PIN No. Number Name NET "DRV_DTACK_B" LOC = "B19"; // 3 IO_L01P_1 NET "RCVD_DS1_B" LOC = "D18"; // 5 IO_L02P_1 NET "RCVD_AS_B" LOC = "B14"; // 31 IO_L54P_1 NET "RCVD_SYSRESET_B" LOC = "B16"; // 21 IO_L22P_1 NET "RCVD_GEO_B(0)" LOC = "B18"; // 9 IO_L03P_1_VRN_1 NET "RCVD_GEO_B(1)" LOC = "D17"; // 11 IO_L04P_1_VREF_1 NET "RCVD_GEO_B(2)" LOC = "B17"; // 15 IO_L05P_1 NET "RCVD_GEO_B(3)" LOC = "D16"; // 17 IO_L21P_1 NET "RCVD_GEO_B(4)" LOC = "D15"; // 23 IO_L49P_1 NET "OCB_DATA(0)" LOC = "A18"; // 10 IO_L03N_1_VRP_1 NET "OCB_DATA(1)" LOC = "A17"; // 16 IO_L05N_1 NET "OCB_DATA(2)" LOC = "A16"; // 22 IO_L22N_1 NET "OCB_DATA(3)" LOC = "B15"; // 26 IO_L51P_1 NET "OCB_DATA(4)" LOC = "A14"; // 32 IO_L54N_1 NET "OCB_DATA(5)" LOC = "A13"; // 38 IO_L93N_1 NET "OCB_DATA(6)" LOC = "D13"; // 33 IO_L92P_1 NET "OCB_DATA(7)" LOC = "D14"; // 27 IO_L52P_1 NET "OCB_DATA(8)" LOC = "C18"; // 6 IO_L02N_1 NET "OCB_DATA(9)" LOC = "C17"; // 12 IO_L04N_1 NET "OCB_DATA(10)" LOC = "C16"; // 18 IO_L21N_1_VREF_1 NET "OCB_DATA(11)" LOC = "C15"; // 24 IO_L49N_1 NET "OCB_DATA(12)" LOC = "C14"; // 28 IO_L52N_1 NET "OCB_DATA(13)" LOC = "C13"; // 34 IO_L92N_1 NET "OCB_DATA(14)" LOC = "C12"; // 40 IO_L94N_1 NET "OCB_DATA(15)" LOC = "B13"; // 37 IO_L93P_1 // // Now list the signals that control the VME Interface Chips // // - To help understand these signals please refer // to the drawing of the H-Clk card's VME Interface. // // - The DATA_BUF_DIR signal comes from the FPGA and sets the // direction of the VME Data Bus Transceiver U304. When // DATA_BUF_DIR is HI the the transceiver sends H-Clk card // data to the bus, i.e. a VME READ Cycle. When DATA_BUF_DIR // is LOW the transceiver receives data from the bus, i.e. // a VME WRITE Cycle. // // - The DATA_BUF_ENB_B signal comes from the FPGA and enables // the output drivers of the VME Data Bus Transceiver U304. // Which side of the transceiver has its output drivers // enabled is controlled by the DATA_BUF_DIR signal. // When DATA_BUF_ENB_B is voltage hi - neither side's output // drivers are enabled. // // - The VME_LTCH_CLK signal comes from the FPGA and controls // whether or not the bus receiver chips U301 and U302 are // transparent (i.e. follow their inputs) or hold. When // VME_LTCH_CLK is HI the outputs from U301 and U302 follow // their inputs. When VME_LTCH_CLK is LOW the outputs from // these bus receives hold at the state that existed at the // time when VME_LTCH_CLK made its transition from Hi to Low. // // // MEZ-456 FSI FPGA // VME Interface FPGA J1 Pin Signal // Control Signals U1 PIN No. Number Name NET "DATA_BUF_DIR" LOC = "A19"; // J1-4 IO_L01N_1 NET "DATA_BUF_ENB_B" LOC = "A15"; // J1-25 IO_L51N_1_VREF_1 NET "VME_LTCH_CLK" LOC = "H19"; // J4-76 IO_L45N_2 // // Now list the FPGA signals that operate the Front Panel LEDs, // the Front Panel Switch S1, the J5 DeBug connector, and the 4 // FPGA signals that are just routed to vias on the H-Clk card. // All of these signals route to the H-Clk card via // FSI connector J1. // // - To help understand the following signals please refer // to the drawing of the H-Clk card's LEDs and Pushbuttons. // // // LED, Switch, MEZ-456 FSI FPGA // Debug & Spare FPGA J1 Pin Signal // Signals U1 PIN No. Number Name NET "LED_2L_ON_B" LOC = "B5"; // 92 IO_L03N_0_VRP_0 NET "LED_2C_ON_B" LOC = "B4"; // 98 IO_L01N_0 NET "LED_2R_ON_B" LOC = "C5"; // 96 IO_L02P_0 NET "LED_1L_ON_B" LOC = "A5"; // 91 IO_L03P_0_VRN_0 NET "LED_1C_ON_B" LOC = "D6"; // 90 IO_L04N_0_VREF_0 NET "LED_1R_ON_B" LOC = "C6"; // 89 IO_L04P_0 NET "SWTCH_1_NC" LOC = "C4"; // 95 IO_L02N_0 NET "SWTCH_1_NO" LOC = "A4"; // 97 IO_L01P_0 NET "DEBUG_01" LOC = "C9"; // 73 IO_L52P_0 NET "DEBUG_02" LOC = "D9"; // 74 IO_L52N_0 NET "DEBUG_03" LOC = "A8"; // 75 IO_L49P_0 NET "DEBUG_04" LOC = "B8"; // 76 IO_L49N_0 NET "DEBUG_05" LOC = "C8"; // 77 IO_L24P_0 NET "DEBUG_06" LOC = "D8"; // 78 IO_L24N_0 NET "DEBUG_07" LOC = "A7"; // 79 IO_L22P_0 NET "DEBUG_08" LOC = "B7"; // 80 IO_L22N_0 NET "SPARE_SIG_V13" LOC = "B6"; // 86 IO_L05N_0 NET "SPARE_SIG_V14" LOC = "D7"; // 84 IO_L21N_0 NET "SPARE_SIG_V15" LOC = "B9"; // 70 IO_L54N_0 NET "SPARE_SIG_V16" LOC = "E10"; // 62 IO_L91N_0_VREF_0 // // Now list the signals involved with the GPS receiver // and the 40 MHz clock generation. All of these signals // route to the H-Clk card via FSI connector J1. Some of // these signals are LVDS pairs. // // To help understand the following signals please refer // to the drawings of the H-Clk card's: // // - GPS Serial Data connection // - Receivers for the GPS 10 MHz and 1 PPS signals // - the FPGA's Clock inputs and PLL pre-scaler // - the 40 MHz PLL // - the Access Connector clock type signals // // // MEZ-456 FSI FPGA // FPGA J1 Pin Signal // GPS & Clock Signals U1 PIN No. Number Name // GPS Serial Data NET "SERIAL_TO_FPGA" LOC = "C7"; // 83 IO_L21P_0_VREF_0 NET "SERIAL_FROM_FPGA" LOC = "A6"; // 85 IO_L05P_0 // 10 MHz from GPS Receiver LVDS NET "DRVN_10_MHZ_DIR" LOC = "C11"; // 58 IO_L95P_0_GCLK6S NET "DRVN_10_MHZ_CMP" LOC = "D11"; // 56 IO_L95N_0_GCLK7P // 1 PPS from GPS Receiver LVDS NET "DRVN_1_PPS_DIR" LOC = "A11"; // 57 IO_L96P_0_GCLK4S NET "DRVN_1_PPS_CMP" LOC = "B11"; // 55 IO_L96N_0_GCLK5P // 40 MHz Clock from the PLL Output LVDS NET "CLK_40_DIR_FOR_FPGA" LOC = "D12"; // 43 IO_L95P_1_GCLK0S NET "CLK_40_CMP_FOR_FPGA" LOC = "E12"; // 45 IO_L95N_1_GCLK1P // Reference Clock to the PLL LVDS NET "PLL_REF_DIR" LOC = "C10"; // 67 IO_L92P_0 NET "PLL_REF_CMP" LOC = "D10"; // 68 IO_L92N_0 // Feedback Clock to the PLL LVDS NET "PLL_FBK_DIR" LOC = "A10"; // 63 IO_L93P_0 NET "PLL_FBK_CMP" LOC = "B10"; // 64 IO_L93N_0 // Access Conn Clock Signal to FPGA LVDS NET "EXT_FPGA_CLK_BUF_OUT_DIR" LOC = "F13"; // 44 IO_L96P_1_GCLK2S NET "EXT_FPGA_CLK_BUF_OUT_CMP" LOC = "F12"; // 46 IO_L96N_1_GCLK3P // FPGA signal to Access Connector LVDS Driver NET "FPGA_BUFD_LVDS_DRV_IN" LOC = "B12"; // 39 IO_L94P_1_VREF_1 // // FSI connector J1 has 2 pins that are connected to the FPGA on // the MEZ-456 card but are not used on the H-Clk card. They are // FSI connector J1 pins 61 and 69. They are FPGA pins: // // FSI J1 pin 61 runs to Mez-456 U1-F10 IO_L91P_0 // FSI J1 pin 69 runs to Mez-456 U1-A9 IO_L54P_0 // // This is the end of the list of FPGA signals // that appear on the H-Clk card. // There are a five additional FPGA signals, that appear only // on the MEZ-456 card, that the user could have access to if // necessary. These five signals appear on the MEZ-456 card's // J5 "access" connector. // // MEZ-456 FSI FPGA // MEZ-456 Card FPGA Pin Signal // Access Conn Signals U1 PIN No. Number Name NET "MEZ_ACCESS_PIN_22" LOC = "E11"; // -- IO_L94N_0_VREF_0 NET "MEZ_ACCESS_PIN_24" LOC = "M5"; // -- IO_L93N_6_VREF_6 NET "MEZ_ACCESS_PIN_26" LOC = "M6"; // -- IO_L93P_6 NET "MEZ_ACCESS_PIN_28" LOC = "V12"; // -- IO_L94P_4 NET "MEZ_ACCESS_PIN_30" LOC = "U12"; // -- IO_L94N_4_VREF_4 // --------------------------------------------------------------------- // End of H-Clk FPGA Pinout Constraints // ---------------------------------------------------------------------