HAWC Time ------------- Orig Ver 29-OCT-2010 Current Ver 18-Oct-2011 The receiver that we want is the NAVSYNC "CW46". This has the CW25-TIM receiver plus dc/dc power converter and signal drivers all inside a weatherproff IP67 case. Power requirement is: 5 to 18 Volts DC at < 5 Watts. It looks like all the default setting will be OK to start with: You get UART #1 connection by default which is the NMEA 0183 stream at a default 38400 baud 8 bits, no parity, no handshake. This is about 3,840 characters per second. The GPZDA message for example is about 50 characters long and thus takes about 0.013 seconds to transmit. Once locket you get 10 MHz and 1 pps by default. The 1 pps is 100 usec wide and the rising edge marks the top of the second. "Bulgin" connector NMEA Messages ------------- There are 2 types of messages: "Approved" and "Proprietary". All NMEA sentences begin with a $, are delimited with commas, and end with a CR LF pair. Approved sentences have 5 defined characters after the $ which in 2 characters define the kind of sender (GP for GPS) and then in 3 characters define the type of information. The Approved NMEA message type that looks interesting is: GPZDA which gives Data and Time. Proprietary sentences are indicated by a P after the $ sign as the first of the 5 characters. The next 3 characters indicate the manufacturer. The 5th character indicates the proprietary message type. The Proprietary type message that looks interesting is: POLYT which gives the Date and Time. 8.2.1.7 GPZDA - UTC Time and Date This message transfers UTC Time and Date. Since the latency of preparing and transferring the message is variable, and the time does not refer to a particular position fix, the seconds precision is reduced to 2 decimal places. $GPZDA,hhmmss.sss,dd,mm,yyyy,Int,Unsigned*cs Name Description $GPZDA NMEA sentence header (Time and Date) hhmmss.sss UTC Time in hours, minutes, seconds. dd UTC day mm UTC month yyyy UTC year Int Unsigned Local zone hours Int Unsigned Local zone minutes kph Speed over ground (kph) K Kilometers per hour fixed field cs Message checksum in hexadecimal 8.2.1.5 GPRMC - Recommended Minimum data The Recommended Minimum sentence is defined by NMEA for GPS/Transit system data. $GPRMC,hhmmss.sss,status,latitude,N,Hemisphere,longitude,E, spd,cmg,ddmmyy,mv,mvd,Mode*cs Name Description $GPRMC NMEA sentence header (Recommended Minimum Sentence) hhmmss.sss UTC Time in hours, minutes, seconds. status Status:V=navigation receiver warning, A=data valid Latitude User datum latitudedegrees, minutes, decimal minutes format (ddmm.mmmmmm) N Hemisphere: N = North, or S = South Longitude User datum longitude degrees, minutes, decimal minutes format (dddmm.mmmmmm) E Longitude Direction: E = East, W = West spd Speed over ground (knots). cmg Course made good ddmmyy Date in Day, Month Year format mv Magnetic variation mvd Magnetic variation direction Mode Mode Indicator: D = Valid, Differential, A = Valid, Autonomous, E = Invalid, Estimated, N = Invalid, Not Valid cs Message checksum in hexadecimal Proprietary NMEA Messages 8.2.1.8 POLYT - Time of Day $POLYT,hhmmss.sss,ddmmyy, UTC_TOW ,week, GPS_TOW, Clk_B , Clk_D ,PG,LocalTTag,BAcc,TAcc,BLANK*cs Name Description $POLYT Navsync Proprietary NMEA sentence header (Position Data) hhmmss.sss UTC Time in hours, minutes, seconds and decimal seconds format. ddmmyy Date in day, month, year format. UTC_TOW UTC Time of Week (seconds with microseconds resolution) week GPS week number (continues beyond 1023) GPS_TOW GPS Time of Week (seconds with microseconds resolution) Clk_B Receiver clock Bias (nanoseconds) Clk_D Receiver clock Drift (nanoseconds/second) PG 1PPS Granularity (nanoseconds) LocalTTag Local receiver time-tag since start-up [msec] BAcc Bias Accuracy TAcc Time Accuracy cs Message checksum in hexadecimal Commands to the Receiver ------------------------ 9.1 NMEA Configuration Query ($PRTHQ, UxOP): The command takes the form $PRTHQ,UxOP where x is a port number. On the CW25 platform, the port number is always between 1 and 3 inclusive. The remainder of the strings is of the form $PRTHR,UxOP,GLL=1,GSV=4,PLT=1 where x is the port number for which the information was requested. The specific contents supported are dependent on the NMEA sentences supported by the system. Only the settings which are to be altered need to be listed. A NMEA checksum of the form *4D is appended to the output string. The list of currently supported NMEA sentences is as shown below. To turn a sentence output off completely, simply specify zero as the duration for that command. Subsequent commands may reassign an output period to sentences disabled in this way, effectively re-enabling the output sentence. This command also supports a shortcut by means of an ALL specifier. When this is encountered, the period specified is applied to all sentences. An example of this is shown below, where every message output on port1 will be printed at a 5-second period with the exception of the GPRMC sentence, which will be output every second, and the POLYT sentence, which will be disabled. $PRTHS, U1OP, ALL=5, RMC=1. PLT=0 An example response string is shown below. In this example, all sentences are output every second, except GPGSV, which is output every three seconds, and POLYT, which is not output at all (i.e. the sentence output is disabled). $PRTHR,U1OP,GLL=1,RMC=1,VTG=1,GGA=1,GSA=1,GSV=3,PLT=0,PLP=1,PLS=1,PLI=1*0C Difference between Query and Configuration Set ========================================================================= 12-NOV-10 FPGA on a Mezzanine Theory Put on the Mezzanine: FPGA, power supplies from +5V, Configuration PROMs, PMC and PTA NIM A AMP part #AMP120527 64 position surface mount connector is used to make the physical connection. The XC2V1000-FG456 has about 324 User I/Os The PMC has four 50 pin SAMTEC FTS connectors that can be used to connect to a PIXEL DETECTOR PROJECT Programmable Mezzanine Card (PMC) Document # ESE-PIX-20001101 ========================================================================= 19-NOV-10 Configuration Memory device could be XC18V04 series 44-TFQFP pkg about $26 each non-stock at DK but current I think. On Mez power regulators could be National LMS 1587 3.3 1.5 Digi-Key does have Bulgin 10 pin series connectors in stock. Will wait to order any until we know what is in the CW46 kit. |------|-------------|-------|-----|---|----|----|---|--------------| | S.No.|NOM_CATALOGUE| Rep |Value|TOL|Powe|Tens|Qty| FORME | |======|=============|=======|=====|===|====|====|===|==============| | 12|LMS1587IS_3V3| RG2 | | | | | 1| TO263 | |------|-------------|-------|-----|---|----|----|---|--------------| | 13|LMS1587CS_1V5| RG1 | | | | | 1| TO263 | |------|-------------|-------|-----|---|----|----|---|--------------| | 1|XC18V04 FP | IC10, | | | | | 2| VQFP44 | |------|-------------|-------|-----|---|----|----|---|--------------| | 11|MAX3222E P | IC1 | | | | | 1| DIP18_3 | |------|-------------|-------|-----|---|----|----|---|--------------| Dalas DS276S RS-232 to FPGA translator or is it LMS1537 ?? The two most likely Samtec zif connectors are the dual row 40 pins per row or 50 pins per row connectors, i.e. 80 or 100 contacts. These are part numbers: FSI-140-06-L-D-E-AD FSI-150-06-L-D-E-AD FSI-140-10-L-D-E-AD FSI-150-10-L-D-E-AD The dual 40 and 50 pin connectors each have 3 mounting screws and 2 guide pins. The overall length is: 62.09mm or 72.09mm The space between an end mounting hole and the center mounting hole is: 27.62mm or 32.62mm The center to center distance between the end mounting screws is: 45.24mm or 55.24mm The diameter of the guide pins is 1.07mm I think that the center of the guide pin is at the center of the last electrical contact. The connector is about 9mm wide and either 3mm, 6mm, or 10mm stack height. Files samtec_fsi_doc_3.pdf and samtec_fsi_doc_2.pdf appear to be the correct layout for the 6 or 10mm version. Files samtec_fsi_doc_4.pdf and samtec_fsi_doc_2.pdf appear to be the correct layout for the 3 version. The wipe contact pads are: 0.61mm wide x 3.55mm long They start 0.89mm from the center line --> 8.88mm overall width The pad center to center around the middle screw is 9.00 mm The fixed contact pads are: 0.62 mm wide x 1.13mm long They start 4.39mm from the center line --> 11.04mm overall width The current general idea is: wipe contacts pads on the Mez-456 and fixed contact pads on the main card. Mount the FPGA between the two cards. Current probable connector is: FSI-150-06-L-D-E-AD $13.41 each but not in stock at DK. The LMS1587 regulators look OK at either 3A or 5A. They come from either National or Linear Tech. The overall foot print is about 11m x 16mm for the SMD package (plus heat sink area). Board size about 80mm x 80mm about 400 connections All 3.3V I/O P.S. Regulators on Board 6 layer Mez-456 Going off card: I/Os, Initiate Config (jumper enabled) Config Done, JTAG, Prom Config lines (jumper select) LEDs connector footprint on the same side as the FPGA. Basically LVDS I/O Terminators for receiving at FPGA ? Global Clock Lines 20-NOV-10 --------- It would be an easier layout (less vias) to put the wipe contacts on the same side as the FPGA and all the other parts - but that means no air flow - and this will have linear regulators on the Mez. So the more rational idea is to use the 3mm stand off connectors and put the wipe pads on the back of the Mez-456. Thus the part number of the connector is: FSI-150-03-G-D-E-AD For this 100 contact 3mm thick connector the overal length is 72.09mm the distance from the center to the end hole is 32.62mm the main body width is 8,76mm overall body width is 10.04mm the fixed contact pads are 0.61mm wide 1.13mm long the fixed contact pads start 4.13mm out from the CL --> 10.52mm overall fixed contact pad layout width the wipe contact pads are 0.61mm wide 3.55mm long the wipe contact pads start 0.89mm out from the CL --> 8.88mm overall wipe contact pad layout width Making a courtyard of 74mm x 12mm for this connector and putting 4 of them around the 4 side of a square card makes the minimum size of the square card: 98mm on a side and gives a clear space of 74mm x 74mm inside the connectors --> 5476 sqmm clear space. If you make it a rectangulare card then it is 98mm x 74mm and has a clear space of 50mm x 74mm inside the connectors --> 3700 sqmm clear space. The fg456 package is about 25mm x 25mm 625 sqmm The regulators are about 11m x 16mm each 352 sqmm for both The configuration prom is about 14mmx14mm 196 sqmm ------ 1173 sqmm absolute minimum i.e. can't prove that you can't do a Mez-456 layout. UART The default baud rate is 38,400 I *think* that I recall from 400 years ago that this means 1/38400 = 26.04 usec per bit and 11 bits per character (1 start, 8 data, 2 stop, no parity) --> 3491 characters per second. An 8x clock rate for UART would require 8 x 38,400 = 307,200 Hz and this is 40 MHz divided by 130.21. 307,200 is 1/8 of 2,457,600 Hz - is that the normal old rock frequency ? 16 x 38,400 = 614,400 Hz and that is 40 MHz divised by 65.104. 21-NOV-10 --------- Recall the basic Inputs and Outputs of the HCLK module: LEDs: All power OK, GPS Locked, GPS Receiver: 10 MHz, 1 pps, and RS-232 ASCII all from the receiver Power and RS-232 ASCII to the receiver Outputs: 100 Hz "triggers" to the Scaler DAQ ECL/LVDS ? How Many ? 40 MHz clock to the TDCs, Is this the fanout for this signal ? ? kHz "trigger" for Continuous TDC DAQ Time Code pulses to TDCs for timestamp readout LVDS Level, 2 copies Inputs: ?? VME: ?? Backup Power: ?? Decoding the Approved NMEA Time Message 8.2.1.7 GPZDA - UTC Time and Date This message transfers UTC Time and Date. Since the latency of preparing and transferring the message is variable, and the time does not refer to a particular position fix, the seconds precision is reduced to 2 decimal places. $GPZDA,hhmmss.sss,dd,mm,yyyy,Int,Unsigned*cs Name Description $GPZDA NMEA sentence header (Time and Date) hhmmss.sss UTC Time in hours, minutes, seconds. dd UTC day mm UTC month yyyy UTC year Int Unsigned Local zone hours Int Unsigned Local zone minutes kph Speed over ground (kph) K Kilometers per hour fixed field cs Message checksum in hexadecimal So order of magnitude we need to decode 18 characters, e.g. $GPZDA,hhmmss.sss, with 9 of them fixed $GPZDA,******.***, the format fixed and the $ always indicating the start of the string. 22-NOV-10 --------- The order for the GPS "sensors" will be one CW46 and one CW46S. I believe that the Bulgin IP68 cable connector is part number: PX0410/10P/6065. GPS sensors should ship today. The CW46S will need RS-422 The pinout appears to be: Pin RS-422 Function RS-232 Function ----- ------------------ ----------------- 3 Serial Receive + Serail Receive \__ 1 Serial Receive - Not Connected / CW46S Input 2 Serial Transmit + Serial Transmit \__ 8 Serial Transmit - Not Connected / CW46S Output 4 Pulse Per Sec + Pulse Per Sec + \__ 5 Pulse Per Sec - Pulse Per Sec - / RS-422 6 10 MHz Sine Wave 3.1 Vpp into 100 Ohm 7 Cable Shiled Cable Shield 9 Supply Voltage +6.5V to +30 V about 100 mA 10 Ground and Power Supply Return Connection NAVSYNC CW46 Round Connector pinout: Looking into the connector on the CW46 Receiver 1 2 8 3 9 10 7 4 6 5 \_______ Key Note: the CW46S says data stream description says: 8 Bits, no parity, and 1 stop bit. Recall: RS-422 says a differential signal of 2V to 10V amplitude with a 100 Ohm terminator. It does not look like they ground the center of the terminator at the receiver. Look at RS-422 parts from LT: LTC2858-1 20 MHz full Dpx 5V MSOP-10 with enables LTC2858-2 0.25 MHz full Dpx 5V MSOP-10 with enables DK has these for about $3 each: LTC2858CMS-1#PBF-ND LTC2858CMS-1#PBF LTC2858IMS-2#PBF-ND LTC2858IMS-2#PBF 23-NOV-10 --------- The standard LVDS converter parts are the 65LVDS31 and 32. LVDS In/Out Buffers from National: DS15BR400, DS15BR401, DS90LV001, DS90LV004, DS10BR150, DS90LV804 LVSD to LVDS fanouts DS90LV110AT, DS90LV110T, DS91M125 Receive (in just one day) the CW46 and CW46S. A question remains, is there a difference between the RS-232 and RS-422 part numbers ? 24-NOV-10 --------- Start the HMEZ Mentor design. The CW46S has MAX3089 and MAX3232E parts in it. There is also a not-installed part that looks very much like it could be a differential driver/receiver part. There are 2 switch blocks of 4 keys each. In both blocks all 4 keys are at the number side of the block. The MAX3089 is one RS422 transmitter and one RS422 receiver both 10 MHz and enableable. It runs off of +5V power. The MAX3232E is a "true" RS-232 transceiver consisting of 2 receivers and 2 drivers. It runs off of +3V to +5.5V power. The CW46 is a different pcb. The Clk and PPS signals come directly out of the TIM-25 with no buffers. It has a MAX-3232. There are 2 switch blocks of 4 keys each. In both blocks all 4 keys are at the number side of the block. LM1089 regulator. The TIM-25 module in both receivers says the samething: CW25-TIM ISW-0002 Rev A2 2710. On both receivers it looks like the 8 wires from the 2 switch blocks go to TIM-25 pins: SW1: 1 --> 2 --> 6 RX[1] 3 --> 5 TX[1] 4 --> 4 RX[2]/EV2_IN SW2: 1 BSEL--> 2 NPOR --> 3 --> 4 --> 2 RX[0] The messages that come out of the CW46 after nominal power up are: $GPGLL $GPRMC $GPGGA $GPGSA $GPGSV $GPZDA $POLYT $POLYP $POLYS $POLYI ---> NOTE The cables are NOT interchangable between CW46 and CW46S ---> I expect that the wrong cable cold damage the sensor. 8-APR-11 -------- Pinout of the Bulgin IP68 connector on the CW46S RS232 receiver. On the CW46S-RS232 receiver (single cable receiver) pin #7 of the Bulgin IP68 is nearest the TIM-25 module on the circuit board. Of the 2 "center pins", pin #10 is nearer the TIM-25 module. Pin #1, named "Not Connected", is actually tied to pin #8 on the MAX3232, i.e. receiver #2 input. Pin #2, named "Serial Transmit rs232 Output", is tied to pin #14 on the MAX3232, i.e. transmitter #1 output. Pin #3, named "Serial Receive rs232 Input", the furthest pin from the TIM-25, is tied to pin #13 on the MAX3232, i.e. receiver #1 input. Pin #4, named "PPS+", is tied to pin #9 on the MAX3089, This signal comes from pin #38 on the TIM-25. Pin #5, named "PPS-", is tied to pin #10 on the MAX3089, This signal comes from pin #38 on the TIM-25. Pin #6, named "10M", the 10 MHz single ended output, is tied to via "J2" on the pcb, and ties up through C29, C31, L2, R18, C30, U7, C18, R17 and comes from pin #39 on the TIM-25. I think that this is a capacitor coupled output. Pin #7 the "C Shield" appears to tie to the ground plane in the CW46S receiver through a capacitor. Pin #8, named "Not Connected", is actually tied to pin #7 on the MAX3232, i.e. transmitter #2 output. Pin #9, named "Vin, is tied to the big via "S1 1" near the connector and then runs to series diode D5 and capacitor C5 before going into the switching power supply which is maybe on its own ground plane. Pin #10, named "GND", is tied to the ground plane on the CW46S pcb. The keyway on the Bulgin IP68 connector on the receiver is between pins 5 and 6. Looking at the pin entry side of this connector on the receiver, the pins are numbered CCW. The 10 MHz signal is about 3.2Vpp open circuit. Yes, it is AC coupled in the CW46S receiver so it swings about +-1.6V wrt ground. It is a rather nice sine waveform. With a 100 Ohm load it is about 2.2 Vpp. The 1 PPS signal was only looked at differentially with a 100 Ohm load. The pulse is about 100 usec wide. The positive side swings from about +1.2V and pulses up to about +3.7V. The negative side swings from about +3.7V and pulses down to about +1.3V. The positive going edge of the positive pulse side is in sync with the zero crossing of the 10 MHz signal, i.e. their positive edges happen at the same time. The 65LVDS9637 Receiver wants at its input: 100 mV min 600 mV max differential input voltage The minimum common mode voltage is 1/2 of the magnitude of the differential input voltage. The maximum common mode voltage is 2.4V minus 1/2 of the magnitude of the differential input voltage. This implies that the center of the common mode input voltage range is 1.2 Volts. The test circuit shows inputs of 1.0 and 1.4 Volts. 25-NOV-10 --------- Run the CW46S at home so that it can see the sky. From inisde the front room I get e.g. $GPGLL,4244.046205,N,08428.277587,W,010441.023,A,A*47 $GPRMC,010441.023,A,4244.046205,N,08428.277587,W,0.021,351.81,271110,,,A*49 $GPGGA,010441.023,4244.046205,N,08428.277587,W,1,8,1.42,258.183,M,-34.241,M,,*65 $GPGSA,A,3,15,21,09,03,27,22,26,18,,,,,2.25,1.42,1.75*06 $GPGSV,3,1,11,15,48,052,35,21,68,183,20,09,44,124,20,03,15,297,24*76 $GPGSV,3,2,11,27,45,088,32,22,39,290,36,06,21,286,,26,11,048,16*7F $GPGSV,3,3,11,14,16,229,,19,07,327,,18,71,324,35*47 $GPZDA,010441.023,27,11,2010,00,00*51 $POLYT,010441.023,271110,522281.0233081,1611,522296.0233081,691905,661.222,25,4713504,00018,00018,*5C $POLYP,010441.023,4244.046205,N,08428.277587,W,223.942,G3,002.3,005.5,0.038,351.81,0.009,,1.42,1.75,2.25,2.60,1.31,8,,0*18 $POLYS,11,15,U,052,48,35,255,21,U,183,68,20,,09,U,124,44,20,,03,U,297,15,24,,27,U,088,45,32,,22,U, 290,39,36,200,06,e,286,21,,,26,U,048,11,16,,14,-,229,16,,,19,-,327,07,,,18,U,324,71,35,255*16 $POLYI,JN,17,EXT,HPOS,VPOS,INT,TSYNC,*16 $GPGLL,4244.046396,N,08428.277612,W,010508.031,A,A*4C $GPRMC,010508.031,A,4244.046396,N,08428.277612,W,0.021,351.12,271110,,,A*48 $GPGGA,010508.031,4244.046396,N,08428.277612,W,1,7,1.58,257.975,M,-34.241,M,,*64 $GPGSA,A,3,15,09,03,27,22,26,18,,,,,,2.36,1.58,1.75*0C $GPGSV,3,1,11,15,48,052,35,21,67,183,16,09,45,124,26,03,15,297,22*7D $GPGSV,3,2,11,27,45,088,33,22,39,290,37,06,21,286,,26,11,048,18*71 $GPGSV,3,3,11,14,16,229,,19,07,327,,18,71,324,36*44 $GPZDA,010508.031,27,11,2010,00,00*5E $POLYT,010508.031,271110,522308.0312902,1611,522323.0312902,-290227,661.761,25,4740512,00017,00017,*7C $POLYP,010508.031,4244.046396,N,08428.277612,W,223.734,G3,002.2,005.5,0.039,351.12,0.010,,1.58,1.75,2.36,2.70,1.33,7,,0*1B $POLYS,11,15,U,052,48,35,255,21,e,183,67,16,,09,U,124,45,26,,03,U,297,15,22,,27,U,088,45,33,018,22,U, 290,39,37,227,06,e,286,21,,,26,U,048,11,18,,14,-,229,16,,,19,-,327,07,,,18,U,324,71,36,255*1C $POLYI,JN,18,EXT,HPOS,VPOS,INT,TSYNC,*19 27-NOV-10 --------- The $PRTHS,U1OP,ALL=0,ZDA=1 command to the gps receiver seems to work as expected. It appears that this must be in capitals. The receiver appears to remember this configuration stuff from one power up through a power off to the next power up. The big issue is that it is in terms of unit seconds only - not tenths of a second. So far it seems like it wants to output the ascii stuff at 0.2 or 0.1 or 0.0x seconds and not at 0.999 but I have no way to know if this is guaranteed or how to change it if it wakes up at 0.999 sec ascii output. 30-NOV-10 --------- My Samtec FSI connector documents: samtec_fsi_doc_1.pdf Body drawings of the 6mm and 10mm connectors 3 pages samtec_fsi_doc_2.pdf Wipe contact pattern for 3mm, 6mm, and 10mm samtec_fsi_doc_3.pdf Fixed contact pattern for the 6mm and 10mm connector samtec_fsi_doc_4.pdf Fixed contact pattern for the 3mm connector samtec_fsi_doc_5.pdf Data sheet for the 3mm connector samtec_fsi_doc_6.pdf Data sheet for the 6mm and 10mm connector samtec_fsi_doc_7.pdf Body drawings of the 3mm connectors 4 pages So the wipe contact pattern is the same for all three connector stack heights i.e. MEZ-456 is independent of the connector stack height used. The fixed contact pattern differ in the spacing from the center-line to the edge of the pad. For the 3mm hight connector this is 4.13mm and for the 6mm or 10mm height connector this is 4.39mm. There may be other differences. 6-DEC-2010 ---------- The VX1190A TDC has a 2x8 Control Bus connector. The pinout is: 16 AUX_B 15 AUX 8 CLK_B 7 CLK 14 OUT_PROG_B 13 OUT_PROG 6 CLR_B 5 CLR 12 L2_REJ_B 11 L2_REJ 4 TRG_B 3 TRG 10 L2_ACP_B 9 L2_ACP 2 CRST_B 1 CRST It is 110 Ohm Differential ECL signal level on ALL signals. All signals are inputs except for the OUT_PROG AUX, L2_REJECT, and L2_ACCEPT are not used. I do not know if the one output signal provides it pull down current or if the inputs are expected to provide the pull down current. The OUT_PROG signal can be programmed via the OUT_PROG Control Register (see 6.23) to indicate either: Data-Ready, Full, Almost_Full, or Error. Summary, per TDC module, the H_Clk will need to: Drive: CRST, TRG, CLR, and CLK 4 signals total Receive: OUT_PROG 1 signal total Control Bus to/from the Trigger system from Mike Duvernois via Udara Last week I was able to talk with Mike Duvernois about the new fanout requirements for our new Hunt-Xilinx trigger. Following is the requirement list I ended up with. For the HAWC 300 we'd have 6 1st level boards which required 40 MHz clock, Pause and a Busy signal per each board, and their would be a one second level board. The second level board provides the trigger signal and it needs only the 40 MHz clock as an input. Clock, Pause and Busy signals has to be LVDS 3.3Vcco or LVDS 2.5Vcco, and the trigger output signal is LVDS 2.5Vcco. The summary is as follows. Number of required   Number of required LVDS output pins LVDS input pins 40 MHz Clock    7           7x2 Busy            6           6x2 Pause           6           6x2 Trigger Signal 1                                1x2 -------------         ------------- Total  Pins                38                     2 We required one full mezzanine board + 6 pins of LVDS outputs for this trigger. 1. Does the H_Clk "enforce" the Pause and Busy on the Trigger signal that it sends out or does it just pass these signals along ? 7-DEC-2010 ---------- The basic set of Onsemi devices is: 100 EPT24 is +3.3V TTL or CMOS to negative differential ECL powered from -3.3V 10 or 100 ELT24 is +5V TTL or CMOS to negative differential ECL powered from -4.5V to -5.2V 10 or 100 ELT25 negative differential ECL powered from -4.5V to -5.2V to +5V powered +5V TTL or CMOS logic 100 EPT25 negative differential ECL powered from -3.3V to -5.2V to +3.3V powered +3V TTL or CMOS logic So the most rational to look at for a starting place are the: 100EPT24 +3.3V TTL or CMOS input to negative differential ECL output, powered from +3.3V and -3.0V to -3.6V, 1 channel per part, 8-SOICN at $8.80 or 8-TSSOP at $7.40 100EPT25 negative differential ECL input to +3.3V TTL (and CMOS ?), powered from +3.3V and -3.0V to -5.5V 1 channel per part, 8-SOICN at $8.80 or 8-TSSOP at $8.00 The basic LVDS Driver is the SN65LVDS31 which is a quad driver in a SOIC-16 package. The SN65LVDS9638 is the dual Driver version of this part in an SOIC-8 package. The basic LVDS Receiver is the SN65LVDS32 which is a quad receiver in a SOIC-16 package. The SN65LVDS9637 is the dual Receiver version of this part in an SOIC-8 package. LVDS In/Out Buffers from National: DS10BR150 sing lvds in/out buffer wo-pre_emphasis w-term +3.3V 1GHz 8-LLP DS15BR400 quad lvds in/out buffer w-pre_emphasis w-term +3.3V 2GHz tqfp48 DS15BR401 quad lvds in/out buffer w-pre_emphasis wo-term +3.3V 2GHz tqfp48 DS90LV001 sing lvds in/out buffer wo-pre_emph wo-term +3.3V 0.8GHz 8-LL SO DS90LV004 quad lvds in/out buffer w-pre_emph w-term +3.3V 1.5GHz TQFP DS90LV804 quad lvds in/out buffer wo-pre_emph w-term +3.3V 0.8GHz LLP LVSD to LVDS fanouts: DS90LV110AT failsafe version of ds90lv110 I think DS90LV110T 1:10 LVDS In LVDS Out 400 MHz +3.3V TSSOP-28 has land DS91M125 1:4 LVDS In M-LVDS Out 125 MHz +3.3V SOIC-16 Issues in the lauout so far: No nice high density ECL drivers so far. It will be a major push to get 16+ ECL Control Bus connections and 7+ LVDS Control Bus connections all on one card along with everything else. Does the Fanout enforce no triggers during e.g. reset What control bus like stuff is needed for the Scaler DAQ For scaler DAQ the time stamps must be at the 100 Hz One idea may be to punt on making a do everything card and instead make M_Clk do the Clock stuff and a first level of fanout and then a dumb fanout to 16 or 20 ECL control bus runs. Keep the M_Clk board all LVDS. 8-DEC-2010 ---------- Test to see if on a 160mm x 233mm you can layout the Control Buss connections for 16x ECL TDC and 8x LVDS Trigger all in a rational way. This is the common signals: CLK, CLR, TRG, and CRST and 24 individual signals for: OUT_PROG aka Almost_Full This fanout card should include drive to a default level for the: AUX, L2_RE, L2_ACP signals. Call this fanout card, "CB_Fan" and its pcb is "CB_Fab_pcb". The connectors on this card will require: 4x of the 64 pin connectors for the ECL C-Bus 4 C-Bus per connector 2x of the 64 pin connectors for the LVDS C-Bus 4 C-Bus per connector 1x of the 64 pin connector to connect with the H-Clk card CLK, CLR, TRG, and CRST from H-Clk to CB-Fan 4 signals 24x OUT_PROG aka Almost_Full from CB-Fan to H-Clk 24 signals all LVDS If there is space, then in each case the hard to use 64 pin connector could be replaced with 2 easy to use 34 pin connectors. The unused pair could: goto vias, gnd guard the Clk, be active for emergency, ... 4x of the 34 pin male connectors with latch/eject ears do not fit in the 233mm Y height of the card. 4x of the plan 4 wall 34 pin headers probably do fit. If so is there room for cable clamps and front panel mounts ? A 24 pin plan 4 wall header is about 1.52 inches long, which is 1.1" for pins and thus 0.42" for the end walls. So a 34 pin plan 4 wall must be 1.6" of pins + 0.42" = 2.02" long 51.3mm long 4x 51.3mm = 205.2mm 233 - 205.2 = 27.8 mm of free Y space 1.1" So it may be possible. Make a 34 pin plan 4 wall geometry. Base the straight geometry on the 3M series 303 part number 30334-6002HB and 30334-5002HB for the right angle. Should we also have individual "trigger" signals for each Control Bus cable ?? i.e. partition the DAQ system for testing. Could still have common resets. Could use 2 of the CB-Fan cards. 9-DEC-2010 ---------- Leave the CB-Fan as it is for now and work on the H-Clk to make it: all LVDS, use 34 pin plan 4 wall headers, add some of the VME IF chips, add some of the GPS IF and PLL chips. Try for 10x of the 34 pin all LVDS I/O on the lower section of the H-Clk card. 10-DEC-2010 ----------- The current draft of the H-Clk card is: 10x 34 pin GP I/O connectors all LVDS put quality 40 MHz on the 17th pair the mix of I's and O's is controlled at build time by using either 65LVDS9638D drivers or 65LVDS9637D receivers which have the same layout foot print use the D SOIC package so that you can swap these parts if needed separate 34 pin connector for the GPS sensor power, 1 pps, 10 MHz, ascii from, ascii to and repeat this did in LVDS so that one can daisy chain the H-Clk card is needed. Supporting this 160 channels of GP I/O requires 160 single ended I/Os on the Mez-456 which has 64 I/Os per side (minus the Global Clock pins). This is the bulk of 3 sides of the Mez-456. Estimate the pin count to support the VME interface. Think about this as either a A24D16 or A24D32 Slave only interface. Address 24 Adrs Modif 6 Data 16 or 32 AS 1 DS 1 Write 1 LWord 1 IACK 1 Reset + 1 -------- 52 I/Os for D16 68 I/Os for D32 So this as expected will take the 4th side of the Mez-456. The 2 channel LVDS parts in the small DGK package is OK from the thermo point of view compared to the 4 channel parts in the PW package that we have used before without trouble. For the Driver: 65LVDS31 35 mA max --> 116 mW PW pkg 496 mW at 70 deg C 65LVDS9638 13 mA max --> 43 mW DGK pkg 272 mW at 70 deg C 116 mW 43 mW -------- = 23.4 % -------- = 15.4 % 496 mW 272 mW 65LVDS31 typically 25mW per driver at 200 MHz 65LVDS31 with 4 drivers loaded running at 100 MHz is typically 25mA total supply current = 83 mW DGK package at 25 Deg C is rated for 425 mW For the Receiver: 65LVDS32 18 mA max --> 59 mW PW pkg 496 mW at 70 deg C 65LVDS9637 10 mA max --> 33 mW DGK pkg 272 mW at 70 deg C 59 mW 33 mW -------- = 12.0 % -------- = 12.1 % 496 mW 272 mW 65LVDS32 with 4 receivers loaded with 10 pFd running at 100 MHz is typically 55 mA total supply current = 182 mW DGK package at 25 Deg C is rated for 425 mW The texas DGK package is a: 2.90mm : 3.10mm square body NOT Power Pad package 4.75mm : 5.05mm pin end to pin end 0.25mm : 0.38mm pin width 0.65mm pin pitch Data sheet hints at pad pattern of: pads 0.40mm by 1.60mm pad pitch 0.65mm center to center pad rows 4.20mm solder mask relief on all edges 0.07mm Finally find dgk8_boardstation.v8.7.zip at TI. 13-DEC-2010 ----------- Work on setting up the ti_dgk_8_pin in the standard way. Can I loop the Global clock out of the I/O Block on the Vertex without a timing penalty ? 13-DEC-2010 ----------- Work on the Vectron VCXO order. Before we used: 60.6905 MHz +- 50 ppm Pull Range Voltage Controlled Crystal Oscillator Vectron Part No. VCUGCD Frequency 60.6905 MHz Order directly from Vectron price about $29.20 ea VCUGCD --> V Type, +5V, VCXO, +-50ppm, 0/70 deg, 50/50+-5% TriState pin 2 Want: V-Type, +5V, VCXO, +-50ppm, 0/70 deg, ??? 40.0000 MHz 18-Oct-2011 ----------- Check to verify the transfer function of the Vectron VCXO Vectron part number: VX-7031-DAT-KKKA-40M00000 Control Frequency Voltage kHz ------- ------------ 2.400 V 39,999.362 2.450 V 39,999.569 2.500 V 39,999.777 2.550 V 39,999.986 2.560 V 40,000.026 2.600 V 40,000.193 2.650 V 40,000.400 2.700 V 40,000.608 Gain 2.400 to 2.700 - 4153 Hz/Volt Gain 2.450 to 2.650 - 4155 Hz/Volt Gain 2.500 to 2.600 - 4160 Hz/Volt or 1 Hz is about 241 uVolt ===================================================================