# MEZ-456 FPGA I/O Bank Nets # ------------------------------ # # # Original Rev. 2-Dec-2010 # Most Recent Rev. 2-Dec-2010 # # This file defines the nets to 38 pins in Bank 0. # This file defines the nets to 38 pins in Bank 1. # This file defines the nets to 42 pins in Bank 2. # This file defines the nets to 42 pins in Bank 3. # This file defines the nets to 40 pins in Bank 4. # This file defines the nets to 40 pins in Bank 5. # This file defines the nets to 42 pins in Bank 6. # This file defines the nets to 42 pins in Bank 7. # ------ # This file defines the nets to 324 pins in total. # Xilinx pin names that used a "/" have had that # character replaced with a "_". # # Replaced String "/" with "_" qty 90 of them. # NET 'IO_L01N_0' U1-B4 NET 'IO_L01P_0' U1-A4 NET 'IO_L02N_0' U1-C4 NET 'IO_L02P_0' U1-C5 NET 'IO_L03N_0_VRP_0' U1-B5 NET 'IO_L03P_0_VRN_0' U1-A5 NET 'IO_L04N_0_VREF_0' U1-D6 NET 'IO_L04P_0' U1-C6 NET 'IO_L05N_0' U1-B6 NET 'IO_L05P_0' U1-A6 NET 'IO_L06N_0' U1-E7 NET 'IO_L06P_0' U1-E8 NET 'IO_L21N_0' U1-D7 NET 'IO_L21P_0_VREF_0' U1-C7 NET 'IO_L22N_0' U1-B7 NET 'IO_L22P_0' U1-A7 NET 'IO_L24N_0' U1-D8 NET 'IO_L24P_0' U1-C8 NET 'IO_L49N_0' U1-B8 NET 'IO_L49P_0' U1-A8 NET 'IO_L51N_0' U1-E9 NET 'IO_L51P_0_VREF_0' U1-F9 NET 'IO_L52N_0' U1-D9 NET 'IO_L52P_0' U1-C9 NET 'IO_L54N_0' U1-B9 NET 'IO_L54P_0' U1-A9 NET 'IO_L91N_0_VREF_0' U1-E10 NET 'IO_L91P_0' U1-F10 NET 'IO_L92N_0' U1-D10 NET 'IO_L92P_0' U1-C10 NET 'IO_L93N_0' U1-B10 NET 'IO_L93P_0' U1-A10 NET 'IO_L94N_0_VREF_0' U1-E11 NET 'IO_L94P_0' U1-F11 NET 'IO_L95N_0_GCLK7P' U1-D11 NET 'IO_L95P_0_GCLK6S' U1-C11 NET 'IO_L96N_0_GCLK5P' U1-B11 NET 'IO_L96P_0_GCLK4S' U1-A11 NET 'IO_L96N_1_GCLK3P' U1-F12 NET 'IO_L96P_1_GCLK2S' U1-F13 NET 'IO_L95N_1_GCLK1P' U1-E12 NET 'IO_L95P_1_GCLK0S' U1-D12 NET 'IO_L94N_1' U1-C12 NET 'IO_L94P_1_VREF_1' U1-B12 NET 'IO_L93N_1' U1-A13 NET 'IO_L93P_1' U1-B13 NET 'IO_L92N_1' U1-C13 NET 'IO_L92P_1' U1-D13 NET 'IO_L91N_1' U1-E13 NET 'IO_L91P_1_VREF_1' U1-E14 NET 'IO_L54N_1' U1-A14 NET 'IO_L54P_1' U1-B14 NET 'IO_L52N_1' U1-C14 NET 'IO_L52P_1' U1-D14 NET 'IO_L51N_1_VREF_1' U1-A15 NET 'IO_L51P_1' U1-B15 NET 'IO_L49N_1' U1-C15 NET 'IO_L49P_1' U1-D15 NET 'IO_L24N_1' U1-F14 NET 'IO_L24P_1' U1-E15 NET 'IO_L22N_1' U1-A16 NET 'IO_L22P_1' U1-B16 NET 'IO_L21N_1_VREF_1' U1-C16 NET 'IO_L21P_1' U1-D16 NET 'IO_L06N_1' U1-E16 NET 'IO_L06P_1' U1-E17 NET 'IO_L05N_1' U1-A17 NET 'IO_L05P_1' U1-B17 NET 'IO_L04N_1' U1-C17 NET 'IO_L04P_1_VREF_1' U1-D17 NET 'IO_L03N_1_VRP_1' U1-A18 NET 'IO_L03P_1_VRN_1' U1-B18 NET 'IO_L02N_1' U1-C18 NET 'IO_L02P_1' U1-D18 NET 'IO_L01N_1' U1-A19 NET 'IO_L01P_1' U1-B19 NET 'IO_L01N_2' U1-C21 NET 'IO_L01P_2' U1-C22 NET 'IO_L02N_2_VRP_2' U1-E18 NET 'IO_L02P_2_VRN_2' U1-F18 NET 'IO_L03N_2' U1-D21 NET 'IO_L03P_2_VREF_2' U1-D22 NET 'IO_L04N_2' U1-E19 NET 'IO_L04P_2' U1-E20 NET 'IO_L06N_2' U1-E21 NET 'IO_L06P_2' U1-E22 NET 'IO_L19N_2' U1-F19 NET 'IO_L19P_2' U1-F20 NET 'IO_L21N_2' U1-F21 NET 'IO_L21P_2_VREF_2' U1-F22 NET 'IO_L22N_2' U1-G18 NET 'IO_L22P_2' U1-H18 NET 'IO_L24N_2' U1-G19 NET 'IO_L24P_2' U1-G20 NET 'IO_L43N_2' U1-G21 NET 'IO_L43P_2' U1-G22 NET 'IO_L45N_2' U1-H19 NET 'IO_L45P_2_VREF_2' U1-H20 NET 'IO_L46N_2' U1-H21 NET 'IO_L46P_2' U1-H22 NET 'IO_L48N_2' U1-J17 NET 'IO_L48P_2' U1-J18 NET 'IO_L49N_2' U1-J19 NET 'IO_L49P_2' U1-J20 NET 'IO_L51N_2' U1-J21 NET 'IO_L51P_2_VREF_2' U1-J22 NET 'IO_L52N_2' U1-K17 NET 'IO_L52P_2' U1-K18 NET 'IO_L54N_2' U1-K19 NET 'IO_L54P_2' U1-K20 NET 'IO_L91N_2' U1-K21 NET 'IO_L91P_2' U1-K22 NET 'IO_L93N_2' U1-L17 NET 'IO_L93P_2_VREF_2' U1-L18 NET 'IO_L94N_2' U1-L19 NET 'IO_L94P_2' U1-L20 NET 'IO_L96N_2' U1-L21 NET 'IO_L96P_2' U1-L22 NET 'IO_L96N_3' U1-M21 NET 'IO_L96P_3' U1-M20 NET 'IO_L94N_3' U1-M19 NET 'IO_L94P_3' U1-M18 NET 'IO_L93N_3_VREF_3' U1-M17 NET 'IO_L93P_3' U1-N17 NET 'IO_L91N_3' U1-N22 NET 'IO_L91P_3' U1-N21 NET 'IO_L54N_3' U1-N20 NET 'IO_L54P_3' U1-N19 NET 'IO_L52N_3' U1-N18 NET 'IO_L52P_3' U1-P18 NET 'IO_L51N_3_VREF_3' U1-P22 NET 'IO_L51P_3' U1-P21 NET 'IO_L49N_3' U1-P20 NET 'IO_L49P_3' U1-P19 NET 'IO_L48N_3' U1-R22 NET 'IO_L48P_3' U1-R21 NET 'IO_L46N_3' U1-R20 NET 'IO_L46P_3' U1-R19 NET 'IO_L45N_3_VREF_3' U1-R18 NET 'IO_L45P_3' U1-P17 NET 'IO_L43N_3' U1-T22 NET 'IO_L43P_3' U1-T21 NET 'IO_L24N_3' U1-T20 NET 'IO_L24P_3' U1-T19 NET 'IO_L22N_3' U1-U22 NET 'IO_L22P_3' U1-U21 NET 'IO_L21N_3_VREF_3' U1-U20 NET 'IO_L21P_3' U1-U19 NET 'IO_L19N_3' U1-T18 NET 'IO_L19P_3' U1-U18 NET 'IO_L06N_3' U1-V22 NET 'IO_L06P_3' U1-V21 NET 'IO_L04N_3' U1-V20 NET 'IO_L04P_3' U1-V19 NET 'IO_L03N_3_VREF_3' U1-W22 NET 'IO_L03P_3' U1-W21 NET 'IO_L02N_3_VRP_3' U1-Y22 NET 'IO_L02P_3_VRN_3' U1-Y21 NET 'IO_L01N_3' U1-W20 NET 'IO_L01P_3' U1-AA20 NET 'IO_L01N_4_BUSY_DOUT' U1-AB19 NET 'IO_L01P_4_INIT_B' U1-AA19 NET 'IO_L02N_4_D0_DIN' U1-V18 NET 'IO_L02P_4_D1' U1-V17 NET 'IO_L03N_4_D2_ALT_VRP_4' U1-W18 NET 'IO_L03P_4_D3_ALT_VRN_4' U1-Y18 NET 'IO_L04N_4_VREF_4' U1-AA18 NET 'IO_L04P_4' U1-AB18 NET 'IO_L05N_4_VRP_4' U1-W17 NET 'IO_L05P_4_VRN_4' U1-Y17 NET 'IO_L06N_4' U1-AA17 NET 'IO_L06P_4' U1-AB17 NET 'IO_L19N_4' U1-V16 NET 'IO_L19P_4' U1-V15 NET 'IO_L21N_4' U1-W16 NET 'IO_L21P_4_VREF_4' U1-Y16 NET 'IO_L22N_4' U1-AA16 NET 'IO_L22P_4' U1-AB16 NET 'IO_L24N_4' U1-W15 NET 'IO_L24P_4' U1-Y15 NET 'IO_L49N_4' U1-AA15 NET 'IO_L49P_4' U1-AB15 NET 'IO_L51N_4' U1-U14 NET 'IO_L51P_4_VREF_4' U1-V14 NET 'IO_L52N_4' U1-W14 NET 'IO_L52P_4' U1-Y14 NET 'IO_L54N_4' U1-AA14 NET 'IO_L54P_4' U1-AB14 NET 'IO_L91N_4_VREF_4' U1-U13 NET 'IO_L91P_4' U1-V13 NET 'IO_L92N_4' U1-W13 NET 'IO_L92P_4' U1-Y13 NET 'IO_L93N_4' U1-AA13 NET 'IO_L93P_4' U1-AB13 NET 'IO_L94N_4_VREF_4' U1-U12 NET 'IO_L94P_4' U1-V12 NET 'IO_L95N_4_GCLK3S' U1-W12 NET 'IO_L95P_4_GCLK2P' U1-Y12 NET 'IO_L96N_4_GCLK1S' U1-AA12 NET 'IO_L96P_4_GCLK0P' U1-AB12 NET 'IO_L96N_5_GCLK7S' U1-AA11 NET 'IO_L96P_5_GCLK6P' U1-Y11 NET 'IO_L95N_5_GCLK5S' U1-W11 NET 'IO_L95P_5_GCLK4P' U1-V11 NET 'IO_L94N_5' U1-U11 NET 'IO_L94P_5_VREF_5' U1-U10 NET 'IO_L93N_5' U1-AB10 NET 'IO_L93P_5' U1-AA10 NET 'IO_L92N_5' U1-Y10 NET 'IO_L92P_5' U1-W10 NET 'IO_L91N_5' U1-V10 NET 'IO_L91P_5_VREF_5' U1-V9 NET 'IO_L54N_5' U1-AB9 NET 'IO_L54P_5' U1-AA9 NET 'IO_L52N_5' U1-Y9 NET 'IO_L52P_5' U1-W9 NET 'IO_L51N_5_VREF_5' U1-AB8 NET 'IO_L51P_5' U1-AA8 NET 'IO_L49N_5' U1-Y8 NET 'IO_L49P_5' U1-W8 NET 'IO_L24N_5' U1-U9 NET 'IO_L24P_5' U1-V8 NET 'IO_L22N_5' U1-AB7 NET 'IO_L22P_5' U1-AA7 NET 'IO_L21N_5_VREF_5' U1-Y7 NET 'IO_L21P_5' U1-W7 NET 'IO_L19N_5' U1-AB6 NET 'IO_L19P_5' U1-AA6 NET 'IO_L06N_5' U1-Y6 NET 'IO_L06P_5' U1-W6 NET 'IO_L05N_5_VRP_5' U1-V7 NET 'IO_L05P_5_VRN_5' U1-V6 NET 'IO_L04N_5' U1-AB5 NET 'IO_L04P_5_VREF_5' U1-AA5 NET 'IO_L03N_5_D4_ALT_VRP_5' U1-Y5 NET 'IO_L03P_5_D5_ALT_VRN_5' U1-W5 NET 'IO_L02N_5_D6' U1-AB4 NET 'IO_L02P_5_D7' U1-AA4 NET 'IO_L01N_5_RDWR_B' U1-Y4 NET 'IO_L01P_5_CS_B' U1-AA3 NET 'IO_L01P_6' U1-V5 NET 'IO_L01N_6' U1-U5 NET 'IO_L02P_6_VRN_6' U1-Y2 NET 'IO_L02N_6_VRP_6' U1-Y1 NET 'IO_L03P_6' U1-V4 NET 'IO_L03N_6_VREF_6' U1-V3 NET 'IO_L04P_6' U1-W2 NET 'IO_L04N_6' U1-W1 NET 'IO_L06P_6' U1-U4 NET 'IO_L06N_6' U1-U3 NET 'IO_L19P_6' U1-V2 NET 'IO_L19N_6' U1-V1 NET 'IO_L21P_6' U1-U2 NET 'IO_L21N_6_VREF_6' U1-U1 NET 'IO_L22P_6' U1-T5 NET 'IO_L22N_6' U1-R5 NET 'IO_L24P_6' U1-T4 NET 'IO_L24N_6' U1-T3 NET 'IO_L43P_6' U1-T2 NET 'IO_L43N_6' U1-T1 NET 'IO_L45P_6' U1-R4 NET 'IO_L45N_6_VREF_6' U1-R3 NET 'IO_L46P_6' U1-R2 NET 'IO_L46N_6' U1-R1 NET 'IO_L48P_6' U1-P6 NET 'IO_L48N_6' U1-P5 NET 'IO_L49P_6' U1-P4 NET 'IO_L49N_6' U1-P3 NET 'IO_L51P_6' U1-P2 NET 'IO_L51N_6_VREF_6' U1-P1 NET 'IO_L52P_6' U1-N6 NET 'IO_L52N_6' U1-N5 NET 'IO_L54P_6' U1-N4 NET 'IO_L54N_6' U1-N3 NET 'IO_L91P_6' U1-N2 NET 'IO_L91N_6' U1-N1 NET 'IO_L93P_6' U1-M6 NET 'IO_L93N_6_VREF_6' U1-M5 NET 'IO_L94P_6' U1-M4 NET 'IO_L94N_6' U1-M3 NET 'IO_L96P_6' U1-M2 NET 'IO_L96N_6' U1-M1 NET 'IO_L96P_7' U1-L2 NET 'IO_L96N_7' U1-L3 NET 'IO_L94P_7' U1-L4 NET 'IO_L94N_7' U1-L5 NET 'IO_L93P_7_VREF_7' U1-K1 NET 'IO_L93N_7' U1-K2 NET 'IO_L91P_7' U1-K3 NET 'IO_L91N_7' U1-K4 NET 'IO_L54P_7' U1-L6 NET 'IO_L54N_7' U1-K6 NET 'IO_L52P_7' U1-K5 NET 'IO_L52N_7' U1-J5 NET 'IO_L51P_7_VREF_7' U1-J1 NET 'IO_L51N_7' U1-J2 NET 'IO_L49P_7' U1-J3 NET 'IO_L49N_7' U1-J4 NET 'IO_L48P_7' U1-H1 NET 'IO_L48N_7' U1-H2 NET 'IO_L46P_7' U1-H3 NET 'IO_L46N_7' U1-H4 NET 'IO_L45P_7_VREF_7' U1-J6 NET 'IO_L45N_7' U1-H5 NET 'IO_L43P_7' U1-G1 NET 'IO_L43N_7' U1-G2 NET 'IO_L24P_7' U1-G3 NET 'IO_L24N_7' U1-G4 NET 'IO_L22P_7' U1-F1 NET 'IO_L22N_7' U1-F2 NET 'IO_L21P_7_VREF_7' U1-F3 NET 'IO_L21N_7' U1-F4 NET 'IO_L19P_7' U1-G5 NET 'IO_L19N_7' U1-F5 NET 'IO_L06P_7' U1-E1 NET 'IO_L06N_7' U1-E2 NET 'IO_L04P_7' U1-E3 NET 'IO_L04N_7' U1-E4 NET 'IO_L03P_7_VREF_7' U1-D1 NET 'IO_L03N_7' U1-D2 NET 'IO_L02P_7_VRN_7' U1-C1 NET 'IO_L02N_7_VRP_7' U1-C2 NET 'IO_L01P_7' U1-E5 NET 'IO_L01N_7' U1-E6 # MEZ-456 FPGA Power Supply Nets # -------------------------------- # # # Original Rev. 2-Dec-2010 # Most Recent Rev. 2-Dec-2010 # # This file defines the nets to 116 pins. # I/O Bank Vcc Supplies NET 'VDD' U1-G11 # Vcco_0 Bank 0 +3.3 Volts NET 'VDD' U1-G10 # Vcco_0 NET 'VDD' U1-G9 # Vcco_0 NET 'VDD' U1-F8 # Vcco_0 NET 'VDD' U1-F7 # Vcco_0 NET 'VDD' U1-G14 # Vcco_1 Bank 1 +3.3 Volts NET 'VDD' U1-G13 # Vcco_1 NET 'VDD' U1-G12 # Vcco_1 NET 'VDD' U1-F16 # Vcco_1 NET 'VDD' U1-F15 # Vcco_1 NET 'VDD' U1-L16 # Vcco_2 Bank 2 +3.3 Volts NET 'VDD' U1-K16 # Vcco_2 NET 'VDD' U1-J16 # Vcco_2 NET 'VDD' U1-H17 # Vcco_2 NET 'VDD' U1-G17 # Vcco_2 NET 'VDD' U1-T17 # Vcco_3 Bank 3 +3.3 Volts NET 'VDD' U1-R17 # Vcco_3 NET 'VDD' U1-P16 # Vcco_3 NET 'VDD' U1-N16 # Vcco_3 NET 'VDD' U1-M16 # Vcco_3 NET 'VDD' U1-U16 # Vcco_4 Bank 4 +3.3 Volts NET 'VDD' U1-U15 # Vcco_4 NET 'VDD' U1-T14 # Vcco_4 NET 'VDD' U1-T13 # Vcco_4 NET 'VDD' U1-T12 # Vcco_4 NET 'VDD' U1-U8 # Vcco_5 Bank 5 +3.3 Volts NET 'VDD' U1-U7 # Vcco_5 NET 'VDD' U1-T11 # Vcco_5 NET 'VDD' U1-T10 # Vcco_5 NET 'VDD' U1-T9 # Vcco_5 NET 'VDD' U1-T6 # Vcco_6 Bank 6 +3.3 Volts NET 'VDD' U1-R6 # Vcco_6 NET 'VDD' U1-P7 # Vcco_6 NET 'VDD' U1-N7 # Vcco_6 NET 'VDD' U1-M7 # Vcco_6 NET 'VDD' U1-L7 # Vcco_7 Bank 7 +3.3 Volts NET 'VDD' U1-K7 # Vcco_7 NET 'VDD' U1-J7 # Vcco_7 NET 'VDD' U1-H6 # Vcco_7 NET 'VDD' U1-G6 # Vcco_7 # Auxiliary Circuits Supply Net +3.3 Volts NET 'VDD' U1-AB11 # VccAux NET 'VDD' U1-AA22 # VccAux NET 'VDD' U1-AA1 # VccAux NET 'VDD' U1-M22 # VccAux NET 'VDD' U1-L1 # VccAux NET 'VDD' U1-B22 # VccAux NET 'VDD' U1-B1 # VccAux NET 'VDD' U1-A12 # VccAux # Core Supply Net +1.5 Volts NET 'VCCINT' U1-U17 # VccInt NET 'VCCINT' U1-U6 # VccInt NET 'VCCINT' U1-T16 # VccInt NET 'VCCINT' U1-T15 # VccInt NET 'VCCINT' U1-T8 # VccInt NET 'VCCINT' U1-T7 # VccInt NET 'VCCINT' U1-R16 # VccInt NET 'VCCINT' U1-R7 # VccInt NET 'VCCINT' U1-H16 # VccInt NET 'VCCINT' U1-H7 # VccInt NET 'VCCINT' U1-G16 # VccInt NET 'VCCINT' U1-G15 # VccInt NET 'VCCINT' U1-G8 # VccInt NET 'VCCINT' U1-G7 # VccInt NET 'VCCINT' U1-F17 # VccInt NET 'VCCINT' U1-F6 # VccInt # Ground Net NET 'GROUND' U1-AB22 # Ground NET 'GROUND' U1-AB1 # Ground NET 'GROUND' U1-AA21 # Ground NET 'GROUND' U1-AA2 # Ground NET 'GROUND' U1-Y20 # Ground NET 'GROUND' U1-Y3 # Ground NET 'GROUND' U1-W19 # Ground NET 'GROUND' U1-W4 # Ground NET 'GROUND' U1-P14 # Ground NET 'GROUND' U1-P13 # Ground NET 'GROUND' U1-P12 # Ground NET 'GROUND' U1-P11 # Ground NET 'GROUND' U1-P10 # Ground NET 'GROUND' U1-P9 # Ground NET 'GROUND' U1-N14 # Ground NET 'GROUND' U1-N13 # Ground NET 'GROUND' U1-N12 # Ground NET 'GROUND' U1-N11 # Ground NET 'GROUND' U1-N10 # Ground NET 'GROUND' U1-N9 # Ground NET 'GROUND' U1-M14 # Ground NET 'GROUND' U1-M13 # Ground NET 'GROUND' U1-M12 # Ground NET 'GROUND' U1-M11 # Ground NET 'GROUND' U1-M10 # Ground NET 'GROUND' U1-M9 # Ground NET 'GROUND' U1-L14 # Ground NET 'GROUND' U1-L13 # Ground NET 'GROUND' U1-L12 # Ground NET 'GROUND' U1-L11 # Ground NET 'GROUND' U1-L10 # Ground NET 'GROUND' U1-L9 # Ground NET 'GROUND' U1-K14 # Ground NET 'GROUND' U1-K13 # Ground NET 'GROUND' U1-K12 # Ground NET 'GROUND' U1-K11 # Ground NET 'GROUND' U1-K10 # Ground NET 'GROUND' U1-K9 # Ground NET 'GROUND' U1-J14 # Ground NET 'GROUND' U1-J13 # Ground NET 'GROUND' U1-J12 # Ground NET 'GROUND' U1-J11 # Ground NET 'GROUND' U1-J10 # Ground NET 'GROUND' U1-J9 # Ground NET 'GROUND' U1-D19 # Ground NET 'GROUND' U1-D4 # Ground NET 'GROUND' U1-C20 # Ground NET 'GROUND' U1-C3 # Ground NET 'GROUND' U1-B21 # Ground NET 'GROUND' U1-B2 # Ground NET 'GROUND' U1-A22 # Ground NET 'GROUND' U1-A1 # Ground # # MEZ-456 FPGA All Other Nets # -------------------------------- # # # Original Rev. 2-Dec-2010 # Most Recent Rev. 8-Aug-2011 # # This file shows 28 pins. # 16 of these pins are shown only in this file. # This file defines the nets to 11 of these pins. # Xilinx pin names that used a "/" have had that # character replaced with a "_". # The 10 special connections along the A1-A22 edge include: NET 'PROG_B' U1-A2 # Pin Symb "P" Active Low Configuration Request NET 'DXP' U1-A3 # Pin Symb "A" Temperature Diode No Connection NET 'DXN' U1-D5 # Pin Symb "N" Temperature Diode No Connection NET 'Reserved' U1-A20 # Pin Symb "R" No Connection NET 'VBATT' U1-A21 # Pin Symb "+" No Connection NET 'HSWAP_EN' U1-B3 # Pin Symb "H" pulled up by 4.9k NET 'JTAG_TMS' U1-B20 # Pin Symb "M" JTAG NET 'JTAG_TCK' U1-C19 # Pin Symb "K" JTAG NET 'FPGA_TDI' U1-D3 # Pin Symb "I" JTAG NET 'FPGA_TDO' U1-D20 # Pin Symb "O" JTAG # Of these 10 signals, only PROG_B, HSWAP_EN, and the 4 JTAGs # need to be routed out. # The 18 special connections along the AB1-AB22 edge include: NET 'M0' U1-AB2 # Pin Symb "0" route to resistor pull up/down NET 'M1' U1-W3 # Pin Symb "1" route to resistor pull up/down NET 'M2' U1-AB3 # Pin Symb "2" route to resistor pull up/down NET 'CCLK' U1-Y19 # Pin Symb "C" route to Config PROM CCLK NET 'DONE' U1-AB20 # Pin Symb "D" route to Config PROM CE & LED & PU NET 'PWRDWN_B' U1-AB21 # Pin Symb "W" no connection # # The following special signals are defined in the I/O Banks. # ----------- ### AB19 IO_L01N_4/BUSY/DOUT # no connection ### AA19 IO_L01P_4_INIT_B # route to Config PROM OE/RESET_B & pullup ### V18 IO_L02N_4_D0_DIN # route to Config PROM D0 ### V17 IO_L02P_4_D1 ### W18 IO_L03N_4_D2_ALT_VRP_4 ### Y18 IO_L03P_4_D3_ALT_VRN_4 ### Y5 IO_L03N_5_D4_ALT_VRP_5 ### W5 IO_L03P_5_D5_ALT_VRN_5 ### AB4 IO_L02N_5_D6 ### AA4 IO_L02P_5_D7 ### Y4 IO_L01N_5_RDWR_B # route to pull low ### AA3 IO_L01P_5_CS_B # route to pull low # Of these 18 signals, a few need to be routed out. # MEZ-456 Connector J1 Nets # --------------------====------- # # # Original Rev. 2-Dec-2010 # Most Recent Rev. 10-Oct-2011 # # This connector has the Bank 1 and Bank 0 I/O connections # # This file defines the nets to 100 pins. # Start with Bank #1 at the pin #1 end of J1. # We can only route out 32 of these LVDS pairs # so pick the easiest to access 32 and put them # into a rational route out order. NET 'GROUND' J1-1 NET 'GROUND' J1-2 NET 'IO_L01P_1' J1-3 # U1-B19 NET 'IO_L01N_1' J1-4 # U1-A19 NET 'IO_L02P_1' J1-5 # U1-D18 NET 'IO_L02N_1' J1-6 # U1-C18 NET 'GROUND' J1-7 NET 'GROUND' J1-8 NET 'IO_L03P_1_VRN_1' J1-9 # U1-B18 NET 'IO_L03N_1_VRP_1' J1-10 # U1-A18 NET 'IO_L04P_1_VREF_1' J1-11 # U1-D17 NET 'IO_L04N_1' J1-12 # U1-C17 NET 'GROUND' J1-13 NET 'GROUND' J1-14 NET 'IO_L05P_1' J1-15 # U1-B17 NET 'IO_L05N_1' J1-16 # U1-A17 NET 'IO_L21P_1' J1-17 # U1-D16 NET 'IO_L21N_1_VREF_1' J1-18 # U1-C16 NET 'GROUND' J1-19 NET 'GROUND' J1-20 NET 'IO_L22P_1' J1-21 # U1-B16 NET 'IO_L22N_1' J1-22 # U1-A16 NET 'IO_L49P_1' J1-23 # U1-D15 NET 'IO_L49N_1' J1-24 # U1-C15 NET 'IO_L51N_1_VREF_1' J1-25 # U1-A15 NET 'IO_L51P_1' J1-26 # U1-B15 NET 'IO_L52P_1' J1-27 # U1-D14 NET 'IO_L52N_1' J1-28 # U1-C14 NET 'GROUND' J1-29 NET 'GROUND' J1-30 NET 'IO_L54P_1' J1-31 # U1-B14 NET 'IO_L54N_1' J1-32 # U1-A14 NET 'IO_L92P_1' J1-33 # U1-D13 NET 'IO_L92N_1' J1-34 # U1-C13 NET 'GROUND' J1-35 NET 'GROUND' J1-36 NET 'IO_L93P_1' J1-37 # U1-B13 NET 'IO_L93N_1' J1-38 # U1-A13 NET 'IO_L94P_1_VREF_1' J1-39 # U1-B12 NET 'IO_L94N_1' J1-40 # U1-C12 NET 'GROUND' J1-41 NET 'GROUND' J1-42 NET 'IO_L95P_1_GCLK0S' J1-43 # U1-D12 - clock NET 'IO_L95N_1_GCLK1P' J1-45 # U1-E12 - order pair NET 'IO_L96P_1_GCLK2S' J1-44 # U1-F13 - clock NET 'IO_L96N_1_GCLK3P' J1-46 # U1-F12 - order pair NET 'GROUND' J1-47 NET 'GROUND' J1-48 NET 'VCC' J1-49 NET 'VCC' J1-50 ### ### Currently the following 6 I/O signals from ### Bank 1 are not routed off the MEZ-456 card. # ### NET 'IO_L06P_1' J1- # U1-E17 ### NET 'IO_L06N_1' J1- # U1-E16 # ### NET 'IO_L24P_1' J1- # U1-E15 ### NET 'IO_L24N_1' J1- # U1-F14 # ### NET 'IO_L91P_1_VREF_1' J1- # U1-E14 ### NET 'IO_L91N_1' J1- # U1-E13 # Now route Bank #0 at the pin #100 end of J1. # We can only route out 32 of these LVDS pairs # so pick the easiest to access 32 and put them # into a rational route out order. NET 'VCC' J1-51 NET 'VCC' J1-52 NET 'GROUND' J1-53 NET 'GROUND' J1-54 NET 'IO_L96N_0_GCLK5P' J1-55 # U1-B11 - clock NET 'IO_L96P_0_GCLK4S' J1-57 # U1-A11 - order pair NET 'IO_L95N_0_GCLK7P' J1-56 # U1-D11 - clock NET 'IO_L95P_0_GCLK6S' J1-58 # U1-C11 - order pair NET 'GROUND' J1-59 NET 'GROUND' J1-60 NET 'IO_L91P_0' J1-61 # U1-F10 NET 'IO_L91N_0_VREF_0' J1-62 # U1-E10 NET 'IO_L93P_0' J1-63 # U1-A10 NET 'IO_L93N_0' J1-64 # U1-B10 NET 'GROUND' J1-65 NET 'GROUND' J1-66 NET 'IO_L92P_0' J1-67 # U1-C10 NET 'IO_L92N_0' J1-68 # U1-D10 NET 'IO_L54P_0' J1-69 # U1-A9 NET 'IO_L54N_0' J1-70 # U1-B9 NET 'GROUND' J1-71 NET 'GROUND' J1-72 NET 'IO_L52P_0' J1-73 # U1-C9 NET 'IO_L52N_0' J1-74 # U1-D9 NET 'IO_L49P_0' J1-75 # U1-A8 NET 'IO_L49N_0' J1-76 # U1-B8 NET 'IO_L24P_0' J1-77 # U1-C8 NET 'IO_L24N_0' J1-78 # U1-D8 NET 'IO_L22P_0' J1-79 # U1-A7 NET 'IO_L22N_0' J1-80 # U1-B7 NET 'GROUND' J1-81 NET 'GROUND' J1-82 NET 'IO_L21P_0_VREF_0' J1-83 # U1-C7 NET 'IO_L21N_0' J1-84 # U1-D7 NET 'IO_L05P_0' J1-85 # U1-A6 NET 'IO_L05N_0' J1-86 # U1-B6 NET 'GROUND' J1-87 NET 'GROUND' J1-88 NET 'IO_L04P_0' J1-89 # U1-C6 NET 'IO_L04N_0_VREF_0' J1-90 # U1-D6 NET 'IO_L03P_0_VRN_0' J1-91 # U1-A5 NET 'IO_L03N_0_VRP_0' J1-92 # U1-B5 NET 'GROUND' J1-93 NET 'GROUND' J1-94 NET 'IO_L02N_0' J1-95 # U1-C4 NET 'IO_L02P_0' J1-96 # U1-C5 NET 'IO_L01P_0' J1-97 # U1-A4 NET 'IO_L01N_0' J1-98 # U1-B4 NET 'GROUND' J1-99 NET 'GROUND' J1-100 ### ### Currently the following 6 I/O signals from ### Bank 0 are not routed off the MEZ-456 card. # # ### NET 'IO_L06P_0' J1- # U1-E8 ### NET 'IO_L06N_0' J1- # U1-E7 # ### NET 'IO_L51P_0_VREF_0' J1- # U1-F9 ### NET 'IO_L51N_0' J1- # U1-E9 # ### NET 'IO_L94P_0' J1- # U1-F11 ### NET 'IO_L94N_0_VREF_0' J1- # U1-E11 # ### Also: IO_L01P_7 U1-E5 and IO_L01N_7 U1-E6 ### which are pins physically in this octant but ### logically in another octant are not routed out. # MEZ-456 Connector J2 Nets # --------------------====------- # # # Original Rev. 3-Dec-2010 # Most Recent Rev. 17-Aug-2011 # # This connector has the Bank 7 and Bank 6 I/O connections # # This file defines the nets to 100 pins. # Start with Bank #7 at the pin #1 end of J2. # We can only route out 32 of these LVDS pairs # so pick the easiest to access 32 and put them # into a rational route out order. NET 'GROUND' J2-1 NET 'GROUND' J2-2 NET 'IO_L02P_7_VRN_7' J2-3 # U1-C1 NET 'IO_L02N_7_VRP_7' J2-4 # U1-C2 NET 'IO_L03P_7_VREF_7' J2-5 # U1-D1 NET 'IO_L03N_7' J2-6 # U1-D2 NET 'GROUND' J2-7 NET 'GROUND' J2-8 NET 'IO_L04P_7' J2-9 # U1-E3 NET 'IO_L04N_7' J2-10 # U1-E4 NET 'IO_L06P_7' J2-11 # U1-E1 NET 'IO_L06N_7' J2-12 # U1-E2 NET 'GROUND' J2-13 NET 'GROUND' J2-14 NET 'IO_L21P_7_VREF_7' J2-15 # U1-F3 NET 'IO_L21N_7' J2-16 # U1-F4 NET 'IO_L22P_7' J2-17 # U1-F1 NET 'IO_L22N_7' J2-18 # U1-F2 NET 'GROUND' J2-19 NET 'GROUND' J2-20 NET 'IO_L24P_7' J2-21 # U1-G3 NET 'IO_L24N_7' J2-22 # U1-G4 NET 'IO_L43P_7' J2-23 # U1-G1 NET 'IO_L43N_7' J2-24 # U1-G2 NET 'IO_L46P_7' J2-25 # U1-H3 NET 'IO_L46N_7' J2-26 # U1-H4 NET 'IO_L48P_7' J2-27 # U1-H1 NET 'IO_L48N_7' J2-28 # U1-H2 NET 'GROUND' J2-29 NET 'GROUND' J2-30 NET 'IO_L49P_7' J2-31 # U1-J3 NET 'IO_L49N_7' J2-32 # U1-J4 NET 'IO_L51P_7_VREF_7' J2-33 # U1-J1 NET 'IO_L51N_7' J2-34 # U1-J2 NET 'GROUND' J2-35 NET 'GROUND' J2-36 NET 'IO_L91P_7' J2-37 # U1-K3 NET 'IO_L91N_7' J2-38 # U1-K4 NET 'IO_L93P_7_VREF_7' J2-39 # U1-K1 NET 'IO_L93N_7' J2-40 # U1-K2 NET 'GROUND' J2-41 NET 'GROUND' J2-42 NET 'IO_L94P_7' J2-43 # U1-L4 NET 'IO_L94N_7' J2-44 # U1-L5 NET 'IO_L96P_7' J2-45 # U1-L2 NET 'IO_L96N_7' J2-46 # U1-L3 NET 'GROUND' J2-47 NET 'GROUND' J2-48 NET 'VCC' J2-49 NET 'VCC' J2-50 ### ### Currently the following 10 I/O signals from ### Bank 7 are not routed off the MEZ-456 card. # ### NET 'IO_L01P_7' J2- # U1-E5 ### NET 'IO_L01N_7' J2- # U1-E6 # ### NET 'IO_L19P_7' J2- # U1-G5 ### NET 'IO_L19N_7' J2- # U1-F5 # ### NET 'IO_L45P_7_VREF_7' J2- # U1-J6 ### NET 'IO_L45N_7' J2- # U1-H5 # ### NET 'IO_L52P_7' J2- # U1-K5 ### NET 'IO_L52N_7' J2- # U1-J5 # ### NET 'IO_L54P_7' J2- # U1-L6 ### NET 'IO_L54N_7' J2- # U1-K6 # Now route Bank #6 at the pin #100 end of J2. # We can only route out 32 of these LVDS pairs # so pick the easiest to access 32 and put them # into a rational route out order. NET 'VCC' J2-51 NET 'VCC' J2-52 NET 'GROUND' J2-53 NET 'GROUND' J2-54 NET 'IO_L96P_6' J2-55 # U1-M2 NET 'IO_L96N_6' J2-56 # U1-M1 NET 'IO_L94P_6' J2-57 # U1-M4 NET 'IO_L94N_6' J2-58 # U1-M3 NET 'GROUND' J2-59 NET 'GROUND' J2-60 NET 'IO_L91P_6' J2-61 # U1-N2 NET 'IO_L91N_6' J2-62 # U1-N1 NET 'IO_L54P_6' J2-63 # U1-N4 NET 'IO_L54N_6' J2-64 # U1-N3 NET 'GROUND' J2-65 NET 'GROUND' J2-66 NET 'IO_L51P_6' J2-67 # U1-P2 NET 'IO_L51N_6_VREF_6' J2-68 # U1-P1 NET 'IO_L49P_6' J2-69 # U1-P4 NET 'IO_L49N_6' J2-70 # U1-P3 NET 'GROUND' J2-71 NET 'GROUND' J2-72 NET 'IO_L46P_6' J2-73 # U1-R2 NET 'IO_L46N_6' J2-74 # U1-R1 NET 'IO_L45P_6' J2-75 # U1-R4 NET 'IO_L45N_6_VREF_6' J2-76 # U1-R3 NET 'IO_L43P_6' J2-77 # U1-T2 NET 'IO_L43N_6' J2-78 # U1-T1 NET 'IO_L24P_6' J2-79 # U1-T4 NET 'IO_L24N_6' J2-80 # U1-T3 NET 'GROUND' J2-81 NET 'GROUND' J2-82 NET 'IO_L21P_6' J2-83 # U1-U2 NET 'IO_L21N_6_VREF_6' J2-84 # U1-U1 NET 'IO_L06P_6' J2-85 # U1-U4 NET 'IO_L06N_6' J2-86 # U1-U3 NET 'GROUND' J2-87 NET 'GROUND' J2-88 NET 'IO_L19P_6' J2-89 # U1-V2 NET 'IO_L19N_6' J2-90 # U1-V1 NET 'IO_L03P_6' J2-91 # U1-V4 NET 'IO_L03N_6_VREF_6' J2-92 # U1-V3 NET 'GROUND' J2-93 NET 'GROUND' J2-94 NET 'IO_L04P_6' J2-95 # U1-W2 NET 'IO_L04N_6' J2-96 # U1-W1 NET 'IO_L02P_6_VRN_6' J2-97 # U1-Y2 NET 'IO_L02N_6_VRP_6' J2-98 # U1-Y1 NET 'GROUND' J2-99 NET 'GROUND' J2-100 ### ### Currently the following 10 I/O signals from ### Bank 6 are not routed off the MEZ-456 card. # ### NET 'IO_L01P_6' J2- # U1-V5 ### NET 'IO_L01N_6' J2- # U1-U5 # ### NET 'IO_L22P_6' J2- # U1-T5 ### NET 'IO_L22N_6' J2- # U1-R5 # ### NET 'IO_L48P_6' J2- # U1-P6 ### NET 'IO_L48N_6' J2- # U1-P5 # ### NET 'IO_L52P_6' J2- # U1-N6 ### NET 'IO_L52N_6' J2- # U1-N5 # ### NET 'IO_L93P_6' J2- # U1-M6 ### NET 'IO_L93N_6_VREF_6' J2- # U1-M5 # MEZ-456 Connector J3 Nets # --------------------====------- # # # Original Rev. 3-Dec-2010 # Most Recent Rev. 18-Nov-2011 # # This connector has the Bank 5 and Bank 6 I/O connections # # This file defines the nets to 100 pins. # Start with Bank #5 at the pin #1 end of J3. # We can only route out 32 of these LVDS pairs # so pick the easiest to access 32 and put them # into a rational route out order. NET 'GROUND' J3-1 NET 'GROUND' J3-2 NET 'IO_L01P_5_CS_B' J3-3 # U1-AA3 NET 'IO_L01N_5_RDWR_B' J3-4 # U1-Y4 NET 'IO_L03P_5_D5_ALT_VRN_5' J3-5 # U1-W5 NET 'IO_L03N_5_D4_ALT_VRP_5' J3-6 # U1-Y5 NET 'GROUND' J3-7 NET 'GROUND' J3-8 NET 'IO_L02P_5_D7' J3-9 # U1-AA4 NET 'IO_L02N_5_D6' J3-10 # U1-AB4 NET 'IO_L06P_5' J3-11 # U1-W6 NET 'IO_L06N_5' J3-12 # U1-Y6 NET 'GROUND' J3-13 NET 'GROUND' J3-14 NET 'IO_L04P_5_VREF_5' J3-15 # U1-AA5 NET 'IO_L04N_5' J3-16 # U1-AB5 NET 'IO_L21P_5' J3-17 # U1-W7 NET 'IO_L21N_5_VREF_5' J3-18 # U1-Y7 NET 'GROUND' J3-19 NET 'GROUND' J3-20 NET 'IO_L19P_5' J3-21 # U1-AA6 NET 'IO_L19N_5' J3-22 # U1-AB6 NET 'IO_L49P_5' J3-23 # U1-W8 NET 'IO_L49N_5' J3-24 # U1-Y8 NET 'IO_L22P_5' J3-25 # U1-AA7 NET 'IO_L22N_5' J3-26 # U1-AB7 NET 'IO_L52P_5' J3-27 # U1-W9 NET 'IO_L52N_5' J3-28 # U1-Y9 NET 'GROUND' J3-29 NET 'GROUND' J3-30 NET 'IO_L51P_5' J3-31 # U1-AA8 NET 'IO_L51N_5_VREF_5' J3-32 # U1-AB8 NET 'IO_L92P_5' J3-33 # U1-W10 NET 'IO_L92N_5' J3-34 # U1-Y10 NET 'GROUND' J3-35 NET 'GROUND' J3-36 NET 'IO_L54P_5' J3-37 # U1-AA9 NET 'IO_L54N_5' J3-38 # U1-AB9 NET 'IO_L93P_5' J3-39 # U1-AA10 NET 'IO_L93N_5' J3-40 # U1-AB10 NET 'GROUND' J3-41 NET 'GROUND' J3-42 NET 'IO_L96P_5_GCLK6P' J3-43 # U1-Y11 - clock NET 'IO_L96N_5_GCLK7S' J3-45 # U1-AA11 - order pair NET 'IO_L95P_5_GCLK4P' J3-44 # U1-V11 - clock NET 'IO_L95N_5_GCLK5S' J3-46 # U1-W11 - order pair NET 'GROUND' J3-47 NET 'GROUND' J3-48 NET 'VCC' J3-49 NET 'VCC' J3-50 ### ### Currently the following 8 I/O signals from ### Bank 5 are not routed off the MEZ-456 card. # ### NET 'IO_L05P_5_VRN_5' J3- # U1-V6 ### NET 'IO_L05N_5_VRP_5' J3- # U1-V7 # ### NET 'IO_L24P_5' J3- # U1-V8 ### NET 'IO_L24N_5' J3- # U1-U9 # ### NET 'IO_L91P_5_VREF_5' J3- # U1-V9 ### NET 'IO_L91N_5' J3- # U1-V10 # ### NET 'IO_L94P_5_VREF_5' J3- # U1-U10 ### NET 'IO_L94N_5' J3- # U1-U11 # Now route Bank #4 at the pin #100 end of J3. # We can only route out 32 of these LVDS pairs # so pick the easiest to access 32 and put them # into a rational route out order. NET 'VCC' J3-51 NET 'VCC' J3-52 NET 'GROUND' J3-53 NET 'GROUND' J3-54 NET 'IO_L96N_4_GCLK1S' J3-55 # U1-AA12 - clock NET 'IO_L96P_4_GCLK0P' J3-57 # U1-AB12 - order pair NET 'IO_L95N_4_GCLK3S' J3-56 # U1-W12 - clock NET 'IO_L95P_4_GCLK2P' J3-58 # U1-Y12 - order pair NET 'GROUND' J3-59 NET 'GROUND' J3-60 NET 'IO_L91P_4' J3-61 # U1-V13 NET 'IO_L91N_4_VREF_4' J3-62 # U1-U13 NET 'IO_L93P_4' J3-63 # U1-AB13 NET 'IO_L93N_4' J3-64 # U1-AA13 NET 'GROUND' J3-65 NET 'GROUND' J3-66 NET 'IO_L92P_4' J3-67 # U1-Y13 NET 'IO_L92N_4' J3-68 # U1-W13 NET 'IO_L54P_4' J3-69 # U1-AB14 NET 'IO_L54N_4' J3-70 # U1-AA14 NET 'GROUND' J3-71 NET 'GROUND' J3-72 NET 'IO_L52P_4' J3-73 # U1-Y14 NET 'IO_L52N_4' J3-74 # U1-W14 NET 'IO_L49P_4' J3-75 # U1-AB15 NET 'IO_L49N_4' J3-76 # U1-AA15 NET 'IO_L24P_4' J3-77 # U1-Y15 NET 'IO_L24N_4' J3-78 # U1-W15 NET 'IO_L22P_4' J3-79 # U1-AB16 NET 'IO_L22N_4' J3-80 # U1-AA16 NET 'GROUND' J3-81 NET 'GROUND' J3-82 NET 'IO_L21P_4_VREF_4' J3-83 # U1-Y16 NET 'IO_L21N_4' J3-84 # U1-W16 NET 'IO_L06P_4' J3-85 # U1-AB17 NET 'IO_L06N_4' J3-86 # U1-AA17 NET 'GROUND' J3-87 NET 'GROUND' J3-88 NET 'IO_L05P_4_VRN_4' J3-89 # U1-Y17 NET 'IO_L05N_4_VRP_4' J3-90 # U1-W17 NET 'IO_L04P_4' J3-91 # U1-AB18 NET 'IO_L04N_4_VREF_4' J3-92 # U1-AA18 NET 'GROUND' J3-93 NET 'GROUND' J3-94 NET 'IO_L03P_4_D3_ALT_VRN_4' J3-95 # U1-Y18 NET 'IO_L03N_4_D2_ALT_VRP_4' J3-96 # U1-W18 NET 'IO_L01P_3' J3-97 # U1-AA20 \ NOT a NET 'IO_L01N_4_BUSY_DOUT' J3-98 # U1-AB19 / LVDS Pair NET 'GROUND' J3-99 NET 'GROUND' J3-100 ### ### Currently the following 8 I/O signals from ### Bank 4 are not routed off the MEZ-456 card. # ### NET 'IO_L94P_4' J3- # U1-V12 ### NET 'IO_L94N_4_VREF_4' J3- # U1-U12 # ### NET 'IO_L51P_4_VREF_4' J3- # U1-V14 ### NET 'IO_L51N_4' J3- # U1-U14 # ### NET 'IO_L19P_4' J3- # U1-V15 ### NET 'IO_L19N_4' J3- # U1-V16 # ### NET 'IO_L02P_4_D1' J3- # U1-V17 Config PROM D1 ### NET 'IO_L02N_4_D0_DIN' J3- # U1-V18 Config PROM D0 # ### NET 'IO_L01P_4_INIT_B' J3- # U1-AA19 to Config PROM OE/RESET_B # # MEZ-456 Connector J4 Nets # --------------------====------- # # # Original Rev. 2-Dec-2010 # Most Recent Rev. 18-Nov-2011 # # This connector has the Bank 3 and Bank 2 I/O connections # # This file defines the nets to 100 pins. # Start with Bank #3 at the pin #1 end of J4. # We can only route out 32 of these LVDS pairs # so pick the easiest to access 32 and put them # into a rational route out order. NET 'GROUND' J4-1 NET 'GROUND' J4-2 NET 'IO_L02P_3_VRN_3' J4-3 # U1-Y21 NET 'IO_L02N_3_VRP_3' J4-4 # U1-Y22 NET 'IO_L03P_3' J4-5 # U1-W21 NET 'IO_L03N_3_VREF_3' J4-6 # U1-W22 NET 'GROUND' J4-7 NET 'GROUND' J4-8 NET 'IO_L04P_3' J4-9 # U1-V19 NET 'IO_L04N_3' J4-10 # U1-V20 NET 'IO_L06P_3' J4-11 # U1-V21 NET 'IO_L06N_3' J4-12 # U1-V22 NET 'GROUND' J4-13 NET 'GROUND' J4-14 NET 'IO_L21P_3' J4-15 # U1-U19 NET 'IO_L21N_3_VREF_3' J4-16 # U1-U20 NET 'IO_L22P_3' J4-17 # U1-U21 NET 'IO_L22N_3' J4-18 # U1-U22 NET 'GROUND' J4-19 NET 'GROUND' J4-20 NET 'IO_L24P_3' J4-21 # U1-T19 NET 'IO_L24N_3' J4-22 # U1-T20 NET 'IO_L43P_3' J4-23 # U1-T21 NET 'IO_L43N_3' J4-24 # U1-T22 NET 'IO_L46P_3' J4-25 # U1-R19 NET 'IO_L46N_3' J4-26 # U1-R20 NET 'IO_L48P_3' J4-27 # U1-R21 NET 'IO_L48N_3' J4-28 # U1-R22 NET 'GROUND' J4-29 NET 'GROUND' J4-30 NET 'IO_L49P_3' J4-31 # U1-P19 NET 'IO_L49N_3' J4-32 # U1-P20 NET 'IO_L51P_3' J4-33 # U1-P21 NET 'IO_L51N_3_VREF_3' J4-34 # U1-P22 NET 'GROUND' J4-35 NET 'GROUND' J4-36 NET 'IO_L54P_3' J4-37 # U1-N19 NET 'IO_L54N_3' J4-38 # U1-N20 NET 'IO_L91P_3' J4-39 # U1-N21 NET 'IO_L91N_3' J4-40 # U1-N22 NET 'GROUND' J4-41 NET 'GROUND' J4-42 NET 'IO_L94P_3' J4-43 # U1-M18 NET 'IO_L94N_3' J4-44 # U1-M19 NET 'IO_L96P_3' J4-45 # U1-M20 NET 'IO_L96N_3' J4-46 # U1-M21 NET 'GROUND' J4-47 NET 'GROUND' J4-48 NET 'VCC' J4-49 NET 'VCC' J4-50 ### ### Currently the following 10 I/O signals from ### Bank 3 are not routed off the MEZ-456 card. # ### NET 'IO_L01P_3' J4- # U1-AA20 <-- Used on J3 ### NET 'IO_L01N_3' J4- # U1-W20 # ### NET 'IO_L19P_3' J4- # U1-U18 ### NET 'IO_L19N_3' J4- # U1-T18 # ### NET 'IO_L45P_3' J4- # U1-P17 ### NET 'IO_L45N_3_VREF_3' J4- # U1-R18 # ### NET 'IO_L52P_3' J4- # U1-P18 ### NET 'IO_L52N_3' J4- # U1-N18 # ### NET 'IO_L93P_3' J4- # U1-N17 ### NET 'IO_L93N_3_VREF_3' J4- # U1-M17 # # Now route Bank #2 at the pin #100 end of J4. # We can only route out 32 of these LVDS pairs # so pick the easiest to access 32 and put them # into a rational route out order. NET 'VCC' J4-51 NET 'VCC' J4-52 NET 'GROUND' J4-53 NET 'GROUND' J4-54 NET 'IO_L96P_2' J4-55 # U1-L22 NET 'IO_L96N_2' J4-56 # U1-L21 NET 'IO_L94P_2' J4-57 # U1-L20 NET 'IO_L94N_2' J4-58 # U1-L19 NET 'GROUND' J4-59 NET 'GROUND' J4-60 NET 'IO_L91P_2' J4-61 # U1-K22 NET 'IO_L91N_2' J4-62 # U1-K21 NET 'IO_L54P_2' J4-63 # U1-K20 NET 'IO_L54N_2' J4-64 # U1-K19 NET 'GROUND' J4-65 NET 'GROUND' J4-66 NET 'IO_L51P_2_VREF_2' J4-67 # U1-J22 NET 'IO_L51N_2' J4-68 # U1-J21 NET 'IO_L49P_2' J4-69 # U1-J20 NET 'IO_L49N_2' J4-70 # U1-J19 NET 'GROUND' J4-71 NET 'GROUND' J4-72 NET 'IO_L46P_2' J4-73 # U1-H22 NET 'IO_L46N_2' J4-74 # U1-H21 NET 'IO_L45P_2_VREF_2' J4-75 # U1-H20 NET 'IO_L45N_2' J4-76 # U1-H19 NET 'IO_L43P_2' J4-77 # U1-G22 NET 'IO_L43N_2' J4-78 # U1-G21 NET 'IO_L24P_2' J4-79 # U1-G20 NET 'IO_L24N_2' J4-80 # U1-G19 NET 'GROUND' J4-81 NET 'GROUND' J4-82 NET 'IO_L21P_2_VREF_2' J4-83 # U1-F22 NET 'IO_L21N_2' J4-84 # U1-F21 NET 'IO_L19P_2' J4-85 # U1-F20 NET 'IO_L19N_2' J4-86 # U1-F19 NET 'GROUND' J4-87 NET 'GROUND' J4-88 NET 'IO_L06P_2' J4-89 # U1-E22 NET 'IO_L06N_2' J4-90 # U1-E21 NET 'IO_L04P_2' J4-91 # U1-E20 NET 'IO_L04N_2' J4-92 # U1-E19 NET 'GROUND' J4-93 NET 'GROUND' J4-94 NET 'IO_L03P_2_VREF_2' J4-95 # U1-D22 NET 'IO_L03N_2' J4-96 # U1-D21 NET 'IO_L01P_2' J4-97 # U1-C22 NET 'IO_L01N_2' J4-98 # U1-C21 NET 'GROUND' J4-99 NET 'GROUND' J4-100 ### ### Currently the following 10 I/O signals from ### Bank 2 are not routed off the MEZ-456 card. # ### NET 'IO_L02P_2_VRN_2' J4- # U1-F18 ### NET 'IO_L02N_2_VRP_2' J4- # U1-E18 # ### NET 'IO_L22P_2' J4- # U1-H18 ### NET 'IO_L22N_2' J4- # U1-G18 # ### NET 'IO_L48P_2' J4- # U1-J18 ### NET 'IO_L48N_2' J4- # U1-J17 # ### NET 'IO_L52P_2' J4- # U1-K18 ### NET 'IO_L52N_2' J4- # U1-K17 # ### NET 'IO_L93P_2_VREF_2' J4- # U1-L18 ### NET 'IO_L93N_2' J4- # U1-L17 # # MEZ-456 Configuration PROM all Nets # -------------------------------------- # # # Original Rev. 2-Dec-2010 # Most Recent Rev. 8-Aug-2011 # # This file shows all 20 pins of the Configuration PROM. # # Config PROM pins with nets that connect to the FPGA use # the net_name of the FPGA pin that they are connected to. # NET 'IO_L02N_4_D0_DIN' U2-1 # Config PROM Data 0 to the FPGA ## Do Not Connect U2-2 # DNC Do Not Connect Pin NET 'CCLK' U2-3 # CCLK from the FPGA NET 'CONFIG_PROM_TDI' U2-4 # Config PROM JTAG TDI NET 'JTAG_TMS' U2-5 # JTAG TMS NET 'JTAG_TCK' U2-6 # JTAG TCK NET 'CF_BAR' U2-7 # Config PROM CF_Bar pin, Config pin NET 'IO_L01P_4_INIT_B' U2-8 # Config PROM OE/RESET_BAR pin is driven # by INIT_B from the FPGA which pulses # voltage low while the FPGA is clearing # its configuration memory, this # resets the PROM. ## Do Not Connect U2-9 # DNC Do Not Connect Pin NET 'DONE' U2-10 # Config PROM CE_bar pin is driven by # the FPGA DONE signal. When the FPGA # finishes configuration it drives the # PROM's CE_bar to the voltage hi, i.e. # inactive state. Power down the PROM. NET 'GROUND' U2-11 ## Do Not Connect U2-12 # DNC Do Not Connect Pin NET 'CEO_BAR' U2-13 # PROM CEO_bar pin - No Connection # This pin allows the PROM to pass # CEO to the next device. ## Do Not Connect U2-14 # DNC Do Not Connect Pin ## Do Not Connect U2-15 # DNC Do Not Connect Pin ## Do Not Connect U2-16 # DNC Do Not Connect Pin NET 'FPGA_TDI' U2-17 # Config PROM JTAG TDO --> FPGA JTAG TDI NET 'VDD' U2-18 # Config PROM Internal 3.3V Vdd NET 'VDD' U2-19 # Config PROM Output Buf 3.3V Vdd NET 'VDD' U2-20 # Config PROM JTAG Buf 3.3V Vdd # MEZ-456 Power Supply Nets and ByPass Capacitor Nets # ---------------------------------------------------------- # # # Original Rev. 29-July-2011 # Most Recent Rev. 11-NOV-2011 # # This net_list file defines the pins on both regulator chips, # all the tantalum and ceramic bypass capacitors, and the resistors # and the LED that is in the Mez-456 power supply circuits. # Mez-456 +1.5 Volt Regulator NET 'VCC' C1-1 C13-1 U3-1 # Input power to the +1.5V regulator. NET 'GROUND' C1-2 C13-2 # Ground the input filter capacitors NET 'GROUND' U3-3 # Ground the regulator gnd pin NET 'VCCINT' U3-2 U3-4 C2-1 # +1.5V Regulator output and filter capacitor NET 'GROUND' C2-2 # Ground the output filter capacitor NET 'VCC' D1-3 # Protection Diode across the +1.5V Regulator NET 'VCCINT' D1-1 D1-2 # Protection Diode across the +1.5V Regulator NET 'VCCINT' R13-2 R14-1 # +1.5V Regulator output load resistors NET 'GROUND' R13-1 R14-2 # Ground the +1.5V load resistors # Mez-456 +3.3 Volt Regulator NET 'VCC' C3-1 C14-1 U4-1 # Input power to the +3.3V regulator. NET 'GROUND' C3-2 C14-2 # Ground the input filter capacitors NET 'GROUND' U4-3 # Ground the regulator gnd pin NET 'VDD' U4-2 U4-4 C4-1 # +3.3V Regulator output and filter capacitor NET 'GROUND' C4-2 # Ground the output filter capacitor NET 'VCC' D2-3 # Protection Diode across the +3.3V Regulator NET 'VDD' D2-1 D2-2 # Protection Diode across the +3.3V Regulator NET 'VDD' R15-1 # +3.3V Regulator output LED resistor NET 'RES_LED1' R15-2 LED1-2 # LED resistor to LED1 NET 'GROUND' LED1-1 # +3.3V Indicator LED1 to ground NET 'VDD' R27-2 # +3.3V Regulator output load resistors NET 'GROUND' R27-1 # Ground the +3.3V load resistors # Tantalum "B" Case bypass capacitors on the VCCINT bus NET 'VCCINT' C5-1, C6-1 # VCCINT Tant_B caps NET 'GROUND' C5-2, C6-2 # ground side # Tantalum "B" Case bypass capacitors on the VDD bus NET 'VDD' C7-1, C8-1 # VDD Tant_B caps NET 'GROUND' C7-2, C8-2 # ground side # 100 nFd Ceramic bypass capacitors on the VCCINT bus NET 'VCCINT' C23-2, C24-1, C31-2, C44-1 # VCCINT 100 nFd caps NET 'GROUND' C23-1, C24-2, C31-1, C44-2 # ground side # 47 nFd Ceramic bypass capacitors on the VCCINT bus NET 'VCCINT' C21-2, C26-1, C33-2, C42-1 # VCCINT 47 nFd caps NET 'GROUND' C21-1, C26-2, C33-1, C42-2 # ground side # 4.7 nFd Ceramic bypass capacitors on the VCCINT bus NET 'VCCINT' C18-2, C29-1, C36-2, C39-1 # VCCINT 4.7 nFd caps NET 'GROUND' C18-1, C29-2, C36-1, C39-2 # ground side # 100 nFd Ceramic bypass capacitors on the VDD bus NET 'VDD' C17-2, C30-1, C37-2, C38-1 # VDD 100 nFd caps NET 'GROUND' C17-1, C30-2, C37-1, C38-2 # ground side NET 'VDD' C20-1, C27-2, C34-1, C41-2 # VDD 100 nFd caps NET 'GROUND' C20-2, C27-1, C34-2, C41-1 # ground side # 47 nFd Ceramic bypass capacitors on the VDD bus NET 'VDD' C19-2, C28-1, C35-2, C40-1 # VDD 47 nFd caps NET 'GROUND' C19-1, C28-2, C35-1, C40-2 # ground side # 4.7 nFd Ceramic bypass capacitors on the VDD bus NET 'VDD' C22-2, C25-1, C32-2, C43-1 # VDD 4.7 nFd caps NET 'GROUND' C22-1, C25-2, C32-1, C43-2 # ground side # 100 nfd and 47 nfd bypass caps on the Config PROM NET 'VDD' C15-1, C16-1 # VDD bypass caps Config PROM NET 'GROUND' C15-2, C16-2 # ground side # Additional 100 nFd Ceramic bypass capacitors on the VDD bus NET 'VDD' C9-2, C10-1, C11-2, C12-1 # VDD 100 nFd caps NET 'GROUND' C9-1, C10-2, C11-1, C12-2 # ground side # Additional 100 nFd Ceramic bypass capacitors on the VCCINT bus NET 'VCCINT' C45-2, C46-1, C47-2, C48-1 # VCCINT 100 nFd caps NET 'GROUND' C45-1, C46-2, C47-1, C48-2 # ground side # More Additional 100 nFd Ceramic bypass capacitors on the VDD bus NET 'VDD' C49-2, C51-1 # VDD 100 nFd caps NET 'GROUND' C49-1, C51-2 # ground side # More Additional 100 nFd Ceramic bypass capacitors on the VCCINT bus NET 'VCCINT' C50-2, C52-1 # VCCINT 100 nFd caps NET 'GROUND' C50-1, C52-2 # ground side # # MEZ-456 Everything Else Nets # ---------------------------------- # # # Original Rev. 6-Dec-2010 # Most Recent Rev. 10-NOV-2011 # # This file contains the nets for all other # components on the MEZ-456 Card, e.g.: # # M0, M1, M2 connections # Configuration push button and connector connections # DONE LED connections and connector # JTAG connections and connector # RDWR_B and CS_B Configuration connections # # This file also contains all the connections to # the J5 Access Connector. These J5 connections # appear at various places in this file. # # # MEZ-456 Access Connector J5 # # # 39 ___ 1 # +--------+ +--------+ # | | # +---------------------+ # 40 2 # # Looking down onto the pcb connector # # # # Pin Function Pin Function # --- ---------------------------- --- ---------------------------- # 1 Gnd JTAG 2 Vref JTAG Vdd # 3 Gnd JTAG 4 TMS JTAG # 5 Gnd JTAG 6 TCK JTAG # 7 Gnd JTAG 8 TDO JTAG # 9 Gnd JTAG 10 TDI JTAG # # 11 Gnd 12 Gnd # 13 GND 14 PROG_B to the FPGA # 15 Gnd 16 Gnd # 17 GND 18 DONE fron the FPGA # 19 CEO_BAR fron the PROM 20 CF_BAR from the PROM # # 21 Gnd 22 IO_L94N_0_VREF_0 U1-E11 Grn # 23 Gnd 24 IO_L93N_6_VREF_6 U1-M5 Grn # 25 Gnd 26 IO_L93P_6 U1-M6 Red # 27 Gnd 28 IO_L94P_4 U1-V12 Grn # 29 Gnd 30 IO_L94N_4_VREF_4 U1-U12 Blu # # 31 Gnd 32 no connection # 33 Gnd 34 no connection # 35 Gnd 36 no connection # 37 Gnd 38 no connection # 39 Gnd 40 no connection # # # # Configuration Mode Signal Mo, M1, M2 NET 'M0' R7-2 R10-2 # Config "M0" route to resistor pull up/down NET 'VDD' R7-1 # pull-up resistor for config M0 4.7k NET 'GROUND' R10-1 # pull-down resistor for config M0 4.7k NET 'M1' R8-2 R11-2 # Config "M1" route to resistor pull up/down NET 'VDD' R8-1 # pull-up resistor for config M1 4.7k NET 'GROUND' R11-1 # pull-down resistor for config M1 4.7k NET 'M2' R9-2 R12-2 # Config "M2" route to resistor pull up/down NET 'VDD' R9-1 # pull-up resistor for config M2 4.7k NET 'GROUND' R12-1 # pull-down resistor for config M2 4.7k # Configuration DONE signal NET 'DONE' R4-1 # pull-up on the DONE signal 330 Ohms NET 'VDD' R4-2 # pull-up DONE to VDD NET 'DONE' J5-18 # Connect DONE to the Access Conn Pin 18 NET 'DONE' R26-1 # DONE LED Series Resistor NET 'DONE_LED' R26-2 LED2-1 # DONE LED is ON when FPGA NET 'VDD' LED2-2 # is NOT Configured. # Configuration INIT_B signal NET 'IO_L01P_4_INIT_B' R5-2 # pull-up on the INIT_B signal 4.7 K Ohm NET 'VDD' R5-1 # pull-up INIT_B to VDD # Configuration PROG_B signal NET 'PROG_B' R6-2 # pull-up on the PROG_B signal 330 Ohms NET 'VDD' R6-1 # pull-up PROG_B to VDD NET 'PROG_B' J5-14 # Connect PROG_B to the Access Conn Pin 14 # FPGA HSWAP_EN signal NET 'HSWAP_EN' R16-2 # Pull-UP on HSWAP_EN signal with 4.7 k NET 'VDD' R16-1 # Pull-UP HSWAP_EN to VDD # FPGA PWRDWN_B signal NET 'PWRDWN_B' R17-1 # Pull-UP on PWRDWN_B signal with 4.7 k NET 'VDD' R17-2 # Pull-UP PWRDWN_B to VDD # Connect 2 Configuration PROM signals to the Access Connector NET 'CEO_BAR' J5-19 # Connect Config PROM CEO_BAR to Access Conn pin 19 NET 'CF_BAR' J5-20 # Connect Config PROM CF_BAR to Access Conn pin 20 # JTAG Signals # JTAG_Data_IN ---> PROM ---> FPGA ---> JTAG_Data_Out NET 'JTAG_TCK' J5-6 R1-1 # JTAG TCK from Access Connector pin #6 NET 'VDD' R1-2 # with 4.7k pull-up to PROM and FPGA NET 'JTAG_TMS' J5-4 R2-1 # JTAG TMS from Access Connector pin #4 NET 'VDD' R2-2 # with 4.7k pull-up to PROM and FPGA NET 'CONFIG_PROM_TDI' J5-10 # JTAG TDI data from the Controller to the PROM NET 'CONFIG_PROM_TDI' R3-1 # with a 4.7k Ohm pull-up resistor to VDD NET 'VDD' R3-2 # on pin #10 NET 'FPGA_TDO' J5-8 # JTAG TDO data from FPGA to the Controller pin #8 NET 'VDD' J5-2 # JTAG_VREF VDD +3.3V to the JTAG Controller NET 'GROUND' J5-1, J5-3, J5-5, J5-7 # Access Connector Grounds NET 'GROUND' J5-9, J5-11, J5-12, J5-16 # for the JTAG & Config connections NET 'GROUND' J5-13, J5-15, J5-17 # Ground the Odd Number Pins 21:39 # of the Access Connector J5 NET 'GROUND' J5-21, J5-23, J5-25, J5-27, J5-29 # Ground Pin NET 'GROUND' J5-31, J5-33, J5-35, J5-37, J5-39 # at top of J5 # Terminate the Global Clock Input LVDS Lines on Connector J1: # Global Clock #4 & 5 NET 'IO_L96N_0_GCLK5P' R22-2 NET 'IO_L96P_0_GCLK4S' R22-1 # Global Clock #6 & 7 NET 'IO_L95N_0_GCLK7P' R23-2 NET 'IO_L95P_0_GCLK6S' R23-1 # Global Clock #2 & 3 NET 'IO_L96N_1_GCLK3P' R24-2 NET 'IO_L96P_1_GCLK2S' R24-1 # Global Clock #0 & 1 NET 'IO_L95N_1_GCLK1P' R25-2 NET 'IO_L95P_1_GCLK0S' R25-1 # Terminate the Global Clock Input LVDS Lines on Connector J3: # Global Clock #6 & 7 NET 'IO_L96N_5_GCLK7S' R18-1 NET 'IO_L96P_5_GCLK6P' R18-2 # Global Clock #4 & 5 NET 'IO_L95N_5_GCLK5S' R19-1 NET 'IO_L95P_5_GCLK4P' R19-2 # Global Clock #2 & 3 NET 'IO_L95N_4_GCLK3S' R20-1 NET 'IO_L95P_4_GCLK2P' R20-2 # Global Clock #0 & 1 NET 'IO_L96N_4_GCLK1S' R21-1 NET 'IO_L96P_4_GCLK0P' R21-2 # FPGA I/O Lines to the Access Connector # Five FPGA Lines are brought to the Access Connector NET 'IO_L94N_0_VREF_0' J5-22 NET 'IO_L93N_6_VREF_6' J5-24 NET 'IO_L93P_6' J5-26 NET 'IO_L94P_4' J5-28 NET 'IO_L94N_4_VREF_4' J5-30