# # MEZ-456 Configuration PROM all Nets # -------------------------------------- # # # Original Rev. 2-Dec-2010 # Most Recent Rev. 8-Aug-2011 # # This file shows all 20 pins of the Configuration PROM. # # Config PROM pins with nets that connect to the FPGA use # the net_name of the FPGA pin that they are connected to. # NET 'IO_L02N_4_D0_DIN' U2-1 # Config PROM Data 0 to the FPGA ## Do Not Connect U2-2 # DNC Do Not Connect Pin NET 'CCLK' U2-3 # CCLK from the FPGA NET 'CONFIG_PROM_TDI' U2-4 # Config PROM JTAG TDI NET 'JTAG_TMS' U2-5 # JTAG TMS NET 'JTAG_TCK' U2-6 # JTAG TCK NET 'CF_BAR' U2-7 # Config PROM CF_Bar pin, Config pin NET 'IO_L01P_4_INIT_B' U2-8 # Config PROM OE/RESET_BAR pin is driven # by INIT_B from the FPGA which pulses # voltage low while the FPGA is clearing # its configuration memory, this # resets the PROM. ## Do Not Connect U2-9 # DNC Do Not Connect Pin NET 'DONE' U2-10 # Config PROM CE_bar pin is driven by # the FPGA DONE signal. When the FPGA # finishes configuration it drives the # PROM's CE_bar to the voltage hi, i.e. # inactive state. Power down the PROM. NET 'GROUND' U2-11 ## Do Not Connect U2-12 # DNC Do Not Connect Pin NET 'CEO_BAR' U2-13 # PROM CEO_bar pin - No Connection # This pin allows the PROM to pass # CEO to the next device. ## Do Not Connect U2-14 # DNC Do Not Connect Pin ## Do Not Connect U2-15 # DNC Do Not Connect Pin ## Do Not Connect U2-16 # DNC Do Not Connect Pin NET 'FPGA_TDI' U2-17 # Config PROM JTAG TDO --> FPGA JTAG TDI NET 'VDD' U2-18 # Config PROM Internal 3.3V Vdd NET 'VDD' U2-19 # Config PROM Output Buf 3.3V Vdd NET 'VDD' U2-20 # Config PROM JTAG Buf 3.3V Vdd