# MEZ-456 Connector J1 Nets # --------------------====------- # # # Original Rev. 2-Dec-2010 # Most Recent Rev. 10-Oct-2011 # # This connector has the Bank 1 and Bank 0 I/O connections # # This file defines the nets to 100 pins. # Start with Bank #1 at the pin #1 end of J1. # We can only route out 32 of these LVDS pairs # so pick the easiest to access 32 and put them # into a rational route out order. NET 'GROUND' J1-1 NET 'GROUND' J1-2 NET 'IO_L01P_1' J1-3 # U1-B19 NET 'IO_L01N_1' J1-4 # U1-A19 NET 'IO_L02P_1' J1-5 # U1-D18 NET 'IO_L02N_1' J1-6 # U1-C18 NET 'GROUND' J1-7 NET 'GROUND' J1-8 NET 'IO_L03P_1_VRN_1' J1-9 # U1-B18 NET 'IO_L03N_1_VRP_1' J1-10 # U1-A18 NET 'IO_L04P_1_VREF_1' J1-11 # U1-D17 NET 'IO_L04N_1' J1-12 # U1-C17 NET 'GROUND' J1-13 NET 'GROUND' J1-14 NET 'IO_L05P_1' J1-15 # U1-B17 NET 'IO_L05N_1' J1-16 # U1-A17 NET 'IO_L21P_1' J1-17 # U1-D16 NET 'IO_L21N_1_VREF_1' J1-18 # U1-C16 NET 'GROUND' J1-19 NET 'GROUND' J1-20 NET 'IO_L22P_1' J1-21 # U1-B16 NET 'IO_L22N_1' J1-22 # U1-A16 NET 'IO_L49P_1' J1-23 # U1-D15 NET 'IO_L49N_1' J1-24 # U1-C15 NET 'IO_L51N_1_VREF_1' J1-25 # U1-A15 NET 'IO_L51P_1' J1-26 # U1-B15 NET 'IO_L52P_1' J1-27 # U1-D14 NET 'IO_L52N_1' J1-28 # U1-C14 NET 'GROUND' J1-29 NET 'GROUND' J1-30 NET 'IO_L54P_1' J1-31 # U1-B14 NET 'IO_L54N_1' J1-32 # U1-A14 NET 'IO_L92P_1' J1-33 # U1-D13 NET 'IO_L92N_1' J1-34 # U1-C13 NET 'GROUND' J1-35 NET 'GROUND' J1-36 NET 'IO_L93P_1' J1-37 # U1-B13 NET 'IO_L93N_1' J1-38 # U1-A13 NET 'IO_L94P_1_VREF_1' J1-39 # U1-B12 NET 'IO_L94N_1' J1-40 # U1-C12 NET 'GROUND' J1-41 NET 'GROUND' J1-42 NET 'IO_L95P_1_GCLK0S' J1-43 # U1-D12 - clock NET 'IO_L95N_1_GCLK1P' J1-45 # U1-E12 - order pair NET 'IO_L96P_1_GCLK2S' J1-44 # U1-F13 - clock NET 'IO_L96N_1_GCLK3P' J1-46 # U1-F12 - order pair NET 'GROUND' J1-47 NET 'GROUND' J1-48 NET 'VCC' J1-49 NET 'VCC' J1-50 ### ### Currently the following 6 I/O signals from ### Bank 1 are not routed off the MEZ-456 card. # ### NET 'IO_L06P_1' J1- # U1-E17 ### NET 'IO_L06N_1' J1- # U1-E16 # ### NET 'IO_L24P_1' J1- # U1-E15 ### NET 'IO_L24N_1' J1- # U1-F14 # ### NET 'IO_L91P_1_VREF_1' J1- # U1-E14 ### NET 'IO_L91N_1' J1- # U1-E13 # Now route Bank #0 at the pin #100 end of J1. # We can only route out 32 of these LVDS pairs # so pick the easiest to access 32 and put them # into a rational route out order. NET 'VCC' J1-51 NET 'VCC' J1-52 NET 'GROUND' J1-53 NET 'GROUND' J1-54 NET 'IO_L96N_0_GCLK5P' J1-55 # U1-B11 - clock NET 'IO_L96P_0_GCLK4S' J1-57 # U1-A11 - order pair NET 'IO_L95N_0_GCLK7P' J1-56 # U1-D11 - clock NET 'IO_L95P_0_GCLK6S' J1-58 # U1-C11 - order pair NET 'GROUND' J1-59 NET 'GROUND' J1-60 NET 'IO_L91P_0' J1-61 # U1-F10 NET 'IO_L91N_0_VREF_0' J1-62 # U1-E10 NET 'IO_L93P_0' J1-63 # U1-A10 NET 'IO_L93N_0' J1-64 # U1-B10 NET 'GROUND' J1-65 NET 'GROUND' J1-66 NET 'IO_L92P_0' J1-67 # U1-C10 NET 'IO_L92N_0' J1-68 # U1-D10 NET 'IO_L54P_0' J1-69 # U1-A9 NET 'IO_L54N_0' J1-70 # U1-B9 NET 'GROUND' J1-71 NET 'GROUND' J1-72 NET 'IO_L52P_0' J1-73 # U1-C9 NET 'IO_L52N_0' J1-74 # U1-D9 NET 'IO_L49P_0' J1-75 # U1-A8 NET 'IO_L49N_0' J1-76 # U1-B8 NET 'IO_L24P_0' J1-77 # U1-C8 NET 'IO_L24N_0' J1-78 # U1-D8 NET 'IO_L22P_0' J1-79 # U1-A7 NET 'IO_L22N_0' J1-80 # U1-B7 NET 'GROUND' J1-81 NET 'GROUND' J1-82 NET 'IO_L21P_0_VREF_0' J1-83 # U1-C7 NET 'IO_L21N_0' J1-84 # U1-D7 NET 'IO_L05P_0' J1-85 # U1-A6 NET 'IO_L05N_0' J1-86 # U1-B6 NET 'GROUND' J1-87 NET 'GROUND' J1-88 NET 'IO_L04P_0' J1-89 # U1-C6 NET 'IO_L04N_0_VREF_0' J1-90 # U1-D6 NET 'IO_L03P_0_VRN_0' J1-91 # U1-A5 NET 'IO_L03N_0_VRP_0' J1-92 # U1-B5 NET 'GROUND' J1-93 NET 'GROUND' J1-94 NET 'IO_L02N_0' J1-95 # U1-C4 NET 'IO_L02P_0' J1-96 # U1-C5 NET 'IO_L01P_0' J1-97 # U1-A4 NET 'IO_L01N_0' J1-98 # U1-B4 NET 'GROUND' J1-99 NET 'GROUND' J1-100 ### ### Currently the following 6 I/O signals from ### Bank 0 are not routed off the MEZ-456 card. # # ### NET 'IO_L06P_0' J1- # U1-E8 ### NET 'IO_L06N_0' J1- # U1-E7 # ### NET 'IO_L51P_0_VREF_0' J1- # U1-F9 ### NET 'IO_L51N_0' J1- # U1-E9 # ### NET 'IO_L94P_0' J1- # U1-F11 ### NET 'IO_L94N_0_VREF_0' J1- # U1-E11 # ### Also: IO_L01P_7 U1-E5 and IO_L01N_7 U1-E6 ### which are pins physically in this octant but ### logically in another octant are not routed out.