# # MEZ-456 Everything Else Nets # ---------------------------------- # # # Original Rev. 6-Dec-2010 # Most Recent Rev. 10-NOV-2011 # # This file contains the nets for all other # components on the MEZ-456 Card, e.g.: # # M0, M1, M2 connections # Configuration push button and connector connections # DONE LED connections and connector # JTAG connections and connector # RDWR_B and CS_B Configuration connections # # This file also contains all the connections to # the J5 Access Connector. These J5 connections # appear at various places in this file. # # # MEZ-456 Access Connector J5 # # # 39 ___ 1 # +--------+ +--------+ # | | # +---------------------+ # 40 2 # # Looking down onto the pcb connector # # # # Pin Function Pin Function # --- ---------------------------- --- ---------------------------- # 1 Gnd JTAG 2 Vref JTAG Vdd # 3 Gnd JTAG 4 TMS JTAG # 5 Gnd JTAG 6 TCK JTAG # 7 Gnd JTAG 8 TDO JTAG # 9 Gnd JTAG 10 TDI JTAG # # 11 Gnd 12 Gnd # 13 GND 14 PROG_B to the FPGA # 15 Gnd 16 Gnd # 17 GND 18 DONE fron the FPGA # 19 CEO_BAR fron the PROM 20 CF_BAR from the PROM # # 21 Gnd 22 IO_L94N_0_VREF_0 U1-E11 Grn # 23 Gnd 24 IO_L93N_6_VREF_6 U1-M5 Grn # 25 Gnd 26 IO_L93P_6 U1-M6 Red # 27 Gnd 28 IO_L94P_4 U1-V12 Grn # 29 Gnd 30 IO_L94N_4_VREF_4 U1-U12 Blu # # 31 Gnd 32 no connection # 33 Gnd 34 no connection # 35 Gnd 36 no connection # 37 Gnd 38 no connection # 39 Gnd 40 no connection # # # # Configuration Mode Signal Mo, M1, M2 NET 'M0' R7-2 R10-2 # Config "M0" route to resistor pull up/down NET 'VDD' R7-1 # pull-up resistor for config M0 4.7k NET 'GROUND' R10-1 # pull-down resistor for config M0 4.7k NET 'M1' R8-2 R11-2 # Config "M1" route to resistor pull up/down NET 'VDD' R8-1 # pull-up resistor for config M1 4.7k NET 'GROUND' R11-1 # pull-down resistor for config M1 4.7k NET 'M2' R9-2 R12-2 # Config "M2" route to resistor pull up/down NET 'VDD' R9-1 # pull-up resistor for config M2 4.7k NET 'GROUND' R12-1 # pull-down resistor for config M2 4.7k # Configuration DONE signal NET 'DONE' R4-1 # pull-up on the DONE signal 330 Ohms NET 'VDD' R4-2 # pull-up DONE to VDD NET 'DONE' J5-18 # Connect DONE to the Access Conn Pin 18 NET 'DONE' R26-1 # DONE LED Series Resistor NET 'DONE_LED' R26-2 LED2-1 # DONE LED is ON when FPGA NET 'VDD' LED2-2 # is NOT Configured. # Configuration INIT_B signal NET 'IO_L01P_4_INIT_B' R5-2 # pull-up on the INIT_B signal 4.7 K Ohm NET 'VDD' R5-1 # pull-up INIT_B to VDD # Configuration PROG_B signal NET 'PROG_B' R6-2 # pull-up on the PROG_B signal 330 Ohms NET 'VDD' R6-1 # pull-up PROG_B to VDD NET 'PROG_B' J5-14 # Connect PROG_B to the Access Conn Pin 14 # FPGA HSWAP_EN signal NET 'HSWAP_EN' R16-2 # Pull-UP on HSWAP_EN signal with 4.7 k NET 'VDD' R16-1 # Pull-UP HSWAP_EN to VDD # FPGA PWRDWN_B signal NET 'PWRDWN_B' R17-1 # Pull-UP on PWRDWN_B signal with 4.7 k NET 'VDD' R17-2 # Pull-UP PWRDWN_B to VDD # Connect 2 Configuration PROM signals to the Access Connector NET 'CEO_BAR' J5-19 # Connect Config PROM CEO_BAR to Access Conn pin 19 NET 'CF_BAR' J5-20 # Connect Config PROM CF_BAR to Access Conn pin 20 # JTAG Signals # JTAG_Data_IN ---> PROM ---> FPGA ---> JTAG_Data_Out NET 'JTAG_TCK' J5-6 R1-1 # JTAG TCK from Access Connector pin #6 NET 'VDD' R1-2 # with 4.7k pull-up to PROM and FPGA NET 'JTAG_TMS' J5-4 R2-1 # JTAG TMS from Access Connector pin #4 NET 'VDD' R2-2 # with 4.7k pull-up to PROM and FPGA NET 'CONFIG_PROM_TDI' J5-10 # JTAG TDI data from the Controller to the PROM NET 'CONFIG_PROM_TDI' R3-1 # with a 4.7k Ohm pull-up resistor to VDD NET 'VDD' R3-2 # on pin #10 NET 'FPGA_TDO' J5-8 # JTAG TDO data from FPGA to the Controller pin #8 NET 'VDD' J5-2 # JTAG_VREF VDD +3.3V to the JTAG Controller NET 'GROUND' J5-1, J5-3, J5-5, J5-7 # Access Connector Grounds NET 'GROUND' J5-9, J5-11, J5-12, J5-16 # for the JTAG & Config connections NET 'GROUND' J5-13, J5-15, J5-17 # Ground the Odd Number Pins 21:39 # of the Access Connector J5 NET 'GROUND' J5-21, J5-23, J5-25, J5-27, J5-29 # Ground Pin NET 'GROUND' J5-31, J5-33, J5-35, J5-37, J5-39 # at top of J5 # Terminate the Global Clock Input LVDS Lines on Connector J1: # Global Clock #4 & 5 NET 'IO_L96N_0_GCLK5P' R22-2 NET 'IO_L96P_0_GCLK4S' R22-1 # Global Clock #6 & 7 NET 'IO_L95N_0_GCLK7P' R23-2 NET 'IO_L95P_0_GCLK6S' R23-1 # Global Clock #2 & 3 NET 'IO_L96N_1_GCLK3P' R24-2 NET 'IO_L96P_1_GCLK2S' R24-1 # Global Clock #0 & 1 NET 'IO_L95N_1_GCLK1P' R25-2 NET 'IO_L95P_1_GCLK0S' R25-1 # Terminate the Global Clock Input LVDS Lines on Connector J3: # Global Clock #6 & 7 NET 'IO_L96N_5_GCLK7S' R18-1 NET 'IO_L96P_5_GCLK6P' R18-2 # Global Clock #4 & 5 NET 'IO_L95N_5_GCLK5S' R19-1 NET 'IO_L95P_5_GCLK4P' R19-2 # Global Clock #2 & 3 NET 'IO_L95N_4_GCLK3S' R20-1 NET 'IO_L95P_4_GCLK2P' R20-2 # Global Clock #0 & 1 NET 'IO_L96N_4_GCLK1S' R21-1 NET 'IO_L96P_4_GCLK0P' R21-2 # FPGA I/O Lines to the Access Connector # Five FPGA Lines are brought to the Access Connector NET 'IO_L94N_0_VREF_0' J5-22 NET 'IO_L93N_6_VREF_6' J5-24 NET 'IO_L93P_6' J5-26 NET 'IO_L94P_4' J5-28 NET 'IO_L94N_4_VREF_4' J5-30