#
#                 MEZ-456 FPGA  All Other  Nets
#                --------------------------------
#
#
#                                               Original Rev.  2-Dec-2010
#                                            Most Recent Rev.  8-Aug-2011
#
#  This file shows  28  pins.
#  16 of these pins are shown only in this file.
#  This file defines the nets to  11  of these pins.


#  Xilinx pin names that used a "/" have had that
#  character replaced with a "_".


#  The 10 special connections along the A1-A22 edge include:

NET  'PROG_B'     U1-A2     # Pin Symb "P"  Active Low Configuration Request

NET  'DXP'        U1-A3     # Pin Symb "A"  Temperature Diode  No Connection
NET  'DXN'        U1-D5     # Pin Symb "N"  Temperature Diode  No Connection
NET  'Reserved'   U1-A20    # Pin Symb "R"  No Connection
NET  'VBATT'      U1-A21    # Pin Symb "+"  No Connection

NET  'HSWAP_EN'   U1-B3     # Pin Symb "H"  pulled up by 4.9k

NET  'JTAG_TMS'   U1-B20    # Pin Symb "M"  JTAG
NET  'JTAG_TCK'   U1-C19    # Pin Symb "K"  JTAG
NET  'FPGA_TDI'   U1-D3     # Pin Symb "I"  JTAG
NET  'FPGA_TDO'   U1-D20    # Pin Symb "O"  JTAG

#  Of these 10 signals, only PROG_B, HSWAP_EN, and the 4 JTAGs
#  need to be routed out.






#  The 18 special connections along the AB1-AB22 edge include:

NET  'M0'         U1-AB2    # Pin Symb "0"  route to resistor pull up/down
NET  'M1'         U1-W3     # Pin Symb "1"  route to resistor pull up/down
NET  'M2'         U1-AB3    # Pin Symb "2"  route to resistor pull up/down
NET  'CCLK'       U1-Y19    # Pin Symb "C"  route to Config PROM CCLK
NET  'DONE'       U1-AB20   # Pin Symb "D"  route to Config PROM CE & LED & PU

NET  'PWRDWN_B'   U1-AB21   # Pin Symb "W"  no connection




#
#  The following special signals are defined in the I/O Banks.
#                                -----------

###  AB19   IO_L01N_4/BUSY/DOUT      # no connection
###  AA19   IO_L01P_4_INIT_B         # route to Config PROM OE/RESET_B & pullup 
###   V18   IO_L02N_4_D0_DIN         # route to Config PROM D0
###   V17   IO_L02P_4_D1
###   W18   IO_L03N_4_D2_ALT_VRP_4
###   Y18   IO_L03P_4_D3_ALT_VRN_4

###    Y5   IO_L03N_5_D4_ALT_VRP_5
###    W5   IO_L03P_5_D5_ALT_VRN_5
###   AB4   IO_L02N_5_D6
###   AA4   IO_L02P_5_D7

###    Y4   IO_L01N_5_RDWR_B         # route to pull low
###   AA3   IO_L01P_5_CS_B           # route to pull low

#  Of these 18 signals,  a few need to be routed out.