MEZ-456 Module Description ------------------------------- Original Rev. 22-NOV-2010 Current Rev. 21-NOV-2011 This file is the description of the Mez-456 module. The Mez-456 is a small 95mm x 95mm FPGA mezzanine card. The Mez-456 is attached to a main circuit board via 4 100 pin Samtec FSI zero insertion force connectors. Each of these 4 connectors carries: 64 FPGA I/O lines, 32 Ground pins, and 4 Vcc +5V pins. The FPGA's I/O lines are arranged in LVDS pairs so that they can be used as LVDS signals if that is needed. These lines include 16 Global Clock Input lines. This gives a total signal count on the 4 Samtec FSI connectors of: - 256 FPGA I/O signals arranged so they can be used as LVDS pairs this includes 16 Global Clock lines - 128 Ground pins - 16 +5 Volt power pins The FPGA pins that are involved with JTAG and with Configuration are not brought off the Mez-456 card on these Samtec FSI connectors. Rather the JTAG connection to the Mez-456 is made via a small "Access Connector" pin header. Configuration of the FPGA is accomplished from a small PROM that is on the Mez-456. The Access Connector also carries the signals that are necessary to initiate configuration and to verify that it has completed OK. Only +5V Vcc power is provided to the Mez-456. Regulators on the Mez-456 provide the +3.3V Vdd I/O voltage and the FPGA core's +1.5V Vccint supply. MEZ-456 FPGA Configuration and Special Connections: ---------------------------------------------------- The following 21 pins are the FPGA signals that are involved with Configuration of the FPGA and the other "special" FPGA pins: FPGA Pin Pin Type On the MEZ-456 Card: ---------- ---------------- ----------------------------------------- TDI, TDO, TMS, TCK Dedicated Weak pull-ups R1, R2, R3 on TDI, TMS, and TCK route to Access_Conn. M0, M1, M2 Config Dedicated Route to resistor pads R7:R12 to either All 3 are Inputs pull up or down. Master Serial -> all Low. PROG_B Config Dedicated Route to Pull-Up resistor R6 and Input then to the Access Connector. CCLK Config Dedicated Route to the Config PROM CLK pin Master Serial Mode --> FPGA sends out the CCLK signal to the PROM. DONE Config Dedicated Route to a pull-up resistor and to the Open Drain Output Config PROM's CE_B pin and to the Access Conn, and to LED which is ON when the FPGA is NOT configured. The Config PROM CE_B connection powers down the Config PROM after the FPGA is configured. HSWAP_EN Config Dedicated Mez-456 pulls HSWAP_EN up to Vdd Input with resistor R16. INIT_B Used During Configuration Route to pull-up R5 and then to as an input and as an the Config PROM's OE/RESET_B open drain output, after pin. Resets the Config PROM configuration it is so that it is ready for the a normal I/O pin next configuration cycle. Not used for GPIO on the Mez-456. DIN (D0) Used During Configuration Connected to the serial data as the input for the output pin of the Config PROM. serial configuration data Not used for GPIO on the Mez-456 After config it is a normal I/O pin BUSY Used During Configuration Used for GPIO on the Mez-456. then a normal I/O Not used in Master Serial mode Configuration RDWR_B Used During Configuration Used for GPIO on the Mez-456. then a normal I/O Not used in Master Serial mode Configuration CS_B Used During Configuration Used for GPIO on the Mez-456. then a normal I/O Not used in Master Serial mode Configuration VBATT Decryptor key memory backup supply. No connection Do not connect if battery is not used. to this pin on the Mez-456 card. PWRDWN_B Active Low power-down pin (unsupported). Mez-456 pulls Driving this pin Low can adversely affect this pin up to device operation and configuration. Vdd with PWRDWN_B is internally pulled High, which resistor R17. is its default state. Reserved Reserved - make no connection Mez-456 N.C. DXN, DXP Temperature Diode Mez-456 N.C. MEZ-456 FPGA Configuration: --------------------------- Mez-456 will use the "Master Serial Configuration Mode". In this case the FPGA drives the CCLK line sending a clock signal to the PROM. With each clock the PROM returns one serial bit of configuration data to the FPGA. M0, M1, M2 are all LOW to select the Master Serial mode of configuration. The FPGA's DONE pin, which goes Voltage High at the end of the Configuration process can be used to drive the PROM's CE_B input pin. The point of this is to power down the Configuration PROM except for when it is actually needed. A pull-up is required on the DONE pin - the book says 330 Ohm - why so low ? The FPGA's INIT_B pin, which goes voltage low for a short period of time early in the configuration process, while the FPGA is clearing its configuration memory, is tied to the OE/RESET_B pin on the Configuration PROM. This resets the Configuration PROM right before it is needed. A pull-up is required on the INIT_B pin - a nominal 4.7k is fine. Configuration PROM Pins: ------------------------ Pins on the XCF04S are: Pin Num Name Function --- ---------- --------------------------------------------- 1 DO Serial Configuration Data output to the FPGA 2 (DNC) Do Not Connect 3 CLK Configuration Clock input from FPGA's CCLK 4 TDI JTAG Serial Data In 5 TMS JTAG Mode Select 6 TCK JTAG Clock 7 CF_B Configuration_Pulse_B output to Access Conn. 8 OE/RESET_B Output_Enb/Reset_B input from FPGA's INIT_B 9 (DNC) Do Not Connect 10 CE_B Chip_Enable_B input from FPGA's DONE 11 GND Ground 12 (DNC) Do Not Connect 13 CEO_B Chip_Enable_Output_B output to Access Conn. 14 (DNC) Do Not Connect 15 (DNC) Do Not Connect 16 (DNC) Do Not Connect 17 TDO JTAG Serial Data Out 18 VCCINT +3.3V supply for internal logic. 19 VCCO Supply for the FPGA drivers and receivers 20 VCCJ Supply for the JTAG drivers and receivers As used in the Mez-456 application, all 3 Vcc supply pins, i.e. VCCINT, VCCO, VCCJ are connected to the +3.3V VDD_Logic supply. As used in the Mez-456 application, all of the XCF04S Configuration PROM's pins are used except for the D0_Not_Connect pins. The CF_B and CEO_B pins run only to the Access Connector. Programming the Configuration PROM: ----------------------------------- The XCF04S Configuration PROM is programmed from a PC via the JTAG bus using the Xilinx software. Access to the JTAG bus on the MEZ-456 card is made via the pins at the pin #1 end of the J5 Access Connector. These Access Connector pins are arranged in the same order as the pins on the Xilinx JTAG adaptor pod, i.e. in a signal/gnd pair version of the JTAG bus that Xilinx uses. The MEZ-456 does not provide for re-programming its Configuration PROM via the VME bus or for holding multiple versions of firmware in the Configuration PROM at one time. The order of the devices on the JTAG bus is shown in the drawing that illustrates all the JTAG and Configuration components on the MEZ-456 card. MEZ-456 Power Supplies: ----------------------- Only the +5 Volt supply is brought onto the Mez-456 card. 16 pins on the Samtec FSI connectors are used to carry the +5 Volt supply. From the +5 Volt supply 2 low dropout linear regulators are used to make the +3.3V and the +1.5V supplies that actually operate all the components on the MEZ-456. Large tantalum capacitors are used at the input and output of these regulators. A diode across each regulator protects it against a shorted input. A minimum 10 mA load is provided for each regulator to guarantee stability. The type of regulator used will remain stable even with very large capacitive load on its output, e.g. before the FPGA starts up. Access Connector: ----------------- A 40 pin 2x20 2mm surface mount header is used as an Access connector on the Mez-456. This connector allows access to various auxiliary signals on the Mez-456 card, e.g. PROG_B to the FPGA. This connector is reference designator J5. MEZ-456 Access Connector J5 39 ___ 1 +--------+ +--------+ | | +---------------------+ 40 2 Looking down onto the pcb connector Pin Function Pin Function --- ------------------------ --- -------------------------- 1 Gnd JTAG 2 Vref JTAG Vdd 3 Gnd JTAG 4 TMS JTAG 5 Gnd JTAG 6 TCK JTAG 7 Gnd JTAG 8 TDO JTAG 9 Gnd JTAG 10 TDI JTAG 11 Gnd 12 Gnd 13 GND 14 PROG_B to the FPGA 15 Gnd 16 Gnd 17 GND 18 DONE from the FPGA 19 CEO_BAR fron the PROM 20 CF_BAR from the PROM 21 Gnd 22 IO_L94N_0_VREF_0 U1-E11 23 Gnd 24 IO_L93N_6_VREF_6 U1-M5 25 Gnd 26 IO_L93P_6 U1-M6 27 Gnd 28 IO_L94P_4 U1-V12 29 Gnd 30 IO_L94N_4_VREF_4 U1-U12 31 Gnd 32 no connection 33 Gnd 34 no connection 35 Gnd 36 no connection 37 Gnd 38 no connection 39 Gnd 40 no connection FPGA Global Clock Inputs: ------------------------- List of Where the Global Clock Nets Are Located ------------------------------------------------- On J1: NET 'IO_L95P_1_GCLK0S' J1-43 # U1-D12 - clock NET 'IO_L95N_1_GCLK1P' J1-45 # U1-E12 - order pair NET 'IO_L96P_1_GCLK2S' J1-44 # U1-F13 - clock NET 'IO_L96N_1_GCLK3P' J1-46 # U1-F12 - order pair NET 'IO_L96N_0_GCLK5P' J1-55 # U1-B11 - clock NET 'IO_L96P_0_GCLK4S' J1-57 # U1-A11 - order pair NET 'IO_L95N_0_GCLK7P' J1-56 # U1-D11 - clock NET 'IO_L95P_0_GCLK6S' J1-58 # U1-C11 - order pair On J2: None On J3: NET 'IO_L96P_5_GCLK6P' J3-43 # U1-Y11 - clock NET 'IO_L96N_5_GCLK7S' J3-45 # U1-AA11 - order pair NET 'IO_L95P_5_GCLK4P' J3-44 # U1-V11 - clock NET 'IO_L95N_5_GCLK5S' J3-46 # U1-W11 - order pair NET 'IO_L96N_4_GCLK1S' J3-55 # U1-AA12 - clock NET 'IO_L96P_4_GCLK0P' J3-57 # U1-AB12 - order pair NET 'IO_L95N_4_GCLK3S' J3-56 # U1-W12 - clock NET 'IO_L95P_4_GCLK2P' J3-58 # U1-Y12 - order pair On J4: None Pads are provided on the MEZ-456 card to put LVDS termination resistors on all of the Global Clock lines. Any additional terminators will go on the supporting circuit card.