MEZ-456 PCB Design Layout ------------------------------- Original Rev. 22-NOV-2010 Current Rev. 21-NOV-2011 This file is the pcb layout details of the MEZ-456 circuit board. Build the MEZ-456 as a square 95mm x 95mm layout. This will be 8 layers: PCB Layer #1, no FG456 escapes, all comps, non-I/O traces top Layer #2, escape the outer 2 rings of I/O signals Layer #3, Ground plane Layer #4, VDD supply fill Layer #5, escape the 3rd ring of I/O signals \ Diff Pair LVDS Layer #6, escape the 4th ring of I/O signals / Clock Signals Layer #7, VCCINT supply fill Layer #8, Ground plane fill bottom The intent is that this card will mount near the top of the 6U 160mm deep VME card. It will probably mount somewhat near the front edge to give space for VME transceiver chips on the main board. It makes sense to bring in the VME stuff along which ever edge is up. That gives the East, West, and South edges the closest access to the bulk of the "user" I/O. The layout should be oriented to put all the other non user I/O connections on top. Thus for best routing I think that it makes sense to put the A1-A22 edge of the FPGA up and the AB1-AB22 edge down. This is the standard text book orientation . There are enough I/O pins so that we do not need to reuse all the dual purpose configuration pins. The 10 special connections along the A1-A22 edge include: A2 "P" PROG_B active low starts Configuration pull up A3 "A" DXP no connection temperature diode D5 "N" DXN no connection temperature diode A20 "R" Reserved no connection A21 "+" VBATT no connection B3 "H" HSWAP_EN pull-up 4.7k default HI turns off pull ups B20 "M" JTAG TMS C19 "K" JTAG TCK D3 "I" JTAG TDI D20 "O" JTAG TDO Of these 10 signals, only PROG_B, HSWAP_EN, and the 4 JTAGs need to route out. The 18 special connections along the AB1-AB22 edge include: AB2 "0" M0 route to resistor pull-down W3 "1" M1 route to resistor pull-down AB3 "2" M2 route to resistor pull-down Y19 "C" CCLK route to Config PROM CCLK AB20 "D" DONE route to Config PROM CE_B and pull-up AA19 IO_L01P_4/INIT_B route to Config PROM OE/RESET_B & pullup V18 IO_L02N_4/D0/DIN route to Config PROM Serial Data Output AB21 "W" PWRDWN_B routed to resistor pull-up with 4.7 k Ohm AB19 IO_L01N_4/BUSY/DOUT could be use for general I/O Y4 IO_L01N_5/RDWR_B could be use for general I/O AA3 IO_L01P_5/CS_B could be use for general I/O V17 IO_L02P_4/D1 could be use for general I/O W18 IO_L03N_4/D2/ALT_VRP_4 could be use for general I/O Y18 IO_L03P_4/D3/ALT_VRN_4 could be use for general I/O Y5 IO_L03N_5/D4/ALT_VRP_5 could be use for general I/O W5 IO_L03P_5/D5/ALT_VRN_5 could be use for general I/O AB4 IO_L02N_5/D6 could be use for general I/O AA4 IO_L02P_5/D7 could be use for general I/O MEZ-456 8 Layer Stackup: ------------------------- Let's try a 8 layer strategy for the Mez-456 with the following stackup: PCB Stackup Mentor Layer Layer Function ------- ------ ------------------------------------------------------ 1 Sig-1 no FG456 escapes, all comps, non-I/O traces top 2 Sig-4 escape 1st & 2nd ring I/O signals 3 Pow-1 Ground plane 4 Sig-5 VDD supply fill 5 Sig-2 escape the 3rd ring of I/O signals \ Diff Pair LVDS 6 Sig-3 escape the 4th ring of I/O signals / Clock Signals 7 Sig-6 VCCINT supply fill 8 Sig-7 Ground plane fill bottom The 8 layer routing stratigy is: - Use a FG456 escape layout that has pad vias on all I/O pads (even the outer 2 rings). - Escape the first 2 rings of I/O pads on layer #2. - Escape the 3rd ring of I/O pads on layer #3. - Escape the 4th ring of I/O pads on layer #4 - Try not to use very many I/O signals from the 5th and 6th rings. - Traces that run to the outer ring of FSI pads will run out past the inner ring of FSI pads and then via down to the bottom layer and run directly to their pad. - Traces that run to the inner ring of FSI pads will run to just in front of their FSI pad and then via down to the bottom layer and run directly to their pad. - All components (except for the FSI pads) are on the top layer of the card. Non-I/O traces for connecting these components are routed on the top layer. Traces and Vias: ---------------- Layer 1 traces into 1st or 2nd ring of FG456 pads: 0.15 Layer 1 traces between the outer ring of FG456 array vias: 0.13 Layer 1! traces between vias in the FG456 array: 0.13 or 0.15 ?? Layer All signal routing: 0.15 0.20 0.25 Layer All signal traces in the VME connectors: 0.25 Layer All power traces in the VME connectors: 0.35 power traces to the 0603 bypass caps 0.50 power traces to tantalum bypass caps 1.20 Layer 1 traces to the 2x20 2mm connector 0.75 Layer 1 signal traces into the TSSOP parts: 0.20 Layer 1 power traces into the TSSOP parts: 0.25 With the 0.61 mm via lands in the FG456 array, there are basically 2 choices for this routing: 0.15mm traces with 0.12mm trace to pin clearance 0.13mm traces with 0.13mm trace to pin clearance Traces and Vias Actually Used on MEZ-456: ----------------------------------------- For the GPIO runs from the FPGA to the FSI connectors Mez-456 will use: 0.20mm traces with 0.13mm traces to escape the FG456 with 0.13mm trace to pin clearance. A few traces run right to FG456 pads on the top surface of the card. These traces are 0.20 mm The 0603 bypass caps use 0.75mm traces with the via_mm65. The via center is 0.5mm from the end of the 0603 pad. The 2x20 2mm Access Connector J5 uses 0.75mm traces with the via_mm65. The via center is 0.6mm from the end of the connector pad. The FSI Connectors J1:J4 use 0.50mm traces with the via_mm65. For the ground connections the via center is 0.5mm from the end of the connector pad. For the signal connections the via is either centered between the 2 rows of pads or else its center is 1.5mm from the end of the connector pad. The via for the signal pin nerest the out end of each end of the connector is blocked by the mounting pin hole. These 2 pin have a special via location on each connector. The power and ground traces that connect to the Config PROM are 0.35mm. The other signal traces on the top of the card are 0.20mm. The traces that connect to the 3 terminal regulators are 0.75mm or for traces to the Tants 1.20mm. The traces that connect to the "D" case Tants are 1.20mm. Small signal vias: via_mm65 power vias: via_0_6_mm 40 pin 2x20 2mm connector vias: via_mm65 The two vias used on the Mez-456 are: via_mm65 0.65mm land pad 1.10mm plane relief 0.30mm hole via_1mm1 1.10mm land pad 1.65mm plane relief 0.60mm hole This is the same as used before except for the via_mm65 the plane felief has been opened from the old 1.00mm to the 1.10mm used in this design. Two via_mm65 can be placed 1.0mm apart if no trace is routed between them. Where space is available then a 1.1mm c to c placement looks better. The BGA FG456 used a 0.40mm pad with a 0.50mm solder mask opening. The via in the FGA array is: 0.30mm drill, 0.61mm via pad, 0.85mm power relief --> 0.12mm clearance on the power plane. The FSI connector wipe pads will use a 0.50mm trace to leave the pad and run to a via_mm65 and then run to the FPGA with 0.20mm trace. The via is placed as close to the pad as the clearance rule allows. The vias are outside of the ring of pads. The ground and power pads in the FSI connectors are setup in the same way. Via Column Spacing with 0.20mm traces and spacing or with 0.15mm traces on 0.40 centers. Two via_mm65 with 0 traces between can be 1.00 mm apart. Two via_mm65 with 1 traces between can be 1.25 mm apart. Two via_mm65 with 2 traces between can be 1.65 mm apart. Two via_mm65 with 3 traces between can be 2.05 mm apart. Two via_mm65 with 4 traces between can be 2.45 mm apart. Planes vs Fills: ---------------- Should the power planes be done as planes or as fills. I think that the fills have the advantage of easily allowing one to flood the plane into the via drill. The ground plane need to run to within 0.20mm or whatever of the edge of the card. The VDD and VCCINT planes only need to run out to their regulators and passive components. Thus there is space on one of these layers for the +5 Volt power input trace. Net Lists: ---------- The following 3 net_list files define just the FPGA net names and pin numbers using the signal names in the Xilinx documentation as the net names. mez_fpga_io_banks.txt mez_fpga_gnd_pow_nets.txt mez_fpga_all_other_nets.txt The following 4 net_list files define all 100 pins in each of the Samtex FSI connectors, i.e. giving each pin a power or ground net name or a net name that is an FPGA I/O signal name. mez_conn_j1_nets.txt mez_conn_j2_nets.txt mez_conn_j3_nets.txt mez_conn_j4_nets.txt The following net_list file defines all 20 pins on the Conf PROM mez_config_prom_nets_all.txt The following net_list file defines all the pins on the power supply regulator chips and on the tantalum and ceramic bypass capacitors for the +5V input, +3.3V VDD, and +1.5V VCCINT nets, and for the resistors and the LED in the power supply circuit. mez_power_and_bypass_cap_nets.txt The following net_list file defines all the remaining component pins especially including the Access Connector J5. mez_everything_else_nets.txt Modifications to the Defalut FG456 Mentor Geometry: --------------------------------------------------- Our default Mentor Geometry for the FG456 package has all of the normal escapes and vias that are shown in the Xilinx documentation for the standard routing for the xc2v1000 on page 394 of UG002. The following are required rational modifications to this plain 4 quadrant geometry. - Remove the via from pin A2 PROG_B this pin may be routed out and it does not need to be connected to a plane. - Remove the via from pin A3 DXP this pin may be routed out and it does not need to be connected to a plane. - Remove the via from pin A20 RESERVED because this pin is to be left floating. - Remove the via from pin A21 VBATT because this pin is to be left floating. - Remove the via from pin B20 TMS this pin may be routed out and it does not need to be connected to a plane. - Remove the via from pin D5 DXN this pin may be routed out and it does not need to be connected to a plane. - Remove the via from pin E11 IO_L94N_0 this pin may be routed out and it does not need to be connected to a plane. - Remove the via from pin M5 IO_L93N_6 this pin may be routed out and it does not need to be connected to a plane. - Remove the via from pin V12 IO_L94P_4 this pin may be routed out and it does not need to be connected to a plane. - Remove the via from pin AB2 M0 this pin may be routed out and it does not need to be connected to a plane. - Remove the via from pin AB3 M1 this pin may be routed out and it does not need to be connected to a plane. - Remove the via from pin AB20 DONE this pin may be routed out and it does not need to be connected to a plane. - Remove the via from pin AB21 PWRDWN_B this pin may be routed out and it does not need to be connected to a plane. - Add East vias to pins: B22 VCCAUX and AA22 VCCAUX and add West vias to pins: B1 VCCAUX and AA1 VCCAUX because although these VCCAUX pins are in the position normally used by signal pins - they do need to get to the VDD plane. - Remove the via from the following 61 pins. These are mostly the inner ring signal I/O pins that are not used in the MEZ-456 design. E: 5, 6, 7, 8, 9, 13, 14, 15, 16, 17, 18 F: 5, 9, 11, 14, 18 G: 5, 18 H: 5, 18 J: 5, 6, 17, 18 K: 5, 6, 17, 18 L: 6, 17, 18 M: 17 N: 5, 6, 17, 18 P: 5, 6, 17, 18 R: 5, 18 T: 5, 18 U: 5, 9, 10, 11, 14, 18 V: 5, 6, 7, 8, 9, 10, 14, 15, 16, 17 W: 20 Net Type Rules for the Default Net_Type: ---------------------------------------- Stable and in use 11-NOV-2011 Pin Via Trc Fil Pin 0.50 Via 0.15 0.35 Trc 0.13 0.20 0.25 Fil 0.13 0.35 0.40 0.25 Area Fills Procedure: --------------------- Then to generate the Area Fill Recall that MEZ-456 has a separate area fill shape for: Signal Layer 5 Physical Layer 6 Vdd Signal Layer 6 Physical Layer 7 Vccint and a separate area fill shape for: Signal Layer 7 Physical Layer 8 Ground fill. Pull Down Setup --> Shape Edit Mode ON Select the shape from the Shape Edit layer Right Click --> Change Shape to Fill: Area Fill ? vs Power Fill ? This is an Area Fill because it is on a trace layer and not on a power plane layer. Select Layer = Signal_5, _6, _7 Select Net = Vdd, Vccint, GROUND Keep all Area Fill defaults NO delete the original shape typical warning: Area Fill is fractured into "N" pieces. After generating the 3 area fills, setup the view as you like and then make a save all. If necessary to delete and area fill use FabLink: Select the Area Fill on its Signal_ layer Area Fill Panel Menu --> Delete vertexes Then do atleast a "save traces" The following setup looks OK on 24AUG11 Modify Net Type Rules for Area Fill Generation: Pin Via Trc Fil Pin 0.50 Via 0.15 0.35 Trc 0.13 0.20 0.25 Fil 0.13 0.35 0.40 0.25 Modify the Setup Area Fill i.e. Setup Routing --> Area Fill Pad Isolation Shape = Polygon Tolerance = 0.01 Manufacturing Aperature Size = 0.1 Minimum Pad Sloting Threshold = 0.01 Solid Keep Islands = NO Allow Area Fill Merge = YES Ignore area fill to via clearance for same net = NO Ignore area fill to pin flearance for same net = NO Thermal Tie SMD = Thermal Tie, prefer 4, min 3, 45-135, 0.13 Pin = Flood Via = Flood Note that on this design this works OK only because the only component with "pins" is the FG456 - all other fill isolations are from "vias". Thus it is simple to control this with the Net Type Rules for Default Nets using different fill to pin and fill to via clearances. There are separate Shape Outlines for the Vdd Vccint files and for the GROUND fill. The Vdd Vccint files have cutouts for Vcc traces to run to the regulators. The GROUND fill is big enough to just reach the inner ring of FSI ground connections. The Vdd, Vccint, and GROUND fills are all generated using the above "Net Type Rules" and "Area Fill Setup". Notes: - The large "Fill to Trace" clearance is to make the the GROUND fill look good where it connects to the inner ring of FSI ground pins. 31-Aug-11 1298/138 build Vdd --> 1252/55 on signal 5 build Vccint --> 1237/14 on signal 6 build Gnd --> 1313/0 on signal 7 cp to a named traces file for pre-fill generation tar and then delete the "saved" nets files that are no longer current. 17-Nov-11 The final version of the design files before making the fills are: Traces_75 Comps_180 Nets_95 right before the final fills are generated: Conn = 1207 Fin = 1081 Un-Fin = 44 Guide = 82 1207(126) Setup right after the final fills are generated: Traces_76 Conn = 1162 Fin = 1162 Un-Fin = 0 Guide = 0 Components: 94 (0) Traces 1162 (0) 18-Nov-11 The final version of the design files before making the fills are: Traces_80 Comps_180 Nets_98 right before the final fills are generated: Conn = 1228 Fin = 1101 Un-Fin = 47 Guide = 80 1228(127) Setup right after the final fills are generated: Traces_81 Conn = 1161 Fin = 1161 Un-Fin = 0 Guide = 0 Components: 94 (0) Traces 1161 (0) Why one less Connection than yesterday ?? Modifications on 10-OCT-2011: ----------------------------- Edit the J1 and J3 net list files (mez_conn_j1_nets.txt and mez_conn_j3_nets.txt) so that the Global Clock input LVDS pin pairs are side by side in the FSI connectors. That is make the following LVDS pin pairs: 43-45, 44-46, 55-57, and 56-58 for the Global Clock net inputs. This intent of this change is to make cleaner LVDS input signal pairs for the Global Clock signals. Edit all the references in the MEZ-456 and H-Clk documentation about which Global Clock nets are on which J1 and J3 FSI connector pins. Recall that the Mez-456 components file is now under the control of the Mentor Comps file. Modification on 18-NOV-2011: ---------------------------- I had used FPGA signal/pin IO_L01P_4_INIT_B U1-AA19 as the connection to Mez-456 general I/O pin J3-97. This would have worked OK but its not really very clean because INIT_B might have to pull the output of an H-Clk card LVDS receiver low (which it could do) and/or one would be banging away at the Config PROM's OE/RESET_B pin (which would have been OK because the PROM would have been disabled). But this is not very clean. So change the net_list so that J3-97 is now tied to FPGA pin/signal IO_L01P_3 U1-AA20. This requires editing the BGA-456 rev 6 Geometry so that AA20 has a via. Doing that requires deleting the 3 fills and starting the whole process of checking traces, generating fills, and generating Gerber and Drills again. Note that J3-97 and J3-98 are no longer a LVDS pair - but that makes no difference to how Mez-456 will be used on the H-Clk card so for now this sounds more rational than using continuing with INIT_B as a General I/O signal on H_Clk. Modification on 21-NOV-2011: ---------------------------- Change to the more rational stackup as indicated in the following table. I believe that I have gone back through this document so that all places where the board physical layers are described, that the following now stackup is indicated. Obviously no change is being made in the Mentor layers at this point in the design. The Gerber plotting script is beging edited so that the plots will be generated with rational monotonic file numbers. The Gerbers must then be re-generated and checked. PCB Stackup Mentor Layer Layer Function ------- ------ ------------------------------------------------------ 1 Sig-1 no FG456 escapes, all comps, non-I/O traces top 2 Sig-4 escape 1st & 2nd ring I/O signals 3 Pow-1 Ground plane 4 Sig-5 VDD supply fill 5 Sig-2 escape the 3rd ring of I/O signals \ Diff Pair LVDS 6 Sig-3 escape the 4th ring of I/O signals / Clock Signals 7 Sig-6 VCCINT supply fill 8 Sig-7 Ground plane fill bottom Making this stackup change requires editing the following files: this mez-456 design layout file art work order script "geometry" mez-456 pcb geometry file that labels the layers (on & off pcb) the bare pcb manufacturing instructions file re-generate and re-check all 14 Gerber files Design Rule Checks ------------------ Check --> Traces --> Check_Traces Entire Board Remove Trace Violations NOT Selected Check Net Against Itself NOT Selected Check Trace Widths Less Than Net Rules NOT Selected Check All Thermal Ties on Pins and Vias Selected Check Same Net Pad to Pad Clearances Selected Remove Duplicate Routing NOT Selected Check Pad Connectivity With Fill Hatch NOT Selected Report Off Grid Vias as: Not Checked Report Uncovered Plated Drill Holes as: Warnings At the start of a number of passes with the design rule checker there were about 56 warnings of the type, "Warning: Two vertices are coincident". I checked a number of these by hand and they were all right up agains the FSI escape routing from Mentor trace copies. I let it run with "Remove Duplicate Routing" enabled and it pulled out about 56 of these. I verified that all of the on purpose duplicate routing was still there, e.g. double grounds on the Tant caps and regulators, and the 6 Vcc traces around the perimeter. After this I wrote Traces_75 on 16-Nov. This leaves 20 warnings about the "Not Covered - Un-Plated Drill Holes". There are 5 warnings from each of the 4 FSI connectors. The issue is no plane relief on the mounting and alignment holes for the FSI connectors. Add this relief to its Geometry. Note that the fills are not generated at this point. Ran DRC and saved the result "no_fills" in .../Work/Text/ Currently: Conn = 1207 Fin = 1081 Un-Fin = 44 Guide = 82 1207(126) Note that during this "pre-fill" round of DRC Checks I could change the design rules up to: Pin Via Trc Fil Pin 0.50 Via 0.16 0.35 Trc 0.13 0.27 0.27 and it was still error free. Even with Pin-Pin very large there were no violations of that type (duh its all SMD). The other 5 clearances shown above are right at their limit. Trace-Pin of 0.14 makes 690 errors. Trace-Pin of 0.23 makes 690 errors. Trace-Pin of 0.24 makes 714 errors. 17-Nov-11 make the final DRC runs now with the fills generated in the design. All clean except for I believe 70 warnings about poor GND fill coverage on Physical_8. This is expected as I have only 1/2 of these Gnd vias covered on purpose - the other 1/2 of the via is a Gnd trace to an FSI connector pin. If the count is 70 I do not understand that yet. It should be 16 x 4 plus 2 x 2 = 68. Need to double check the DRC report. Final before and after fills DRC reports are in ...Work/Text/ 18-NOV-11 make the final DRC runs back with the fills removed from the design. This is running on Traces_80. All of the vias and traces and such look OK to the eye, i.e. double things are there. As shown above this had zero errors with clearances set to: Pin Via Trc Fil Pin 0.50 Via 0.16 0.35 Trc 0.13 0.27 0.27 Traces_80 has: Connections 1228 Finished 1101 Un-Finished 47 Guides 80 1228 (127) And now make a run of DRC with the fills back in the design. This has the expected 70 warnings about poor fill coverage. Save a copy of this DRC in ../Work/Text/. The design has 1161 connections and 1161 finished traces. Why one less Connection than yesterday ?? It has 349 Nets. Gerber Plot Generation Final ----------------------------- Assume that the Gerber Format has been setup and saved. Gerber Data is in mm 3.2 format. If necessary use: Right Click --> Artwork --> Change Artwork Format Image Scale: 1 Units: mm Mode: Absolute Plot Offsets: Manual with X=0.0 Y=0.0 G_Code: Allow Zero Suppression: None Interpolation: Linear with 8 Segments Output Format: 3 Significant and 2 decimal Data Record Length: 80 Header String: none Sub-Header String: none Trailer String: none Machine Stop Code: M02 XY-Modal: not checked Open Shutter Modal: not checked View Artwork Format: not checked Command Block End Character: * Aperature Table: Right Click --> Artwork --> Change Aperature Table --> Delete All Apertures Right Click --> Artwork --> Change Aperature Table --> Fill Aperature Table Select the Apertures for ALL Aizes Select NO ReSize and NO ReScale Flash Complex Padstacks: not checked Replace the table Report the Aperture Table (from Report Pull Down Menu) Include the ArtWork Format: yes Save and Display the Report Save Report to .../Work/Text/ Replace the existing Report May/Will need to Edit the Power Apertures: After the Aperture Table is filled it is necessary to edit the 3 Power Apertures (aka thermal reliefs) to get the desired layout. To edit a Power Aperture Right Click --> Artwork --> Change Aperture Table --> Change Power Aperture For each Power Aperture select the Aperture Position and then set the: Tie Width, Air Gap, and Rotation and then click OK. Note that the outer diameter of each Power Aperture is driven by its "power plane relief" diameter in its Geometry. We must set the Air Gap to get the desired pad size and set the Tie Width to get the desired amount of Copper connection. This version of Mentor lets us control the Tie Rotation. After editing the Power Apertures are the following: Position Shape Diameter Power Dcode -------- ------ -------- ----- ----- 29 circle 1.10 true 129 30 circle 1.65 true 130 32 circle 0.85 true 132 Recall that the Diameter shown for the Power Apertures is the Diameter of the Plane Relief. Edit to have: Position 29 is the via_mm65 i.e. 0.65mm Land 1.10mm Relief --> Tie 0.30 mm Air 0.22 mm Rotate 0 deg. Position 30 is the via_1mm1 i.e. 1.10mm Land 1.65mm Relief --> Tie 0.35 mm Air 0.25 mm Rotate 45 deg. Position 32 is the BGA_Via5 i.e. 0.61mm Land 0.85mm Relief --> Tie 0.20 mm Air 0.11 mm Rotate 45 deg. In all cases this gives slightly larger Land than in the associated via's Signal layers and it gives rational Tie Width. Gerber Data Generation: Right Click --> Artwork --> Creat Artwork Data Gerber Data is Gerber 274X format Stroke the Area Fill, Flash the Polygon ASCII Data, for the BOARD, ALL ArtWork Numbers (1:14) NO Tear Drops, REMOVE Unused Pins, REMOVE Unused Via's NO Output UnPlated Holes NO ReSize, NO ReScale Right Click --> Artwork --> Creat Artwork Data All settings are the same except create Gerber Data for just ArtWork Numbers 1 and 8 i.e. the top and bottom pcb layers, but use the option Output ALL Pins, Output ALL Via's Gerber Data Viewing: Right Click --> Artwork --> Simulate Artwork Data Gerber Generation Notes: - At close of this work it was left with aperture_talble_27 as the current one. Art_Format = 24. Drill File Generation Final ---------------------------- Assume that the Drill Format has been setup and saved. Drill Data Format is: Drill Origin X=0 Y=0, Units = mm, Scale =1, Zero Supp = none, Mode = Absolute, NO Drill at Origin, Format mm 3.2 Stop Code = M30, nothing else is set. Drill Table: Right Click --> Drill --> Change Drill Table --> Delete All Drills Right Click --> Drill --> Change Drill Table --> Fill Drill Table Select Replace the Drill Table Right Click --> Drill --> Creat Drill Data Excellon, Board, ASCII, Drill Hole Type: Both Output Hole Types: ALL, NO Mirror. Report the Drill Table (from Report Pull Down Menu) Include the Drill Format Save and Display the Report Save Report to Design with .../Work/Text/ filename Replace the existing Report Look at the Simulation of the Drill Data and find: Drill Drill Position Size Count Function ---------- ------ ----- -------------------- 1 0.30 923 via_mm65 & BGA_Via 2 0.60 21 via_1mm1 3 1.00 2 Molex 2mm conn Alignment 4 1.19 8 Sam FSI Conn Alignment 5 2.54 12 Sam FSI Conn Screws This drill data was generated with Drill_Table_25 Drill_Format_24. ====================================================================== ====================================================================== TO-DO WORK 7. generating the parts order information for ordering all of the parts to build the cards part of this step is checking what we have in stock that either exactly matches what is currently in the design or is close enough 8. talking to a couple of bare pcb houses and assembly houses to find a company to do this work and to get a cost for doing this work ====================================================================== ====================================================================== Old material from this and other designs ---------------------------------------- abandon the 6 layer stackup But let's try a 6 layer strategy for the Mez-456 with the following stackup: Layer #1, Top, escape the outer two rings of I/O pins Layer #2, escape the next 2 rings of I/O pins using pad/vias Layer #3, VCCINT supply plane Layer #4, Ground plane Layer #5, VDD supply plane Layer #6, escape the inner most I/O pins using pad/vias Initial routing stratigy for this 6 layer layout is: - Use only the outing 4 rings of I/O pins on the FPGA. This keeps free of traces escaping the FG456 basically all of the bottom layer of the card. - The top layer escapes from the FG456 will run only a short distance and then all of them will go into vias. This must be a very tight set of vias. They probably need to be 2 (or 3) concentric rings of vias with one trace between. . Traces that run to the outer ring of FSI pads will dive down to layer #2, run to the outside of the outer ring of pads, and then via down to the bottom layer and connect to their FSI pad. . Traces that run to the inner ring of FSI pads will dive down to the bottom layer. - The layer #2 FG456 escape traces will either: . Traces to the outer ring of FSI pads will stay on layer #2, run to the outside of the outer ring of pads, and then via down to the bottom layer and connect to their FSI pad. . Traces that run to the inner ring of FSI pads will dive down to the bottom layer. - All other components, e.g. regulators, capacitors, resistors, config prom, must be placed on the top surface of the card, and must be placed outside of these rings of FG456 escape vias. - The bottom layer of the card, inside of the rings of FG456 escape vias, is the only layer for routing random signals, e.g. config prom signals, access connector signals. Second routing stratigy for this 6 layer layout is: - Use only the outing 4 rings of I/O pins on the FPGA. Do this by placing vias on all the FG456 signal pads. - Escape the first two rings of signal pads on Layer #2. Run them over to the FSI connector on Layer #2 and then via down to the FSI pads on the bottom layer of the card. This keeps free of traces escaping the FG456 basically all of the bottom layer of the card. Third routing stratigy for this 6 layer layout is: Initial routing stratigy for this 6 layer layout is: - Use only the outing 4 rings of I/O pins on the FPGA. This keeps free of traces escaping the FG456 basically all of the bottom layer of the card. - The top layer escapes from the FG456 will run only a short distance and then all of them will go into vias. This must be a very tight set of vias. They probably need to be 4 concentric rings of vias with 3 trace between on the top layer and 4 traces betwteen on layer #2. . Traces that run to the outer ring of FSI pads will dive down to layer #2, run to the outside of the outer ring of pads, and then via down to the bottom layer and connect to their FSI pad. . Traces that run to the inner ring of FSI pads will dive down to the bottom layer. - The layer #2 FG456 escape traces will either: . Traces to the outer ring of FSI pads will stay on layer #2, run to the outside of the outer ring of pads, and then via down to the bottom layer and connect to their FSI pad. . Traces that run to the inner ring of FSI pads will dive down to the bottom layer. - All other components, e.g. regulators, capacitors, resistors, config prom, must be placed on the top surface of the card, and must be placed outside of these rings of FG456 escape vias. - The bottom layer of the card, inside of the rings of FG456 escape vias, is the only layer for routing random signals, e.g. config prom signals, access connector signals. Second routing stratigy for this 6 layer layout is: - Use only the outing 4 rings of I/O pins on the FPGA. Do this by placing vias on all the FG456 signal pads. - Escape the first two rings of signal pads on Layer #2. Run them over to the FSI connector on Layer #2 and then via down to the FSI pads on the bottom layer of the card. This keeps free of traces escaping the FG456 basically all of the bottom layer of the card. Third routing stratigy for this 6 layer layout is: abandon the 6 layer stackup Why 6 layer will not work In theory one can escape all the FG456 signal traces on just 3 layers. Another 3 layers are required for the power and ground planes. Thus in theory the Mez-456 could be built as a 6 layer card. I do not think that this will work because: - The top surface of the card needs to be almost clear of traces to hold the Config PROM and the Regulators. - Traces that escape the BGA would need to drop down to an inner layer before or soon after the ring of bypass capacitors that must be around the FPGA. There is not much space available in this area for all of the vias to drop the top layer signal traces down to the middle or bottom trace layers. - There is no space on layer #2 for all the traces from the top layer. Layer #2 already has a trace every 0.5mm - There is not enough space between pads for the FSI connector on the bottom of the card to run a trace. So traces to the outer ring of FSI pads must get outside of the inner ring of FSI pads on an inner layer and then via down to the bottom layer and run to the outer ring of pads. - You can get about 5 bypass capacitors per side around the FG456 package - 0603 capacitors. This is probably just on the bottom side. There is no space on the top of the card for capacitors right next to the FG456 package. There is no space within the FG456 package foot print for any 0603 size capacitors.