Front-End Board Replacement Limited Scope Version ---------------------------------------------------- Rev. 2-APR-2010 - The primary goal of this design is to replace the part of the functionality of the existing Analog and Digital Front-End Boards that is actually used in the HAWC experiment and to do this in an inexpensive way using contemporary electronics. - The secondary goal of this design is to think about more modern ways to implement the whole TDC front-end system for the HAWC experiment. - A major item in controlling the cost of replacement FEBs will be to reduce the size and number of the boards. Specifically the Analog and Digital cards should be combined into one card and the size reduced from 9U to 6U. 9U cards are inherently expensive not only because of the extra material used to make them but especially because of the limited number of pcb companies and assembly companies that want to work with these, now days, uncommonly large cards. - This limited scope version of the replacement FEB will have a VME interface that allows setup and control of the card but does not support event trigger speed readout of data from the card. That is, this limited scope replacement FEB still uses the external TDC and Scaler DAQ systems. A more ambitious replacement card could consider bring the TDC, Scaler, and event readout functions on board. - The combination of a 6U card size and the fact that the PMT signals are logically handled 3 at a time (a tanks worth) together imply that a 9 channel card may be a rational layout. - Only the SHV PMT cable connectors should be on the front of the card. All of the outputs should move to the back of the card where the cabling from these outputs may remain permanently installed. The backplane P0 and P2 connectors together can conveniently provide 56 differential output signals that may be routed through non-bused user defined backplane pins to cable connectors. By using more specialized cables another 23 differential output signals may be routed through the backplane to cable connectors if this many output signals are required. - The digital output signal levels from the replacement FEB should be LVDS instead of the differential ECL used on the original FEBs. - The digital outputs from the replacement FEB must include all of those actually used on the current Digital FEBs, that is individual PMT channel signals to: TDC, Scaler, and Trigger. Note that externally splitting the current low threshold solar output to feed both the Scaler and the Trigger will not be required with the replacement FEBs. - Optional Digital outputs might include: a "group trigger" signal based on all 9 PMT channels, or 3 "group trigger" signals with each one based on a tank's worth of PMTs, or a special high threshold scaler signal. - An optional Analog output, one from each PMT channel, to send a signal to a fast ADC system is possible if such and ADC system will be used sometime in the future. - This output signal count described above is comfortably within the backplane pin count that is available. - High voltage layout on a dense card that must operate at high altitude is clearly an issue. There are both IPC and UL guidelines and specification for how this should be done. A significant point is that coating the HV section of these card will be useful. - Clean layout of the HV and low level signal input section will be very important on these cards to achieve a low inherent noise level. It will be useful to move to all surface mount components in this section of the card (to eliminate sharp cut component leads). The required components are available but have a long lead times. It would be very nice if the long tail of the SHV input connectors could be used to do a "reach over" layout, i.e. HV distribution on one side and low level analog input on the other side. - It will save significant money if the HV and low level signal input section of the card can be layed out cleanly enough so that it does not require metal shielding as is used on the current FEBs. Individual analog ground fingers should be used in the layout. - The low level signal input section should contain a good sturdy diode protection network against over voltage inputs, e.g. from cable breakdown or lightning strikes. Experience handling this problem on the current FEBs should be taken into account. Ample layout space to easily replace these components should be provided. - There are many nice commercial high speed amplifiers and comparators to choose from when selecting parts for the analog section of the replacement FEBs. No special ASICs or exotic components should be required for these functions. As on the current Analog FEBs a clean differential layout may be very useful in this low level analog section. Also as implemented on the current Analog FEBs a small amount of positive feedback hysteresis around the comparators will be useful. - It would be inexpensive to provide separate comparators on each PMT channel for: low TDC threshold, high TDC threshold, Scaler threshold, and Trigger threshold if that would make the replacement FEBs more useful. - Many of the functions on the current Digital FEBs are implemented with digital ECL flip-flops functioning as analog "one shots". These are used for example to guarantee that an asserted signal from the low threshold comparator is at least 25 nsec long and that the TDC sees a signal that falls below the low threshold at least 40 nsec after it fell below its high threshold. In a replacement design all of the digital board's logic can be moved onto one CPLD or very small FPGA. These will be very low power devices compared to the current Digital FEBs. To the extent that "one shot" functions are still needed they can be implemented digitally, e.g. with a granularity of 5 nsec if running from a 200 MHz clock. The front edge of the signal will pass through the digital stretcher un-effected by the 5 nsec time increments. Its only the stretch duration that will have a 5 nsec uncertainty. With the new CAEN TDCs it not even clear that we still needs these "TDC protection" features in the signals. - An estimate of the CPLD or small FPGA pin count is: 36 inputs (9 channels x 4 thresholds) and 32 outputs (9 channels x TDC,Scaler, Trigger + 4 "group trigger" signals + 1 special scaler signal) 68 I/O total. - Implementing all the digital functions in a CPLD or small FPGA will not be expensive and it will provide both a lot more logic and a lot more flexibility than exists on the current Digital FEB. - Although CPLDs and small FPGAs exist that can directly drive LVDS transmission lines it may be better to use separate discreet LVDS driver chips. That would make any board repair that is necessary to replace damaged line drives a lot easier and a non specialized process. There are few enough digital outputs that discreet drivers will not require much board real-estate. - Putting the PMT HV supply right on the replacement FEBs is an option that may have many advantages. Small HV supply modules that are designed to be soldered onto a circuit board of the required voltage and current for this application are available from a number of companies. Using a separate HV supply for each tank's worth of PMTs is an option. Control of the HV setting and readback of the HV voltage and the current draw over the VME bus would be a natural part of such a system. - List of the things that it would be practical to control and read back from the VME bus: Comparator Thresholds: TDC (low & hi), Scaler, Trigger PMT HV per group of 3 PMTs readback voltage and current Disable any PMT channel, e.g. if its signal has become noisy Control "special outputs", e.g. which PMT channel is driving a special monitoring scaler output Control the "group trigger" outputs, e.g. how many PMTs of the 3 in a tank must fire at once for the "tank trigger" signal to be asserted, and how long will the "tank trigger" signals be asserted for after its firing condition is meet.