Inspection Study of the VX1190A --------------------------------- Rev. Date 24-June-11 Received the card on 21-June-11. It is a VX1190A. It came with a revision n.9 22-Feb-2010 instruction book. It had been opened at Maryland and a sticker with the number "UMD 207013" had been attached to the front panel. The CAEN label on the back of the card shows a date of 240310. The card is about 71 mils thick and does not use milled edges for the card guides. Top of the Card: ---------------- It uses real solder tail 5 column VME-64X P1 P2 connectors from Sour ? It has a foot print for a not installed 3x10 P0 connector. I assume that this was for a CERN V430 Jaux "P0" connector. On the bottom only they have the slot ground static discharge trace. The input connectors are stepped or tiered - the mezzanine level input connectors stick out about 0.40" past the main board input connectors. In both cases they are the expected 3M connectors (3M part number P50E-068-P1-SR1-TG ) with "FD8341" stamped on them. In the center of the card, running most of the way from front to back, there is space for another mezzanine card that is serviced by 2 100 pin connectors. Is this a standard IP card (or whatever it is called now) layout format ? There is a 10 pin 0.1" x 0.1" vertical header on the card. I assume that this is a JTAG connection. The 4 TDC ASICs are labeled: "HPTDC CERN June 2005". The card's TDC input circuit uses discrete SMD transistors, resistors, capacitors. It looks like basically the same layout on the main card and on the 2 32 channel mezzanine cards. It does not use an exact "cell" type structure. In a block the layout is on both sides, i.e. 16 channels on top and 16 channels on the bottom. See the drawings that go with these notes. The main (only) FPGA is an ALTERA ACEX EP1K100FC484-2N This is an old small "100k gate", "49,152 RAM Bits" device. Is this the same part as either FPGA on the 1495 board ? There are 9 National LM1086 CS ADJ regulators with mild heat sinking. I assume that at least 8 of these are for the HPTDC ASICs. One National LM337 LM CEAC 8 pin SOIC adjustable negative regulator. There is 1 Fairchild NDP6020P on a much more significant heat sink. 1x MXAB L45B 8 pin mini SOIC which is a ? connected to the 2 outer pin of the above NDP6020 and a capacitor. There is 1 packaged DC/DC converter 4.7V to 9V input - 5V 1.6A output. I assume that this is for the -5V ECL parts. The Control Bus input uses a standard 3M 90 deg solder tail latching connector. The LEMO Trigger input uses a condo LEMO connector LEMO EPY.00 U6 is not installed. It is a 16 pin DIP SOIC foot print that is wired up. It clearly looks to be for a MAX RS-232 part with capacitor voltage generation. There are 2 small mezzanine cards with 2 hex rotor switches each and a Texas F520 each. Each of these switch mezzanine cards is mounted up on 20 pins in a DIP pattern and one of them has main card ICs mounted under it. There is a mezzanine card near the top of the P1 connector. It appears to be some kind of power control, maybe hot swap, type of thing. It is mounted up on 40 pins in a DIP pattern. Some of the traces to it are clearly for power. It has about 4 transistors on it: 4466, 4936, and Fairchild NF52. It has what are probably some current sense resistors on it. There are 2 ICs on it: LTC 1421 CG a Linear Technology hot swap controller and a LS74. The P1 VME Bus connector is received/driven by: 4x LCX16543, 1x 74AS757, 1x LVC16244A. ATMEL ATMEGA16L 8AU 0824K one of these with a not installed rock "X1" connected to its foot print. This is an 8 bit microcontroller with 16k bytes of in system flash program memory. One IDT 72V3690 L10PFG X0817P this is an IDT 32k x 36 bit FIFO. One CY7B991V - 7JXC 0837 This is a Cypress zero delay programmable skew clock buffer One AD96687B 0836 16 pin SOIC dual ECL comparator. One half of this is connected to the "Out_Prog" front panel Control Bus connector. The other half may not be wired - so far I can not tell. One Fairchild FIN1047 PH7AB 16 pin SOIC a 4 channel LVTTL to LVDS differential driver 400 MHz. 1x ATMEL TINY 13V 10SU 0942 8 pin SOIC CMOS 8-bit microcontroller 1x ATMEL 45DB081D SU 0951 8 pin SOIC 8 Mbit serial flash memory 2x OnSemi 10H125G differential QUAD ECL to TTL receivers 2x IDT QS3861 SO IDT Quick Switch Bus Switches, i.e. FETs that are used to connect terminators to the Control Bus. Bottom of the Card: ------------------- IDT 71V016 SA10PHG H0945P This is an IDT 64k by 16 bit Static RAM 2x Fairchild LCX16543 connected to the P2 connector's center row of pins VME signals. The LCX16543 is 16 non-inverting transceivers with registers with output enables 3.3V part 5V tolerant. Texas LC244A 3 pin SMD SO23 with "2A side J" U39 not installed but wired 28 pin SMD package U44 not installed but wired 32 pin square SMD package Trigger and Control Bus Interface: ---------------------------------- U17 and U23 are the two QS3861 U27 is the AD96687 U26 and U28 are the 10H125 Conn IC Conn IC IC Signal Pin Pin Pin Pin Ref -------- --- --- --- --- --- AUX 15 --> 6 16 --> 7 U17 Out_Prog 13 --> 10 14 --> 11 U23 Out_Prog 13 --> 1 14 --> 2 U27 Out_Prog 13 --> 19 14 --> ?? U26 L2_Rej 11 --> 9 12 --> 8 U26 L2_Acp 9 --> 14 10 --> 13 U28 CLK 7 --> 19 8 --> 18 U28 CLR 5 --> 4 6 --> 3 U26 TRG 3 --> 9 4 --> 8 U28 CRST 1 --> 14 2 --> 13 U26 TDC Channel Input Circuits: --------------------------- This is their LVDS or Differential ECL input circuit. Order of magnitude the inputs appear to be terminated in 110 Ohms and have a high Ohm value spreader bias resistors up and down to set a default state. The inputs also go through 39 Ohm resistors to the bases of two BSF17A mark E2P NPN transistor in a long tail pair. The individual collectors go to the HPTDC ASIC differential inputs and are pulled up with 39 Ohm resistors to some bus. The long tail emmiters go to the collector of a third BSF17A which is the current source. This current source transistor has a 220 Ohm (or is it 2.2 k Ohm) current setting emitter resistor and I assume that its base goes to a reference supply. LEMO Trigger Input Circuit: --------------------------- Order of magnitude the loop through LEMO center pins are tied driectly together. There is probably a high value pull up (or default direction) resistor and then 39 Ohm series resistor to the base of a BSF17A mark E2P NPN transistor. This is probably basically and emitter follower. The collector probably goes to a bus, e.g. ground. The emitter is probably pulled to -5.2V with a 470 Ohm resistor and the emitter runs to pin number 3 of U28 a 10H125 Diff ECL to TLL receiver.