T962 TPC Wire Order and ADF-2 Channel Numbering --------------------------------------------------- Original Rev. 2-JULY-2008 Current Rev. 18-AUG-2008 This file describes the Channel Numbering used on the ADF-2 Card when it is running the LArTPC firmware in its Data Path FPGAs and is used with the T962 PFC-16 preamp filter cards. The current version of firmware for the LArTPC application is: l1_three.exo date 17-Jan-2006. First understand just the connection of the PFC-16 card channels to the channels on the ADF-2 card and the VME starting address of the circular buffer for each channel on the ADF-2 card when it is running the LArTPC firmware. When the PFC-16 card is plugged into the UPPER connector on the ATC card: ----- PFC-16 Via the ATC Card Which is ADF-2 LArTPC Circular Channel Connect to ADF-2 ADF-2 Relative Channel Buffer DP_FPGA Number Pin Numbers Eta, Phi Name & VME Start Adrs ------- ---------------- -------------- ------- ---------------- 0 A15,A16 3,1 HD 13HD 1 0xB800 1 C15,C16 3,1 EM 13EM 1 0xB000 2 A13,A14 2,1 HD 9HD 1 0x3800 3 C13,C14 2,1 EM 9EM 1 0x3000 4 A11,A12 1,1 HD 5HD 0 0xB800 5 C11,C12 1,1 EM 5EM 0 0xB000 6 A9,A10 1,1 HD 1HD 0 0x3800 7 C9,C10 1,1 EM 1EM 0 0x3000 8 A7,A7 3,0 HD 12HD 1 0x9800 9 C7,C8 3,0 EM 12EM 1 0x9000 10 A5,A6 2,0 HD 8HD 1 0x1800 11 C5,C6 2,0 EM 8EM 1 0x1000 12 A3,A4 1,0 HD 4HD 0 0x9800 13 C3,C4 1,0 EM 4EM 0 0x9000 14 A1,A2 0,0 HD 0HD 0 0x1800 15 C1,C2 0,0 EM 0EM 0 0x1000 When the PFC-16 card is plugged into the LOWER connector on the ATC card: ----- PFC-16 Via the ATC Card Which is ADF-2 LArTPC Circular Channel Connect to ADF-2 ADF-2 Relative Channel Buffer DP_FPGA Number Pin Numbers Eta, Phi Name & VME Start Adrs ------- ---------------- -------------- ------- ---------------- 0 A31,A32 3,3 HD 15HD 1 0xF800 1 C31,C32 3,3 EM 15EM 1 0xF000 2 A29,A30 2,3 HD 11HD 1 0x7800 3 C29,C30 2,3 EM 11EM 1 0x7000 4 A27,A28 1,3 HD 7HD 0 0xF800 5 C27,C28 1,3 EM 7EM 0 0xF000 6 A25,A26 0,3 HD 3HD 0 0x7800 7 C25,C26 0,3 EM 3EM 0 0x7000 8 A23,A24 3,2 HD 14HD 1 0xD800 9 C23,C24 3,2 EM 14EM 1 0xD000 10 A21,A22 2,2 HD 10HD 1 0x5800 11 C21,C22 2,2 EM 10EM 1 0x5000 12 A19,A20 1,2 HD 6HD 0 0xD800 13 C19,C20 1,2 EM 6EM 0 0xD000 14 A17,A18 0,2 HD 2HD 0 0x5800 15 C17,C18 0,2 EM 2EM 0 0x5000 For use with the BVDC cards and the PFC-16 cards in the T962 setup it is useful to assign the ADF-2 cards a channel number that runs 0:31. This is NOT the ADF-2 card 0:15 EM & HD channel labelling that is used in the D-Zero application. This is NOT the ADF-2 card eta,phi channel labelling that is used in the D-Zero application. This is NOT the ADF-2 card D-Zero channel numbers just layed out in monotonic order and re-labeled 0:31 e.g. it is NOT 0 EM = 0 0 HD =1 1 EM =2 Rather the ADF-2 Card 0:31 Channel Number in the T962 LArTPC application comes from taking the ADF-2 card channels, in the natural order that they connect with the PFC-16 cards. This channel number is not in silkscreen on the ADF-2 cards. This channel number only appears to be "natural" if you study the pinout of the ADF-2 cards and ATC cards and PFC cables, the 3M connectors, and the PFC-16 cards. When the PFC-16 card is plugged into the UPPER connector on the ATC card: ----- Connects to PFC-16 T962 LArTPC Aplc Which is ADF-2 LArTPC Circular Channel ADF-2 Card 0:31 ADF-2 Relative Channel Buffer DP_FPGA Number Channel Number Eta, Phi Name & VME Start Adrs ------- ---------------- -------------- ------- ---------------- 0 0 3,1 HD 13HD 1 0xB800 1 1 3,1 EM 13EM 1 0xB000 2 2 2,1 HD 9HD 1 0x3800 3 3 2,1 EM 9EM 1 0x3000 4 4 1,1 HD 5HD 0 0xB800 5 5 1,1 EM 5EM 0 0xB000 6 6 1,1 HD 1HD 0 0x3800 7 7 1,1 EM 1EM 0 0x3000 8 8 3,0 HD 12HD 1 0x9800 9 9 3,0 EM 12EM 1 0x9000 10 10 2,0 HD 8HD 1 0x1800 11 11 2,0 EM 8EM 1 0x1000 12 12 1,0 HD 4HD 0 0x9800 13 13 1,0 EM 4EM 0 0x9000 14 14 0,0 HD 0HD 0 0x1800 15 15 0,0 EM 0EM 0 0x1000 When the PFC-16 card is plugged into the LOWER connector on the ATC card: ----- Connects to PFC-16 T962 LArTPC Aplc Which is ADF-2 LArTPC Circular Channel ADF-2 Card 0:31 ADF-2 Relative Channel Buffer DP_FPGA Number Channel Number Eta, Phi Name & VME Start Adrs ------- ---------------- -------------- ------- ---------------- 0 16 3,3 HD 15HD 1 0xF800 1 17 3,3 EM 15EM 1 0xF000 2 18 2,3 HD 11HD 1 0x7800 3 19 2,3 EM 11EM 1 0x7000 4 20 1,3 HD 7HD 0 0xF800 5 21 1,3 EM 7EM 0 0xF000 6 22 0,3 HD 3HD 0 0x7800 7 23 0,3 EM 3EM 0 0x7000 8 24 3,2 HD 14HD 1 0xD800 9 25 3,2 EM 14EM 1 0xD000 10 26 2,2 HD 10HD 1 0x5800 11 27 2,2 EM 10EM 1 0x5000 12 28 1,2 HD 6HD 0 0xD800 13 29 1,2 EM 6EM 0 0xD000 14 30 0,2 HD 2HD 0 0x5800 15 31 0,2 EM 2EM 0 0x5000 Now finally put this together with the information at the end of the file www.pa.msu.edu/~edmunds/LArTPC/T962/t962_readout_signal_path.txt and write the order that the ADF-2 channels need to be written into the T962 event file for the data in the event file to appear in TPC wire order. # LArTPC Circular Buffer # ADF-2 Card ------------------------------- # T962 ------------ Data Path Register Register # Wire_Number Crate Slot FPGA Start Count # ----------- ----- ---- --------- -------- -------- 1 0 8 0 0x7800 2048 2 0 8 0 0xF800 2048 3 0 8 1 0x7800 2048 4 0 8 1 0xF800 2048 5 0 8 0 0x1800 2048 6 0 8 0 0x9800 2048 7 0 8 1 0x1800 2048 8 0 8 1 0x9800 2048 9 0 8 0 0x3800 2048 10 0 8 0 0xB800 2048 11 0 8 1 0x3800 2048 12 0 8 1 0xB800 2048 13 0 8 1 0xB000 2048 14 0 8 1 0x3000 2048 15 0 8 0 0xB000 2048 16 0 8 0 0x3000 2048 17 0 8 1 0x9000 2048 18 0 8 1 0x1000 2048 19 0 8 0 0x9000 2048 20 0 8 0 0x1000 2048 21 0 8 1 0xF000 2048 22 0 8 1 0x7000 2048 23 0 8 0 0xF000 2048 24 0 8 0 0x7000 2048 25 0 9 0 0x1800 2048 26 0 9 0 0x9800 2048 27 0 9 1 0x1800 2048 28 0 9 1 0x9800 2048 29 0 9 0 0x3800 2048 30 0 9 0 0xB800 2048 31 0 9 1 0x3800 2048 32 0 9 1 0xB800 2048 33 0 8 0 0x5800 2048 34 0 8 0 0xD800 2048 35 0 8 1 0x5800 2048 36 0 8 1 0xD800 2048 37 0 8 1 0xD000 2048 38 0 8 1 0x5000 2048 39 0 8 0 0xD000 2048 40 0 8 0 0x5000 2048 41 0 9 1 0xB000 2048 42 0 9 1 0x3000 2048 43 0 9 0 0xB000 2048 44 0 9 0 0x3000 2048 45 0 9 1 0x9000 2048 46 0 9 1 0x1000 2048 47 0 9 0 0x9000 2048 48 0 9 0 0x1000 2048 49 0 10 0 0x3800 2048 50 0 10 0 0xB800 2048 51 0 10 1 0x3800 2048 52 0 10 1 0xB800 2048 53 0 9 0 0x5800 2048 54 0 9 0 0xD800 2048 55 0 9 1 0x5800 2048 56 0 9 1 0xD800 2048 57 0 9 0 0x7800 2048 58 0 9 0 0xF800 2048 59 0 9 1 0x7800 2048 60 0 9 1 0xF800 2048 61 0 9 1 0xF000 2048 62 0 9 1 0x7000 2048 63 0 9 0 0xF000 2048 64 0 9 0 0x7000 2048 65 0 9 1 0xD000 2048 66 0 9 1 0x5000 2048 67 0 9 0 0xD000 2048 68 0 9 0 0x5000 2048 69 0 10 1 0xB000 2048 70 0 10 1 0x3000 2048 71 0 10 0 0xB000 2048 72 0 10 0 0x3000 2048 73 0 10 0 0x5800 2048 74 0 10 0 0xD800 2048 75 0 10 1 0x5800 2048 76 0 10 1 0xD800 2048 77 0 10 0 0x7800 2048 78 0 10 0 0xF800 2048 79 0 10 1 0x7800 2048 80 0 10 1 0xF800 2048 81 0 10 0 0x1800 2048 82 0 10 0 0x9800 2048 83 0 10 1 0x1800 2048 84 0 10 1 0x9800 2048 85 0 10 1 0x9000 2048 86 0 10 1 0x1000 2048 87 0 10 0 0x9000 2048 88 0 10 0 0x1000 2048 89 0 10 1 0xF000 2048 90 0 10 1 0x7000 2048 91 0 10 0 0xF000 2048 92 0 10 0 0x7000 2048 93 0 10 1 0xD000 2048 94 0 10 1 0x5000 2048 95 0 10 0 0xD000 2048 96 0 10 0 0x5000 2048 Update on 18-AUG-2008: ---------------------- It now appears that there is a problem with the readout from T962. - The individual BVDC cards are being readout in the correct order, one after the other, starting from the beam input end of the TPC, i.e. the end closest to the cryostat flange cover. - But within the data from a given BVDC card all of the channels are backwards, i.e. first you get the actual wire data from the TPC wire furthest from the beam input end of the TPC and lastly you get the data for the wire closest to the beam input end of the TPC. Looking at two pictures on the web this is exactly what I would expect :-) - You can see the top surface of a BVDC card with the wire order labeled 24:13 12:1 in silkscreen by the connectors that plugs the BVDC onto the TPC wire frame at: www.pa.msu.edu/~edmunds/LArTPC/T962/Bias_Voltage_Distribution_Card/ pict_bvdc_cards_top.jpg - You can see the BVDC on the TPC in a picture that I took before the TPC was slid the whole way into the cryostat at: www.pa.msu.edu/~edmunds/LArTPC/T962/Bias_Voltage_Distribution_Card/ pict_bvdc_installed_2.jpg I think that the Cathode side and the readout wire side of the TPC have been swapped since things were originally designed, i.e. the Cathode is no longer on the side of the cryostat that has the port for attaching the internal HV lead to the TPC Cathode. I must ask Mitch about this. I will not edit any of the tables in this document at this time but I will prepare a readout control file for T962 that swaps the channels end for end within a block of 24.