PFC-16 Layout Details ----------------------------- Original Rev. 17-JULY-2007 Current Rev. 7-NOV-2007 This file contains a technical description of the 16 Channel Preamplifier and Filter Card. This is basically a set of notes that collected during the design of the PFC-16 circuit board. This file is divided into the following sections: PFC-16 Description Functions and Purpose Standard Orientation and Board Size Net Lists Power Connectors Input Connector Output Signal Connector and mapping to ADF-2 Board Layers Ground Plane and Power Plane Layer Names Net Names Mentor Layer Usage Board Stackup Trace Routing PCB Design Rule Summary Vias and Terminals used in Routing Signals and Power Generation of the Area Fills Generation of the Gerber Data and Hand Editing Generation of Drill Data Parts List PFC-16 Description Functions and Purpose ---------------------------------------- The intent of the PFC-16 is to provide a low cost low noise flexible front-end for a small LArTPC DAQ system at Fermilab. The signal flow through the PFC-16 has the following sections: - At the input there is a dual FET charge to Voltage preamplifier. This typically runs with a 1.8 pFd feedback capacitor for a conversion gain of 0.5 mVolts out per femto Coulomb inputs. The feedback resistor is 50 Meg Ohms. - Next there is a single-ended to differential buffer with gain stage. The gain of this stage is either: 3.11, 5.13, 6.00, or 7.98 depending on what species of ADF-2 card a given PFC-16 channel will be driving. - Next there are two differential stages of filtering with gain. First is a two pole low pass filter with a nominal gain of 5. Finally there is a two pole high pass filter with a nominal gain of 4.7 The differential output from this final filter stage feeds the pleated foil cable running to the ADF-2 card through a back terminator RC network. - The differential analog output from the PFC-16 is isolated from the ground structure of the low level signal section of the card and is available on connectors that provide for direct connection to the ADF-2 cards (where the signals are digitized and stored in circular buffers). - The detector wire signals are assumed to arrive at the PFC-16 cards without any DC Wire Bias Voltage. DC blocking capacitors must be included in the detector wire readout path ahead of the PFC-16 cards. - Filtering and distribution of the low Voltage power supplies for the Pre-Amplifiers and Filters is provided on the PFC-16. PFC-16 Standard Orientation and Board Size ------------------------------------------- The standard orientation for looking at and describing the PFC-16 circuit board will be looking at the "component side" of the card with its wire signal inputs on the left and its analog output to the ADF-2 cards on the right. Channel #15 is at the top and channel #0 is at the bottom. PFC-16 will be made about the size of a standard 6U by 160mm VME card. It will be 233.0mm tall "Y" direction by 165.0 mm wide "X" direction. The 0,0 origin of the card is in its lower left hand corner. Standard VME is 233.35mm tall by 160 mm wide. The intent is that we can stack the PFC-16 cards in normal 6U "VME" card file mechanics. 165.0, 233.0 / ______________________________________________________ | | | Ground Filter | | Connector Ch #15 Power | | ... Connector | | Ch #8 | | | | Wire Output | | Signal PreAmps Buffers Filters Connector | | Inputs Ch 0:15 | | | | Ch #7 | | ... PreAmp | | Ground Ch #0 Power | | Connector Connector | |______________________________________________________| / 0,0 PFC-16 Net Lists ----------------- The net list for the PFC-16 will be maintained in a number of managable size files. They are built into the full netlist using a script that calls the multiple instance tool to build the 16 channels from the single template. These net list files are kept in .../PFC-16/Work/Netlists/. The overall net list file for the PFC-16 is built using a script file which is also located in .../PFC-16/Work/Netlists/. There are separate script files in that directory to move the netlist file into the Mentor area and give it a Mentor version number and a script file to generate a "sorted netlist", i.e. sorted by the number of connections the net has a alphabetically. PFC-16 Power Connectors ------------------------ The following connectors are headers with 0.025" square pins on a 0.1" grid. The pinout of these connectors is symmetric and designed so that an offset of 1 will not cause damaging power supply connections. PreAmp Power Connector +---+---+---+ | 5 | 3 | 1 | 1 PAMP_VCC 4 GROUND +---+---+---+ 2 PAMP_VEE 5 PAMP_VEE | 6 | 4 | 2 | 3 GROUND 6 PAMP_VCC +---+---+---+ For the PreAmps the VCC supply is +8 Volts and the VEE supply is -6 Volts. Filter Power Connector +---+---+---+ | 5 | 3 | 1 | 1 FLTR_VCC 4 GROUND +---+---+---+ 2 FLTR_VEE 5 FLTR_VEE | 6 | 4 | 2 | 3 GROUND 6 FLTR_VCC +---+---+---+ For the Filters the VCC supply is +5 Volts and the VEE supply is -5 Volts. PFC-16 Signal Input Connectors ------------------------------- The wire signal input connector is a standard 90 degree 34 pin header. The wire signals inputs are on the even pin numbers starting with pin #2. This is to insure that in the cables that all signals will have a Ground Guard wire on both sides of it. All odd numbered pins are at Ground. Pin #34 is also tied to Ground. PFC-16 Card Wire Signal Channel Number Input Pin Number -------------- ---------------- 0 2 1 4 2 6 3 8 4 10 5 12 6 14 7 16 8 18 9 20 10 22 11 24 12 26 13 28 14 30 15 32 PFC-16 Output Connector and Channel Mapping to the ADF-2 ------------------------------------------------------------ The output connector is a 36 pin 3M MDR type right angle connector. The output connector on the PFC-16 card carries the analog signals from the PFC-16 to the ATC card and thus into the ADF-2 card which contains the ADCs and circular buffer memories. The channels on the ADF-2 card are numbered 0:15 EM & HD. In the internals of the ADF-2 card these channels appear in the following order: 0 EM, 0 HD, 1 EM, 1 HD, ... 30 EM, 30 HD, 31 EM, 31 HD. The Output Connector on the PFC-16 card is: J2 Connects PFC-16 Chs 0:05 to ADF-2 Chs 0,4,8,12,1,5,9,13 EM & HD or to Chs 2,6,10,14,3,7,11,15 EM & HD The Mentor Geometry for this 3M MDR connector will have its pin numbering setup to match the "Fermi standard" (which is not the 3M system) so that this numbering will match that on the ATC card schematics. 3M MDR Connector Pin Numbering (Fermi system) Circuit Board Foot Print Top Side of the Circuit Board | 36 18 | 35 17 | |\ 34 16 | | \ 33 15 | | \ 32 14 | | | 31 13 | | | 30 12 | | | The narrow side 29 11 | | | of the "D" is 28 10 | | | down against the 27 9 | | | top surface of 26 8 | | | the circuit board. 25 7 | | | 24 6 | | | 23 5 | | | 22 4 | | / 21 3 | | / 20 2 | |/ 19 1 | | | PCB Edge --->| PFC-16 Output Connector Pin Connections J2 Output J2 Output PFC-16 Connector PFC-16 Connector Channel Pin Numbers Channel Pin Numbers Number Dir Comp Number Dir Comp ------- ------------ ------- ------------ 0 2 20 8 10 28 1 3 21 9 11 29 2 4 22 10 12 30 3 5 23 11 13 31 4 6 24 12 14 32 5 7 25 13 15 33 6 8 26 14 16 34 7 9 27 15 17 35 Pins: 1, 18, 19, 36 and the connector shell are all GROUND. Reception of the analog signals on the ADF-2 Card PFC Connector Pin Numbers -------------------------- ADF-2 EM HD ADF-2 Relative Pin Numbers Pin Numbers Channel Number Eta, Phi Dir Cmp Dir Cmp -------------- -------------- ----------- ----------- 0 or 2 0,0 or 0,2 17 35 16 34 4 or 6 1,0 or 1,2 15 33 14 32 8 or 10 2,0 or 2,2 13 31 12 30 12 or 14 3,0 or 3,2 11 29 10 28 1 or 3 0,1 or 0,3 9 27 8 26 5 or 7 1,1 or 1,3 7 25 6 24 9 or 11 2,1 or 2,3 5 23 4 22 13 or 15 3,1 or 3,3 3 21 2 20 Pins: 1, 18, 19, 36 and the connector shell are all GROUND. In summary there are the following 2 ways to plug the PFC-16 into the ADF-2: Plug PFC-16 J2 into Plug PFC-16 J2 into the Upper ATC Connector the Lower ATC Connector PFC-16 Channel ADF-2 Channel PFC-16 Channel ADF-2 Channel -------------- ------------- -------------- ------------- 0 13 HD 0 15 HD 1 13 EM 1 15 EM 2 9 HD 2 11 HD 3 9 EM 3 11 EM 4 5 HD 4 7 HD 5 5 EM 5 7 EM 6 1 HD 6 3 HD 7 1 EM 7 3 EM 8 12 HD 8 14 HD 9 12 EM 9 14 EM 10 8 HD 10 10 HD 11 8 EM 11 10 EM 12 4 HD 12 6 HD 13 4 EM 13 6 EM 14 0 HD 14 2 HD 15 0 EM 15 2 EM As a final illustration of the channel numbering look at the situation when you connect two PFC-16 cards to the Upper and Lower connectors on an ATC to ADF-2 card. Recall that DAQ System Channel Number is equal to (ADF-2_Card_Num x 32) + channel number on the ADF-2 card: PFC-16 Card #0 DAQ System Channels 0:15 Upper ATC Connector PFC-16 Card #1 DAQ System Channels 16:31 Lower ATC Connector ** Note ** the following table is still under constructions ** ************************************************************** System PFC-16 PFC-16 ADF-2 ADF-2 Data Channel Card Channel Channel Path FPGA ------- ------ ------- ------- ---------- 0 0 15 0 EM 0 1 0 14 0 HD 0 2 0 13 4 EM 0 3 0 12 4 HD 0 4 0 11 8 EM 1 5 0 10 8 HD 1 6 0 9 12 EM 1 7 0 8 12 HD 1 8 0 7 1 EM 0 9 0 6 1 HD 0 10 0 5 5 EM 0 11 0 4 5 HD 0 12 0 3 9 EM 1 13 0 2 9 HD 1 14 0 1 13 EM 1 15 0 0 13 HD 1 16 1 15 2 EM 0 17 1 14 2 HD 0 18 1 13 6 EM 0 19 1 12 6 HD 0 20 1 11 10 EM 1 21 1 10 10 HD 1 22 1 9 14 EM 1 23 1 8 14 HD 1 24 1 7 3 EM 0 25 1 6 3 HD 0 26 1 5 7 EM 0 27 1 4 7 HD 0 28 1 3 11 EM 1 29 1 2 11 HD 1 30 1 1 15 EM 1 31 1 0 15 HD 1 PFC-16 Board Layers -------------------- The PFC-16 is a 4 layer card. In different setions of the card the layers are used in different ways. The crossection through the card is shown below for 4 different sections of the card. Output PreAmp S-End PostAmp to ADF-2 Stack Input to Diff Filter Connector Layer Section Buffer Section Section ----- ------- ------- ----------- --------- 1 Trc&Pad Trc&Pad Trc&Pad Trc&Pad Top 2 Ground Ground Ground Ground 3 PAMP Vcc&Vee FLTR Vee&Vcc FLTR Vcc&Vee All Vcc&Vee 4 <-- Traces and Pads burried in --> Pads Bot Ground Plane as required There is a Ground Area Fill on the top layer around the perimeter. The whole of Layer 4, except for the output connector, is a Ground Area Fill. PFC-16 Ground Plane and Power Plane Layer Names Net Names ---------------------------------------------------------- In addition to GROUND, the PFC-16 has 4 different Power Planes that will be implemented on just 1 layer in the stackup. As is the custom, each of these power planes will be handled as a separate layer in the Mentor Graphics design. These layers are concatenated when the Gerber data is generated. Power Plane Power Plane Nominal Mentor Plane Function Net Name Design Voltage Logical Layer ------------------ ----------- -------------- ------------- Ground GROUND - POWER_1 PreAmp Vcc PAMP_VCC +8 Volts POWER_2 PreAmp Vee PAMP_VEE -6 POWER_3 Filter Vcc FLTR_VCC +5 POWER_4 Filter Vee FLTR_VEE -5 POWER_5 All 4 Power Planes are implemented on one pcb layer. All 4 planes are plotted at once as "negative data". On a separate Mentor layer (DAM_1) there are cut lines drawn between the planes and keep outs drawn under other sections, e.g. the power planes are removed from the area of the Input and Output connectors. Ground and Power Plane Implementation ------------------------------------- The Ground Plane is implemented on three layers of the stackup: - Layer #1 (Top) This is a normal "positive" Mentor signal layer. It has a perimeter of Ground all around it. This perimeter of ground is done as an area fill. - Layer #2 Is a complete normal ground plane. It is implemented as a normal Mentor ground plane. It is plotted as "negative data" i.e. plot something where we do NOT want copper. The "lines" to keep the copper out of any sections where we do not want this ground plane and the "lines" to isolate the ground plane around the Output Connector are on a separate Mentor Layer (DAM_2) that will be plotted at the same time. - Layer #3 This is the set of 4 power planes. This is normal negative Mentor plane data. Lines to separate the various planes and to keep these planes out from under any sections where we do not want them are on the Mentor DAM_1 layer. NOTE: that the power planes under the individual preamps are isolated from the main preamp power distribution planes by 10 Ohm resistors. Thus there are really: 32 planes under preamps + 2 Preamp power distribution planes + 2 Filter power distribution planes = 36 planes in total. NOTE: that the area in the power planes directly under the PreAmp circuit feedback trace has been removed. NOTE: that areas in Layer #3 that are not needed for service as power planes are isolated from the rest of Layer #3 and are tied to Ground by "unrelieving" some of the Distributed Ground Vias in these areas. - Layer #4 (Bottom) Is is normal positive Mentor signal layer with ground fill in in all sections. There are a large number of bypass capacitors (both ceramic and Tantalum) on this layer. This layer may also be used for the one feedback signal trace in the PreAmp section that will not route on the top layer. The main Signal GROUND connections along the Input Connector edge of the PFC-16 card are tied to all of the Ground Planes. Note that the Ground connections to the shell of the output connector and to the 4 ground pins in the output connector are isolated from the pcb ground planes. The shell of the output connector and to the 4 ground pins in the output connector are connected to the Preamp shield box by a separate wire. PFC-16 Mentor Layer Usage -------------------------- The assignment of Mentor Physical Layers to Mentor Logical Layers is: Mentor Physical Mentor Plane Layer Logical Layer Net Name -------- ------------- ---------- 1 SIGNAL_1 2 POWER_1 GROUND 3 POWER_2 PAMP_VCC 4 POWER_3 PAMP_VEE 5 POWER_4 FLTR_VCC 6 POWER_5 FLTR_VEE 7 SIGNAL_2 PFC-16 Board Stackup --------------------- Stackup Layer Layer Type Content on this Layer ------------- -------------- --------------------- PCB Layer #1 Trace Layer #1 SIGNAL_1 and PAD_1 PCB Layer #2 Plane Layer #2 POWER_1 net GROUND DAM_2 Ground Plane Cuts PCB Layer #3 Plane Layer #3 POWER_2 net PAMP_VCC POWER_3 net PAMP_VEE POWER_4 net FLTR_VCC POWER_5 net FLTR_VEE DAM_1 Power Plane Cuts PCB Layer #4 Trace Layer #4 SIGNAL_2 and PAD_2 Ceramic and Tantalum Bypass Capacitors -------------------------------------- Each PreAmp is isolated from the PreAmp_VCC and PreAmp_VEE power distribution planes by a pair of 10 Ohm resistors. Each PreAmp has a 10 uFd Tantalum capacitor and two ceramic capacitors on its private VCC plane. Each PreAmp has a 10 uFd Tantalum capacitor and one ceramic capacitor on its private VEE plane. In total the PreAmp Section uses 32 Tantalum capacitors and 48 ceramic capacitors. The three differential opamps in each channel share two Tantalum capacitors; one on the FLTR_VCC and one on the FLTR_VEE. Each differential opamp has its own private pair of ceramic bypass capacitors. In total the Filter Section uses 32 Tantalum capacitors and 96 ceramic capacitors. All of these Tantalum and ceramic bypass capacitors are on the back side of the pcb. This is a total of 64 Tantalum capacitors (all 10 uFd 16V B case). There are 144 ceramic bypass capacitors ( 128 are 100 nFd 50 V 0805 and 16 are 470 nFd 25V 0805). Power Supplies -------------- The expected power requirements for the whole T962 system usings 30 of the PFC-16 cards is expected to be the followings: Full Complete 480 Power per PFC per PFC Card File Channel System Supply Channel Card 21 PFC Cards 30 PFC Cards ----------- --------- --------- ------------ -------------- Preamp +8V 14.0 mA 224 mA 4.704 Amps 6.720 Amps Preamp -6V 3.5 mA 56 mA 1.176 Amps 1.680 Amps Filter +5V 38.7 mA 619 mA 13.003 Amps 18.576 Amps Filter -5V 38.7 mA 619 mA 13.003 Amps 18.576 Amps Total Watts 0.52 Watts 8.32 Watts 175 Watts 250 Watts All of the raw power supply bricks are commercial linear power supplies. There is a separate Power Supply Chassis for each of the two PFC-16 card files, i.e. there are two Power Supply Chassies in the running system. - The Preamp +8V will come from a 12 Volt 10.2 Amp power supply Power One model number: HE12-10.2-A. I must demonstrate that this supply can run at 8 Volts and it may be best to use resistors in series with the bulk DC to limit the heat in the pass bank. HE12-10.2-A (not RoHS) is 179-2047-ND @ $115.00 in stock HE12-10.2-AG (Lead Free) is 179-2340-ND @ $115.00 zero stock - The Preamp -6Volts will come from a 5 Volt 6 Amp power supply Power One model number: HC5-6/0VP-A. I must demonstrate that this supply can be cranked up to 6.0 Volts output. HC5-6/OVP-AG (Lead Free) is 179-2325-ND @ $57.50 in stock - The Filter + & - 5 Volts will come from 5 Volt 25 Amp power supplies Power One model number: F5-25/0VP-A. F5-25/OVP-A (not RoHS) is 179-2026-ND @ $185.00 ?? zero stock Power Entry Circuits -------------------- The area along the Output Connector edge near the top of the card is used for the Filter circuit Power Entry. Along the same edge near the bottom of the card is the Preamp circuit Power Entry area. Each power entry area uses a 6 pin (2x3 0.1"x0.1" header) to bring the power supply on card. Each supply has a Transient Voltage Suppressor diode, a high quality 470 uFd 16 Volt Aluminum electrolytic capacitor, and a 100 uFd Tantalum capacitor right where the supply comes on board. In addition the PreAmp VCC supply has 5 more 100 uFd Tantalum capacitors and the PreAmp VEE supply has 1 more 100 uFd Tantalum capacitor in these PreAmp power distribution networks. Aluminum Electrolytic Capacitors The good SMD Aluminum Electrolytic Capacitors are Panasonic FK series. These are: 470 uFd 16 Volt 2000-5000 hours at 105 deg C 600 ma ripple current 0.16 Ohm ESR Panasonic Part No. EEV-FK1C471P The less fancy version of this capacitor is the Panasonic HA series. These are: 470 uFd 16 Volt 1000 hours at 105 deg C 190 ma ripple current ?.? Ohm ESR Panasonic Part No. EEV-HA1C471UP The large fancy Tantalum power capacitors are Kemet T520 series. This capacitor is: 150 uFd 10 Volt SMD mount Case Size D 0.025 Ohm ESR at 100 kHz 1 Amp ripple current. Kemet Part No. T520D157M010ASE025 The somewhat less fancy large Tantalum power capacitor (which is available in 16 Volt rating for the PreAmp Vcc) is the Kemet T495 series. This capacitor is: 100 uFd 16 Volt SMD mount Case Size D 0.10 Ohm ESR at 100 kHz 1.2 Amp ripple current. The standard small Tantalum capacitors out in each channel are standard Kemet 491 series. This capacitor is: 10 uFd 16 Volt SMD mount Case Size B 3.5 Ohm ESR at 100 kHz Kemet Part No. T491B106K016AS PreAmp Feedback Resistor ------------------------ The feedback resistor in the PreAmp is in the 50 to 100 Meg Ohm range. It would be nice if this could be a low noise metal film resistor. This must be a SMD component. It would be nice if it were a single 0805 component but making it a single 1206 or two 0805 resistors in series would also work. Some potential parts are the following: Caddock type CHR with the style FC terminals Resistance: 10, 20, 25, 40, 50, 75, 80, 100 Meg Ohm Tolerance: 1% Temp Coef: 35 ppm / deg C Size: 2520 6.35mm long 5.08 mm wide 0.7 mm thick Pads: solderable pads with standrd solder Voltage Coef of Resistance: ? Constructions: thin/thick metal ? Comment: "These high resistance precision chip resistors are designed for use in extremely low signal detection and amplification circuits. Applications include: Photodiode signal amplification, photomultipliers, ionization detection, etc." IRC type PFC-CR Resistance: 20 Meg Ohm max in the 2512 package 5 Meg max in 1206 Tolerance: 5%, 2%, 1%, 0.5%, 0.1% Temp Coef: 50 or 100 ppm / deg C Pads: solderable pads (with Ni barriers) with standrd solder Voltage Coef of Resistance: ? Constructions: Chromaxx thin film IRC type HR Resistance: 100 Meg to 50 G Tolerance: 5% and 10% Temp Coef: 0 to -1000 ppm / deg C Size: 0805, 1005, 1206 Pads: normal wrap-around leach resistant pads Voltage Coef of Resistance: 0.2% max for 1206 size going 10V to 25V Constructions: Thick film --> 133 ppm/V Comment: HR 1206 F 100M J T IRC type HVC Resistance: 100k to 100 Meg Tolerance: 5%, 10% Temp Coef: 100 ppm / deg C Size: 1206 2010 2512 2512 is 6.5mm by 3.2mm Pads: normal wrap-around Ni barrier leach resistant pads Voltage Coef of Resistance: 5 to 25 ppm/V max 2512 are best Constructions: Thick Film Comment: HVC 2512 100M J Vishay OCU 0805 Resistance: 11M to 130M Tolerance: 5% Temp Coef: 100 ppm/DegC below 47 Meg 250 ppm/DegC above 51 Meg Size: 0805 Pads: normal wrap-around Ni barrier leach resistant pads Voltage Coef of Resistance: 0.05%/V --> 500 ppm/V Constructions: assume thick film Comment: 47 Meg Ohm and 2 pFd --> 94 usec 100 Meg Ohm and 2 pFd --> 200 usec Decision: Plan on using the IRC type HVC in the 2512 size package. Plan on trying to get a spool of both 47 Meg and 100 Meg Ohm Resistance vs Trace Width and vs AWG Wire Size -------------------------------------------------- Wire Resistance Size per Foot Cross Section AWG in Ohms Area in sq-in Diameter in mils ---- --------- ------------- ---------------- 12 0.00162 0.00512 80.7 14 0.00258 0.00322 64.0 16 0.00409 0.00203 50.8 18 0.00651 0.00127 40.2 22 0.01646 0.00051 25.5 Start with the resistance of Copper at 25 degrees C. A bar of 1 square inch cross section and 1 foot long has a resistance of about 8.30 micro Ohms at 25 degrees C. The coefficient of resistance is positive and is about 0.38 % per degree C. So for 1 oz coper (i.e. 0.0014 inch thickness) we have the following table. Trace Trace Width Cross Section Approximate Resistance mills. square inches Wire Gauge Ohms per ft ------ ------------- ----------- ----------- 1 1.40 E-6 - 5.929 Ohm 7 9.80 E-6 39 0.85 10 1.40 E-5 37 0.59 15 2.10 E-5 36 0.40 20 2.80 E-5 35-34 0.30 25 3.50 E-5 33 0.24 50 7.00 E-5 31-30 0.12 75 1.05 E-4 29 0.079 100 1.40 E-4 28-27 0.059 For 1 oz coper (i.e. 0.0014 inch thickness) we have the following: Trace aprox Trace Width Width Resistance mm mils Ohms per ft ------ ----- ----------- 0.25 9.8 0.602 0.30 11.8 0.502 0.35 13.8 0.430 0.40 15.7 0.376 0.70 27.6 0.215 0.80 31.5 0.188 1.00 39.4 0.151 1.20 47.2 0.125 1.70 66.9 0.089 5.00 196.9 0.030 For more details see: www.pa.msu.edu/hep/d0/ftp/l1/framework/hardware/general/ resistance_and_z_of_traces.txt PFC-16 Trace Routing --------------------- Trace widths that will be used: PreAmp signal traces 0.4 mm use 0mm65 via PreAmp FET drain bus 0.8 mm PreAmp connections to planes 0.8 mm use 0mm65 via 0.8 from pad PreAmp power connections 1.0 mm use 1mm1 via 0.9 from pad PreAmp B Case Tant Caps 1.0 mm use 0mm65 via Diff OpAmp Ceramic ByPass Caps 0.70 mm use 0mm65 via Diff OpAmp Power Pins 0.35 mm use 0mm65 via Diff OpAmp "Gnd" Pins 0.30 mm use 0mm65 via Diff OpAmp all signals except output 0.30 mm only for output 0.35 mm Diff OpAmp B Case Tant Caps 1.2 mm use 1mm1 via Input Connector Escape Trace 0.3 mm Input Connector to PreAmp Run 0.4 mm Output Signal Routing Section: 0.30 mm traces with 0.30 mm gap use 0mm65 land via via center 0.7mm minimum from the center of the nearest trace ?.?? mm space between adjactent traces in different pairs Output Connector: within the output connector itself use 0.25 mm trace where dual track routing to escape the connector pins Power Connector traces: 1.70 mm use 1mm1 land via D Case Tantalum Bypass Capacitor Power and Ground traces: 1.20 mm use 1mm1 land via PCB Design Rule Summary ----------------------- What they What is in will Build this Design --------------- ---------------- Minimum Finished Hole Diameter: 10 mil 0.25 mm 12 mil 0.30 mm Narrowest annular ring: 7 mil 0.18 mm 7 mil 0.175 mm Narrowest trace width: 8 mil 0.20 mm 10 mil 0.25 mm Narrowest trace to bla space: 8 mil 0.20 mm 10 mil 0.25 mm Inner layer minimum distance from edge of hole to unconnected copper: 15 mil 0.38 mm Vias and Terminals used in Routing Signals and Power ----------------------------------------------------- Standard Small Routing Via: name: via_mm65 Drill Hole size (finished): 12 mil 0.30 mm Land diameter: 26 mil 0.65 mm --> ring width 7 mil 0.175 mm Plane to via relief: 43 mil 1.10 mm --> plane isolation Air Gap 9 mil 0.225 mm Tented via, no opening in the Solder_Mask. Power and Ground Larger Via: name: via_1mm1 Drill Hole size (finished): 24 mil 0.60 mm Land diameter: 43 mil 1.10 mm --> ring width 10 mil 0.25 mm Plane to via relief: 61 mil 1.55 mm --> plane isolation Air Gap 9 mil 0.225 mm Tented via, no opening in the Solder_Mask. Terminal used on the one pin via component: component name: wrap_1mm1 Padstack name: TERM_0_6_MM Drill Hole size (finished): 24 mil 0.60 mm Land diameter: 43 mil 1.10 mm --> ring width 10 mil 0.25 mm Plane to via relief: 65 mil 1.65 mm --> plane isolation Air Gap 11 mil 0.275 mm Solder Mask Opening diameter: 43 mil 1.10 mm Tent it ??? Terminal used on the 0.1" x 0.1" 25 mil square pin headers e.g. SAM2x6 The hole diameter must fit the diagonal of the 25 mil pins, i.e. a 35 mil diagonal. hole diameter 1.00 mm 39.4 mils pad land diameter 1.64 mm 64.6 mils ==> ring width 0.32 mm 12.6 mils plane relief 2.24 mm 88.2 mils ==> air gap 0.30 mm 11.8 mils With the 1.64 mm pad land diameter you can route a 0.30 mm trace that has 0.30 mm spaces on each side. DRILL_SIZE 1.00 mm PAD 1.64 mm SOLDER_MASK 1.64 mm POWER 2.24 mm Terminals used on the 36 pin 3M output connectors This connector has 4 columns of pins. There are 9 pins in each column. The columns are 75 mils apart. Within a column the pins are 100 mils apart. The required pin holes are 28 mils +- 4 mils. The closest approach of pins is not within a column but rather between adjacent pins in adjacent columns. They are about 90.1 mils apart, i.e. sqrt (75 sqrd + 50 sqrd). We need a one track route between adjacent pins in adjacent columns and two track route between adjacent pins in the back most column. The two track route will be the hardest. 100 - 28 is 72 mils to be divided between 2 rings, 3 spaces, and 2 traces. 72 mils divided by 7 is about 10.28 mils or about 0.26 mm. Pad Details and expected Clearances hole diameter 0.70 mm 27.6 mils pad land diameter 1.20 mm 47.2 mils ==> ring width 0.25 mm 9.8 mils plane relief 1.90 mm 74.8 mils ==> air gap 0.35 mm 13.8 mils With the 1.20 mm pad land diameter you can route two 0.25 mm traces between adjacent pins in a column and have a 0.25 mm space between the pads and the traces and between the two traces. In addition there is 0.11 mm of slop which is used to go from the English connector to the metric grid. With a plane relief of 1.90 mm you get a 0.35 mm Air Gap between a pad and the plane while still getting 0.39 mm of connectivity between adjacent pins in adjacent columents to the interior parts of the plane. Summary: DRILL_SIZE 0.70 mm PAD 1.20 mm SOLDER_MASK 1.20 mm POWER 1.90 mm Generation of the Area Fills in LAYOUT: ----------------------------------------- First recall the Mentor NET Type Rules for this design: Default Net Type Pin Via Trace Fill ----- ----- ----- ----- Pin 0.5 - - - Via 0.25 0.35 - - Trace 0.26 0.32 0.25 - Fill 0.7 0.7 0.7 0.25 Note: that for some other designs the clearance between the Fill and a Pin, Via, or Trace has been held out to 1.0 mm. Setup the Area Fill clearances from the: Setup Routing --> Setup Net Type Rules menue. For the Default_Net_Type pick a 0.7 mm clearance between Fill and Pin or Via or Trace Sellect a Thermo pattern for pins and Pads. Select Floading for Ground Vias. Pull Down Setup Routing --> Setup Area Fill Pad Isolation : Polygon Tolerance = 0.025 mm Manufacture Aperature: 0.50 mm Slot Threshold: try 1.1 mm Solid Fill, NO Keep Islands, YES Allow Merge Do Not ignore area fill to via clearance for the same net Do Not ignore area fill to pin clearance for the same net Thernal: Pins, and Pads use thermal ties all setup the same Prefer 4 ties, Minimum 3 ties, prefer 45/135 degree Tie_Bar_Width 0.5 mm Select Floading for Via's then to generate the Area Fill If a special version of the PCB Geometry is needed for the Area Fill generation use Librarian to restore it. For example you may want a version of some geometries with their mounting screw holes commented out so that these mounting screw holes will flood with the are fill. Pull Down Setup --> Shape Edit Mode ON Select the shape from the Shape Edit layer Right Click --> Change Shape to Fill: Area Fill ? vs Power Fill ? This is an Area Fill because it is on a trace layer and not on a power plane layer. Select Layer = Signal_1 or Signal_2 Select Net = GROUND Keep all Area Fill defaults NO delete the original shape typical warning: Area Fill is fractured into "N" pieces. Deletion of the Area Fill from FabLink: ----------------------------------------- Select the Area Fill on its Signal_ layer Area Fill Panel Menu --> Delete vertexes Generation of the Gerber Data from FabLink: -------------------------------------------- Assume that the Gerber Format has been setup and saved. Gerber Data is in mm 3.2 format. If necessary use: Right Click --> Artwork --> Change Artwork Format Image Scale: 1 Units: mm Mode: Absolute Plot Offsets: Manual with X=0.0 Y=0.0 G_Code: Allow Zero Suppression: None Interpolation: Linear with 8 Segments Output Format: 3 Significant and 2 decimal Data Record Length: 80 Header String: none Sub-Header String: none Trailer String: none Machine Stop Code: M02 XY-Modal: not checked Open Shutter Modal: not checked View Artwork Format: not checked Command Block End Character: * Aperature Table: Right Click --> Artwork --> Change Aperature Table --> Delete All Apertures Right Click --> Artwork --> Change Aperature Table --> Fill Aperature Table Select the Apertures for ALL Aizes Select NO ReSize and NO ReScale Flash Complex Padstacks: not checked Replace the table Report the Aperture Table (from Report Pull Down Menu) Include the ArtWork Format: yes Save and Display the Report Save Report to Design with standard filename Replace the existing Report May/Will need to Edit the Power Apertures: After the Aperture Table is filled it is necessary to edit the 5 Power Apertures (aka thermal reliefs) to get the desired layout. To edit a Power Aperture Right Click --> Artwork --> Change Aperture Table --> Change Power Aperture For each Power Aperture select the Aperture Position and then set the: Tie Width, Air Gap, and Rotation and then click OK. Note that the outer diameter of each Power Aperture is driven by its "power plane relief" diameter in its Geometry. We must set the Air Gap to get the desired pad size and set the Tie Width to get the desired amount of Copper connection. This version of Mentor lets us control the Tie Rotation. Currently the Power Apertures are at Aperture Positions: Desired for PFC-16 Outer ---------------------- D- Relief Tie Air Position Code Diameter Width Gap Rotate Function -------- ---- --------- ----- ----- ------ ---------- 26 126 1.55 0.25 0.225 45 via_1mm1 28 128 1.10 0.25 0.225 45 via_mm65 29 129 1.65 0.25 0.275 45 wrap_1mm1 30 130 2.24 0.35 0.3 45 samtec, Amp 33 133 1.90 0.35 0.35 45 3M Conn From the 30-AUG-2006 Aperture Table Report Position Shape Type Diameter Power Dcode -------- ------ ----- -------- ----- ----- 26 circle flash 1.55 true 126 28 circle flash 1.10 true 128 29 circle flash 1.65 true 129 30 circle flash 2.24 true 130 33 circle flash 1.90 true 133 Gerber Data Generation: Right Click --> Artwork --> Creat Artwork Data Gerber Data is Gerber 274X format Stroke the Area Fill, Flash the Polygon ASCII Data, for the BOARD, ALL ArtWork Numbers (1:11) NO Tear Drops, REMOVE Unused Pins, REMOVE Unused Via's NO Output UnPlated Holes NO ReSize, NO ReScale Right Click --> Artwork --> Creat Artwork Data All settings are the same except create Gerber Data for just ArtWork Numbers 1 and 4 i.e. the top and bottom pcb layers, but use the option Output ALL Pins, Output ALL Via's Gerber Data Viewing: Right Click --> Artwork --> Simulate Artwork Data Hand Editing of the Final PFC-16 Gerber Data -------------------------------------------- Hand Edits of the Gerber Files 1. Need to disconnect some power connector pins from the places where they come through the Layer #3 Power Plane. To do this edit the Layer #3 file, i.e. Art_3 and add a flash of the Plane Relief aperture DCode 131 (aperture position 31) in the locations shown below. Note that in the un-edited version of the Art_3 files these 4 locations are receiving a thermo tie connect flash of DCode 130 (aperture position 30). What we need to do is to add a flash of the Plane Relief aperture at these 4 locations to isolate these pins from the power plane. Specifically to the list of locations that receive the Plane Relief flash DCode 131 add the following 4 locations: X15573Y01316D03* X15573Y01824D03* X15573Y21476D03* X15573Y21984D03* The D131 flash list starts at about line number 403. Search for "D131". - The Layer #3 file for the Power Planes needs to be edited to cover up (i.e. disconnect) the PreAmp-Filter Power connector J3 pins 1 and 5 from the Power Planes. at about X = 155.73 mm Y = 18.24 mm at about X = 155.73 Y = 13.16 - The Layer #3 file for the Power Planes needs to be edited to cover up (i.e. disconnect) the Filter Power connector J4 pins 1 and 5 from the Power Planes. at about X = 155.73 mm Y = 219.84 mm at about X = 155.73 Y = 214.76 2. The way that I know of to connect the floating sections of the Layer #3 power plane to ground is to, by hand, remove the relief flash from the wrap_1mm1 Distributed Ground Via's that you want to use to tie to the floating sections of the layer #3 power plane to grounded. Along the West Input edge there are 12 Distributed Ground Vias that need to be "unrelieved" from Layer #3. The 8 Distributed Ground Vias along the East output connector edge need to be "unrelieved" from Layer #3. Note: that two of these vias attach the isolated Output Connector Ground to the isolated section of Layer #3 below it. Specifically: In the Art_3 the Power Planes file remove the flash of DCode 135 (Aperture Position 35) from the following 20 locations: X = 6.0 mm Y = 13.9 mm # Input Edge X = 6.0 mm Y = 26.6 mm X = 6.0 mm Y = 52.0 mm X = 6.0 mm Y = 71.0 mm X = 6.0 mm Y = 162.0 mm X = 6.0 mm Y = 181.0 mm X = 6.0 mm Y = 206.4 mm X = 6.0 mm Y = 219.1 mm X = 15.0 mm Y = 8.1 mm X = 15.0 mm Y = 224.9 mm X = 26.2 mm Y = 8.1 mm X = 26.2 mm Y = 224.9 mm X = 158.0 mm Y = 30.0 mm # Output Connector Edge X = 158.0 mm Y = 53.5 mm X = 158.0 mm Y = 77.0 mm X = 156.65 mm Y = 88.5 mm # Output Conn Gnd Pln X = 156.65 mm Y = 144.5 mm # Output Conn Gnd Pln X = 158.0 mm Y = 156.0 mm X = 158.0 mm Y = 179.5 mm X = 158.0 mm Y = 203.0 mm To find this section of the file search for, "D135". It will be at about line number 430. Remove the flowing flashes: X00600Y01390D03* X00600Y02660D03* X00600Y05200D03* X00600Y07100D03* X00600Y16200D03* X00600Y18100D03* X00600Y20640D03* X00600Y21910D03* X01500Y00810D03* X01500Y22490D03* X02620Y00810D03* X02620Y22490D03* X15665Y08850D03* X15665Y14450D03* X15800Y03000D03* X15800Y05350D03* X15800Y07700D03* X15800Y15600D03* X15800Y17950D03* X15800Y20300D03* NOTE: Not all flashed of D135 are removed from the file. D135 must continue to flash 17 times to isolate the via component rivets from the power plane that do not land in floating locations. Generation of the Drill Data from FabLink: ------------------------------------------- Assume that the Drill Format has been setup and saved. Drill Data is in mm 3.2 format. Drill Table: Right Click --> Drill --> Change Drill Table --> Delete All Drills Right Click --> Drill --> Change Drill Table --> Fill Drill Table Select Replace the Drill Table Right Click --> Drill --> Creat Drill Data Excellon, Board, ASCII, Drill Hole Type: Both Output Hole Types: ALL, NO Mirror. Report the Drill Table (from Report Pull Down Menu) Include the Drill Format Save and Display the Report Save Report to Design with standard filename Replace the existing Report Look at the Simulation of the Drill Data and find: Drill Position Drill Size Count -------------- ---------- ----- 1 0.3 576 via_mm65 2 0.6 311 via_1mm1 & wrap_1mm1 3 0.7 36 pins on 3M 36 pin 4 1.0 46 pin on 2x3 and 2x17 5 2.6924 2 34 pin mounting 6 3.2 2 3M 36 pin mounting 7 3.5 6 front bracket mounting